327 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 128K x 36/256K x 18 Synchronous-Pipelined Cache RAM Features • • • • • • • • • • • • • • • • • Fast access times: 3.5, 3.8, and 4.0 ns Fast clock speed: 166, 150, 133, and 117 MHz Provide high performance 3-1-1-1 access rate Fast OE access times: 3.5 ns and 3.8 ns Optimal for performance (double cycle chip deselect, depth expansion without wait state) 3.3V –5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1348A/GVT71128F36 and CY7C1328A/ GVT71256F18 SRAM integrate 262,144x18 and 131,072x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW1, BW2, BW3, BW4, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1 controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1348A/GVT71128F36/CY7C1328A/GVT71256F18 operates from a +3.3V core power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that benefit from a wide synchronous data bus. Selection Guide 7C1328A-166 71256F18-3 7C1348A-166 71128F36-3 7C1328A-150 71256F18-4 7C1348A-150 71128F36-4 7C1328A-133 71256F18-5 7C1348A-133 71128F36-5 7C1328A-117 71256F18-6 7C1348A-117 71128F36-6 Maximum Access Time (ns) 3.5 3.8 4.0 4.0 Maximum Operating Current (mA) 425 400 375 350 Maximum CMOS Standby Current (mA) 10 10 10 10 Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of International Business Machines, Incorporated. Cypress Semiconductor Corporation Document #: 38-05152 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 19, 2003 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Functional Block Diagram—128Kx36[1] BYTE 1 WRITE BW1# BWE# D Q CLK BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE ENABLE D CE2 Q D Q byte 2 write byte 1 write CE# Q byte 3 write D byte 4 write BW4# CE2# OE# ZZ Power Down Logic Input Register A16-A2 Address Register CLR ADV# OUTPUT REGISTER 128K x 9 x 4 SRAM Array ADSC# D Output Buffers ADSP# Q Binary Counter & Logic A1-A0 DQ1-DQ32, DQP1,DQP2 DQp3,DQp4 MODE Functional Block Diagram—256Kx18[1] UPPER BYTE WRITE WEH# BWE# D Q LOWER BYTE WRITE D Q CE# lo byte write GW# ENABLE D CE2 Q D Q hi byte write WEL# CE2# ZZ Power Down Logic OE# ADSP# ADSC# CLR ADV# A1-A0 Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers Address Register 256K x 9 x 2 SRAM Array A17-A2 Input Register DQ1DQ16, DQP1, DQP2 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05152 Rev. *B Page 2 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Pin Configurations MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 Document #: 38-05152 Rev. *B DQP2 DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 DQP1 NC NC NC VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1328A/GVT71256F18 (256K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C1348A/GVT71128F36 (128K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 A16 A17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQP3 DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 DQP4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP Top View Page 3 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Pin Descriptions Name Type Description A0 A1 A2–A17 InputSynchronous Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. BW1 BW2 BW3 BW4 InputSynchronous Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW1 controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls DQ25–DQ32 and DQP4. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. BW1 is equal to WEL and BW2 is equal to WEH for X18 device. BWE InputSynchronous Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. GW InputSynchronous Global Write: This active LOW input allows a full 38-bit (18-bit for X18 device) WRITE to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. CLK InputSynchronous Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE InputSynchronous Chip Enable: This active LOW input is used to enable the device and to gate ADSP. CE2 InputSynchronous Chip Enable: This active LOW input is used to enable the device. CE2 InputSynchronous Chip Enable: This active HIGH input is used to enable the device. OE Input ADV InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). ADSP InputSynchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. ADSC InputSynchronous Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. ZZ InputAsynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). DQ1–8 DQ9–16 DQ17–24 DQ25–32 Input/ Output Data Inputs/Outputs: Byte one is DQ1–DQ8. Byte two is DQ9–DQ16. Byte three is DQ17–DQ24. Byte four is DQ25–DQ32. Input data must meet set-up and hold times around the rising edge of CLK. X18 only has two bytes (Byte one and Byte two). DQP1– DQP4 Input/ Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16. DQP3 is parity bit for DQ17–DQ24 and DQP4 is parity bit for DQ25–DQ32. VCC Supply Power Supply: +3.3V –5% and +10%. VSS Ground Ground: GND. VCCQ I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC). VSSQ I/O Ground Output Buffer Ground: GND. NC - (A17 for X18) Document #: 38-05152 Rev. *B Output Enable: This active LOW asynchronous input enables the data output drivers. No Connect: These signals are not internally connected. User can connect them to VCC, VSS, or any signal. They can be left unconnected as floating. Page 4 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Burst Address Table (MODE = NC/VCC) Burst Address Table (MODE = GND) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE Deselected Cycle, Power Down None H X X Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H Deselected Cycle, Power Down None L X Deselected Cycle, Power Down CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ X L X X X L-H High-Z L X X X X L-H High-Z X L X X X X L-H High-Z L H L X X X L-H High-Z None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D Notes: 2. X = “Don’t Care.” H = logic HIGH. L = logic LOW. WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH. 3. BWa enables write to DQa. BWb enables write to DQb. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. Document #: 38-05152 Rev. *B Page 5 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Partial Truth Table for READ/WRITE Function GW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE one byte H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V VIN ...........................................................–0.5V to VCC+0.5V Storage Temperature (plastic) .......................–55°C to +150° Junction Temperature ..................................................+150° Power Dissipation.......................................................... 1.0W Short Circuit Output Current........................................ 50 mA Operating Range Range Com’l Ambient Temperature[9] VCC[10,11] 0°C to +70°C 3.3V −5%/+10% Note: 9. TA is the case temperature. 10. Please refer to waveform (c) 11. Power Supply ramp-up should be monotonic. Document #: 38-05152 Rev. *B Page 6 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [12, 13] VIHD Input High (Logic 1) Voltage VIH VIl Input Low (Logic 0) Voltage Min. Max. Unit Data Inputs (DQxx) 1.7 VCC+0.3 V All Other Inputs 1.7 4.6 V –0.3 0.7 V –2 2 µA 2 µA [12, 13] [14] ILI Input Leakage Current 0V < VIN < VCC ILO Output Leakage Current Output(s) disabled, 0V < VOUT < VCC –2 VOH Output High Voltage[12, 15] IOH = –2.0 mA 1.7 VOL Output Low Voltage VCC Supply Voltage VCCQ [12] Description V IOL = 2.0 mA [12] I/O Supply Voltage Parameter [12, 15] 0.7 V 3.135 3.6 V 2.375 VCC V Conditions Typ. -4 -4.4 -5 -6 Unit Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open 150 425 400 375 350 mA ICC Power Supply Current: Operating[16, 17, 18] ISB2 CMOS Standby[17, 18] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or >VCC – 0.2; all inputs static; CLK frequency = 0 5 10 10 10 10 mA ISB3 TTL Standby[17, 18] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 10 20 20 20 20 mA ISB4 Clock Running[17, 18] Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 40 90 80 70 60 mA Capacitance[19] Parameter Description Test Conditions CI Input Capacitance CO Input/Output Capacitance (DQ) Typ. Max. Unit 5 7 pF 7 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Thermal Resistance Description Test Conditions Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case) Symbol TQFP Typ. Unit ΘJA 25 °C/W ΘJC 9 °C/W Note: 12. All voltages referenced to VSS (GND). 13. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 15. AC I/O curves are available upon request. 16. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 17. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 18. Typical values are measured at 3.3V, 25°C, and 8.5-ns cycle time. 19. This parameter is sampled. Document #: 38-05152 Rev. *B Page 7 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 AC Test Loads and Waveforms[20] ALL INPUT PULSES 2.5V Q 10% Z0 =50Ω (a) 0V 50Ω Rise Time: 1 V/ns Vt = 1.25V tPU 90% 10% 90% = 200us V c c ty p V c c m in F o r p ro p e r R E S E T b r in g V c c d o w n t o 0 V Fall Time: 1 V/ns (b) (c) Switching Characteristics Over the Operating Range[21] -3 166 MHz Parameter Description Min. Max. -4 150 MHz Min. Max. -5 133 MHz Min. -6 117 MHz Max. Min. Max. Unit Clock tKC Clock Cycle Time 6.0 6.7 7.5 8.5 ns tKH Clock HIGH Time 2.4 2.6 2.8 3.4 ns tKL Clock LOW Time 2.4 2.6 2.8 3.4 ns Output Times tKQ Clock to Output Valid tKQX Clock to Output Invalid tKQLZ 3.5 Clock to Output in Low-Z tKQHZ 4.0 ns 1.5 1.5 ns [19, 22, 23] 0 0 0 0 ns [19, 22, 23] 1.5 [24] tOEQ OE to Output Valid tOELZ OE to Output in Low-Z[19, 22, 23] OE to Output in High-Z 4.0 1.5 Clock to Output in High-Z tOEHZ 3.8 1.5 6.0 1.5 6.7 3.5 0 [19, 22, 23] 1.5 3.5 0 7.5 1.5 3.8 0 3.5 3.5 8.5 ns 3.8 ns 0 3.8 ns 3.8 ns Set-up Times tS Address, Controls, and Data In[25] 1.5 1.5 1.5 2.0 ns Address, Controls, and Data In[25] 0.5 0.5 0.5 0.5 ns Hold Times tH Typical Output Buffer Characteristics Output High Voltage Pull-Up Current Output Low Voltage Pull-Down Current IOL (mA) Min. IOL(mA) Max. VOH (V) IOH (mA) Min. IOH (mA) Max. VOL (V) –0.5 –38 –105 –0.5 0 0 0 –38 –105 0 0 0 0.8 –38 –105 0.4 10 20 1.25 –26 –83 0.8 20 40 1.5 –20 –70 1.25 31 63 2.3 0 –30 1.6 40 80 2.7 0 –10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 Notes: 20. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. 21. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 22. Output loading is specified with CL = 5 pF as in AC Test Loads. 23. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 24. OE is a “Don’t Care” when a byte write enable is sampled LOW. 25. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table. Document #: 38-05152 Rev. *B Page 8 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Switching Waveforms Read Timing[26, 27] tKC tKL CLK tKH tS ADSP# tH ADSC# tS ADDRESS A1 BW1#, BW2#, BW3#, BW4#, BWE#, GW# A2 tH tS CE# tS ADV# tH OE# tKQ DQ tKQLZ tOELZ Q(A1) tOEQ tKQ Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Notes: 26. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. 27. For X18 product, there are only BW1 (i.e., WEL) and BW2 (i.e., WEH) for byte write control. Document #: 38-05152 Rev. *B Page 9 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Switching Waveforms (continued) Write Timing[26, 27] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 tH BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# tS ADV# tH OE# tKQX DQ Q tOEHZ D(A1) SINGLE WRITE Document #: 38-05152 Rev. *B D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 10 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Switching Waveforms (continued) Read/Write Timing[26, 27] CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 BW1#, BW2#, BW3#, BW4#, BWE#, GW# A3 A4 A5 tH CE# ADV# OE# DQ Q(A1) Q(A2) Single Reads D(A3) Single Write Q(A4) Q(A4+1) Q(A4+2) D(A5) Burst Read D(A5+1) Burst Write Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range Commercial 166 CY7C1328A-166AC/ GVT71256F18T-3 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 150 CY7C1328A-150AC/ GVT71256F18T-4 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 133 CY7C1328A-133AC/ GVT71256F18T-5 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 117 CY7C1328A-117AC/ GVT71256F18T-6 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 166 CY7C1348A-166AC/ GVT71128F36T-3 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 150 CY7C1348A-150AC/ GVT71128F36T-4 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 133 CY7C1348A-133AC/ GVT71128F36T-5 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 117 CY7C1348A-117AC/ GVT71128F36T-6 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Document #: 38-05152 Rev. *B Page 11 of 13 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05152 Rev. *B Page 12 of 13 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 Document Title: CY7C1328A/GVT71256F18, CY7C1348A/GVT71128F36 128K x 36/256K x 18 Synchronous-Pipelined Cache RAM Document Number: 38-05152 REV. ECN NO. Issue Date Orig. of Change ** 109896 09/22/01 SZV Change from Spec number: 38-00999 to 38-05152 *A 111423 01/31/02 GLC Removed preliminary from data sheet. *B 123138 01/20/03 RBI Add power up requirements to operating conditions information Document #: 38-05152 Rev. *B Description of Change Page 13 of 13