HY57V653220B 4 Banks x 512K x 32Bit Synchronous DRAM D E S C R IP T IO N The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V653220B is organized as 4banks of 524,288x32. H Y 5 7 V 6 5 3 2 2 0 B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • JEDEC standard 3.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 86pin TSOP-II with 0.5mm of • Programmable Burst Length and Burst Type pin pitch - 1, 2, 4, 8 or full page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM0,1,2 and 3 • Programmable C A S Latency ; 2, 3 Clocks • Internal four banks operation • Burst Read Single Write operation O R D E R IN G IN F O R M A T IO N Part No. Clock Frequency HY57V653220BTC-6I 166MHz H Y 5 7 V 6 5 3 2 2 0 B T C -7 I 14 3 M H z HY57V653220BTC-10I 100MHz HY57V653220BLTC-6I 166MHz HY57V653220BLTC-7I 143MHz HY57V653220BLTC-10I 100MHz Power Normal Organization 4Banks x 512Kbits x32 Interface Package LVTTL 400mil 86pin TSOP II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6/Aug.01 HY57V653220 B P IN C O N F IG U R A T IO N V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 NC V DD DQM0 /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 V DD NC DQ16 V SSQ DQ17 DQ18 V DDQ DQ19 DQ20 V SSQ DQ21 DQ22 V DDQ DQ23 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86pin TSOP II 4 0 0 m i l x 8 7 5 m il 0.5mm pin pitch 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 V SS NC DQ31 V DDQ DQ30 DQ29 V SSQ DQ28 DQ27 V DDQ DQ26 DQ25 V SSQ DQ24 V SS P IN D E S C R IP T IO N PIN P I N N A M E CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A10 Address Row Address Strobe, RAS, CAS, W E Column Address Strobe, Write Enable D E S C R IPTIO N The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 R A S , C A S and W E define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask C ontrols output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin V D D /V S S Power Supply/Ground P o w e r s u p p l y f o r i n t e r n a l c i r c u i t s a n d i n p u t b u f f e rs V D D Q /V S S Q Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.6/Aug.01 2 HY57V653220 B F U N C T IO N A L B L O C K D IA G R A M 5 1 2 K b i t x 4 b a n k s x 3 2 I/O S y n c h r o n o u s D R A M Self Refresh Logic Internal Row & Timer Counter 512Kx32 Bank 3 C L K Row Active Row 512Kx32 Bank 2 Decoders Column Cell Array Pre D Q M 1 Decoders D Q M 2 D Q M 3 Y decoders D Q 0 I/O Buffer & Logic Active Memory Sense AMP & I/O Gate Column D Q M 0 X decoders W E 512Kx32 Bank 0 X decoders C A S State Machine R A S 512Kx32 Bank 1 X decoders C S X decoders Pre C K E D Q 1 D Q 3 0 D Q 3 1 Column Add Bank Select A 0 Address A 1 Register Address buffers A10 Counter Burst Counter B A 0 B A 1 Rev. 0.6/Aug.01 CAS Latency Mode Registers Data Out Control Pipe Line Control 3 HY57V653220 B A B S O L U T E M A X IM U M R A T IN G S P a r a m e ter Symbol Rating Unit Ambient Temperature TA -40 ~ 85 °C Storage Temperature T STG -55 ~ 125 °C Voltage on Any Pin relative to V SS V IN, V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S V DD, VD D Q -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ T i m e T SOLDER 260 ⋅ 10 °C ⋅ S e c N o te : O p e r a t i o n a t a b o v e a b s o l u t e m a x i m u m r a t i n g c a n a d v e r s e l y a f f e c t d e v i c e r e l i a b i l i t y D C O P E R A T IN G C O N D IT IO N P a r a m e ter (TA= -40 to 8 5 ° C ) Symbol M in Typ. Max Unit N o te Power Supply Voltage VD D , VDDQ 3 .0 3.3 3.6 V 1 ,2 Input high voltage V IH 2.0 3.0 V D D Q + 0.3 V 1 ,3 Input low voltage V IL V S S Q - 0.3 0 0.8 V 1 ,4 Note N o te : 1 .A l l v o l t a g e s a r e r e f e r e n c e d t o V S S = 0 V 2.V IH ( m a x ) i s a c c e p t a b l e 5 . 6 V A C p u l s e w i d t h w i t h ≤ 3ns of duration with no input clamp diodes 3 .V I L ( m in ) i s a c c e p t a b l e - 2 . 0 V A C p u l s e w i d t h w i t h ≤ 3 n s o f d u r a t i o n w i t h n o i n p u t c l a m p d i o d e s A C O P E R A T IN G C O N D IT IO N ( T A = - 4 0 t o 8 5 ° C , 3. 0 V ≤V D D ≤ 3 . 6 V , V S S = 0 V - N o t e 1 ) Parameter Symbol Value Unit V IH / V I L 2.4/0.4 V Vtrip 1.4 V Input rise / fall time tR / tF 1 ns Output timing measurement reference level Voutref 1.4 V CL 30 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement 1 N o te : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) F o r d e t a i l s , r e f e r t o A C / D C o u t p u t l o a d c ir c uit Rev. 0.6/Aug.01 4 HY57V653220 B C A P A C IT A N C E ( T A = 2 5 °C , f = 1 M H z , V D D = 3 . 3 V ) P a r a m e ter Pin Input capacitance Symbol M in Max Unit CLK CI1 2.5 4 pF A 0 ~ A 1 0 , B A 0 , B A 1 , C K E , C S , R A S, C I2 2.5 5 pF C I/O 4 6.5 pF CAS, W E, DQM0~3 Data input / output capacitance DQ0 ~ DQ31 O U T P U T L O A D C IR C U IT V t t= 1 . 4 V Vtt=1.4V RT=500 Ω R T =50 Ω Output Z 0 = 5 0Ω Output 30pF 30pF DC Output Load Circuit D C C H A R A C T E R IS T IC S I (D C Parameter AC Output Load Circuit operating conditions unless otherwise noted) S y m b o l M in. Max U n it N o te Input leakage current IL I -1 1 uA 1 Output leakage current IL O -1.5 1.5 uA 2 Output high voltage VOH 2.4 - V IO H = - 2 m A Output low voltage VOL - 0.4 V IO L = + 2 m A Note : 1 .V IN = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t u n d e r t e s t = 0 V 2 .D O U T i s d i s a b l e d , V O U T = 0 t o 3 . 6 V Rev. 0.6/Aug.01 5 HY57V653220 B D C C H A R A C T E R IS T IC S II (D C operating conditions unless otherwise noted) Speed Parameter Symbol Test Condition -6I -7I Unit Note mA 1 -10I Burst Length=1, One bank active Operating Current Precharge Standby Current ID D 1 tRAS ≥ tRAS(min), tRP ≥ tRP(min), IOL=0mA ID D 2 P C K E ≤ VIL(max), tCK = 15ns 2 ID D 2 P S C K E ≤ VIL(max), tCK = ∞ 2 180 170 150 mA in power down mode CKE ≥ VIH(min), C S ≥ VIH(min), tCK = 15ns ID D 2 N ID D 2 N S 15 mA CKE ≥ VIH(min), tCK = ∞ 10 Input signals are stable. ID D 3 P C K E ≤ VIL(max), tCK = 15ns 3 ID D 3 P S C K E ≤ VIL(max), tCK = ∞ 3 ID D 3 N CKE ≥ VIH(min), C S ≥ VIH(min), tCK = 15ns Input signals are changed one time during 40 Active Standby Current in power down mode Input signals are changed one time during 2clks. All other pins ≥ V D D - 0 . 2 V o r ≤ 0.2V Precharge Standby Current in non power down mode mA 2clks. All other pins ≥ V D D - 0 . 2 V o r ≤ 0.2V Active Standby Current mA in non power down mode ID D 3 N S Burst Mode Operating Current IDD4 CKE ≥ VIH(min), tCK = ∞ 25 Input signals are stable t C K ≥ tCK(min), CL=3 tRAS ≥ tRAS(min), IOL=0mA All banks active CL=2 Auto Refresh Current ID D 5 tRRC ≥ tRRC(min), All banks active Self Refresh Current ID D 6 C K E ≤ 0.2V 240 250 210 160 mA 1 mA 2 2 mA 3 1.0 mA 4 220 190 N o te : 1 . ID D 1 a n d I D D 4 d e p e n d o n o u t p u t l o a d i n g a n d c y c l e r a t e s . S p e c i f i e d v a l u e s a r e m e a s u r e d w i t h t h e o u t p u t o p e n 2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II 3.HY57V653220BTC-6I/7I/10I 4.HY57V653220BLTC-6/7I/10I Rev. 0.6/Aug.01 6 HY57V653220 B A C C H A R A C T E R IS T IC S I ( A C operating conditions unless otherwise noted) -6 Parameter cycle time C A S Latency = 3 tCK3 Max 6 M in Max 7 1000 Min 10 1000 ns 1000 10 Clock high pulse width tCHW 2.5 - 3 - 3.5 - ns 1 Clock low pulse width tCLW 2.5 - 3 - 3.5 - ns 1 C A S Latency = 3 tAC3 - 5.5 - 5.5 - 6 ns C A S Latency = 2 tAC2 - 6 - - - 6 ns Data-out hold time tOH 2 - 2 - 2 - ns 3 Data-Input setup time tDS 1.5 - 1.75 - 2.5 - ns 1 Data-Input hold time tDH 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.75 - 2.5 - ns 1 Address hold time tAH 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.75 - 2.5 - ns 1 CKE hold time tCKH 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.75 - 2.5 - ns 1 Command hold time tCH 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - ns C A S Latency = 3 tOHZ3 - 5.5 - 5.5 - 6 ns C A S Latency = 2 tOHZ2 - 6 - 6 - 6 ns clock CLK to data output in high Z-time - Note Max tCK2 Access time from C A S Latency = 2 -10I Unit M in System clock -7I Symbol 12 ns 2 Note : 1 .A s s u m e t R / t F ( i n p u t r i s e a n d f a l l t i m e ) i s 1 n s 2 .A c c e s s t i m e s t o b e m e a s u r e d w i t h i n p u t s i g n a l s o f 1 v / n s e d g e r a t e , 0 . 8 v t o 2 . 0 v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination Rev. 0.6/Aug.01 7 HY57V653220 B A C C H A R A C T E R IS T IC S II ( A C operating conditions unless otherwise noted) -6 Parameter -7I -10 I Symbol Unit M in Max M in Max Min Max Operation tRC 60 - 63 - 70 - ns Auto Refresh tRRC 60 - 63 - 70 - ns R A S to C A S d e l a y tRCD 18 - 20 - 20 - ns R A S active time tRAS 42 100K 42 100K 50 100K ns RAS precharge time tRP 18 - 20 - 20 - ns R A S to R A S bank active delay tRRD 12 - 2 - 20 - ns C A S to C A S d e l a y tCCD 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - 0 - CLK Data-in to precharge command tDPL 2 - 2 - 2 - CLK Data-in to active command tDAL 5 - 4 - 4 - nd DQM to data-out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to data-in mask tDQM 0 - 0 - 0 - CLK MRS to new command tMRD 2 - 2 - 2 - CLK C A S Latency = 3 tPROZ3 3 - 3 - 3 - CLK C A S Latency = 2 tPROZ2 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms Note R A S cycle time Precharge to data output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.6/Aug.01 8 HY57V653220 B D E V IC E O P E R A T IN G O P T IO N T A B L E HY57V653220B(L)TC-6I C A S Latency tR C D tRAS tR C tRP tA C tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2.0ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2.0ns C A S Latency tR C D tRAS tR C tRP tA C tOH 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns HY57V653220B(L)TC-7I HY57V653220B(L)TC-10I C A S Latency tR C D tRAS tR C tRP tA C tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns Rev. 0.6/Aug.01 9 HY57V653220 B COMMAND TRUTH TABLE C o m m a n d A10/ A D D R CKEn-1 C K E n CS R A S C A S W E D Q M Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X AP RA Read Note V L CA Read with Autoprecharge V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Burst Stop H X DQM H Auto Refresh H H L L L Entry H L L L H H H X Exit L H L L V X V X H X X L H X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge X X X Self Refresh1 H L H X Precharge selected Bank Entry V H Precharge All Banks X X power down Exit Clock BA Entry L H H L Suspend Exit L X H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2 . X = D o n ′t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , Opcode = Operand Code, NOP = No Operation Rev. 0.6/Aug.01 10 HY57V653220 B P A C K A G E IN F O R M A T IO N 4 0 0 m il 8 6 p i n T h i n S m all O u tlin e P a c k a g e Unit : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) Rev. 0.6/Aug.01 0.21(0.008) 0.18(0.007) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 11