HY57V281620HC(L)T-I Series 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16 HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are sync h r o n i z e d w i t h t h e r i s i n g e d g e o f t h e c l o c k i n p u t . T h e d a t a p a t h s a r e i n t e r n a l l y p i p e l i n e d t o a c h i e v e v e r y h i g h b a n d w i d t h . A l l in p u t a n d output voltage levels are compatible with LVTTL. P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d b y a s i n g l e c o n t r o l c o m m a n d ( B u r s t l e n g t h o f 1 , 2 , 4 , 8 , o r f u l l p a g e ) , a n d t h e b u r s t c o u n t s e q u e n c e ( s e q u e n t i a l o r i n t e r l e a v e ) . A bu r s t o f r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type of pin pitch - 1, 2, 4, 8 or Full page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst • Data mask function by UDQM or LDQM • Internal four banks operation • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V281620HCT-6I 166MHz HY57V281620HCT-7I 143MHz HY57V281620HCT-KI 133MHz HY57V281620HCT-HI 133MHz HY57V281620HCT-8I 125MHz HY57V281620HCT-PI 100MHz HY57V281620HCT-SI 100MHz HY57V281620HCLT-6I 166MHz HY57V281620HCLT-7I 143MHz HY57V281620HCLT-KI 133MHz HY57V281620HCLT-HI 133MHz HY57V281620HCLT-8I 125MHz HY57V281620HCLT-PI 100MHz HY57V281620HCLT-SI 100MHz Power Organization Interface Package LVTTL 400mil 54pin TSOP II Normal 4Banks x 2Mbits x16 Low power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9/Sep. 01 HY57V281620HC(L)T PIN CONFIGURATION V DD 1 54 V SS DQ0 2 53 DQ15 V DDQ 3 52 V SSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 V SSQ 6 49 V DDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 V DDQ 9 46 V SSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 V SSQ 12 43 V DDQ DQ7 13 54pin TSOP II 42 DQ8 V DD 14 400mil x 875mil 41 V SS LDQM 15 0.8mm pin pitch 40 NC /WE 16 39 UDQM /CAS 17 38 CLK /RAS 18 37 CKE /CS 19 36 NC BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 V DD 27 28 V SS PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address Row Address Strobe, ColR A S , C A S, W E umn Address Strobe, Write Enable DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 R A S , C A S and W E define the operation Refer function truth table for details UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin V D D /V S S Power Supply/Ground Power supply for internal circuits and input buffers V D D Q /V S S Q Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.9/Sep. 01 3 HY57V281620HC(L)T FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter 2M x 1 6 B a n k 3 CLK Row active Row Pre Decoders 2M x 1 6 B a n k 2 CS Column Pre Decoders Active UDQM LDQM A0 DQ1 DQ14 DQ15 Y decoders Bank Select DQ0 I/O Buffer & Logic Memory Cell Array Sense AMP & I/O Gate Column X decoders WE refresh 2Mx16 Bank 0 X decoders CAS State Machine RAS 2Mx16 Bank 1 X decoders X decoders CKE Column Add Counter Address Registers A1 Address buffers Burst Counter A11 BA0 BA1 Rev. 0.9/Sep. 01 CAS Latency Mode Registers Data Out Control Pipe Line Control 4 HY57V281620HC(L)T ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA -40 ~ 85 °C Storage Temperature TS T G -55 ~ 125 °C Voltage on Any Pin relative to V S S V IN, V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S VDD, VD D Q -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ T i m e TSOLDER 260 ⋅ 10 °C ⋅ S e c Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION Parameter (T A = - 4 0 t o 8 5 ° C ) Symbol Min Typ Max Unit Note Power Supply Voltage VD D , VDDQ 3.0 3.3 3.6 V 1 Input High voltage V IH 2.0 3.0 V DDQ + 0.3 V 1,2 Input Low voltage V IL -0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0 V 2.V IH( m a x ) i s a c c e p t a b l e 5 . 6 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n . 3 . V I L( m i n ) i s a c c e p t a b l e - 2 . 0 V A C p u l s e w i d t h w i t h < = 3 n s o f d u r a t i o n . A C O P E R A T I N G T E S T C O N D I T I O N (TA = - 4 0 t o 8 5° C , V D D = 3 . 3 ± 0 . 3 V , V S S = 0 V ) Parameter Symbol Value Unit AC Input High / Low Level Voltage V IH / V IL 2.4/0.4 V Vtrip 1.4 V tR / tF 1 ns Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement 1 Note : 1 . O u t p u t l o a d t o m e a s u r e a c c e s s t i m e s i s e q u i v a l e n t t o t w o T T L g a t e s a n d o n e c a p a c i t o r ( 5 0 p F ) . F o r d e t a i l s , r e f e r t o A C / D C o u t p ut load circuit Rev. 0.9/Sep. 01 5 HY57V281620HC(L)T CAPACITANCE ( T A = 2 5° C , f = 1 M H z ) -6I/KI/HI Parameter Pin Input capacitance -8I/PI/SI Symbol Unit Min Max Min Max CLK C I1 2.5 3.5 2.5 4.0 pF A0 ~ A11, BA0, BA1, CKE, C S, RAS, CAS , CI 2 2.5 3.8 2.5 5.0 pF C I/O 4.0 6.5 4.0 6.5 pF W E, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50 pF DC Output Load Circuit DC CHARACTERISTICS I Parameter AC Output Load Circuit ( T A = - 4 0 t o 8 5 ° C , V D D = 3 . 3 ±0 . 3 V ) Symbol Min. Max Unit Note Input Leakage Current IL I -1 1 uA 1 Output Leakage Current IL O -1 1 uA 2 Output High Voltage VOH 2.4 - V IO H = - 2 m A Output Low Voltage VOL - 0.4 V IO L = + 2 m A Note : 1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V 2.DO U T is disabled, V O U T =0 to 3.6 Rev. 0.9/Sep. 01 6 HY57V281620HC(L)T DC CHARACTERISTICS II ( T A = - 4 0 t o 8 5 ° C , V DD =3.3 ± 0.3V, V S S = 0 V ) Speed Parameter Operating Current Precharge Standby Current in Power Down Mode Symbol ID D 1 Test Condition Burst length=1, One bank active t R C ≥ tR C ( m i n ) , I O L = 0 m A ID D 2 P C K E ≤ V IL ( m a x ) , t C K = 1 5 n s ID D 2 P S C K E ≤ V IL ( m a x ) , t C K = -6I -7I -KI -HI -8I -PI -SI 130 130 120 120 120 110 110 Unit Note mA 1 2 mA ∞ 1 C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = 1 5 n s ID D 2 N Input signals are changed one time during 20 3 0 n s . A l l o t h e r p i n s ≥ V DD - 0 . 2 V o r ≤ 0 . 2 V Precharge Standby Current mA in Non Power Down Mode ID D 2 N S Active Standby Current in Power Down Mode C K E ≥ V IH ( m i n ) , t C K = ∞ 15 Input signals are stable. ID D 3 P C K E ≤ V IL ( m a x ) , t C K = 1 5 n s ID D 3 P S C K E ≤ V IL ( m a x ) , t C K = 5 mA ∞ 5 C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = 1 5 n s ID D 3 N 30 Input signals are changed one time during 3 0 n s . A l l o t h e r p i n s ≥ V DD - 0 . 2 V o r ≤ 0 . 2 V Active Standby Current mA in Non Power Down Mode ID D 3 N S C K E ≥ V IH ( m i n ) , t C K = ∞ 20 Input signals are stable. Burst Mode Operating Current ID D 4 t C K ≥ t C K ( m i n ) , IO L = 0 m A All banks active Auto Refresh Current ID D 5 tR R C ≥ tR R C ( m i n ) , A l l b a n k s a c t i v e Self Refresh Current ID D 6 C K E ≤ 0.2V CL=3 150 140 130 130 130 110 110 CL=2 160 140 140 140 140 120 120 240 240 220 220 200 200 200 mA 1 mA 2 2 mA 3 800 uA 4 Note : 1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II 3.HY57V281620HCT-6I/KI/HI/8I/PI/SI 4.HY57V281620HCLT-6I/KI/HI/8I/PI/SI Rev. 0.9/Sep. 01 7 HY57V281620HC(L)T AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -6I Parameter tCK3 Max 6 System Clock Cycle Time -KI -HI Min Max Min Max Min 7 1000 7.5 1000 7.5 1000 -PI -SI Max Min 8 1000 7.5 10 Min Max 10 1000 10 Min 10 1000 10 Note Max ns 1000 10 Clock High Pulse Width tCHW 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock Low Pulse Width tCLW 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 C A S Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns C A S Latency = 2 tAC2 - 6 - 6 - 5.4 - 6 - 6 - 6 - 6 ns From Clock 10 Max tCK2 Access Time C A S Latency = 2 -8I Unit Min C A S Latency = 3 -7I Symbol 12 ns 2 Data-Out Hold Time tOH 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - ns Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address Setup Time tAS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns CLK to Data C A S Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 ns Output in High-Z Time C A S Latency = 2 tOHZ2 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 3 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 0.9/Sep. 01 8 HY57V281620HC(L)T AC CHARACTERISTICS II -6I Parameter -7I -KI -HI -8I -PI -SI Symbol Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Operation tRC 60 - 60 - 60 - 65 - 68 - 70 - 70 - ns Auto Refresh tRRC 60 - 65 - 65 - 65 - 68 - 70 - 70 - ns R A S to C A S Delay tRCD 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns R A S Active Time tRAS 42 100K 45 100K 45 100K 45 100K 48 100K 50 100K 50 100K ns RAS Precharge Time tRP 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns R A S to R A S Bank Active Delay tRRD 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns C A S to C A S Delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK Data-In to Precharge Command tDPL 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Data-In to Active Command tDAL 5 - 5 - 4 - 5 - 4 - 3 - 3 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK C A S Latency = 3 tPROZ3 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK C A S Latency = 2 tPROZ2 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms Note R A S Cycle Time Precharge to Data Output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.9/Sep. 01 9 HY57V281620HC(L)T DEVICE OPERATING OPTION TABLE HY57V281620HC(L)T-6I C A S Latency tRCD tRAS tRC tRP tAC tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns HY57V281620HC(L)T-7I C A S Latency tRCD tRAS tRC tRP tAC tOH 143MHz(7ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns 133MHz(7.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns 125MHz(8ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 2.0ns C A S Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.0ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns HY57V281620HC(L)T-KI HY57V281620HC(L)T-HI C A S Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns HY57V281620HC(L)T-8I C A S Latency tRCD tRAS tRC tRP tAC tOH 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.0ns C A S Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.0ns C A S Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.0ns HY57V281620HC(L)T-PI HY57V281620HC(L)T-SI Rev. 0.9/Sep. 01 10 HY57V281620HC(L)T COMMAND TRUTH TABLE Command A10/ ADDR CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X AP RA Read L V H Write L H X L H L L X CA V Write with Autoprecharge H Precharge All Banks H X L L H L X Burst Stop H DQM H Auto Refresh H H L L L H X L L Entry H L L H Exit L H Burst-Read-SingleWRITE X H H H L L V X V X H X X L L X L L H X X X X A9 Pin High MRS (Other Pins OP code) Mode X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge X X X 1 Entry L H X Precharge selected Bank X X power down Exit Clock Note V CA Read with Autoprecharge Self Refresh BA Entry L H H L Suspend Exit L X H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2 . X = D o n′ t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.9/Sep. 01 11 HY57V281620HC(L)T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.80(0.0315)BSC Rev. 0.9/Sep. 01 0.400(0.016) 0.300(0.012) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 12