HY57V561620T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V561620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V561620 is organized as 4 banks of 4,194,304x16. HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3V ± 0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 8192 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type of pin pitch - 1, 2, 4, 8 and Full Page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 and 8 for Interleave Burst • Data mask function by UDQM and LDQM • Internal four banks operation • Programmable C A S Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V561620T-HI 133MHz HY57V561620T-SI 100MHz HY57V561620LT-HI 133MHz HY57V561620LT-SI 100MHz Power Organization Interface Package LVTTL 400mil 54pin TSOP II Normal Power 4Banks x 4Mbits x16 Low Power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 0.1/ Apr.01 HY57V561620T PIN CONFIGURATION V DD 1 54 VS S DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 V DD 14 5 4p i n T S O P I I 400 mil x 875mil 41 VS S LDQM 15 0.8 m m p i n p i t c h 40 NC /W E 16 39 UDQM /C A S 17 38 CLK /R A S 18 37 CKE /C S 19 36 A12 BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 V DD 27 28 VS S PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A12 Address Row Address Strobe, ColRAS, CAS, W E umn Address Strobe, Write Enable DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 R A S , C A S and W E define the operation Refer function truth table for details UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin V D D /V S S Power Supply/Ground Power supply for internal circuits and input buffers V D D Q /V S S Q Data Output Power/Ground Power supply for output buffers NC No Connection No connection Revision 0.1 / Apr.01 2 HY57V561620T FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x16 I/O Synchronous DRAM Self Refresh Logic Internal Row & Timer Counter 4Mx16 Bank 3 CLK Row Active Row 4M x 1 6 B a n k 2 Decoders CS Cell Array Column Active Pre UDQM Decoders DQ0 I/O Buffer & Logic Column Memory Sense AMP & I/O Gate WE 4M x 1 6 B a n k 0 X decoders CAS State Machine RAS 4Mx16 Bank 1 X decoders X decoders Pre CKE DQ1 DQ14 DQ15 LDQM Y decoders Column Add Bank Select A0 Address A1 Register Counter Address buffers Burst Counter A12 BA0 BA1 Revision 0.1 / Apr.01 CAS Latency Mode Registers Data Out Control Pipe Line Control 3 HY57V561620T ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA -40 ~ 85 °C Storage Temperature TS T G -55 ~ 125 °C Voltage on Any Pin relative to V SS V IN , V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S VDD, VD D Q -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ T i m e TS O L D E R 260 ⋅ 10 °C ⋅ S e c Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION Parameter ( T A = - 4 0 t o 8 5 °C ) Symbol Min Typ. Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6 V 1 Input High Voltage V IH 2.0 3.0 V D D Q + 2.0 V 1,2 Input Low Voltage V IL VSSQ-2.0 0 0.8 V 1,3 Note : 1. All voltages are referenced to V S S = 0V 2 . V IH ( m a x ) i s a c c e p t a b l e 5 . 6 V A C p u l s e w i d t h w i t h ≤3 n s o f d u r a t i o n 3 . V IL ( m a x ) i s a c c e p t a b l e - 2 . 0 V A C p u l s e w i d t h w i t h ≤3 n s o f d u r a t i o n AC OPERATING CONDITION ( T A = - 4 0 t o 8 5 °C , V D D = 3 . 3 ± 0 . 3 V , V S S = 0 V ) Parameter Symbol Value Unit AC Input High / Low Level Voltage V IH / V IL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1 Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Revision 0.1 / Apr.01 4 HY57V561620T CAPACITANCE ( T A = 2 5° C , f = 1 M H z ) -HI Parameter Pin Input capacitance -SI Symbol Unit Min Max Min Max CLK C I1 2.5 3.5 2.5 4.0 pF A0 ~ A12, BA0, BA1, CKE, C S, RAS, CAS , CI 2 2.5 3.8 2.5 5.0 pF C I/O 4.0 6.5 4.0 6.5 pF W E, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 OUTPUT LOAD CIRCUIT V t t= 1 . 4 V RT=250 Ω Output Output 50 pF 50pF DC Output Load Circuit DC CHARACTERISTICS I Parameter AC Output Load Circuit ( T A = - 4 0 t o 8 5 ° C , V DD =3.3 ± 0 . 3 V ) Symbol Min. Max Unit Note Input leakage current IL I -1 1 uA 1 Output leakage current IL O -1 1 uA 2 Output high voltage VOH 2.4 - V IO H = - 4 m A Output low voltage VOL - 0.4 V IO L = + 4 m A Note : 1. V IN = 0 to 3.6V, All other pins are not under test = 0V 2. DO U T is disabled, V O U T =0 to 3.6V Revision 0.1 / Apr.01 5 HY57V561620T DC CHARACTERISTICS II ( T A = - 4 0 °C t o 8 5 °C , V D D = 3 . 3 V ± 0 . 3 V , V S S = 0 V ) Speed Parameter Operating Current Symbol ID D 1 Burst Length=1, One bank active tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA -HI -SI 120 100 ID D 2 P C K E ≤ VIL(max), tCK = min. 2 ID D 2 P S C K E ≤ VIL(max), tCK = ∞ 2 ID D 2 N C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. Precharge Standby Current in power down mode Test Condition Unit Note mA 1 mA All other pins ≥ VDD-0.2V or Precharge Standby Current 20 ≤ 0.2V mA in non power down mode ID D 2 N S C K E ≥ VIH(min), tCK = ∞ 10 Input signals are stable. ID D 3 P C K E ≤ VIL(max), tCK = min 3 ID D 3 P S C K E ≤ VIL(max), tCK = ∞ 3 Active Standby Current in power down mode mA C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min ID D 3 N Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or Active Standby Current 25 ≤ 0.2V mA in non power down mode ID D 3 N S Burst Mode Operating C K E ≥ VIH(min), tCK = ∞ Input signals are stable 15 t C K ≥ tCK(min), IDD4 tRAS ≥ tRAS(min), IO=0mA All banks active 150 120 mA 1 Auto Refresh Current ID D 5 t R R C ≥ tRRC(min), All banks active 260 250 mA 2 4 mA 3 Self Refresh Current ID D 6 C K E ≤ 0.2V 2 mA 4 Current Note : 1. ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II 3. HY57V561620T-HI/SI 4.HY57V561620LT-HI/SI Revision 0.1 / Apr.01 6 HY57V561620T AC CHARACTERISTICS I -HI Parameter Unit Min System clock cycle time C A S Latency = 3 -SI Symbol tCK3 Max 7.5 Min 10 1000 ns 1000 tCK2 12 Clock high pulse width tCHW 2.5 - 3 - ns 1 Clock low pulse width tCLW 2.5 - 3 - ns 1 C A S Latency = 3 tAC3 - 5.4 6 ns C A S Latency = 2 tAC2 - 6 6 ns Access time from clock C A S Latency = 2 Note Max 12 ns 2 Data-out hold time tOH 2.5 - 2.5 - ns Data-Input setup time tDS 1.5 - 2 - ns 1 Data-Input hold time tDH 0.8 - 1 - ns 1 Address setup time tAS 1.5 - 2 - ns 1 Address hold time tAH 0.8 - 1 - ns 1 CKE setup time tCKS 1.5 - 2 - ns 1 CKE hold time tCKH 0.8 - 1 - ns 1 Command setup time tCS 1.5 - 2 - ns 1 Command hold time tCH 0.8 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - ns CLK to data output in high Z-time C A S Latency = 3 tOHZ3 2.7 5.4 3 6 ns C A S Latency = 2 tOHZ2 3 6 3 6 ns Note : 1. Assume tR / tF (input rise and fall time ) is 1ns. 2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v Revision 0.1 / Apr.01 7 HY57V561620T AC CHARACTERISTICS II -HI Parameter -SI Symbol Unit Min Max Min Max Operation tRC 65 - 70 - ns Auto Refresh tRRC 65 - 70 - ns R A S to CAS delay tRCD 20 - 20 - ns RAS active time tRAS 45 100K 50 100K ns R A S precharge time tRP 20 - 20 - ns R A S to RAS bank active delay tRRD 15 - 20 - ns C A S to CAS delay tCCD 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - CLK Data-in to precharge command tDPL 2 - 2 - CLK Data-in to active command tDAL 5 - 4 - CLK DQM to data-out Hi-Z tDQZ 2 - 2 - CLK DQM to data-in mask tDQM 0 - 0 - CLK MRS to new command tMRD 2 - 2 - CLK C A S Latency = 3 tPROZ3 3 - 3 - CLK C A S Latency = 2 tPROZ2 - - 2 - CLK Power down exit time tPDE 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - CLK Refresh Time tREF - 64 - 64 ms Note R A S cycle time Precharge to data output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit. Revision 0.1 / Apr.01 8 HY57V561620T DEVICE OPERATING OPTION TABLE HY57V561620(L)T-HI C A S Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.5ns 100MHz(10ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns HY57V561620(L)T-SI C A S Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns Revision 0.1 / Apr.01 9 HY57V561620T COMMAND TRUTH TABLE Command A10/ ADDR CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X RA Read BA Note 1 V L CA Read with Autoprecharge V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Precharge selected Bank Burst Stop H UDQM, LDQM H Auto Refresh H H L L L Entry H L L L X H X Exit L H H L H H L X L V X V X H X X L H X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge H X X X Self Refresh Entry V H Precharge All Banks X X power down Exit Clock AP Entry L H H L Suspend Exit L X H X X X X Note : 1. OP Code : Operand Code 2. V = Valid, X = Don’t care, H = Logic High, L= Logic Low, RA = Row Address, CA = Column Address. Revision 0.1 / Apr.01 10 HY57V561620T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package Unit : mm(Inch) Revision 0.1 / Apr.01 11