IS25C32-2/3 IS25C64-2/3 ISSI ® 32,768/65,536-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM PRELIMINARY INFORMATION NOVEMBER 2001 DESCRIPTION FEATURES • 2.1 MHz Clock Rate • Low power CMOS — Active current less than 3.0 mA (5.5V) — Standby current less than 10 µA (5.5V) • Low-voltage Operation — IS25C64-3 & IS25C32-3 (Vcc = 2.5V to 5.5V) — IS25C64-2 & IS25C32-2 (Vcc = 1.8V to 5.5V) • Block Write Protection — Protect 1/4, 1/2, or Entire Array • 32 byte page write mode • Serial Peripheral Interface (SPI) Compatible — Supports SPI Modes 0 (0,0) and 3 (1,1) • Self timed write cycles (5 ms Typical) • High-reliability — Endurance: 1 million cycles per byte — Data retention: 100 years — ESD protection >4000V • Industrial temperature available • 8-pin PDIP or SOIC, and 14-pin TSSOP Packages PRODUCT OFFERING OVERVIEW Part No IS25C64-2 IS25C64-3 IS25C32-2 IS25C32-3 Voltage 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V Speed 500 KHz 2.1MHz 500 KHz 2.1MHz Standby ICC < 5 µA < 10 µA < 5 µA < 10 µA The IS25C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192x8) electrically Erasable PROM, IS25C64-3 is a 2.5V (2.5V5.5V) 64K bit (8192x8) Electrically Erasable PROM, IS25C32-2 is a 1.8V (1.8V-5.5V) 32K-bit (4096x8) Electrically Erasable PROM, IS25C32-3 is a 2.5V (2.5V-5.5V) 32K-bit (4096x8) Electrically Erasable PROM. The IS25Cxx (IS25C64-2, IS25C64-3, IS25C32-2 and IS25C32-3) family is a low-cost and low voltage/low power SPI Serial EEPROM. It is fabricated using ISSI's advanced CMOS EEPROM technology and provides a low power and low voltage operation for low power industrial and commercial application. The IS25Cxx family is available in 8 pin PDIP, 8 Pin SOIC, and 14 pin TSSOP packages. The IS25Cxx is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four configurations of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin can suspend communications without re-initializing the serial sequence. Read ICC 1 mA 1 mA 1 mA 1 mA Write ICC 3 mA 3 mA 3 mA 3 mA Temperature C,I C,I C,I C,I Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 1 IS25C32-2/3 IS25C64-2/3 ISSI ® PIN CONFIGURATION 14-pin TSSOP 8-Pin DIP and SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO NC NC NC WP GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI PIN DESCRIPTIONS PIN DESCRIPTIONS CS Chip Select SCK SI SO GND VCC WP HOLD NC Serial Data Clock Serial Data Input Serial Data Output Ground Power Write Protect Suspends Serial Input No Connect Serial Clock (SCK) - This pin is used to synchronize the communication between the microcontroller and the IS25C64, IS25C32. Op-codes, byte addresses, or data present on the SI pin and latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1). Serial Data Input (SI) - The SI pin is used to input all opcodes, byte addresses, and data to be written to the device. Input data is latched on the rising edge of the serial clock for SPI modes (0,0 & 1,1). Serial Data Output (SO) - The SO pin is used to transfer data out of the device. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1). Chip Select (CS): When the CS pin is low, the device is enabled. When the CS pin is high the device is disabled. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The devices draws zero current in the Standby mode. A high-to-low transition on CS is required prior to any sequence being initiated. A low-to-high transition on CS after a valid write sequence is what initiates an internal write cycle. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 IS25C32-2/3 IS25C64-2/3 ISSI PIN DESCRIPTIONS Continued: ® SERIAL INTERFACE DESCRIPTION Write Protect (WP) - The WP Pin will allow normal read/ write operations when held high. When WP is tied low and the WPEN bit in the status register is set to "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. Hold (HOLD): The HOLD pin is used to pause transmission to the device while in the middle of a serial sequence without having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transition on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to Vcc or tied to Vcc through a resistor. The HOLD Timing Diagram illustrates hold timing sequence. MASTER: This device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the device always operates as a slave. MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the device, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communications. BLOCK DIAGRAM VCC STATUS REGISTER GND 8192 x 8/4096 x 8 MEMORY ARRAY DATA REGISTER ADDRESS DECODER SI CS WP SCK OUTPUT BUFFER MODE DECODE LOGIC CLOCK so HOLD Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 3 IS25C32-2/3 IS25C64-2/3 ISSI ® FUNCTIONAL DESCRIPTIONS The IS25C32/64 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to low CS transition. Table 3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1(WEN) Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BPO) See Table 4 Bit 3 (BP1) See Table 4 Table 1. Instruction Set Name Instruction Format WREN WRDI RDSR WRSR READ 0000 X110 Set Write Enable Latch 0000 X100 Reset Write Enable Latch 0000 X101 Read Status Register 0000 X001 Write Status Register 0000 X011 Read Data from Memory Array WRITE 0000 X010 Operation Write Data to Memory Array WRITE ENABLE (WREN): This device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. Bits 4 - 6 are 0s when the device is not an internal write cycle. Bits 7 (WPEN) See Table 5. Bits 0-7 are 1s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The device is divided into four array segments. One quarter (1/4), one half (1/2) or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP, BP1 and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, twc, RDSR). READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 4. Status Register Format Status Register Bits Level Table 2. Status Register Format Bit 7 WPEN 4 Bit 6 Bit 5 Bit 4 x x x BP1 BP0 IS25C32 IS25C64 0 0 0 None None 1(1/4) 0 1 2(1/2) 1 0 3(All) 1 1 0C00 -0FFF 0800 -0FFF 0000 -0FFF 1800 -1FFF 1000 -1FFF 0000 -1FFF Bit 3 Bit 2 Bit1 Bit 0 BP1 BP0 WEN RDY Array Addresses Protected Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 IS25C32-2/3 IS25C64-2/3 ISSI The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is '"1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0". When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP pin is held low. Table 5. WPEN Operation WPEN WP WEN Protected Blocks 0 0 1 1 X X X Low Low High 0 1 0 1 0 Protected Protected Protected Protected Protected Protected Writable Protected Writable Protected Protected Writable Protected Protected Protected X High 1 Protected Writable Writable Unprotected Protected Blocks Register READ SEQUENCE (READ): Reading the device via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (A15-A0, Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 ® WRITE SEQUENCE (READ): In order to program the device, two sperate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15-A0) and the data (D7-D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The Low to High transition of the CS pin must occur during the SCK lowtime immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0 , the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. The device is capable of the 32-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over the previously written data will be overwritten. The device is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key Name AN Don't Care Bits IS25C32 IS25C64 A11-A0 A15-A12 A12-A0 A15-A13 5 IS25C32-2/3 IS25C64-2/3 ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.25 –1.0V to + 7.0V –40 to +85 –65 to +150 5 Unit V V °C °C mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (IS25C64-2 and IS25C32-2) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 1.8V to 5.5V 1.8V to 5.5V OPERATING RANGE (IS25C64-3 and IS25C32-3) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.5V to 5.5V 2.5V to 5.5V CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 IS25C32-2/3 IS25C64-2/3 ISSI ® DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit VOL1 Output LOW Voltage VCC = 1.8V, IOL = 0.15 mA — 0.2 V VOL2 Output LOW Voltage VCC = 2.5V, IOL = 1.0 mA — 0.4 V VOH1 Output HIGH Voltage VCC = 1.8V, IOH= -100uA VCC - 0.2 — V VOH2 Output HIGH Voltage VCC = 2.5V, IOH= -1mA VCC - 0.8 — V VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Leakage Current ILO Output Leakage Current VCC X 0.7 VCC + 0.5 –1.0 VIN = VCC max. VCC X 0.3 V V -3.0 3 µA -3.0 3 µA Min. Max. Unit POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions ICC1 Vcc Operating Current READ at 500 KHz (Vcc=5V) — 1.0 mA ICC2 Vcc Operating Current WRITE at 500 KHz (Vcc=5V) — 3.0 mA ISB1 Standby Current Vcc = 1.8V — 5 µA ISB2 Standby Current Vcc = 5.5V, VIN = VCC or GND — 10 µA Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 7 IS25C32-2/3 IS25C64-2/3 ISSI ® AC Characteristics Applicable over recommended operating range from TA= -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 1.8V Symbol Parameter f SCK Max Min Max Units SCK Clock Frequency 0 0.5 0 2.1 MHz tRI Input Rise Time — 2 — 2 µs tFI Input Fall Time — 2 — 2 µs tWH SCK High Time 800 — 200 — ns tWL SCK Low Time 800 — 200 — ns tCS CS High Time 1000 — 250 — ns tCSS CS Setup Time 1000 — 250 — ns tCSH CS Hold Time 1000 — 250 — ns tSU Data In Setup Time 100 — 50 — ns tH Data In Hold Time 100 — 50 — ns tHD Hold Setup Time 400 — 100 — ns tCD Hold Time 400 — 300 — ns tV Output Valid 0 800 0 200 ns tHO Output Hold Time 0 — 0 — ns tLZ Hold to Output Low Z 0 200 0 200 ns tHZ Hold to Output High Z — 200 — 200 ns tDIS Output Disable Time — 1000 — 250 ns Write Cycle Time — 20 — 10 ms 5.0V, 25°C, Page Mode 1M — 1M — Write Cycles tWC (1) Endurance 8 2.5V Min Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 IS25C32-2/3 IS25C64-2/3 ISSI ® TIMING DIAGRAMS Synchronous Data Timing CS tCS VIH VIL tCSH tCSS SK VIH VIL DIN VIH VIL DOUT VOH VOL tWH tSU tWL tH VALID IN tV HIGH-Z tHO tDIS HIGH-Z WREN Timing CS SK DIN WREN OP-CODE HIGH-Z DOUT WRDI Timing CS SK DIN WRDI OP-CODE DOUT Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 HIGH-Z 9 IS25C32-2/3 IS25C64-2/3 ISSI ® RDST Timing CS SK Din Instruction DATA OUT 7 6 5 4 3 2 1 0 Dout WRSR Timing CS SK Din Instruction DATA IN 7 6 5 4 3 2 1 0 Dout READ Timing CS SK Instruction Din Dout 10 BYTE Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA OUT 7 6 5 4 3 2 1 0 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 IS25C32-2/3 IS25C64-2/3 ISSI ® WRITE Timing CS SK Instruction BYTE Address Din DATA IN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Dout HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ DOUT tLZ Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02 11 IS25C32-2/3 IS25C64-2/3 ISSI ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Voltage Frequency Range Part Number Package IS25C32-2P IS25C32-2G IS25C32-2Z IS25C64-2P IS25C64-2G IS25C64-2Z 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 500 KHz 1.8V to 5.5V 500 KHz 1.8V to 5.5V 2.1 MHz 2.5V to 5.5V IS25C32-3P IS25C32-3G IS25C32-3Z 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 2.1 MHz 2.5V to 5.5V IS25C64-3P IS25C64-3G IS25C64-3Z 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP ORDERING INFORMATION Industrial Range: –40°C to +85°C Voltage Frequency Range Part Number Package 500 KHz 1.8V to 5.5V IS25C32-2PI IS25C32-2GI IS25C32-2ZI 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 500 KHz 1.8V to 5.5V IS25C64-2PI IS25C64-2GI IS25C64-2ZI 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 2.1 MHz 2.5V to 5.5V IS25C32-3PI IS25C32-3GI IS25C32-3ZI 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP 2.1 MHz 2.5V to 5.5V IS25C64-3PI IS25C64-3GI IS25C64-3ZI 300-mil Plastic DIP Small Outline (JEDEC STD) 14-pin TSSOP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/25/02