Advance Information CAT25C64/128 64K/128K-Bit SPI Serial CMOS E2PROM FEATURES ■ 1,000,000 Program/Erase Cycles ■ 5 MHz SPI Compatible ■ 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation ■ Self-Timed Write Cycle ■ Hardware and Software Protection ■ 8-Pin DIP/SOIC, 16-Pin SOIC and 20-Pin TSSOP ■ Zero Standby Current ■ 64-Byte Page Write Buffer ■ Low Power CMOS Technology ■ Block Write Protection ■ SPI Modes (0,0) – Protect 1/4, 1/2 or all of E2PROM Array ■ Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C64/128 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC and 20pin TSSOP packages. The CAT25C64/128 is a 64K/128K-Bit SPI Serial CMOS E2PROM internally organized as 8Kx8/16Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C64/ 128 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are PIN CONFIGURATION SOIC Package (S) 1 2 3 4 CS SO WP VSS 8 7 6 5 VCC HOLD SCK SI DIP Package (P) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI BLOCK DIAGRAM SOIC Package (S16) TSSOP Package (U20) 1 2 3 4 CS SO NC NC NC NC 5 6 7 8 WP VSS 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI NC CS SO SO NC NC WP VSS NC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Pin Name CS Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect © 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice WP HOLD SCK SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC CONTROL LOGIC SO SI PIN FUNCTIONS NC VCC HOLD HOLD NC NC SCK SI NC NC XDEC COLUMN DECODERS E2PROM ARRAY DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER 1 25C128 F02 Doc No. 25069-00 6/99 SPI-1 Advance Information CAT25C64/128 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Endurance Min. Max. Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current (Operating Write) 10 mA VCC = 5V @ 5MHz SO=open; CS=Vss ICC2 Power Supply Current (Operating Read) 2 mA VCC = 5.5V FCLK = 5MHz ISB Power Supply Current (Standby) 0 µA CS = VCC VIN = VSS or VCC ILI Input Leakage Current 2 µA ILO Output Leakage Current 3 µA VIL(3) Input Low Voltage -1 VCC x 0.3 V VIH(3) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage VCC - 0.8 V 0.2 VCC-0.2 VOUT = 0V to VCC, CS = 0V 4.5V≤VCC<5.5V IOL = 3.0mA IOH = -1.6mA V 1.8V≤VCC<2.7V V IOL = 150µA IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 25069-00 6/99 SPI-1 2 Advance Information CAT25C64/128 Figure 1. Sychronous Data Timing tCS VIH CS VIL tCSH tCSS VIH tWL tWH SCK VIL tH tSU VIH VALID IN SI VIL tRI tFI tV VOH SO tHO tDIS HI-Z HI-Z VOL A.C. CHARACTERISTICS Limits Vcc= 1.8V-6V VCC = 2.5V-6V Min. tSU Data Setup Time 100 70 35 ns tH Data Hold Time 100 70 35 ns tWH SCK High Time 250 150 80 ns tWL SCK Low Time 250 150 80 ns fSCK Clock Frequency DC tLZ HOLD to Output Low Z 50 tRI(1) Input Rise Time Input Fall Time tFI 1 Min. DC Max. 3 Min. DC Max. Test SYMBOL PARAMETER (1) Max. VCC = 4.5V-5.5V UNITS Conditions 5 MHz 50 50 ns 2 2 2 µs 2 2 2 µs tHD HOLD Setup Time 250 250 40 ns tCD HOLD Hold Time 250 250 40 ns tWC Write Cycle Time 10 10 5 ms tV Output Valid from Clock Low 250 220 100 ns tHO Output Hold Time tDIS Output Disable Time 250 250 100 ns tHZ HOLD to Output High Z 150 150 50 ns tCS CS High Time 1000 330 200 ns tCSS CS Setup Time 1000 100 100 ns tCSH CS Hold Time 1000 100 100 ns 0 0 0 CL = 50pF ns NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. 3 Doc No. 25069-00 6/99 SPI-1 Advance Information CAT25C64/128 FUNCTIONAL DESCRIPTION CS CS: Chip Select The CAT25C64/128 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C64/128 to interface directly with many of today’s popular microcontrollers. The CAT25C64/128 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) CS is the Chip select pin. CS low enables the CAT25C64/ 128 and CS high disables the CAT25C64/128. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The CAT25C64/128 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C64/128. Input data is latched on the rising edge of the serial clock. HOLD HOLD: Hold The HOLD pin is used to pause transmission to the CAT25C64/128 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C64/128. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 25C64/128. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. INSTRUCTION SET Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory Doc. No. 25069-00 6/99 SPI-1 4 Advance Information CAT25C64/128 STATUS REGISTER array. These bits are non-volatile. The Status Register indicates the status of the device. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. The RDY (Ready) bit indicates whether the CAT25C64/ 128 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL RDY BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 25C128: 3000-3FFF 25C64:1800-1FFF Quarter Array Protection 1 0 25C128: 2000-3FFF 25C64:1000-1FFF Half Array Protection 1 1 25C128: 0000-3FFF 25C64:1000-1FFF Full Array Protection WRITE PROTECT ENABLE OPERATION WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable 5 Doc No. 25069-00 6/99 SPI-1 Advance Information CAT25C64/128 After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address (1FFFh for 25C64 and 3FFFh for 25C128) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. DEVICE OPERATION Write Enable and Disable The CAT25C64/128 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C64/128, followed by the 16-bit address(the three Most Significant Bits are don’t care for 25C64 and two most significant bits are don't care for 25C128). Figure 2. WREN Instruction Timing CS SK SI 0 0 0 0 0 1 1 0 HIGH IMPEDANCE SO Figure 3. WRDI Instruction Timing CS SK SI SO Doc. No. 25069-00 6/99 SPI-1 0 0 0 0 0 1 0 HIGH IMPEDANCE 6 0 Advance Information CAT25C64/128 Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the three Most Significant Bits are don’t care for 25C64 and two most significant bits are don't care for 25C128), and then the data to be written. Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. WRITE Sequence The CAT25C64/128 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C64/128. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C64/128. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Figure 4. Read Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 2 1 SK OPCODE SI 0 0 0 0 0 0 1 BYTE ADDRESS* 1 DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 0 MSB *Please check the instruction set table for address Figure 5. RDSR Instruction Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE SI 0 0 0 0 0 DATA OUT SO HIGH IMPEDANCE 3 0 MSB 7 Doc No. 25069-00 6/99 SPI-1 Advance Information CAT25C64/128 restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C64/128 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Page Write The CAT25C64/128 features page write capability. Afer the first initial byte the host may continue to write up to 64 bytes of data to the CAT25C64/128. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. Figure 6. Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31 SK OPCODE SI 0 0 0 0 0 DATA IN 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS HIGH IMPEDANCE SO Figure 7. WRSR Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 1 7 MSB SO Doc. No. 25069-00 6/99 SPI-1 HIGH IMPEDANCE 8 6 5 4 3 Advance Information CAT25C64/128 DESIGN CONSIDERATIONS The CAT25C64/128 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C64/128 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. Figure 8. Page Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 SK DATA IN OPCODE SI 0 0 0 0 0 0 1 0 Data Byte 1 ADDRESS Data Byte 2 Data Byte 3 Data Byte N 0 7..1 HIGH IMPEDANCE SO Figure 9. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ ORDERING INFORMATION Prefix Device # CAT Optional Company ID Suffix 25C64 S Product Number 25C64: 64K 25C128: 128K -1.8 I Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank = 2.5 to 6.0V 1.8 = 1.8 to 6.0V Package P = PDIP S = 8-Pin SOIC S16 = 16-Pin SOIC U20 = 20-Pin TSSOP * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) 9 Doc No. 25069-00 6/99 SPI-1