ETC ISPLSI2064A

®
ispLSI 2064/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
— ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
— ispLSI 2064A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
Input Bus
Output Routing Pool (ORP)
Global Routing Pool
(GRP)
Input Bus
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
Output Routing Pool (ORP)
A0
A1
A2
Logic
Array
D Q
B1
D Q
D Q
B0
A3
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
A5
A4
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
B3
B2
D Q
GLB
B4
Input Bus
• HIGH DENSITY PROGRAMMABLE LOGIC
B5
Output Routing Pool (ORP)
B6
B7
A6
A7
Output Routing Pool (ORP)
Input Bus
Fu
Description
0139Bisp/2064
The ispLSI 2064 and 2064A are High Density Programmable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…B7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064_07
1
April 2000
Specifications ispLSI 2064/A
Functional Block Diagram
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 56
I/O 58
I/O 57
I/O 59
I/O 63
I/O 62
I/O 61
I/O 60
GOE 1
Generic Logic
Blocks (GLBs)
Input Bus
Output Routing Pool (ORP)
Megablock
B7
B1
I/O 46
I/O 45
I/O 44
Input Bus
B2
A2
B0
A3
A6
ispEN
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
I/O 28
I/O 29
I/O 30
I/O 31
I/O 18
I/O 19
I/O 16
I/O 17
Input Bus
I/O 35
I/O 34
I/O 33
I/O 32
SCLK/IN 3
A7
Output Routing Pool (ORP)
RESET
I/O 39
I/O 38
I/O 37
I/O 36
SDO/IN 2
CLK 0
CLK 1
CLK 2
A5
I/O 43
I/O 42
I/O 41
I/O 40
Y0
Y1
Y2
A4
I/O 24
I/O 25
I/O 26
I/O 27
SDI/IN 0
MODE/IN 1
Global Routing Pool
(GRP)
A1
I/O 20
I/O 21
I/O 22
I/O 23
I/O 12
I/O 13
I/O 14
I/O 15
Output Routing Pool (ORP)
I/O 9
I/O 10
I/O 11
B4
B3
A0
Input Bus
I/O 8
B5
I/O 47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
B6
Output Routing Pool (ORP)
GOE 0
Figure 1. ispLSI 2064/A Functional Block Diagram
0139B(1)isp/2064
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064 and 2064A devices are selected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each ispLSI
2064 and 2064A device contains two Megablocks.
2
Specifications ispLSI 2064/A
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +7.0V
Input Voltage Applied .............................. -2.5 to VCC +1.0V
Off-State Output Voltage Applied ........... -2.5 to VCC +1.0V
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
PARAMETER
SYMBOL
Commercial
MIN.
MAX.
UNITS
TA = 0°C to + 70°C
4.75
5.25
V
TA = -40°C to + 85°C
4.5
5.5
V
V
VCC
Supply Voltage
VIL
VIH
Input Low Voltage
0
0.8
Input High Voltage
2.0
Vcc+1
Industrial
V
Table 2 - 0005/2064
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
Dedicated Input Capacitance
8
pf
VCC = 5.0V, VIN = 2.0V
I/O Capacitance
9
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
15
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
C3
PARAMETER
TEST CONDITIONS
Table 2-0006/2064
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
Erase/Reprogram Cycles
Table 2-0008/2064
3
Specifications ispLSI 2064/A
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
≤ 3 ns
Others
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
≤ 2 ns
-125
Input Rise and Fall Time
10% to 90%
R1
Device
Output
See Figure 2
Output Load Conditions (see Figure 2)
TEST CONDITION
A
C
C L*
R2
Table 2-0003/2064
3-state levels are measured 0.5V from
steady-state active level.
B
Test
Point
*CL includes Test Fixture and Probe Capacitance.
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Table 2-0004/2064
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
ICC2, 4
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
µA
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
VIL = 0.0V, VIH = 3.0V
Commercial
–
95
175
mA
fCLOCK = 1 MHz
Industrial
–
95
–
mA
Operating Power Supply Current
Table 2-0007/2064
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .
4
Specifications ispLSI 2064/A
External Timing Parameters
Over Recommended Operating Conditions
4
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
TEST
#2
COND.
-125
DESCRIPTION 1
-80
-100
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
–
15.0
ns
A
2
Data Propagation Delay
–
10.0
–
13.0
–
18.5
ns
3
A
3
Clock Frequency with Internal Feedback
125
–
100
–
81.0
–
MHz
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
100
–
77.0
–
57.0
–
MHz
–
5
Clock Frequency, Max. Toggle
125
–
111
–
100
–
MHz
1
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
5.0
–
6.5
–
9.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.0
–
5.0
–
6.5
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
6.0
–
8.0
–
11.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
4.5
–
6.0
–
8.0
ns
0.0
–
0.0
–
0.0
–
ns
–
10.0
–
13.5
–
17.0
ns
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
5.0
–
6.5
–
10.0
–
ns
B
14 Product Term OE, Enable
–
12.0
–
15.0
–
18.0
ns
C
15 Product Term OE, Disable
–
12.0
–
15.0
–
18.0
ns
B
16 Global OE, Enable
–
7.0
–
9.0
–
12.0
ns
C
17 Global OE, Disable
–
7.0
–
9.0
–
12.0
ns
–
18 External Synchronous Clock Pulse Duration, High
4.0
–
4.5
–
5.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
4.0
–
4.5
–
5.0
–
ns
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2 - 0030B/2064-130
Specifications ispLSI 2064/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#
2
-125
DESCRIPTION
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tio
tdin
GRP
tgrp
GLB
t4ptbp
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
20
Input Buffer Delay
–
0.2
–
0.5
–
1.8
ns
21
Dedicated Input Delay
–
1.5
–
2.2
–
4.4
ns
22
GRP Delay
–
1.3
–
1.7
–
2.6
ns
23
4 Product Term Bypass Comb. Path Delay
–
4.5
–
5.8
–
8.1
ns
24
4 Product Term Bypass Reg. Path Delay
–
5.0
–
5.8
–
6.8
ns
25
1 Product Term/XOR Path Delay
–
5.7
–
6.8
–
8.0
ns
26
20 Product Term/XOR Path Delay
–
6.0
–
7.3
–
8.8
ns
–
6.5
–
8.0
–
9.8
ns
–
0.5
–
0.5
–
1.3
ns
Delay3
27
XOR Adjacent Path
28
GLB Register Bypass Delay
29
GLB Register Setup Time before Clock
0.8
–
1.2
–
1.4
–
ns
30
GLB Register Hold Time after Clock
3.0
–
4.0
–
6.0
–
ns
31
GLB Register Clock to Output Delay
–
0.2
–
0.3
–
0.4
ns
32
GLB Register Reset to Output Delay
–
1.1
–
1.3
–
1.6
ns
33
GLB Product Term Reset to Register Delay
–
4.8
–
6.1
–
8.6
ns
34
GLB Product Term Output Enable to I/O Cell Delay
–
7.3
–
8.6
–
9.0
ns
35
GLB Product Term Clock Delay
3.3
5.6
4.1
7.1
5.6
10.2
ns
36
ORP Delay
–
0.8
–
1.4
–
2.0
ns
ORP Bypass Delay
–
0.3
–
0.4
–
0.5
ns
Output Buffer Delay
–
1.2
–
1.6
–
2.0
ns
Output Slew Limited Delay Adder
–
10.0
–
10.0
–
10.0
ns
I/O Cell OE to Output Enabled
–
3.2
–
4.2
–
4.6
ns
I/O Cell OE to Output Disabled
–
3.2
–
4.2
–
4.6
ns
Global Output Enable
–
3.8
–
4.8
–
7.4
ns
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
2.3
2.7
2.7
3.6
3.6
ns
Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
2.7
2.7
3.6
3.6
ns
–
6.9
–
9.2
–
11.4
ns
37
torpbp
Outputs
38
tob
39
tsl
40
toen
41
todis
42
tgoe
Clocks
tgy0
43
tgy1/2
44
Global Reset
45
tgr
Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2- 0036C/2064-130
Specifications ispLSI 2064/A
ispLSI 2064/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
#25, 26, 27
Q
#38,
39
#36
RST
#45
Reset
#29, 30,
31, 32
Control RE
PTs
OE
#33, 34, CK
35
#40, 41
#43, 44
Y0,1,2
#42
GOE 0,1
0491/2064
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
3.5 ns =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
th
=
=
=
2.6 ns =
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
tco
=
=
=
9.4 ns =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
Table 2- 0042A-2064
Note: Calculations are based upon timing specifications for the ispLSI 2064/A-125L.
7
I/O Pin
(Output)
Specifications ispLSI 2064/A
Power Consumption
used. Figure 4 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2064 and 2064A devices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
Figure 4. Typical Device Power Consumption vs fmax
160
ispLSI 2064/A
150
140
130
ICC (mA)
120
110
100
90
80
70
1
20
40
60
80
100 120 140
fmax (MHz)
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 25° C
ICC can be estimated for the ispLSI 2064/A using the following equation:
ICC(mA) = 38 + (# of PTs * 0.33) + (# of nets * Max freq * 0.007)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127A/2064A
8
Specifications ispLSI 2064/A
Pin Description
NAME
PLCC PIN NUMBERS
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
GOE 0, GOE 1
67,
84
Y0, Y1, Y2
20,
66,
RESET
24
Active Low (0) Reset pin which resets all registers in the device.
ispEN
23
Input — Dedicated in-system programming enable pin. This pin is brought low to
enable the programming mode. When low, the MODE, SDI, SDO and SCLK
controls become active.
SDI/ IN 02
25
Input — This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 also is used
as one of the two control pins for the ISP state machine. When ispEN is high, it
functions as a dedicated pin input.
MODE/ IN 12
42
Input — This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the ISP state machine. When ispEN is high,
it functions as a dedicated input pin.
SDO/IN 22
44
Output/Input — This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. When ispEN is high,
it functions as a dedicated input pin.
SCLK/IN 32
61
Input — This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. When ispEN is high, it functions as
a dedicated input pin.
GND
1,
VCC
21,
65
NC1
2,
19,
22,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
DESCRIPTION
Input/Output Pins — These are the general purpose I/O pins used by the logic
array.
Global Output Enable input pins.
63
43,
Dedicated Clock input. This clock input is connected to one of the clock inputs of
all the GLBs in the device.
64
Ground (GND)
Vcc
62
No Connect
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
9
Table 2-0002A-08isp/2064
Specifications ispLSI 2064/A
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
GOE 0, GOE 1
DESCRIPTION
TQFP PIN NUMBERS
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
66,
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
87
Y0, Y1, Y2
11,
65,
RESET
15
ispEN
14
SDI/IN 02
16
MODE/IN 12
37
SDO/IN 22
39
SCLK/IN 32
60
GND
13,
38,
VCC
12,
64
NC1
1,
25,
50,
74,
89,
2,
26,
51,
75,
99,
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
62
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK controls become active.
Input – This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the ISP state machine.
When ispEN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
63,
88
Ground (GND)
VCC
10,
27,
52,
76,
100
24,
49,
61,
77,
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
10
Table 2-0002-2064b.eps
Specifications ispLSI 2064/A
Pin Configuration
I/O 41
I/O 40
I/O 39
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
GOE 1
I/O 48
NC1
GND
I/O 52
I/O 51
I/O 50
I/O 49
I/O 53
I/O 55
I/O 54
I/O 56
ispLSI 2064/A 84-Pin PLCC Pinout Diagram
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
I/O 57
12
74
I/O 38
I/O 58
I/O 59
13
73
14
72
I/O 37
I/O 36
I/O 60
15
71
I/O 35
I/O 61
16
70
I/O 34
I/O 62
I/O 63
17
69
I/O 33
18
68
1NC
19
67
I/O 32
GOE 0
Y0
VCC
GND
20
66
21
65
ispEN
RESET
23
22
ispLSI 2064/A
64
Y1
VCC
GND
Top View
63
Y2
62
0
25
61
NC1
SCLK/IN 32
I/O 0
I/O 1
26
60
I/O 31
27
59
I/O 30
I/O 2
28
58
I/O 29
I/O 3
29
57
I/O 28
I/O 4
I/O 5
I/O 6
30
56
I/O 27
31
55
32
54
I/O 26
I/O 25
I/O 24
I/O 23
I/O 21
I/O 22
I/O 19
I/O 20
I/O 17
I/O 18
I/O 16
2
GND
2SDO/IN
1
I/O 15
2MODE/IN
I/O 12
I/O 13
I/O 14
I/O 11
I/O 10
I/O 9
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O 7
I/O 8
2SDI/IN
24
0123A/2064
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
11
Specifications ispLSI 2064/A
Pin Configuration
1NC
1NC
ispLSI 2064/A
Top View
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC1
NC1
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0
Y1
VCC
GND
Y2
NC1
SCLK/IN 32
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
NC1
NC1
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
2MODE/IN 1
GND
2SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1NC
1NC
1NC
1NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
VCC
GND
ispEN
RESET
2SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
1NC
1NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC1
NC1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
NC1
GND
GOE 1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
NC1
NC1
ispLSI 2064/A 100-Pin TQFP Pinout Diagram
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
12
0766A-2064-isp
Specifications ispLSI 2064/A
Part Number Description
ispLSI XXXXX – XXX X
X
X
Device Family
2064
2064A
Grade
Blank = Commercial
I = Industrial
Package
J = PLCC
T = TQFP
Power
L = Low
Device Number
Speed
125 = 125 MHz fmax
100 = 100 MHz fmax
80 = 81 MHz fmax
0212/2064/A
ispLSI 2064/A Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
125
7.5
ispLSI 2064A-125LJ84
84-Pin PLCC
125
7.5
ispLSI 2064A-125LT100
100-Pin TQFP
100
10
ispLSI 2064A-100LJ84
84-Pin PLCC
100
10
ispLSI 2064A-100LT100
100-Pin TQFP
81
15
ispLSI 2064A-80LJ84
84-Pin PLCC
81
15
ispLSI 2064A-80LT100
100-Pin TQFP
125
7.5
ispLSI 2064-125LJ
84-Pin PLCC
125
7.5
ispLSI 2064-125LT
100-Pin TQFP
100
10
ispLSI 2064-100LJ
84-Pin PLCC
100
10
ispLSI 2064-100LT
100-Pin TQFP
81
15
ispLSI 2064-80LJ
84-Pin PLCC
15
ispLSI 2064-80LT
100-Pin TQFP
81
Table 2-0041A/2064A
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
81
15
ispLSI 2064A-80LJ84I
84-Pin PLCC
81
15
ispLSI 2064A-80LT100I
100-Pin TQFP
81
15
ispLSI 2064-80LJI
84-Pin PLCC
81
15
ispLSI 2064-80LTI
100-Pin TQFP
ORDERING NUMBER
PACKAGE
Table 2-0041B/2064A
13