® ispLSI 2032V 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • 3.3V LOW VOLTAGE 2032 ARCHITECTURE N • IN-SYSTEM PROGRAMMABLE D Q A5 Input Bus D Q A4 0139Bisp/2000 R — 3.3V In-System Programmability Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality Logic Array A6 D Q A3 Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture GLB D A2 D Q A7 Output Routing Pool (ORP) A1 EW Input Bus fmax = 100 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay Output Routing Pool (ORP) • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — Global Routing Pool (GRP) A0 — Interfaces With Standard 5V TTL Devices — 60 mA Typical Active Current — Fuse Map Compatible with 5V ispLSI 2032 ES IG N S — — — — — FO Description VE The ispLSI 2032V is a High Density Programmable Logic Device that can be used in both 3.3V and 5V systems. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2032V offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. SI 20 Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity The basic unit of logic on the ispLSI 2032V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. pL — — — — — — 32 • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs U SE is • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 2032v_10 1 September 2000 Specifications ispLSI 2032V Functional Block Diagram Figure 1. ispLSI 2032V Functional Block Diagram A2 A5 I/O 27 I/O 26 I/O 25 I/O 24 D A6 Input Bus Global Routing Pool (GRP) A1 EW I/O 12 I/O 13 I/O 14 I/O 15 I/O 31 I/O 30 I/O 29 I/O 28 A7 A3 A4 I/O 19 I/O 18 I/O 17 I/O 16 N TDI/IN 0 TDO/IN 1 I/O 23 I/O 22 I/O 21 I/O 20 Generic Logic Blocks (GLBs) TMS/NC FO Note: *Y1 and RESET are multiplexed on the same pin R ispEN The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5 Volt signal levels to support mixed-voltage systems. CLK 0 CLK 1 CLK 2 I/O 9 I/O 10 I/O 11 Input Bus I/O 8 Output Routing Pool (ORP) I/O 4 I/O 5 I/O 6 I/O 7 A0 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 ES IG N S GOE 0 Y0 Y1* TCK/Y2 0139B/2032V VE basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs SI 20 32 In addition to the standard output configuration, the outputs of the ispLSI 2032V are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC “1”), the output is configured as a totem-pole output. When this fuse is programmed (JEDEC “0”), the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools. is pL Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032V device contains one Megablock. U SE The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2032V device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB 2 Specifications ispLSI 2032V Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +5.6V Input Voltage Applied ............................... -0.5 to +5.6V S Off-State Output Voltage Applied ............ -0.5 to +5.6V ES IG N Storage Temperature .............................. -65 to +150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C EW D 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL VIL VIH Input Low Voltage Capacitance (TA=25°C, f=1.0 MHz) UNITS 3.0 3.6 V Industrial TA = -40°C to + 85°C 3.0 3.6 V 0.8 V 5.25 V VSS – 0.5 2.0 Table 2 - 0005/2032LV TYPICAL UNITS Dedicated Input Capacitance 8 pf VCC = 3.3V, VIN = 2.0V I/O Capacitance 8 pf VCC = 3.3V, VI/O = 2.0V 13 pf VCC = 3.3V, VY = 2.0V PARAMETER 20 32 SYMBOL C1 C2 C3 MAX. TA = 0°C to + 70°C VE Input High Voltage MIN. Commercial R Supply Voltage FO VCC N PARAMETER Clock and Global Output Enable Capacitance TEST CONDITIONS pL SI Table 2-0006/2032LV is Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – SE Data Retention ispLSI Erase/Reprogram Cycles Cycles U Table 2-0008A-2032-isp 3 Specifications ispLSI 2032V Switching Test Conditions GND to 3.0V Figure 2. Test Load ≤ 1.5 ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 3.3V R1 Device Output See Figure 2 Table 2-0003/2032V/LV 3-state levels are measured 0.5V from steady-state active level. S Input Rise and Fall Time 10% to 90% ES IG N Input Pulse Levels Test Point C L* R2 D Output Load Conditions (see figure 2) 316Ω 348Ω 35pF Active High ∞ 348Ω 35pF Active Low 316Ω 348Ω 35pF Active High to Z at VOH -0.5V ∞ 348Ω 5pF Active Low to Z at VOL +0.5V 316Ω 348Ω 5pF 0213A R C CL FO B R2 EW A *CL includes Test Fixture and Probe Capacitance. R1 N TEST CONDITION DC Electrical Characteristics VE Table 2 - 0004A SYMBOL 20 Output High Voltage CONDITION 3 MIN. TYP. MAX. UNITS IOL= 8 mA – – 0.4 V IOH = -4 mA 2.4 – – V 0V ≤ VIN ≤ VIL (Max.) – – -10 µA (VCC - 0.2)V ≤ VIN ≤ VCC – – 10 µA VCC ≤ VIN ≤ 5.25V – – 50 mA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 3.3V, VOUT = 0.5V – – -100 mA Operating Power Supply Current VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz – 60 – mA SI Input or I/O Low Leakage Current pL Input or I/O High Leakage Current SE IIL-isp IIL-PU IOS1 ICC2, 4 Output Low Voltage is VOL VOH IIL IIH PARAMETER 32 Over Recommended Operating Conditions Table 2-0007/2032V U 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using two 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25°C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 4 Specifications ispLSI 2032V External Timing Parameters Over Recommended Operating Conditions 4 -80 -100 1 -60 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 A 2 Data Propagation Delay – 12.0 – 15.0 – 20.0 100 – 80.0 – 61.7 – MHz 3 Clock Frequency with Internal Feedback 1 tsu2 + tco1 ns 4 Clock Frequency with External Feedback ( 83.3 – 64.5 – 51.3 – MHz – 5 Clock Frequency, Max. Toggle 125 – 100 – 71.4 – MHz – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.5 – 7.0 – 9.0 – ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 5.0 – 6.5 – 8.5 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 7.0 – 9.0 – 11.0 – ns – 10 GLB Reg. Clock to Output Delay – 6.5 – 7.5 – 9.5 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration 15 Input to Output Disable EW – 12.0 – 14.0 – 16.0 ns 5.0 – 7.0 – 8.0 – ns – 13.0 – 15.0 – 18.0 ns – 13.0 – 15.0 – 18.0 ns – 7.5 – 10.0 – 12.0 ns – 7.5 – 10.0 – 12.0 ns 4.0 – 5.0 – 7.0 – ns 4.0 – 5.0 – 7.0 – ns N 14 Input to Output Enable R B D – C ) ES IG N A 3 ns S A B 16 Global OE Output Enable C 17 Global OE Output Disable – 18 External Synchronous Clock Pulse Duration, High – 19 External Synchronous Clock Pulse Duration, Low 32 Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. U SE is pL SI 20 1. 2. 3. 4. DESCRIPTION FO tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl TEST 2 # COND. VE PARAMETER 5 Table 2-0030/2032V Specifications ispLSI 2032V Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 -80 -100 DESCRIPTION -60 MIN. MAX. MIN. MAX. MIN. MAX. UNITS – 0.2 – 0.4 – 0.6 ns 21 Dedicated Input Delay – 0.6 – 1.3 – 1.4 ns 22 GRP Delay – 0.7 – 1.2 – 2.1 ns 23 4 Product Term Bypass Path Delay (Combinatorial) – 4.6 – 5.8 – 9.6 ns 24 4 Product Term Bypass Path Delay (Registered) – 6.0 – 7.5 – 10.3 ns 25 1 Product Term/XOR Path Delay – 6.7 – 9.2 – 12.3 ns 26 20 Product Term/XOR Path Delay – 7.5 – 9.5 – 12.3 ns – 8.5 – 11.3 – 14.4 ns – 0.3 – 0.3 – 1.3 ns 0.1 – 0.2 – 0.2 – ns 3.8 – 5.4 – 8.0 – ns – 1.5 – 1.6 – 1.6 ns – 2.2 – 2.5 – 2.8 ns 33 GLB Product Term Reset to Register Delay – 3.8 – 5.6 – 9.3 ns 34 GLB Product Term Output Enable to I/O Cell Delay – 7.2 – 8.5 – 10.4 ns 3.0 4.4 3.8 5.6 6.5 9.3 ns – 1.4 – 1.4 – 1.5 ns – 0.1 – 0.4 – 0.5 ns 38 Output Buffer Delay – 1.9 – 2.2 – 2.2 ns 39 Output Slew Limited Delay Adder – 11.9 – 12.2 – 12.2 ns 40 I/O Cell OE to Output Enabled – ES IG N 20 Input Buffer Delay D tio tdin GRP tgrp 27 XOR Adjacent Path Delay N 29 GLB Register Setup Time befor Clock R 30 GLB Register Hold Time after Clock VE 32 GLB Register Reset to Output Delay FO 31 GLB Register Clock to Output Delay 35 GLB Product Term Clock Delay 36 ORP Delay 20 37 ORP Bypass Delay 32 torp torpbp Outputs SI tob tsl toen todis tgoe – 4.9 – 4.9 ns – 4.9 – 4.9 – 4.9 ns 42 Global Output Enable – 2.6 – 5.1 – 7.1 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.5 1.5 2.3 2.3 4.2 4.2 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.5 1.5 2.3 2.3 4.2 4.2 ns – 6.5 – 7.9 – 9.5 ns pL 4.9 41 I/O Cell OE to Output Disabled is SE tgy0 tgy1/2 3 28 GLB Register Bypass Delay ORP Clocks EW GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck S Inputs U Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 6 Table 2-0036/2032V Specifications ispLSI 2032V ispLSI 2032V Timing Model I/O Cell GRP GLB ORP I/O Cell Ded. In Comb 4 PT Bypass #23 #21 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 20 PT XOR Delays GLB Reg Delay D #25, 26, 27 ES IG N I/O Pin (Input) S Feedback ORP Delay Q #36 RST #45 #29, 30, 31, 32 D Reset #38, 39 EW Control RE PTs OE #33, 34, CK 35 Y0,1,2 N #43, 44 #42 R GOE 0 = = = = Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9) VE Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5) pL 10.1 ns = = = = 32 0.7 ns tco Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0) 20 4.6 ns th = = = = SI tsu 1 FO Derivations of tsu, th and tco from the Product Term Clock Note: Calculations are based on timing specifications for the ispLSI 2032V-100. U SE is Table 2-0042/2032V 7 #40, 41 0491/2032 I/O Pin (Output) Specifications ispLSI 2032V Power Consumption 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 2032V device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure S Figure 3. Typical Device Power Consumption vs fmax ES IG N 100 90 ispLSI 2032V-100/-80/-60 70 D ICC (mA) 80 60 EW 50 0 40 20 60 80 100 R fmax (MHz) N 40 FO Notes: Configuration of two 16-bit counters Typical current at 3.3V, 25° C ICC can be estimated for the ispLSI 2032V using the following equation: VE ICC(mA) = 15 + (# of PTs * 0.78) + (# of nets * Max freq * 0.004) 20 32 Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) SI The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. pL 0127A/2032V Power-up Considerations When Lattice 3.3V 2000V devices are used in mixed 5V/ 3.3V applications, some consideration needs to be given to the power-up sequence. When the I/O pins on the 3.3V ispLSI devices are driven directly by 5V devices, a low impedance path can exist on the 3.3V device between its I/O and Vcc pins when the 3.3V supply is not present. This low impedance path can cause current to flow from the 5V device into the 3.3V ispLSI device. The maximum current occurs when the signals on the I/O pins are driven high by the 5V devices. If a large enough current flows through the 3.3V I/O pins, latch-up can occur and permanent device damage may result. SE is This latch-up condition occurs only during the power-up sequence when the 5V supply comes up before the 3.3V supply. The Lattice 3.3V ispLSI devices are guaranteed to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V. U The recommended power-up options are as follows: Option 1: Ensure that the 3.3V supply is powered-up and stable before the 5V supply is powered up. Option 2: Ensure that the 5V device outputs are driven to a high impedance or logic low state during power-up. 8 Specifications ispLSI 2032V Pin Description NAME PLCC PIN NUMBERS 18, 22, 28, 32, 40, 44, 6, 10 GOE 0 2 Global Output Enable input pin. Y0 11 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. RESET/Y1 35 This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. ispEN 13 Input — Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 14 Input — This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin. TMS/NC1 36 Input — When in ISP Mode, controls operation of ISP state-machine. TDO/IN 1 24 Output/Input — This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. TCK/Y2 33 Input — This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated clock input.This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. GND 1, 23 VCC 12, 34 S 15, 19, 25, 29, 37, 41, 3, 7, ES IG N 17, 21, 27, 31, 39, 43, 5, 9, Input/Output Pins — These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 VE FO R N EW D 16, 20, 26, 30, 38, 42, 4, 8, DESCRIPTION 32 Ground (GND) 20 VCC U SE is pL SI 1. NC pins are not to be connected to any active signals, VCC or GND. 9 Table 2-0002A/2032V Specifications ispLSI 2032V Pin Description NAME TQFP PIN NUMBERS 12, 16, 22, 26, 34, 38, 44, 4 GOE 0 40 Global Output Enable input pin. Y0 5 RESET/Y1 29 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. ispEN 7 Input — Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 8 Input — This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin. TMS/NC1 30 Input — When in ISP Mode, controls operation of ISP state-machine. TDO/IN 1 18 Output/Input — This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. TCK/Y2 27 Input — This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register.It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. GND 17, 39 VCC 6, 28 S 9, 13, 19, 23, 31, 35, 41, 1, ES IG N 11, 15, 21, 25, 33, 37, 43, 3, Input/Output Pins — These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 VE FO R N EW D 10, 14, 20, 24, 32, 36, 42, 2, DESCRIPTION 32 Ground (GND) VCC U SE is pL SI 20 1. NC pins are not to be connected to any active signals, VCC or GND. 10 Table 2-0002B/2032V Specifications ispLSI 2032V Pin Configuration I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 GOE 0 I/O 24 I/O 26 I/O 25 I/O 27 ispLSI 2032V 44-Pin PLCC Pinout Diagram I/O 28 7 39 I/O 18 I/O 29 8 I/O 30 9 38 37 I/O 17 I/O 16 I/O 31 10 11 36 TMS/NC1 RESET/Y1 VCC Y0 VCC 12 ispLSI 2032V 35 34 Top View 13 33 TCK/Y2 14 32 I/O 15 I/O 0 15 16 31 30 I/O 14 17 29 N R I/O 9 I/O 10 I/O 11 I/O 8 TDO/IN 1 0123/2032V FO GND I/O 7 I/O 6 I/O 4 I/O 5 I/O 3 18 19 20 21 22 23 24 25 26 27 28 I/O 13 I/O 12 EW I/O 1 I/O 2 D ispEN TDI/IN 0 1. NC pins are not to be connected to any active signals, VCC or GND. VE Pin Configuration I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 GOE 0 I/O 24 I/O 26 I/O 25 20 I/O 27 32 ispLSI 2032V 44-Pin TQFP Pinout Diagram 44 43 42 41 40 39 38 37 36 35 34 SI I/O 28 I/O 31 Y0 VCC 1 2 33 I/O 18 32 31 I/O 17 I/O 16 30 TMS/NC1 ispLSI 2032V 29 28 RESET/Y1 VCC Top View 3 4 5 6 ispEN 7 27 TCK/Y2 TDI/IN 0 8 26 I/O 15 9 10 11 25 24 23 I/O 14 I/O 13 I/O 12 I/O 0 I/O 1 I/O 2 I/O 9 I/O 10 I/O 11 I/O 8 GND TDO/IN 1 I/O 7 I/O 6 I/O 4 I/O 5 12 13 14 15 16 17 18 19 20 21 22 I/O 3 U SE is pL I/O 29 I/O 30 0851/2032V/LV 1. NC pins are not to be connected to any active signals, VCC or GND. 11 ES IG N S 6 5 4 3 2 1 44 43 42 41 40 Specifications ispLSI 2032V Part Number Description ispLSI XXXXX – XX X XXX X Device Family Device Number 2032V ES IG N Package J = PLCC J44 = PLCC T44 = TQFP S Grade Blank = Commercial I = Industrial Speed 100 = 100 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax ispLSI 2032V Ordering Information ispLSI ORDERING NUMBER PACKAGE 7.5 ispLSI 2032V-100LJ44 44-Pin PLCC 100 7.5 80 80 10 10 ispLSI 2032V-100LT44 ispLSI 2032V-80LJ44 44-Pin TQFP 44-Pin PLCC ispLSI 2032V-80LT44 44-Pin TQFP 60 15 60 15 ispLSI 2032V-60LJ44 ispLSI 2032V-60LT44 44-Pin PLCC 44-Pin TQFP FO VE fmax (MHz) tpd (ns) 60 Table 2-0041A/2032V INDUSTRIAL ORDERING NUMBER PACKAGE 15 ispLSI 2032V-60LJ44I 44-Pin PLCC 15 ispLSI 2032V-60LT44I 44-Pin TQFP Table 2-0041B/2032V U SE is pL SI 60 R tpd (ns) 100 32 FAMILY fmax (MHz) 20 ispLSI N COMMERCIAL FAMILY 0212/2032V EW D Power L = Low 12