Touch Screen Controller AD7877 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC 7 AD7877 X+ 12 X– 10 Y+ 13 Y– 11 X– Y– GND X+ Y+ VREF DUAL 3-1 MUX AUX1/GPIO1 6 AUX2/GPIO2 5 REF– AUX3/GPIO3 4 BAT1 3 BATTERY MONITOR BAT2 2 REF+ CLOCK 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD STOP ACQ LOGIC 20 STOPACQ 14 AGND 15 DGND 22 ALERT 21 GPIO4 17 PENIRQ RESULTS REGISTERS BATTERY MONITOR LIMIT COMPARATOR LIMIT REGISTERS TEMPERATURE SENSOR VREF 31 ALERT STATUS/ MASK REGISTER AOUT 30 ARNG 29 BUF GPIO REGISTERS CONTROL REGISTERS DAC REGISTER 8-BIT DAC CONTROL LOGIC AND SERIAL PORT 18 19 CS DIN 23 ALERT LOGIC 26 DAV DCLK 27 28 DOUT VDRIVE TO GPIO1-3 PEN INTERRUPT AND WAKE-UP ON TOUCH Figure 1. GENERAL DESCRIPTION The AD7877 is a 12-bit successive approximation ADC with a synchronous serial interface and low on resistance switches for driving touch screens. The AD7877 operates from a single 2.7 V to 5.25 V power supply (functional operation to 2.2V), and features throughput rates of 125 kSPS. The AD7877 features direct battery measurement on two inputs, temperature and touch-pressure measurement. The AD7877 also has an on-board reference of 2.5 V. When not in use, it can be shut down to conserve power. An external reference can also be applied and can be varied from 1 V to +VCC, while the analog input range is from 0 V to VREF. The device includes a shutdown mode, which reduces its current consumption to less than 1 µA. To reduce the effects of noise from LCDs, the acquisition phase of the on-board ADC can be controlled via the STOPACQ pin. User-programmable conversion controls include variable acquisition time and first conversion delay. Up to 16 averages can be taken per conversion. There is also an on-board DAC for LCD backlight or contrast control. The AD7877 can run in either slave or master mode, using a conversion sequencer and timer. It is ideal for battery-powered systems such as personal digital assistants with resistive touch screens and other portable equipment. The part is available in a 32-lead lead frame chip scale package (LFCSP). Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03796-001 Personal digital assistants Smart hand-held devices Touch screen monitors Point-of-sale terminals Medical devices Cell phones Pagers IN SEQUENCER 2.5V REF APPLICATIONS 9 TO 1 I/P MUX ADC DATA 4-wire touch screen interface LCD noise reduction feature (STOPACQ pin) Automatic conversion sequencer and timer User-programmable conversion parameters On-chip temperature sensor: −40°C to +85°C On-chip 2.5 V reference On-chip 8-bit DAC 3 auxiliary analog inputs 1 dedicated and 3 optional GPIOs 2 direct battery measurement channels (0.5 V to 5 V) 3 interrupt outputs Touch-pressure measurement Wake up on touch function Specified throughput rate of 125 kSPS Single supply, VCC of 2.7 V to 5.25 V Separate VDRIVE level for serial interface Shutdown mode: 1 µA maximum 32-lead LFCSP 5 mm x 5 mm package AD7877 TABLE OF CONTENTS Specifications..................................................................................... 3 Sequencer Registers ................................................................... 22 Timing Specifications....................................................................... 5 Interrupts..................................................................................... 24 Absolute Maximum Ratings............................................................ 6 Syncronizing the AD7877 to the Host CPU ........................... 25 ESD Caution.................................................................................. 6 8-Bit DAC ........................................................................................ 26 Pin Configuration and Function Descriptions............................. 7 Serial Interface ................................................................................ 28 Terminology ...................................................................................... 9 Writing Data ............................................................................... 28 Typical Performance Characteristics ........................................... 10 Write Timing............................................................................... 29 Circuit Information ........................................................................ 14 Reading Data............................................................................... 29 Touch Screen Principles ............................................................ 14 VDRIVE Pin..................................................................................... 29 Measuring Touch Screen Inputs ............................................... 15 General-Purpose I/O Pins............................................................. 30 Touch-Pressure Measurement .................................................. 16 GPIO Configuration .................................................................. 30 STOPACQ Pin ............................................................................ 16 Grounding and LayouT ................................................................. 32 Temperature Measurement ....................................................... 17 PCB Design Guidelines for Chip Scale Packages................... 32 Battery Measurement................................................................. 18 Register Maps.................................................................................. 33 Auxiliary Inputs .......................................................................... 19 Detailed Register Descriptions ..................................................... 35 Limit Comparison ...................................................................... 19 GPIO Registers ........................................................................... 41 Control Registers ............................................................................ 20 Outline Dimensions ....................................................................... 43 Control Register 1....................................................................... 20 Ordering Guide .......................................................................... 43 Control Register 2....................................................................... 21 REVISION HISTORY 11/04—Changed from Rev. 0 to Rev. A Changes to Absolute Maximum Ratings ...................................... 6 Changes to Figure 4.......................................................................... 7 Changes to Table 4............................................................................ 7 Changes to Grounding and Layout section ................................ 32 Changes to Figure 42...................................................................... 32 Changes to Ordering Guide .......................................................... 43 7/04—Revision 0: Initial Version Rev. A | Page 2 of 44 AD7877 SPECIFICATIONS VCC = 2.7 V to 3.6 V, VREF = 2.5 V internal or external, fDCLK = 2 MHz, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter ADC DC ACCURACY Resolution No Missing Codes Integral Nonlinearity1 Differential Nonlinearity1 Offset Error1 Gain Error1 Noise Power Supply Rejection Internal Clock Ffrequency SWITCH DRIVERS On Resistance1 Y+, X+ Y−, X− ANALOG INPUTS Input Voltage Ranges DC Leakage Current Input Capacitance Accuracy REFERENCE INPUT/OUTPUT Internal Reference Voltage Internal Reference Tempco VREF Input Voltage Range DC Leakage Current VREF Input Impedance TEMPERATURE MEASUREMENT Temperature Range Resolution Differential Method2 Single Conversion Method3 Accuracy Differential Method2 Single Conversion Method3 BATTERY MONITOR Input Voltage Range Input Impedance Accuracy Min Typ 12 11 12 Max Unit 70 70 2 Bits Bits LSB LSB LSB LSB µV rms dB MHz 14 14 Ω Ω ±2 0 ±2 −0.99/+2 ±6 ±4 VREF ±0.1 30 0.3 2.44 2.55 ±50 1 VCC ±1 1 −40 +85 V µA pF % V ppm/°C V µA GΩ Test Conditions/Comments LSB size = 610 µV LSB size = 610 µV VCC = 2.7 V External reference All channels, internal VREF CS = GND or VCC; typically 25 Ω when on-board reference enabled °C 1.6 0.3 °C °C ±4 ±2 °C °C Calibrated at 25°C V kΩ % @VREF = 2.5 V Sampling, 1 GΩ when battery monitor off External/internal reference, see Figure 25 0.5 5 14 1 3.2 Rev. A | Page 3 of 44 AD7877 Parameter DAC Resolution Integral Nonlinearity Differential Nonlinearity Voltage Mode Output Voltage Range Slew Rate Output Settling Time Capacitive Load Stability Output Impedance Short Circuit Current Current Mode Output Current Range Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Throughput Rate POWER REQUIREMENTS VCC (Specified Performance) VDRIVE ICC Converting Mode Static Shutdown Mode Min Typ Max Unit Test Conditions/Comments 8 ±1 ±1 Bits Bits 0 − VCC/2 0 − VCC −0.4, +0.5 12 50 75 21 V V V/µs µs pF kΩ mA DAC register Bit 2 = 0, Bit 0 = 0 DAC register Bit 2 = 0, Bit 0 = 1 µA DAC register Bit 2 = 1, full-scale current is set by RRNG Power-down mode 0 Guaranteed monotonic by design 15 100 1000 Open 0.7 VDRIVE 0.3 VDRIVE ±1 10 V V µA pF 0.4 ±10 10 V V µA pF VDRIVE − 0.2 0 to 3/4 scale, RLOAD = 10 kΩ, CLOAD = 50 pF RLOAD = 10 kΩ Power-down mode Typically 10 nA, VIN = 0 V or VCC ISOURCE = 250 µA, VCC/VDRIVE = 2.7 V to 5.25 V ISINK = 250 µA Straight (natural) binary 8 125 2.7 1.65 240 650 900 150 µs kSPS CS high to DAV low 3.6 VCC V V Functional from 2.2 V to 5.25 V 380 900 µA µA µA µA 1 µA 1 See the Terminology section. Difference between Temp0 and Temp1 measurement. No calibration necessary. Temperature drift is −2.1 mV/°C. 4 Sample tested @ 25°C to ensure compliance. 2 3 Rev. A | Page 4 of 44 Digital I/Ps = 0 V or VCC ADC on, internal reference off, VCC = 3.6 V ADC on, internal reference on, VCC = 3.6 V ADC on, internal reference on, DAC on ADC on, but not converting, internal reference off, VCC = 3.6 V AD7877 TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 2. Parameter fDCLK1 t1 t2 t3 t4 t5 t62 t72 t83 t9 Limit at TMIN, TMAX 10 20 16 20 20 12 12 16 16 16 0 Unit kHz min MHz max ns min ns min ns min ns min ns min ns max ns max ns max ns min Description CS falling edge to first DCLK rising edge DCLK high pulse width DCLK low pulse width DIN setup time DIN hold time CS falling edge to DOUT, three-state disabled DCLK falling edge to DOUT valid CS rising edge to DOUT high impedance CS rising edge to DCLK ignored 1 Mark/space ratio for the DCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 2 CS t1 t2 1 DCLK 2 t9 t3 3 15 16 t5 t4 MSB t7 t6 DOUT LSB MSB t8 LSB Figure 2. Detailed Timing Diagram Rev. A | Page 5 of 44 03796-004 DIN AD7877 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Parameter VCC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Input Current to Any Pin Except Supplies1 ESD Rating Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Package Power Dissipation θJA Thermal Impedance IR Reflow Peak Temperature Pb-Free Parts Only Lead Temperature (Soldering 10 s) 1 Rating −0.3 V to +7 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V 10 mA 2.5 kV −40°C to +85°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 450 mW 135.7°C/W 220°C 260°C (±0.5°C) 300°C 200µA TO OUTPUT PIN IOL 1.6V CL 50pF 200µA IOH 03796-003 Table 3. Figure 3. Load Circuit for Digital Output Timing Specifications Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 44 AD7877 NC VREF AOUT ARNG VDRIVE DOUT DCLK NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 24 NC BAT2 2 23 DAV BAT1 3 AD7877 22 ALERT TOP VIEW (Not to Scale) 21 GPIO4 20 STOPACQ AUX1/GPIO1 6 19 DIN VCC 7 18 CS NC 8 17 PENIRQ AUX3/GPIO3 4 11 12 13 14 15 16 X+ Y+ AGND DGND NC NC = NO CONNECT 10 Y– NC 9 X– AUX2/GPIO2 5 03796-002 NC 1 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8–9 10 11 12 13 14 Mnemonic NC BAT2 BAT1 AUX3/GPIO3 AUX2/GPIO2 AUX1/GPIO1 VCC NC X− Y− X+ Y+ AGND 15 DGND 16, 32 17 18 NC PENIRQ CS 19 DIN 20 STOPACQ 21 22 GPIO4 ALERT 23 DAV 24–25 26 27 NC DCLK DOUT 28 VDRIVE Description No Connect. Battery Monitor Input. ADC Input Channel 7. Battery Monitor Input. ADC Input Channel 6. Auxiliary Analog Input. ADC Input Channel 5. Can be reconfigured as GPIO pin. Auxiliary Analog Input. ADC Input Channel 4. Can be reconfigured as GPIO pin. Auxiliary Analog Input. ADC Input Channel 3. Can be reconfigured as GPIO pin. Power Supply Input. The VCC range for the AD7877 is from 2.2 V to 5.25 V. No Connect. Touch Screen Position Input. Touch Screen Position Input. ADC Input Channel 2. Touch Screen Position Input. ADC Input Channel 0. Touch Screen Position Input. ADC Input Channel 1. Analog Ground. Ground reference point for all analog circuitry on the AD7877. All analog input signals and any external reference signal should be referred to this voltage. Digital Ground. Ground reference for all digital circuitry on the AD7877. All digital input signals should be referred to this voltage. No Connect. Pen Interrupt. Digital active low output (has 50 kΩ internal pull-up resistor). Chip Select Input. Active low logic input. This input provides the dual function of initiating conversions on the AD7877 and enabling the serial input/output register. SPI® Serial Data Input. Data to be written to the AD7877’s registers should be provided on this input and is clocked into the register on the rising edge of DCLK. Stop Acquisition Pin. A signal applied to this pin can be monitored by the AD7877, so that acquisition of new data by the ADC is halted while the signal is active. Used to reduce the effect of noise from an LCD screen on the touch screen measurements. Dedicated general-purpose logic input/output pin. Digital Active Low Output. Interrupt output, which goes low if a GPIO data bit is set, or if the AUX1, TEMP1, BAT1, or BAT2 measurements are out of range. Data Available Output. Active low logic output. Asserts low when new data is available in the AD7877 results registers. This output is high impedance when CS is high. No Connect. External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part. Serial Data Output. Logic output. The conversion result from the AD7877 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high. Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial interface of the AD7877. Rev. A | Page 7 of 44 AD7877 Pin No. 29 30 31 Mnemonic ARNG AOUT VREF Description When the DAC is in current output mode, a resistor from ARNG to GND sets the output range. Analog Output Voltage or Current from DAC. Reference output for the AD7877. The internal 2.5 V reference is available on this pin for use external to the device. The reference output must be buffered before it is applied elsewhere in a system. A capacitor of 100nF is strongly recommended between the VREF pin and GND to reduce system noise effects. Alternatively, an external reference can be applied to this input. The voltage range for the external reference is 1.0 V to VCC. For the specified performance, it is 2.5 V on the AD7877. Rev. A | Page 8 of 44 AD7877 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition), and full scale (a point 1 LSB above the last code transition). Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00…000) to (00…001) from the ideal (AGND + 1 LSB). Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal (VREF − 1 LSB) after the offset error has been adjusted out. On Resistance A measure of the ohmic resistance between the drain and the source of the switch drivers. Rev. A | Page 9 of 44 AD7877 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 125 kHz, fDCLK = 16 × fSAMPLE = 2 MHz, unless otherwise noted. 800 200 ADC, REF, AND DAC 180 160 CURRENT (nA) CURRENT (µA) 700 ADC AND REF 600 140 120 –30 –10 0 30 TEMPERATURE (°C) 50 70 80 –50 90 03796-032 500 –50 03796-030 100 –30 –10 10 30 TEMPERATURE (°C) 50 70 90 Figure 8. Full Power-Down IDD vs. Temperature Figure 5. Supply Current vs. Temperature 1000 0.6 0.5 0.4 900 DELTA FROM 25°C (LSB) ADC, REF, AND DAC 700 ADC AND REF 600 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 03796-031 500 400 2.0 0.3 2.3 2.6 2.9 3.2 3.5 3.8 VCC (V) 4.1 4.4 4.7 –0.5 –0.6 –50 5.0 Figure 6. Supply Current vs. VCC –30 –10 10 30 TEMPERATURE (°C) 50 70 90 Figure 9. Change in ADC Offset vs. Temperature 0.6 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 INL (LSB) 0.1 0 –0.1 –0.2 0.2 0 –0.2 –0.4 –0.3 –0.5 –0.6 –50 –30 –10 10 30 TEMPERATURE (°C) 50 70 03796-044 –0.6 –0.4 03796-039 DELTA FROM 25°C (LSB) 03796-040 CURRENT (µA) 800 –0.8 –1.0 0 90 Figure 7. Change in ADC Gain vs. Temperature 500 1000 1500 2000 2500 CODE Figure 10. ACD INL Plot Rev. A | Page 10 of 44 3000 3500 4000 AD7877 1.0 16 0.8 14 REFERENCE CURRENT (µA) 0.6 0.2 0 –0.2 –0.4 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 10 8 6 4 2 03796-045 –0.6 12 0 –50 4000 Figure 11. ADC DNL Plot 03796-046 DNL (LSB) 0.4 –30 –10 10 30 TEMPERATURE (°C) 50 70 90 Figure 14. External Reference Current vs. Temperature 22 2.520 2.515 20 2.510 18 2.505 VREF (V) RON (Ω) X– TO GND 16 Y– TO GND 14 Y+ TO VDD 2.500 2.495 2.490 12 03796-048 X+ TO VDD 8 2.7 3.1 3.5 3.9 4.3 VDD (V) 4.7 5.1 03796-033 2.485 10 2.480 2.475 –50 5.5 Figure 12. Switch On Resistance vs. VCC (X+, Y+: VCC to Pin; X−, Y−: Pin to GND) –30 –10 10 30 TEMPERATURE (°C) 50 70 90 Figure 15. Internal VREF vs. Temperature 22 2.508 20 2.506 X– TO GND 18 VREF (V) Y– TO GND 14 Y+ TO VDD 2.502 2.500 12 X+ TO VDD 8 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 13. Switch On Resistance vs. Temperature (X+, Y+: VCC to Pin; X−, Y−: Pin to GND) 2.496 2.6 03796-034 2.498 10 03796-049 RON (Ω) 2.504 16 2.9 3.2 3.5 3.8 4.1 VCC (V) 4.4 Figure 16. Internal VREF vs. VCC Rev. A | Page 11 of 44 4.7 5.0 AD7877 6 3145 3135 3115 INTERNAL VREF (V) ADC CODE (Decimal) 3125 3105 3095 3085 3075 NO CAP 0.711µs SETTLING TIME 3 100nF CAP 54.64µs SETTLING TIME 3055 3045 –50 –30 –10 10 30 TEMPERATURE (°C) 50 70 0 –20 90 1182 –10 INPUT TONE AMPLITUDE (dB) 10 1180 1179 1178 3.1 3.2 VCC (V) 3.3 60 80 100 120 3.4 3.5 SNR 70.25dB THD 78.11dB –30 –50 –70 –90 –110 –130 03796-042 1177 3.0 40 03796-035 TEMP1 CODE 1181 2.9 20 Figure 20. Internal VREF vs. Turn-On Time 1183 2.8 0 TURN-ON TIME (µs) Figure 17. ADC Code vs. Temperature (2.7 V Supply) 1176 2.7 03796-047 03796-041 3065 –150 3.6 0 Figure 18. Temp1 vs. VCC 10k 20k FREQUENCY 30k 40k Figure 21. Typical FFT Plot for the Auxiliary Channels of the AD7877 at 90 kHz Sample Rate and 10 kHz Input Frequency 982 3.50 3.25 981 DAC O/P SOURCE ABILITY 3.00 2.75 DAC O/P LEVEL (V) 2.50 979 978 977 2.25 2.00 1.75 1.50 1.25 1.00 975 2.7 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 0.50 DAC O/P SINK ABILITY 0.25 0 0 Figure 19. Temp0 vs. VCC 03796-036 0.75 976 03796-043 TEMP0 CODE 980 1 2 3 4 5 6 7 SOURCE/SINK CURRENT (mA) 8 Figure 22. DAC Source and Sink Current Capability Rev. A | Page 12 of 44 9 10 AD7877 ∆: 144mV @: 1.296V 1 CH1 200mV CH2 100mV M2.00µs CH1 03796-050 03796-037 VDD = 3V TEMPERATURE = 25°C 780mV –2 Figure 23. DAC O/P Settling Time (Zero Scale to Half-Scale) 400 DAC SINK CURRENT 300 200 100 03796-038 DAC SINK CURRENT (µA) 500 0 25 50 75 100 125 150 175 INPUT CODE (Decimal) 200 225 0 ERROR (%) 1 Figure 25. Typical Accuracy for Battery Channel (25°C) 600 0 –1 250 Figure 24. DAC Sink Current vs. Input Code Rev. A | Page 13 of 44 2 AD7877 CIRCUIT INFORMATION The core of the AD7877 is a high speed, low power, 12-bit analog-to-digital converter (ADC) with input multiplexer, on-chip track-and-hold, and on-chip clock. The results of conversions are stored in 11 results registers, and the results from one auxiliary input and two battery inputs can be compared with high and low limits stored in limit registers to generate an out-of-limit ALERT. The AD7877 also contains low resistance analog switches to switch the X and Y excitation voltages to the touch screen, a STOPACQ pin to control the ADC acquisition period, 2.5 V reference, on-chip temperature sensor, and 8-bit DAC to control LCD contrast. The high speed SPI serial bus provides control of, and communication with, the device. Operating from a single supply from 2.2 V to 5 V, the AD7877 offers throughput rates of up to 125 kHz. The device is available in a 5 mm by 5 mm 32-lead lead frame chip scale package. The data acquisition system of the AD7877 has a number of advanced features: • Input channel sequenced automatically or selected by the host • STOPACQ feature to reduce noise from LCD • Averaging of from 1 to 16 conversions for noise reduction • Programmable acquisition time • Power management • Programmable ADC power-up delay before first conversion • Choice of internal or external reference • Conversion at preprogrammed intervals CONDUCTIVE ELECTRODE ON BOTTOM SIDE PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON BOTTOM SIDE Y+ X– Y– X+ CONDUCTIVE ELECTRODE ON TOP SIDE PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON TOP SIDE LCD SCREEN 03796-005 The AD7877 is a complete, 12-bit data acquisition system for digitizing positional inputs from a touch screen in PDAs and other devices. In addition, it can monitor two battery voltages, ambient temperature, and three auxiliary analog voltages, with high and low limit comparisons on three of the inputs, and has up to four general-purpose logic I/O pins. Figure 26. Basic Construction of a Touch Screen The Y layer has conductive electrodes running along the top and bottom edges, allowing the application of an excitation voltage down the layer from top to bottom. Provided that the layers are of uniform resistivity, the voltage at any point between the two electrodes is proportional to the horizontal position for the X layer and the vertical position for the Y layer. When the screen is touched, the two layers make contact. If only the X layer is excited, the voltage at the point of contact, and therefore the horizontal position, can be sensed at one of the Y layer electrodes. Similarly, if only the Y layer is excited, the voltage, and therefore the vertical position, can be sensed at one of the X electrodes. By switching alternately between X and Y excitation and measuring the voltages, the X and Y coordinates of the contact point can be found. In addition to measuring the X and Y coordinates, it is also possible to estimate the touch pressure by measuring the contact resistance between the X and Y layers. The AD7877 is designed to facilitate this measurement. TOUCH SCREEN PRINCIPLES A 4-wire touch screen consists of two flexible, transparent, resistive-coated layers that are normally separated by a small air gap. The X layer has conductive electrodes running down the left and right edges, allowing the application of an excitation voltage across the X layer from left to right. Figure 28 shows an equivalent circuit of the analog input structure of the AD7877, showing the touch screen switches, the main analog multiplexer, the ADC with analog and differential reference inputs, and the dual 3-to-1 multiplexer that selects the reference source for the ADC. Rev. A | Page 14 of 44 AD7877 VCC The voltage seen at the input to the ADC in Figure 28 is VIN = VCC × X+ X– REF INT/EXT Y+ Y– X– Y– GND X+ Y+ VREF DUAL 3-1 MUX 9 TO 1 I/P MUX AUX1/GPIO2 AUX2/GPIO3 AUX3/GPIO4 REF– IN+ BAT1 RY − (1) RYTOTAL The advantage of the single-ended method is that the touch screen excitation voltage can be switched off once the signal has been acquired. Because a screen can draw over 1 mA, this is a significant consideration for a battery-powered system. REF+ 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD 03796-006 BAT2 TEMPERATURE SENSOR Figure 27. Analog Input Structure The AD7877 can be set up to convert specific input channels or to convert a sequence of channels automatically. The results of the ADC conversions are stored in the results registers. See the Serial Interface section for details. When measuring the ancillary analog inputs (AUX1 to AUX3, BAT1 and BAT2), the ADC uses the internal reference, or an external reference applied to the VREF pin, and the measurement is referred to GND. MEASURING TOUCH SCREEN INPUTS When measuring the touch screen inputs, it is possible to measure using the internal (or external) reference, or to use the touch screen excitation voltage as the reference and perform a ratiometric, differential measurement. The differential method is the default and is selected by clearing the SER/DFR bit (Bit 11) in Control Register 1. The single-ended method is selected by setting this bit. Single-Ended Method The single-ended method is illustrated for the Y position in Figure 28. For the X position, the excitation voltage would be applied to X+ and X− and the voltage measured at Y+. The disadvantages of the single-ended method are as follows: • It can be used only if VCC is close to VREF. If VCC is greater than VREF, some positions on the screen are outside the range of the ADC. If VCC is less than VREF, the full range of the ADC is not utilized. • The ratio of VCC to VREF must be known. If VREF and/or VCC vary relative to one another, this can introduce errors. • Voltage drops across the switches can introduce errors. Touch screens can have a total end-to-end resistance of from 200 Ω to 900 Ω. Taking the lowest screen resistance of 200 Ω and a typical switch resistance of 14 Ω, this could reduce the apparent excitation voltage to 200/228 × 100 = 87% of its actual value. In addition, the voltage drop across the low-side switch adds to the ADC input voltage. This introduces an offset into the input voltage, which means that it can never reach zero. The single-ended method is adequate for applications in which the input device is a fairly blunt and imprecise instrument such as a finger. Ratiometric Method The ratiometric method is illustrated in Figure 29. Here, the negative input of the ADC reference is tied to Y− and the positive input is connected to Y+, so the screen excitation voltage provides the reference for the ADC. The input of the ADC is connected to X+ to determine the Y position. VCC VCC Y+ Y+ VREF X+ INPUT (VIA MUX) REF– Y– REF– Y– 03796-007 GND GND REF+ ADC TOUCH SCREEN ADC TOUCH SCREEN INPUT (VIA MUX) 03796-008 X+ REF+ Figure 29. Ratiometric Conversion of Touch Screen Inputs Figure 28. Single-Ended Conversion of Touch Screen Inputs Rev. A | Page 15 of 44 AD7877 MEASURE X POSITION For greater accuracy, the ratiometric method has two significant advantages: X+ TOUCH RESISTANCE • The reference to the ADC is provided from the actual voltage across the screen, so voltage drops across the switches have no effect. X– Y– Y+ X+ MEASURE Z1 POSITION • Because the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. However, it must not change after the signal has been acquired. TOUCH RESISTANCE The disadvantage of the ratiometric method is that the screen must be powered up all the time, because it provides the reference voltage for the ADC. Y– X– Y+ X+ TOUCH RESISTANCE The pressure applied to the touch screen via a pen or finger can also be measured with the AD7877 using some simple calculations. The contact resistance between the X and Y plates is measured. This provides a good indication of the size of the depressed area and, therefore, the applied pressure. The area of the spot touched is proportional to the size of the object touching it. The size of this resistance (RTOUCH) can be calculated using two different methods. First Method The first method requires the user to know the total resistance of the X-plate tablet (RX). Three touch screen conversions are required: Y– X– MEASURE Z2 POSITION 03796-009 TOUCH-PRESSURE MEASUREMENT Figure 30. Three Measurements Required for Touch Pressure Second Method The second method requires that the resistance of the X-plate and Y-plate tablets be known. Three touch screen conversions again are required, a measurement of the X Position (XPOSITION), Y Position (YPOSITION), and Z1 position. The following equation also calculates the touch resistance: • Measurement of the X position, XPOSITION (Y+ input). RTOUCH = RXPlate × (XPOSITION /4096) × [(4096/Z1) − 1] (3) − RYPlate × [1 − (YPOSITION /4096)] • Measurement of the Y− input with the excitation voltage applied to Y+ and X− (Z1 measurement). STOPACQ PIN • Measurement of the X+ input with the excitation voltage applied to Y+ and X− (Z2 measurement). These three measurements are illustrated in Figure 30. The AD7877 has two special ADC channel settings that configure the X and Y switches for Z1 and Z2 measurement and store the results in the Z1 and Z2 results registers. The Z1 measurement is ADC Channel 1010b, and the result is stored in the register with Read Address 11010b. The Z2 measurement is ADC Channel 0010b, and the result is stored in the register with Read Address 10010b. As explained previously, touch screens are composed of two resistive layers, normally placed over an LCD screen. Because these layers are in close proximity to the LCD screen, noise can be coupled from the screen onto these resistive layers, causing errors in the touch screen positional measurements. For example, a jitter might be noticeable in the cursor onscreen. In most LCD touch screen systems, a signal, such as an LCD invert signal or other control signal, is present, and noise is usually coupled onto the touch screen during this signal’s active period, as shown in Figure 31. The touch resistance can then be calculated using the following equation: LCD SIGNAL (2) TOUCH SCREEN SIGNAL NOISY PERIOD NOISY PERIOD Figure 31. LCD Noise Affects Touch Screen Measurements Rev. A | Page 16 of 44 03796-010 RTOUCH = (RXPlate) × (XPOSITION /4096 × [Z2/Z1) − 1] Y+ AD7877 It is only during the sample or acquisition phase of the AD7877’s ADC operation that noise from the LCD screen has an effect on the ADC’s measurements. During the hold or conversion phase, the noise has no effect, because the voltage at the input of the ADC has already been acquired. Therefore, to minimize the effect of noise on the touch screen measurements, the ADC acquisition phase should be halted. The LCD control signal should be applied to the STOPACQ pin. To ensure that acquisition never takes place during the noisy period when the LCD signal is active, the AD7877 monitors this signal. No acquisitions take place when the control signal is active. Any acquisition that is in progress when the signal becomes active is aborted and restarts when the signal becomes inactive again. To accommodate signals of different polarities on the STOPACQ pin, a user-programmable register bit is used to indicate whether the signal is active high or low. The POL bit is Bit 3 in Control Register 2, Address 02h. Setting POL to 1 indicates that the signal on STOPACQ is active high; setting POL to 0 indicates that it is active low. POL defaults to 0 on power-up. To disable monitoring of STOPACQ, the pin should be tied low if POL = 1, or tied high if POL = 0. Under no circumstances should the pin be left floating. The signal on STOPACQ has no effect while the ADC is in conversion mode, or during the first conversion delay time. (See the Control Registers section for details on first conversion delay.) When enabled, the STOPACQ monitoring function is implemented on all input channels to the ADC: AUX1, AUX2, BAT1, BAT2, TEMP1, and TEMP2, as well as on the touch screen input channels. TEMPERATURE MEASUREMENT Two temperature measurement options are available on the AD7877: the single conversion method and the differential conversion method. The single conversion method requires only a single measurement on ADC Channel 1000b. Differential conversion requires two measurements, one on ADC Channel 1000b and a second on ADC Channel 1001b. The results are stored in the results registers with Addresses 11000b (TEMP1) and 11001b (TEMP2). The AD7877 does not provide an explicit output of the temperature reading. Some external calculations must be performed by the system. Both methods are based on an on-chip diode measurement. Single Conversion Method The single conversion method makes use of the fact that the temperature coefficient of a silicon diode is approximately −2.1 mV/°C. However, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. It is, therefore, necessary to calibrate by measuring the diode voltage at a known temperature to provide a baseline from which the change in forward voltage with temperature can be measured. This method provides a resolution of approximately 0.3°C and a predicted accuracy of ±2.5°C. The temperature limit comparison is performed on the result in the TEMP1 results register, which is simply the measurement of the diode forward voltage. The values programmed into the high and low limits should be referenced to the calibrated diode forward voltage to make accurate limit comparisons. An example is shown in the Limit Comparison section. Differential Conversion Method The differential conversion method is a 2-point measurement. The first measurement is performed with a fixed bias current into a diode (when the TEMP1 channel is selected), and the second measurement is performed with a fixed multiple of the bias current into the same diode (when the TEMP2 channel is selected). The voltage difference in the diode readings is proportional to absolute temperature and is given by the following formula: ∆VBE = (KT/q) × (1n N) (4) where: VBE represents the diode voltage. N is the bias current multiple (typical value for AD7877 =120). k is Boltzmann’s constant. q is the electron charge. This method provides a resolution of approximately 1.6°C, and a guaranteed accuracy of ±4°C without calibration. Determination of the N value on a part-by-part basis improves accuracy. Assuming a current multiple of 120, which is a typical value for the AD7877, taking Boltzmann’s constant, k = 1.38054 × 10−23 electrons V/°K, the electron charge q = 1.602189 × 10−19, then T, the ambient temperature in Kelvin, would be calculated as follows: ∆VBE = (KT/q) × (1n N) T°K = (∆VBE × q)/(k × 1n N) = ∆VBE × 1.602189 × 10−19)/(1.38054 × 10−23 × 4.65) T°C = 2.49 × 103 × ∆VBE − 273 ∆VBE is calculated from the difference in readings from the first conversion and second conversion. The user must perform the calculations to get ∆VBE, and then calculate the temperature value in degrees. Figure 32 shows a block diagram of the temperature measurement circuit. Rev. A | Page 17 of 44 AD7877 TEMP1 TEMP2 Example: 105 × I MUX The internal 2.5 V reference is used. ADC VBE 1. LSB size = 2.5 V/4096 = 6.1 × 10−4 V (610 µV). 2. TEMP1 = 880 and TEMP2 = 1103: ∆VBE = (1103 − 880) × 6.1× 10−4 = 0.136 V 3. T = 0.136 × 2490 − 273 = 65°C. 03796-011 I Figure 32. Block Diagram of Temperature Measurement Circuit BATTERY MEASUREMENT Temperature Calculations If an explicit temperature reading in °C is required, then this can be calculated as follows for the single measurement method: 1. Calculate the scale factor of the ADC in degrees per LSB: Degrees per LSB = ADC LSB size/−2.1 mV = VREF/4096)/−2.1 mV 2. Save the ADC output DCAL at the calibration temperature TCAL. 3. Take ADC reading DAMB at temperature to be measured TAMB. 4. Calculate the difference in degrees between TCAL and TAMB using The AD7877 can monitor battery voltages from 0.5 V to 5 V on two inputs, BAT1 and BAT2. Figure 33 shows a block diagram of a battery voltage monitored through the BAT1 pin. The voltage to the VCC pin of the AD7877 is maintained at the desired supply voltage via the dc/dc regulator while the input to the regulator is monitored. This voltage on BAT1 is divided down by 2 internally, so that a 5 V battery voltage is presented to the ADC as 2.5 V. To conserve power, the divider circuit is on only during the sampling of a voltage on BAT1. The BAT2 input circuitry is identical. The BAT1 input is ADC Channel 0110b and the result is stored in Register 10110b. The BAT2 input is ADC Channel 0111b and the result is stored in Register 10111b. DC-DC CONVERTER BATTERY 0.5V TO 5V VCC BAT1 ∆T = (DAMB − DCAL) × degrees per LSB 5. 5kΩ VREF SW 0.25V–2.5V ADC Add ∆T to TCAL. 5kΩ 03796-012 Example: The internal 2.5 V reference is used. 1. Degrees per LSB = (2.5/4096)/−2.1 × 10−3 = −0.291. 2. The ADC output is 983 decimal at 25°C, equivalent to a diode forward voltage of 0.6 V. 3. The ADC output at TAMB is 880. 4. ∆T = (880 − 983) × −0.291 = 30°. 5. TAMB = 25 + 30 = 55°C. Figure 33. Block Diagram of Battery Measurement Circuit Figure 33 shows the ADC using the internal reference of 2.5 V. If a different reference voltage is used, then the maximum battery voltage that the AD7877 can measure changes. The maximum voltage measurable is VREF × 2, because this voltage gives a full-scale output from the ADC. If a smaller reference is used, such as 2 V, then the maximum battery voltage measurable is 4 V. If a larger reference is used, such as 3.5 V, then the maximum battery voltage measurable is 7 V. The internal reference is particularly suited for use when measuring Li-Ion batteries, where the minimum voltage is about 2.7 V and the maximum is about 4.2 V. A proper choice of external reference ensures that other voltage ranges can be accommodated. To calculate the temperature explicitly using the differential method: 1. Calculate the LSB size of the ADC in V: LSB = VREF/4096 2. Subtract TEMP1 from TEMP2 and multiply by LSB size to get ∆VBE. 3. Multiply by 2490 and subtract 273 to get the temperature in °C. Rev. A | Page 18 of 44 AD7877 AUXILIARY INPUTS The AD7877 has three auxiliary analog inputs, AUX1 to AUX3. These channels have a full-scale input range from 0 V to VREF. The ADC channel addresses for AUX1 to AUX3 are 0011b, 0100b, and 0101b, and the results are stored in Registers 10011b, 10100b, and 10101b. These pins can also be reconfigured as general-purpose logic inputs/outputs, as described in the GPIO Configuration section. LIMIT COMPARISON The AUX1 measurement, the two battery measurements, and the TEMP1 measurement can all be compared with high and low limits, and an out-of-limit result made to generate an alarm output at the ALERT pin. The limits are stored in registers with addresses from 00100b to 01011b. After a measurement from any one of the four channels is converted, it is compared with the corresponding high and low limits. An out-of-limit result sets one of the status bits in the alert status/enable register. For details on these and other registers, see the Register Maps and Detailed Register Descriptions sections. For details on writing and reading data, see the Serial Interface section. As mentioned previously, the temperature comparison is made using the result of the TEMP1 measurement, which is the diode forward voltage. Because the temperature coefficient of the diode is known but the actual forward voltage can have a wide tolerance, it is not possible to program the high and low limit registers with predetermined values. Instead, it is necessary to calibrate the temperature measurement, calculate the TEMP1 readings at the high and low limit temperatures, and then program those values into the limit registers, as follows: 1. Calculate LSB per degree = −2.1 mV/(VREF/4096). 2. Save the calibration reading DCAL at calibration temperature TCAL. 3. Subtract TCAL from limit temperatures THIGH and TLOW to get the difference in degrees between the limit temperatures and the calibration temperature. 4. Multiply this value by LSB per degree to get the value in LSBs. 5. Add these values to the digital value at the calibration temperature to get the digital high and low limit values. Example: The internal 2.5 V reference is used. 1. THIGH = +65°C and TLOW = −10°C. 2. LSB per degree = −2.1 × 10−3/(2.5/4096) = −3.44. 3. DCAL = 983 decimal at 25°C. 4. DHIGH = (65 − 25) × −3.44 + 983 = 845. 5. DLOW = (−10 − 25) × −3.44 + 983 = 1103. Rev. A | Page 19 of 44 AD7877 CONTROL REGISTERS Control Register 1 contains the ADC channel address, the SER/DFR bit (to choose single or differential methods of touch screen measurement), the register read address, and the ADC mode bits. Control Register 1 should always be the last register to be programmed prior to starting conversions. Its power-on default value is 00h. To change any parameter after conversion has begun, the part should first be put into mode 00, the changes made, and then Control Register 1 reprogrammed, ensuring that it is always the last register to be programmed before conversions begin. SER/ DFR 0 CHNL CHNL CHNL CHNL ADD ADD ADD ADD 3 2 1 0 RD ADD 4 RD ADD 3 RD ADD 2 RD ADD 1 RD ADD 0 ADC ADC MODE MODE 1 0 03796-013 11 The AD7877 can also be programmed to convert a sequence of selected channels automatically. The two modes for this type of conversion are slave mode and master mode. Figure 34. Control Register 1 Control Register 2 sets the timer, reference, polarity, first conversion delay, averaging, and acquisition time. Its power-on default value is 00h. See the Detailed Register Descriptions section for more information on the control registers. AVG 1 0 AVG 0 ACQ 1 ACQ 0 PM 1 PM 0 FCD 1 FCD 0 POL REF TMR 1 TMR 0 Figure 35. Control Register 2 CONTROL REGISTER 1 ADC Mode (Control Register 1 Bits <1:0>) These bits select the operating mode of the ADC. The AD7877 has three operating modes. These are selected by writing to the mode bits in Control Register 1. If the mode bits are 00, no conversion is performed. Table 5. Control Register 1 Mode Selection Mode 1 0 0 Mode 0 0 1 1 1 0 1 Function Do not convert (default) Single-channel conversion, AD7877 in slave mode Sequence 0, AD7877 in slave mode Sequence 1, AD7877 in master mode If the mode bits are 01, a single conversion is performed on the channel selected by writing to the channel bits of Control Register 1 (Bits 7 to 10). At the end of the conversion, if the TMR bits in Control Register 2 are set to 00, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a value other than 00 causes the conversion to be repeated, as described in the Timer (Control Register 2 Bits <1:0>) section. The flowchart in Figure 37 shows how the AD7877 operates in mode 01. 03796-014 11 For slave mode operation, the channels to be digitized are selected by setting the corresponding bits in Sequencer Register 0. Conversion is initiated by writing 10b to the mode bits of Control Register 1. The ADC then digitizes the selected channels and stores the results in the corresponding results registers. At the end of the conversion, if the TMR bits in Control Register 2 are set to 00, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a code other than 00 causes the conversion sequence to be repeated. The flowchart in Figure 38 shows how the AD7877 operates in mode 10. For master mode operation, the channels to be digitized are written to Sequencer Register 1. Master mode is then selected by writing 11 to the mode bits in Control Register 1. In this mode, the wake-up on touch feature is active, so conversion does not begin immediately. The AD7877 waits until the screen is touched before beginning the sequence of conversions. The ADC then digitizes the selected channels, and the results are written to the results registers. The AD7877 waits for the screen to be touched again, or for a timer event if the screen remains touched, before beginning another sequence of conversions. Figure 39 is a flowchart, showing how the AD7877 operates in mode 11. ADC Channel (Control Register 1 Bits <10:7>) The ADC channel is selected by Bits 10:7 of Control Register 1 (CHADD3 to CHADD0). In addition, the SER/DFR bit, Bit 11, selects between single-ended and differential conversion. A complete list of channel addresses is given in Table 6. For mode 0 (single-channel) conversion, the channel is selected by writing the appropriate CHADD3 to CHADD0 code to Control Register 1. For sequential channel conversion, channels to be converted are selected by setting bits corresponding to the channel number in Sequencer Register 1 for slave mode sequencing or Sequencer Register 2 for master mode sequencing. For both single-channel and sequential conversion, normal (single-ended) conversion is selected by clearing the SER/DFR bit in Control Register 1. Ratiometric (differential) conversion is selected by setting the SER/DFR bit. Rev. A | Page 20 of 44 AD7877 Table 6. Codes for Selecting Input Channel and Normal or Ratiometric Conversion Channel 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 - SER/DFR CHADD(3:0) 0000 0001 0010 0 01 1 0 1 00 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 10 1 1 1100 1101 1110 1111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Analog Input X+ (Y Position) Y+ (X Position) Y− (Z2) AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) X+ (Y Position) Y+ (X Position) Y− (Z2) AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) X Switches Y Switches OFF ON ON OFF X+ OFF, X− ON Y+ ON, Y− OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF X+ OFF, X− ON Y+ ON, Y− OFF INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS OFF ON ON OFF X+ OFF, X− ON Y+ ON, Y− OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF X+ OFF, X− ON Y+ ON, Y− OFF INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS INVALID ADDRESS +REF Y+ X+ Y+ VREF VREF VREF VREF VREF VREF VREF Y+ −REF Y− X− X− GND GND GND GND GND GND GND X− VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF GND GND GND GND GND GND GND GND GND GND GND CONTROL REGISTER 2 Int/Ext Reference (Control Register 2 Bit <2>) Timer (Control Register 2 Bits <1:0>) If the REF bit in Control Register 2 is 0 (default value), the internal reference is selected. If any connection is made to VREF while the internal reference is selected (for example, to supply a reference to other circuits), it should be buffered. An external power supply should not be connected to this pin while REF is equal to 0, because it might overdrive the internal reference. Note also that, because the internal reference is 2.5 V, it operates only with supply voltages down to 2.7 V. Below this value an external reference should be used. The TMR bits in Control Register 2 enable the ADC to repeatedly perform a conversion or conversion sequence either once only or at intervals of 512 µs, 1.024 ms, or 8.19 ms. In slave mode, the timer starts as soon as the conversion sequence is finished. In master mode, the timer starts at the end of a conversion sequence only if the screen remains touched. If the touch is released at any stage, then the timer stops and, the next time the screen is touched, a conversion sequence begins immediately. Table 7. Control Register 2 Timer Selection TMR1 0 0 1 1 TMR0 0 1 0 1 Function Convert only once (default) Every 1024 clocks (512 µs) Every 2048 clocks (1.024 ms) Every 16,384 clocks (8.19 ms) If the REF bit is 1, the VREF pin becomes an input and the internal reference is powered down. This overrides any setting of the PM bits with regard to the reference. An external reference can then be applied to the REF pin. Rev. A | Page 21 of 44 AD7877 STOPACQ Polarity (Control Register 2 Bit <3>) Acquisition Time (Control Register 2 Bits <9:8>) This bit should be set according to the polarity of the signal applied to the STOPACQ pin. If that signal is active high, that is, no acquisitions should occur during the signal’s high period, then the POL bit should be set to 1. If the signal is active low, then the POL bit should be 0. The default value for POL is 0. The ACQ bits in Control Register 2 allow the selection of acquisition times for the ADC of 2 µs (default), 4 µs, 8 µs, or 16 µs. The user can program the ADC with an acquisition time suitable for the type of signal being sampled. For example, signals with large RC time constants might require longer acquisition times. First Conversion Delay (Control Register 2 Bits <5:4> ) The first conversion delay (FCD) bits in Control Register 2 program a delay of 500 ns (default), 128 µs, 1.024 ms, or 8.19 ms before the first conversion, to allow the ADC time to power up. This delay also occurs before conversion of the X and Y coordinate channels, to allow extra time for screen settling, and after the last conversion in a sequence, to precharge PENIRQ. If the signal on the STOPACQ pin is being monitored and goes active during the FCD, it is ignored until after the FCD period. Table 10. Acquisition Time Selection Table 8. First Conversion Delay Selection Signals from touch screens can be extremely noisy. The AVG bits in Control Register 2 allow multiple conversions to be performed on each input channel and averaged to reduce noise. A single conversion can be selected (no averaging), which is the default, or 4, 8, or 16 conversions can be averaged. Only the final averaged result is written into the results register. FCD1 0 0 1 1 FCD 0 1 0 1 Function 1 clock delay (500 ns) 256 clocks delay (128 µs) 2048 clocks delay (1.024 ms) 16,384 clocks delay (8.19 ms) ACQ1 0 0 1 1 ACQ0 0 1 0 1 Function 4 clock periods (2 µs) 8 clock periods (4 µs) 16 clock periods (8 µs) 32 clock periods (16 µs) Averaging (Control Register 2 Bits <11:10>) Table 11. Averaging Selection The power management (PM) bits in Control Register 2 allow the power management features of the ADC to be programmed. If the PM bits are 00, the ADC is powered down permanently. This overrides any setting of the mode bits in Control Register 1. If the PM bits are 01, the ADC and the reference both power down when the ADC is not converting. If the PM bits are 10, the ADC and reference are powered up continuously. If the PM bits are 11, the ADC, but not the reference, powers down when the ADC is not converting. Table 9. Power Management Selection PM1 0 0 PM0 0 1 1 1 0 1 Function Power down continuously (default) Power down ADC and reference when ADC is not converting (powers up with FCD at start of conversion) Powered up continuously Power down ADC when ADC is not converting (powers up with FCD at start of conversion) AVG1 0 0 1 1 AVG0 0 1 0 1 Function ADC performs 1 average per channel ADC performs 4 averages per channel ADC performs 8 averages per channel ADC performs 16 averages per channel SEQUENCER REGISTERS There are two sequencer registers on the AD7877. Sequencer Register 0 controls the measurements performed during a slave mode sequence. Sequencer Register 1 controls the measurements performed during a master mode sequence. To include a measurement in a slave mode or master mode sequence, the relevant bit must be set in Sequencer Register 0 or Sequencer Register 1. Setting Bit 11 includes a measurement on ADC Channel 0 in the sequence, which is the Y positional measurement. Setting Bit 10 includes a measurement on ADC Channel 1 (X+ measurement), and so on, through Bit 1 for Channel 10. Figure 36 illustrates the correspondence between the bits in the sequencer registers and the various measurements. Bit 0 in both sequencer registers is not used. See also the Detailed Register Descriptions section. 11 0 Y+ X+ Z2 AUX 1 AUX 2 AUX 3 BAT 1 BAT 2 TEMP TEMP 1 2 Figure 36. Sequencer Register Rev. A | Page 22 of 44 Z1 NOT USED 03796-015 Power Management (Control Register 2 Bits <7:6>) AD7877 HOST PROGRAMS AD7877 IN MODE 10 HOST PROGRAMS AD7877 IN MODE 01 IS FCD REQUIRED? VALID SEQUENCE 0? NO NO GOTO MODE 00 YES YES SELECT NEXT CHANNEL START FCD TIMER IS FCD FINISHED? IS FCD REQUIRED? NO NO YES YES YES START FCD TIMER IS FCD FINISHED? IS STOPACQ SIGNAL ACTIVE? NO YES NO IS STOPACQ SIGNAL ACTIVE? YES START ACQUISITION TIMER NO START ACQUISITION TIMER IS STOPACQ SIGNAL ACTIVE? YES YES NO IS STOPACQ SIGNAL ACTIVE? NO NO IS ACQUISITION TIME FINISHED? IS ACQUISITION TIME FINISHED? NO YES CONVERT SELECTED CHANNEL YES CONVERT SELECTED CHANNEL NO IS AVERAGING FINISHED? IS AVERAGING FINISHED? YES YES WRITE RESULT TO REGISTERS WRITE RESULT TO REGISTERS LIMIT COMPARISON LIMIT COMPARISON NO OUT-OF-LIMIT? OUT-OF-LIMIT? NO YES YES UPDATE ALERT ENABLE/STATUS REGISTER UPDATE ALERT ENABLE/STATUS REGISTER ALERT SOURCE ENABLED? NO ALERT SOURCE ENABLED? NO NO YES ASSERT ALERT OUTPUT* YES ASSERT ALERT OUTPUT* LAST CHANNEL IN SEQUENCE? NO YES ONCE-ONLY MODE? GOTO MODE 00 YES YES ONCE-ONLY MODE? GOTO MODE 00 NO START TIMER NO START TIMER YES *NOTE: SEE EXPLANATION IN TEXT NO TIMER FINISHED? YES *NOTE: SEE EXPLANATION IN TEXT Figure 37. Single Channel Operation 03796-017 TIMER FINISHED? 03796-016 NO Figure 38. Slave Mode Sequencer Operation Rev. A | Page 23 of 44 AD7877 INTERRUPTS HOST PROGRAMS AD7877 IN MODE 11 Data Available Output (DAV) GOTO MODE 00 VALID SEQUENCE 1? NO The data available output (DAV) indicates that new ADC data is available in the results registers. While the ADC is idle or is converting, DAV is high. Once the ADC has finished converting and new data has been written to the results registers, DAV goes low. Taking DAV low to read the registers resets DAV to a high condition. DAV is also reset, if a new conversion is started by the AD7877 because the timer expired. The host should attempt to read the results registers only while DAV is low. YES IS SCREEN TOUCHED? NO YES SELECT NEXT CHANNEL IS FCD REQUIRED? NO YES START FCD TIMER CS IS FCD FINISHED? NO YES tCONV IS STOPACQ SIGNAL ACTIVE? AD7877 STATUS NO START ACQUISITION TIMER YES ADC CONVERTING NEW DATA HOST READS AVAILABLE RESULTS IDLE Figure 40. Operation of DAV Output IS STOPACQ SIGNAL ACTIVE? DAV is useful as a host interrupt in master mode. In this mode, the host can program the AD7877 to automatically perform a sequence of conversions, and can be interrupted by DAV at the end of each conversion sequence. NO IS ACQUISITION TIME FINISHED? IDLE SETUP BY HOST 03796-019 DAV YES NO YES CONVERT SELECTED CHANNEL When the on-board timer is programmed to perform automatic conversions, a limited time is available to the host to read the results registers before another sequence of conversions begins. The DAV signal is reset high when the timer expires, and the host should not access the results registers while DAV is high. NO IS AVERAGING FINISHED? YES WRITE RESULT TO REGISTERS LIMIT COMPARISON OUT-OF-LIMIT? Figure 41 shows the worst-case timings for reading the results registers after DAV has gone low. The timer is set at a minimum, and the conversion sequence includes all eleven possible ADC channels. t1 is the time taken for acquisition and conversion on one ADC channel. t2 shows the minimum timer delay, which is 1024 clock periods. t3 is the time taken to read all 11 result registers. If the host wants to read all 11 registers, then it must do so before the timer expires. t4 is the maximum time allowable between DAV going low and the host beginning to read the results registers. If t4 is exceeded, then all registers cannot be read before the start of a new conversion, and incorrect data could be read by the host. NO YES UPDATE ALERT ENABLE/STATUS REGISTER ALERT SOURCE ENABLED? NO YES ASSERT ALERT OUTPUT* NO LAST CHANNEL IN SEQUENCE? YES YES ONCE-ONLY MODE? NO IS SCREEN STILL TOUCHED? AD7877 STATUS NO t1 t2 CHANNEL 11 CONVERSION AND ACQUISITION TIMER INTERVAL CHNL 1 YES DAV TIMER FINISHED? CS YES DOUT NO IS SCREEN STILL TOUCHED? NO *NOTE: SEE EXPLANATION IN TEXT t3 03796-018 YES t4 Figure 41. Timing for Reads after DAV Goes Low Figure 39. Master Mode Sequencer Operation Rev. A | Page 24 of 44 03796-020 START TIMER AD7877 NOT SCREEN TOUCHED t2 = timer interval × tDCLK = (1024 × 50 ns) = 51.2 µs NOT TOUCHED TOUCHED PENIRQ DETECTS TOUCH PENIRQ PENIRQ DETECTS RELEASE TWRITE = TREAD = 16 clk period × tDCLK = 800 ns ADC STATUS t3 = maximum time taken to write read address and read 11 registers = 800 ns (write) + [800 ns (read) × 11] = 9.6 µs. ADC IDLE NOT SCREEN TOUCHED t4MAX = t2 − t3 = 51.2 µs − 9.6 µs = 41.6 µs Pen Interrupt (PENIRQ) Y+ VCC VCC 50kΩ PENIRQ X+ ADC STATUS RELEASE NOT DETECTED PENIRQ DETECTS TOUCH PENIRQ The pen interrupt request output (PENIRQ) goes low whenever the screen is touched. The pen interrupt equivalent output circuitry is outlined in Figure 42. This is a digital logic output with an internal pull-up resistor of 50 kΩ, which means it does not need an external pull-up. The PENIRQ output idles high. The PENIRQ circuitry is always enabled, except during conversions. TOUCHED ADC IDLE NOT TOUCHED PENIRQ DETECTS RELEASE ADC CONVERTING ADC IDLE 03796-022 If fDCLK = 20 MHz (maximum), then tDCLK = 50 ns. Figure 43. PENIRQ Operation for ADC Idle and ADC Converting SYNCRONIZING THE AD7877 TO THE HOST CPU The two suggested methods for synchronizing the AD7877 to its host CPU are slave mode, in which the mode bits can be either 01b or 10b, and master mode, in which the mode bits are 11b. X– TOUCH SCREEN Y– 03796-021 PENIRQ ENABLE In slave mode, PENIRQ can be used as an interrupt to the host. When PENIRQ goes low to indicate that the screen has been touched, the host is awakened. The host can then program the AD7877 to begin converting in either mode 01b or 10b, and can read the result registers after the conversions have completed. Figure 42. PENIRQ Output Equivalent Circuit When the screen is touched, PENIRQ goes low. This can be used to generate an interrupt request to the host. When the screen touch ends, PENIRQ goes high immediately, if the ADC is idle. If the ADC is converting, PENIRQ goes high when the ADC becomes idle. The PENIRQ operation for these two conditions is shown in Figure 43. In master mode, DAV can also be used as an interrupt to the host. However, the host should first initialize the AD7877 in mode 11b. The host can then go into sleep mode to conserve power. The wake-up on touch feature of the AD7877 is active in this mode, so, when the screen is touched, the programmed sequence of conversions begins automatically. When the DAV signal asserts, the host reads the new data available in the AD7877 results registers and returns to sleep mode. This method can significantly reduce the load on the host. Rev. A | Page 25 of 44 AD7877 8-BIT DAC The AD7877 features an on-chip 8-bit DAC for LCD contrast control. The DAC can be configured for voltage output by clearing Bit 2 of the DAC register (Address 1110b), or for current output by setting this bit. The output voltage range can be set to 0 − VCC/2 by clearing Bit 0 of the DAC register, or to 0 − VCC by setting this bit. In current mode, the output range is selectable by an external resistor, RRNG, connected between the ARNG pin and GND. This sets the full-scale output current according to the following equations: In current mode, it is quite easy to calculate the resistor values to give the required adjustment range in VOUT: 1. Find the required maximum and minimum values of VOUT from the LCD manufacturer’s data. 2. Decide on the current around the feedback loop, which for reasonable accuracy of the output voltage should be at least 100 times the input bias current of the dc–dc converter’s comparator. 3. Calculate R3 using the following equation: IFS = VCC/(RRNG × 6) R3 = VFB/IFB = VREF/IFB so RRNG = VCC/(IFS × 6) 4. In current mode, the DAC sinks current, that is, positive current flows into ground. The maximum output current is 1000 µA. The DAC is updated by writing to Address 1110b of the DAC register. The 8 MSBs of the data-word are used for DAC data. The most effective way to control LCD contrast with the DAC is to use it to control the feedback loop of the dc-dc converter that supplies the LCD bias voltage, as shown in Figure 44. The bias voltage for graphic LCDs is typically in the range of 20 V to 25 V, and the dc–dc converter usually has a feedback loop that attenuates the output voltage and compares it with an internal reference voltage. TO LCD DC-DC CONVERTER AD7877 RRNG1 IOUT VFB 5. Because the voltage across R3 does not change, subtract VREF from VOUTMAX and VOUTMIN to get the maximum and minimum voltages across R2. 6. Calculate the change in feedback current between minimum and maximum output voltages: ∆I = VR2(MAX)/R2 − VR2(MIN)/R2 This is the required full-scale current of the DAC. 7. Calculate RRNG from the equation given previously. Example: R12 R3 R2 = R3(VOUT(MIN) − VREF)/VREF VOUT COMP VREF 1. VCC = 5 V. VOUT(MIN) is 20 V and VOUT(MAX) is 25 V. VREF is 1.25 V. 2. Allow 100 µA around the feedback loop. 3. R3 = 1.25 V/100 µA = 12.5 kΩ. Use the nearest preferred value of 12 kΩ and recalculate the feedback current as GND NOTES: 1R RNG IS REQUIRED ONLY IF DAC IS IN CURRENT MODE. 2R1 IS REQUIRED ONLY IF DAC IS IN VOLTAGE MODE. 03796-023 ARNG R2 AOUT 8-BIT DAC Calculate R2 for the minimum value of VOUT, when the DAC has no effect: Figure 44. Using the DAC to Adjust LCD Contrast The circuit operates as follows. If the DAC is in current mode when the DAC output is zero, it has no effect on the feedback loop. Irrespective of what the DAC does, the feedback loop maintains the voltage across R4, VFB, equal to VREF, and the output voltage VOUT is VREF × (R2 + R3)/R3 As the DAC output is increased, it increases the feedback current, so the voltage across R2 and, therefore, the output voltage also increase. Note that the voltage across R3 does not change. This is important for calculation of the adjustment range. IFB = 1.25 V/12 kΩ = 104 µA 4. R2 = (20 V − 1.25 V)/104 µA = 180 kΩ. 5. ∆I = 23.75 V/180 kΩ − 18.75 V/180 kΩ = 28 µA. 6. RRNG = 5 V/(6 × 28 µA) = 30 kΩ. In voltage mode, the circuit operation depends on whether the maximum output voltage of the DAC exceeds the dc–dc converter VREF. When the DAC output voltage is zero, it sinks the maximum current through R1. The feedback current, and, therefore, VOUT are at their maximum. As the DAC output voltage increases, the sink current and, therefore, the feedback current decrease, and Rev. A | Page 26 of 44 AD7877 VOUT falls. If the DAC output exceeds VREF, it starts to source current, and VOUT has to further decrease to compensate. When the DAC output is at full scale, VOUT is at its minimum. Note that the effect of the DAC on VOUT is opposite in voltage mode to that in current mode. In current mode, increasing DAC code increases the sink current, so VOUT increases with increasing DAC code. In voltage mode, increasing DAC code increases the DAC output voltage, reducing the sink current. 5. R1 = VFS/∆. 6. Calculate R3 from R1 and R using R3 = (R1 × RP)/(R1 − RP) Example: 1. VCC = 5 V and VFS = VCC. VOUT(MIN) is 20 V and VOUT(MAX) is 25 V. VREF is 1.25 V. Allow 100 µA around the feedback loop. Calculate the resistor values as follows: 1. Decide on the feedback current as before. 2. RP = 1.25 V/100 µA = 12.5 kΩ. 2. Calculate the parallel combination of R1 and R3 when the DAC output is zero: 3. R2 = 12.5 kΩ × (25 Ω − 1.25 Ω)/1.25 Ω = 237 kΩ. RP = VREF/IFB 4. ∆I = 25 V/240 kΩ − 20 V/240 kΩ = 21 µA. Calculate R2 as before, but use RP and VOUTMAX: 5. R1 = 5 V/21 µA = 238 kΩ. 3. Use nearest preferred value of 240 kΩ. R2 = RP(VOUT(MAX) − VREF)/VREF 4. Use nearest preferred value of 250 kΩ. Calculate the change in feedback current between minimum and maximum output voltages as before using 6. R3 = (180 kΩ × 12.5 kΩ)/(180 kΩ − 12.5 kΩ) =13.4 kΩ. Use nearest preferred value of 13 kΩ. ∆I = VR2(MAX)/R2 − VR2(MIN)/R2 This is equal to the change in current through R1 between zero output and full scale, which is also given by The actual adjustment range using these values is 21 V to 26 V. ∆I = current at zero − current at full scale = V/R1 − (VREF − V)/R1 = V/R1 Rev. A | Page 27 of 44 AD7877 SERIAL INTERFACE The AD7877 is controlled via a 3-wire serial peripheral interface (SPI). The SPI has a data input pin (DIN) for inputting data to the device, a data output pin (DOUT) for reading data back from the device, and a data clock pin (DCLK) for clocking data into and out of the device. A chip-select pin (CS) enables or disables the serial interface. Register Address 1111b is not a physical register, but enables an extended writing mode that allows writing to the GPIO configuration registers. When the register address is 1111b, the next four bits of the data-word are the address of a GPIO configuration register and the eight LSBs are the GPIO configuration data. For details on the configuration of the GPIO pins, see the General-Purpose I/O Pins section. WRITING DATA Register Address 0001b is a physical register, Control Register 1, but this is a special register. It contains data for setting up the ADC channel and operating mode, but Bits 20 to 6 are the register address for reading. These define which register is read back during the next read operation. Control Register 1 should be the last register in the AD7877 to be programmed before starting a conversion. The three types of data-words used for writing are shown in Figure 45. Data is written to the AD7877 in 16-bit words. The first four bits of the word are the register address, which tells the AD7877 which register to write to. The next 12 bits are data. How the AD7877 handles the data bits depends on the register address. Register Address 0000b is a dummy address, which does nothing. Register addresses from 0010b to 1110b are 12-bit registers that perform various functions as described in the register map. 16-BIT DATA-WORD D15 D14 D13 D12 D11 D10 D9 WADD3 WADD2 WADD1 WADD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 RADD0 MODE 1 MODE 0 WRITING TO A REGISTER D8 D7 4-BIT REGISTER WRITE ADDRESS 12 BITS DATA EXTENDED WRITE OPERATION TO GPIO REGISTERS 1 1 1 1 EADD3 EXTENDED WRITE ADDRESS EADD2 EADD1 EADD0 D7 D6 D5 4-BIT EXTENDED ADDRESS 8 BITS GPIO DATA WRITING TO CONTROL REGISTER 1 TO SET ADC CHANNEL, MODE, AND READ REGISTER ADDRESS 0 0 0 0 SER/DFR CHADD3 CHADD2 CHADD1 CHADD0 CONTROL REGISTER 1 ADDRESS RADD4 ADC CHANNEL ADDRESS RADD3 RADD2 RADD1 5-BIT READ REGISTER ADDRESS OPERATING MODE 03796-024 NORMAL (SINGLE-ENDED)/ RATIOMETRIC (DIFFERENTIAL) CONVERSION Figure 45. Designation of Data-Word Bits in AD7877 Write Operations CS 1 16 1 16 DCLK 0000 + 12-BIT DATA3 DOUT1 HIGH-Z 0000 + 12-BIT DATA3 D15 D0 HIGH-Z D15 REGISTER n DATA4 D0 REGISTER n + 1 DATA4 4-BIT ADDRESS + 12-BIT DATA D15 D0 NOTES: 1DATA IS CLOCKED OUT ON THE FALLING EDGE OF DCLK. 2INPUT DATA IS SAMPLED ON THE RISING EDGE OF DCLK. 3FOR 8-BIT REGISTERS, 8 LEADING ZEROS PRECEDE 8 BITS OF DATA. 4REGISTER READ ADDRESS INCREMENTS AUTOMATICALLY, PROVIDED THAT A NEW ADDRESS IS NOT WRITTEN TO CONTROL REGISTER 1. Figure 46. Overall Read/Write Timing Rev. A | Page 28 of 44 03796-025 DIN2 AD7877 WRITE TIMING No serial interface operations can take place while CS is high. To write to the AD7877, CS must be taken low. To write to the device, a burst of 16 clock pulses is input to DCLK while the write data is input to DIN. Data is clocked in on the rising edge of DCLK. If multiple write operations are to be performed, CS must be taken high after the end of each write operation before another write operation can be performed by taking CS low again. READING DATA Data is available on the DOUT pin following the falling edge of CS, when the device is being clocked. The MSB is clocked out on the falling edge of CS, with subsequent data bits clocked out on the falling edge of DCLK. After CS is taken low and the device is clocked, the AD7877 outputs data from the register whose read address is currently stored in Control Register 1. Once this data has been output, the address increments automatically. CS must be taken high between reads. When CS is taken low again, reading continues from the register whose read address is in Control Register 1, provided that a write operation does not change the address. If the register read address reaches 11111b, it is then reset to zero. This feature allows all registers to be read out in sequence without having to explicitly write all their addresses to the device. Note that because data-words are 16 bits long, but the data registers are only 12 bits long, or 8 bits in the case of GPIO registers, the first four bits of a readback data-word are zeros, or the first 8 bits in the case of a GPIO register. VDRIVE PIN The supply voltage to all pins associated with the serial interface (DAV, DIN, DOUT, DCLK, CS, PENIRQ, and ALERT) is separate from the main VCC supply and is connected to the VDRIVE pin. This allows the AD7877 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7877, in fact, as low as 1.7 V. Rev. A | Page 29 of 44 AD7877 GENERAL-PURPOSE I/O PINS The AD7877 has one dedicated general-purpose logic input/ output pin (GPIO4), and any or all of the three auxiliary analog inputs can also be reconfigured as GPIOs. Associated with the GPIOs are two 8-bit control registers and one 8-bit data register, which are accessed using the extended write mode. As mentioned previously, GPIO registers are written to using the extended writing mode. The first four bits of the data-word must be 1111b to access the extended writing map, and the next four bits are the GPIO register address. This leaves 8 bits for the GPIO register data, because all GPIO registers are 8 bits. The GPIO control registers are located at Extended Writing Map Addresses 0000b and 0001b, and the GPIO data register is at Address 0010b. GPIO registers are read in the same way as other registers, by writing a 5-bit address to Control Register 1. The GPIO registers are located at Read Addresses 11011b to 11101b. GPIO CONFIGURATION Each GPIO pin is configured by four bits in one of the GPIO control registers and has a data bit in the GPIO data register. The GPIO configuration bits are described in the following sections and in Table 12. Also see the Detailed Register Descriptions section. Enable—EN These bits enable or disable the GPIO pins. When EN = 0, the corresponding GPIO pin is configured as the alternate function (AUX input). The other GPIO configuration bits have no effect, if the particular GPIO is not enabled. When EN = 1, the pin is configured as a GPIO pin. GPIO4, which does not have an alternate function, does not have an EN bit; it is always enabled. Direction—DIR These bits set the direction of the GPIO pins. When DIR = 0, the pin is an output. Setting or clearing the relevant bit in the GPIO data register outputs a value on the corresponding GPIO pin. The output value depends on the POL bit. If POL = 1 and DIR = 0, a 1 in the GPIO data register bit puts a 1 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 0 on the GPIO output pin. If POL = 0 and DIR = 1, a 1 at the input pin sets the corresponding GPIO data bit to 0. A 0 at the input pin clears the corresponding GPIO data bit to 1. If POL = 0 and DIR = 0, a 1 in the GPIO data register bit puts a 0 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 1 on the GPIO output pin. Alert Enable—ALEN GPIOs can operate as interrupt sources to trigger the ALERT output. This is controlled by the alert enable (ALEN) bits in the GPIO configuration registers. When ALEN = 1, the corresponding GPIO can trigger an ALERT. When ALEN = 0, the corresponding GPIO cannot cause the ALERT output to assert. ALERT is asserted low, if any GPIO data register bit is set when the GPIO is configured as an input. The GPIO data bit is set, if a 1 appears on the GPIO input pin when POL = 1, or if a 0 appears on the GPIO input pin when POL = 0. Note that ALERT is triggered only when the GPIO is configured as an input, that is, when DIR = 1. ALERT can never be triggered by a GPIO that is configured as an output, that is, DIR = 0. ALERT Output The ALERT pin is an alarm or interrupt output that goes low, if any one of a number of interrupt sources is asserted. The results of high and low limit comparisons on the AUX1, BAT1, BAT2, and TEMP1 channels are interrupt sources. An out-of-limit comparison sets a status bit in the alert status/mask register (Address 00011b).There are separate status bits for both the high and low limits on each channel to indicate which limit was exceeded. The interrupt sources can be masked out by clearing the corresponding enable bit in this register. There is one enable bit per channel. ALERT is also asserted, if an input on a GPIO pin sets a bit in the GPIO data register, as explained in the previous section. GPIO interrupts can be disabled by clearing the corresponding ALEN bit in the GPIO control registers. When DIR = 1, the pin is an input. An input value on the relevant GPIO pin sets or clears the corresponding bit in the GPIO data register, depending on the POL bit. A GPIO data register bit is read-only when DIR = 1 for that GPIO. Polarity—POL When POL = 0, the GPIO pin is active low. When POL = 1, the GPIO pin is active high. How this bit affects the GPIO operation also depends on the DIR bit. If POL = 1 and DIR = 1, a 1 at the input pin sets the corresponding GPIO data register bit to 1. A 0 at the input pin clears the corresponding GPIO data bit to 0. The interrupt source can be identified by reading the GPIO data register and the alert status/enable register. ALERT remains asserted until the source of the interrupt has been masked out or removed. If the ALERT source is a GPIO, then masking out the interrupt by clearing the corresponding ALEN bit to 0 or removing the source of the interrupt on the GPIO pin causes ALERT to go high again. Rev. A | Page 30 of 44 AD7877 If the ALERT source is an out-of-limit measurement, writing a 0 to the corresponding status bit in the alert status/enable register causes ALERT to go high. However, the status bit is set to 1 again on the next measurement cycle, if the measurement remains out of limit. The ALERT source can also be masked by clearing the relevant bit in the alert status/enable register to 0. Table 12. GPIO Configuration EN DIR 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 POL X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Data Bit1 ALEN X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 Shaded data values indicate that a change in input voltage on the pin causes a change in the data register bit. Shaded pin voltage values indicate that a change in the data register causes a change in the output voltage on the pin. Rev. A | Page 31 of 44 Pin Voltage2 X 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 ALERT X 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 AD7877 GROUNDING AND LAYOUT It is recommended that the ground pins, AGND and DGND, be shorted together as close as possible to the device itself on the user’s PCB. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. For more information on grounding and layout considerations for the AD7877, refer to the Layout and Grounding Recommendations for Touch Screen Digitizers Technical Note. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGES The lands on the chip scale package (CP-32) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The user should connect the printed circuit board thermal pad to AGND. TO LCD BACKLIGHT VIN OUT FB DC-DC CONVERTER RRNG NC HOST INT1 ALERT 22 AD7877 INT2 GPIO 4 AUX3/GPIO3 5 AUX2/GPIO2 STOPACQ 20 MISO 6 AUX1/GPIO1 DIN 19 MOSI 7 VCC 8 NC GPIO4 21 AGND DGND 9 10 11 12 13 14 15 PENIRQ 17 SCLK CS PENIRQ NC Y+ CS 18 X+ 1.0µF–10µF (OPTIONAL) NC 24 DAV 23 Y– 16 HSYNC SIGNAL FROM LCD NC = NO CONNECT TOUCH SCREEN Figure 47. Typical Application Circuit Rev. A | Page 32 of 44 03796-026 TEMPERATURE MEASUREMENT DIODE 25 DCLK BAT1 26 DOUT 3 27 ARNG BAT2 28 VDRIVE NC 2 0.1µF MAIN BATTERY VREF 1 29 X– VOLTAGE REGULATOR 30 SPI INTERFACE FROM AUDIO REMOTE CONTROL FROM HOTSYNC INPUTS 31 NC SECONDARY BATTERY 32 AOUT 0.1µF NC VCC AD7877 REGISTER MAPS Table 13. Write Register Map WADD3 0 0 Register Address Binary WADD2 WADD1 WADD0 0 0 0 0 0 1 HEX 0 1 Register Name None Control Register 1 0 0 1 0 2 Control Register 2 0 0 1 1 3 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 4 5 6 7 8 9 A B C 1 1 0 1 D 1 1 1 1 1 1 0 1 E F Alert Status/Enable Register AUX1 High Limit AUX1 Low Limit BAT1 High Limit BAT1 Low Limit BAT2 High Limit BAT2 Low Limit TEMP1 Low Limit TEMP1 High Limit Sequencer Register 0 Sequencer Register 1 DAC Register Extended Write Description Unused. Writing to this address has no effect. Contains ADC channel address, register read address, and ADC mode. Contains ADC averaging, acquisition time, power management, first conversion delay, STOPACQ polarity, and reference and timer settings. Contains status of high/low limit comparisons for TEMP1, BAT1, BAT2, and AUX1, and enable bits to allow these channels to become interrupt sources. User-programmable AUX1 upper limit. User-programmable AUX1 lower limit. User-programmable BAT1 upper limit. User-programmable BAT1 lower limit. User-programmable BAT2 upper limit. User-programmable BAT2 lower limit. User-programmable TEMP1 lower limit. User-programmable TEMP1 upper limit. Contains channel selection data for slave mode (software) sequencing. Contains channel selection data for master mode (hardware) sequencing. Contains DAC data and setup information. Not a physical register. Enables writing to extended writing map. Table 14. Extended Writing Map EADD3 0 Register Address Binary EADD2 EADD1 EADD0 0 0 0 HEX 0 0 0 0 1 1 0 0 1 0 2 Register Name GPIO Control Register 1 GPIO Control Register 2 GPIO Data Description Contains polarity, direction, enabling, and interrupt enabling settings for GPIO1 and GPIO2. Contains polarity, direction, enabling, and interrupt enabling settings for GPIO3 and GPIO4. Contains GPIO1 to GPIO4 data. Rev. A | Page 33 of 44 AD7877 Table 15. Read Register Map RADD4 0 0 0 0 RADD3 0 0 0 0 Register Address Binary RADD2 RADD1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Register Name None Control Register 1 Control Register 2 Alert Status/Enable Register AUX1 High Limit AUX1 Low Limit BAT1 High Limit BAT1 Low Limit BAT2 High Limit BAT2 Low Limit TEMP1 Low Limit TEMP1 High Limit Sequencer Register 0 Sequencer Register 1 DAC Register None X+ Y+ Y− (Z2) 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 13 14 15 16 17 18 19 1A AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) 1 1 0 1 1 1B 1 1 1 0 0 1C 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1D 1E 1F GPIO Control Register 1 GPIO Control Register 2 GPIO Data Register None None RADD0 0 1 0 1 HEX 00 01 02 03 Rev. A | Page 34 of 44 Description Reads back all zeros. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. See Table 13. Factory use only. Measurement at X+ input for Y position. Measurement at Y+ input for X position. Measurement at Y− input for touch-pressure calculation Z2. Auxiliary Input 1 measurement. Auxiliary Input 2 measurement. Auxiliary Input 3 measurement. Battery Input 1 measurement. Battery Input 1 measurement. Single-ended temperature measurement. Differential temperature measurement. Measurement at X+ input for touch-pressure calculation Z1. See Table 13. See Table 13. See Table 13. Factory use only. Factory use only. AD7877 DETAILED REGISTER DESCRIPTIONS Register Name: Control Register 1 Write Address: 0001; Read Address: 00001; Default Value: 0x000; Type: Read/Write. Table 16. Bit 0 1 Name MODE0 MODE1 Read/ Write R/W R/W 2 3 4 5 6 7 8 9 10 RD0 RD1 RD2 RD3 RD4 CHADD0 CHADD1 CHADD2 CHADD3 R/W R/W R/W R/W R/W R/W R/W R/W R/W 11 SER/DFR R/W Description LSB of ADC mode code MSB of ADC mode code 00 = No conversion 01 = Single conversion 10 = Conversion sequence (slave mode) 11 = Conversion sequence (master mode) LSB of register read address. To read a register, its address must first be written to Control Register 1. Bit 1 of register read address. To read a register, its address must first be written to Control Register 1. Bit 2 of register read address. To read a register, its address must first be written to Control Register 1. Bit 3 of register read address. To read a register, its address must first be written to Control Register 1. MSB of register read address. To read a register, its address must first be written to Control Register 1. LSB of ADC channel address Bit 1 of ADC channel address Bit 2 of ADC channel address MSB of ADC channel address 0000 = X+ input (Y position) 0001 = Y+ input (X position) 0010 = Y− (Z2) input (used for touch-pressure calculation) 0011 = Auxiliary Input 1 (AUX1) 0100 = Auxiliary Input 2 (AUX2) 0101 = Auxiliary Input 3 (AUX3) 0110 = Battery Monitor Input 1 (BAT1) 0111 = Battery Monitor Input 2 (BAT2) 1000 = Temperature Measurement 1 (used for single conversion) 1001 = Temperature Measurement 2 (used for differential measurement method) 1010 = X+ (Z1) input (used for touch-pressure calculation) Selects normal (single-ended) or ratiometric (differential) conversion 0 = Ratiometric (differential) 1 = Normal (single-ended) Rev. A | Page 35 of 44 AD7877 Register Name: Control Register 2 Write Address: 0010; Read Address: 00010; Default Value: 0x000. Table 17. Bit 0 1 Name TMR0 TMR1 Read/ Write R/W R/W 2 REF R/W 3 POL R/W 4 5 FCD0 FCD1 R/W R/W 6 7 PM0 PM1 R/W R/W 8 9 ACQ0 ACQ1 R/W R/W 10 11 AVG0 AVG1 R/W R/W Description LSB of conversion interval timer MSB of conversion interval timer 00 = Convert only once 01 = Every 1024 clock periods (512 µs) 10 = Every 2048 clock periods (1.024 ms) 11 = Every 16384 clock periods (8.19 ms) Selects internal or external reference 0 = Internal reference 1 = External reference Indicates polarity of signal on STOPACQ pin 0 = Active low 1 = Active high LSB of first conversion delay MSB of first conversion delay This delay occurs before the first conversion after powering up the ADC, before converting the X and Y coordinate channels to allow settling, and after the last conversion to allow PENIRQ precharge. 00 = 1 clock period delay (500 ns) 01 = 256 clock periods delay (128 µs) 10 = 2048 clock periods delay (1.024 ms) 11 = 16384 clock periods delay (8.19 ms) LSB of ADC power management code MSB of ADC power management code 00 = ADC and reference powered down continuously 01 = ADC and reference* powered down when not converting 10 = ADC and reference* powered up continuously 11 = ADC powered down when not converting, reference* powered up *Irrespective of PM bits, reference is always powered down, if REF bit is 1. LSB of ADC acquisition time MSB of ADC acquisition time 00 = 4 clock periods (2 µs) 01 = 8 clock periods (4 µs) 10 = 16 clock periods (8 µs) 11 = 32 clock periods (16 µs) LSB of ADC averaging code MSB of ADC averaging code 00 = No averaging (1 conversion per channel) 01 = 4 measurements per channel averaged 10 = 8 measurements per channel averaged 11 = 16 measurements per channel averaged Rev. A | Page 36 of 44 AD7877 Register Name: Alert Status/Enable Register Write Address: 0011; Read Address: 00011; Default Value: 0x000. Table 18. Bit 0 1 2 3 4 5 6 7 8 Name AUX1LO BAT1LO BAT2LO TEMP1HI AUX1HI BAT1HI BAT2HI TEMP1LO AUX1EN Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 1, the AUX1 channel is below its low limit. When this bit is 1, the BAT1 channel is below its low limit. When this bit is 1, the BAT2 channel is below its low limit. When this bit is 1, the TEMP1 channel is below its high limit. When this bit is 1, the AUX1 channel is above its high limit. When this bit is 1, the BAT1 channel is above its high limit. When this bit is 1, the BAT2 channel is above its high limit. When this bit is 1, the TEMP1 channel is above its low limit. Setting this bit enables AUX1 as an interrupt source to the ALERT output. 9 BAT1EN R/W Setting this bit enables BAT1 as an interrupt source to the ALERT output. 10 BAT2EN R/W Setting this bit enables BAT2 as an interrupt source to the ALERT output. 11 TEMP1EN R/W Setting this bit enables TEMP1 as an interrupt source to the ALERT output. Register Name: AUX1 High Limit Write Address: 0100; Read Address: 00100; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit high limit for Auxiliary Input 1. Register Name: AUX1 Low Limit Write Address: 0101; Read Address: 00101; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit low limit for Auxiliary Input 1. Register Name: BAT1 High Limit Write Address: 0110; Read Address: 00110; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit high limit for Battery Monitoring Input 1. Register Name: BAT1 Low Limit Write Address: 0111; Read Address: 00111; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit low limit for Battery Monitoring Input 1. Register Name: BAT2 High Limit Write Address: 1000; Read Address: 01000; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit high limit for Battery Monitoring Input 2. Register Name: BAT2 Low Limit Write Address: 1001; Read Address: 01001; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit low limit for Battery Monitoring Input 2. Register Name: TEMP1 Low Limit Write Address: 1010; Read Address: 01010; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit low limit for temperature measurement. Register Name: TEMP1 High Limit Write Address: 1011; Read Address: 01011; Default Value: 0x000; Type: Read/Write. This register contains the 12-bit high limit for temperature measurement. Rev. A | Page 37 of 44 AD7877 Register Name: Sequencer Register 0 Write Address: 1100; Read Address: 01100; Default Value: 0x000. Table 19. Bit 0 1 2 3 Name Not Used Z1_SS TEMP2_SS TEMP1_SS Read/ Write R/W R/W R/W R/W 4 5 6 7 8 9 10 11 BAT2_SS BAT1_SS AUX3_SS AUX2_SS AUX1_SS Z2_SS XPOS_SS YPOS_SS R/W R/W R/W R/W R/W R/W R/W R/W Description This bit is not used. Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a slave mode sequence. Setting this bit includes a temperature measurement using differential conversion in a slave mode sequence. Setting this bit includes a temperature measurement using single-ended conversion in a slave mode sequence. Setting this bit includes measurement of Battery Monitor Input 2 in a slave mode sequence. Setting this bit includes measurement of Battery Monitor Input 1 in a slave mode sequence. Setting this bit includes measurement of Auxiliary Input 3 in a slave mode sequence. Setting this bit includes measurement of Auxiliary Input 2 in a slave mode sequence. Setting this bit includes measurement of Auxiliary Input 1 in a slave mode sequence. Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a slave mode sequence. Setting this bit includes measurement of the X position (Y+ input) in a slave mode sequence. Setting this bit includes measurement of the Y position (X+ input) in a slave mode sequence. Register Name: Sequencer Register 1 Write Address: 1101; Read Address: 01101; Default Value: 0x000. Table 20. Bit 0 1 2 Name Not Used Z1_MS TEMP2_MS Read/ Write R/W R/W R/W 3 TEMP1_MS R/W 4 5 6 7 8 9 10 11 BAT2_MS BAT1_MS AUX3_MS AUX2_MS AUX1_MS Z2_MS XPOS_MS YPOS_MS R/W R/W R/W R/W R/W R/W R/W R/W Description This bit is not used. Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a master mode sequence. Setting this bit includes a temperature measurement using differential conversion in a master mode sequence. Setting this bit includes a temperature measurement using single-ended conversion in a master mode sequence. Setting this bit includes measurement of Battery Monitor Input 2 in a master mode sequence. Setting this bit includes measurement of Battery Monitor Input 1 in a master mode sequence. Setting this bit includes measurement of Auxiliary Input 3 in a master mode sequence. Setting this bit includes measurement of Auxiliary Input 2 in a master mode sequence. Setting this bit includes measurement of Auxiliary Input 1 in a master mode sequence. Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a master mode sequence. Setting this bit includes measurement of the X position (Y+ input) in a master mode sequence. Setting this bit includes measurement of the Y position (X+ input) in a master mode sequence. Rev. A | Page 38 of 44 AD7877 Register Name: DAC Register Write Address: 1110; Read Address: 01110; Default Value: 0x000. Table 21. Bit 0 Name RANGE Read/ Write R/W 1 2 Not Used V/I R/W R/W 3 PD R/W 4 5 6 7 8 9 10 11 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 Description Output range of the DAC in voltage mode 0 = 0 to VCC/2 1 = 0 to VCC This bit is not used. Voltage output and current output 0 = Voltage 1 = Current DAC power-down 0 = DAC on 1 = DAC powered down LSB of DAC data Bit 1 of DAC data Bit 2 of DAC data Bit 3 of DAC data Bit 4 of DAC data Bit 5 of DAC data Bit 6 of DAC data MSB of DAC data Register Name: Y Position Write Address: N/A; Read Address: 10000; Default Value: 0x000; Type: Read Only. This register contains the 12-bit result of the measurement at the X+ input with Y layer excited (Y position measurement). Register Name: X Position Write Address: N/A; Read Address: 10001; Default Value: 0x000; Type: Read Only. This register contains the 12-bit result of the measurement at the Y+ input with X layer excited (X position measurement). Register Name: Z2 Write Address: N/A; Read Address: 10010; Default Value: 0x000; Type: Read Only. This register contains the 12-bit result of the measurement at the Y− input with excitation voltage applied to Y+ and X− (used for touchpressure calculation). Register Name: AUX1 Write Address: N/A; Read Address: 10011; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of the measurement at Auxiliary Input 1. Register Name: AUX2 Write Address: N/A; Read Address: 10100; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of the measurement at Auxiliary Input 2. Register Name: AUX3 Write Address: N/A; Read Address: 10101; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of the measurement at Auxiliary Input 3. Rev. A | Page 39 of 44 AD7877 Register Name: BAT1 Write Address: N/A; Read Address: 10110; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of the measurement at Battery Monitor Input 1. Register Name: BAT2 Write Address: N/A; Read Address: 10111; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of the measurement at Battery Monitor Input 2. Register Name: TEMP1 Write Address: N/A; Read Address: 11000; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of a temperature measurement using single-ended conversion. Register Name: TEMP2 Write Address: N/A; Read Address: 11001; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of a temperature measurement using a differential conversion. Register Name: Z1 Write Address: N/A; Read Address: 11010; Default Value: 0x000; Type: Read Only. This register continues the 12-bit result of a measurement at the X+ input with excitation voltage applied to Y+ and X− (used for touchpressure calculation). Rev. A | Page 40 of 44 AD7877 GPIO REGISTERS GPIO registers are written to using an extended 8-bit address. The first four bits of the data-word are always 1111b to access the extended writing map. The next four bits are the register address. This leaves 8 bits for the GPIO data. GPIO registers are read like all other registers, by writing a 5-bit address to Control Register 1, then reading DOUT. See the GPIO Configuration section for information on configuring the GPIOs. Register Name: GPIO Control Register 1 Write Address: [1111] 0000; Read Address: 11011; Default Value: 0x000. Table 22. Bit 0 Name GPIO2_ALEN Read/ Write R/W 1 GPIO2_DIR R/W 2 GPIO2_POL R/W 3 GPIO2_EN R/W 4 GPIO1_ALEN R/W 5 GPIO1_DIR R/W 6 GPIO1_POL R/W 7 GPIO1_EN R/W Description If this bit is 1, GPIO2 is an interrupt source for the ALERT output. Clearing this bit masks out GPIO2 as an interrupt source for the ALERT output. This bit sets the direction of GPIO2. 0 = Output 1 = Input This bit determines if GPIO2 is active high or low. 0 = Active low 1 = Active high This bit selects the function of AUX2/GPIO2. 0 = AUX2 1 = GPIO2 If this bit is 1, GPIO1 is an interrupt source for the ALERT output. Clearing this bit masks out GPIO1 as an interrupt source for the ALERT output. This bit sets the direction of GPIO1. 0 = Output 1 = Input This bit determines if GPIO1 is active high or low. 0 = Active low 1 = Active high This bit selects the function of AUX1/GPIO1. 0 = AUX1 1 = GPIO1 Rev. A | Page 41 of 44 AD7877 Register Name: GPIO Control Register 2 Write Address: [1111] 0001; Read Address: 11100; Default Value: 0x000. Table 23. Bit 0 Name GPIO4_ALEN Read/ Write R/W 1 GPIO4_DIR R/W 2 GPIO4_POL R/W 3 4 Not Used GPIO3_ALEN R/W 5 GPIO3_DIR R/W 6 GPIO3_POL R/W 7 GPIO3_EN R/W Description If this bit is 1, GPIO4 is an interrupt source for the ALERT output. Clearing this bit masks out GPIO3 as an interrupt source for the ALERT output. This bit sets the direction of GPIO4. 0 = Output 1 = Input This bit determines if GPIO4 is active high or low. 0 = Active low 1 = Active high This bit is not used. If this bit is 1, GPIO3 is an interrupt source for the ALERT output. Clearing this bit masks out GPIO4 as an interrupt source for the ALERT output. This bit sets the direction of GPIO3. 0 = Output 1 = Input This bit determines if GPIO3 is active high or low. 0 = Active low 1 = Active high This bit selects the function of AUX3/GPIO3. 0 = AUX3 1 = GPIO3 Register Name: GPIO Data Register Write Address: [1111] 0010; Read Address: 11101; Default Value: 0x000. Table 24. Bit 0 1 2 3 4 5 6 7 Name Not Used Not Used Not Used Not Used GPIO4_DAT GPIO3_DAT GPIO2_DAT GPIO1_DAT Read/ Write R/W R/W R/W R/W Description This bit is not used. This bit is not used. This bit is not used. This bit is not used. GPIO4 data bit. GPIO3 data bit. GPIO2 data bit. GPIO1 data bit. Rev. A | Page 42 of 44 AD7877 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 32 25 24 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 48. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD7877ACP-REEL AD7877ACP-REEL7 AD7877ACP-500RL7 AD7877ACPZ-REEL1 AD7877ACPZ-REEL7 1 AD7877ACPZ-500RL71 EVAL-AD7877EB 1 Operating Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Z = Pb-free part. Rev. A | Page 43 of 44 Package Description 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP Evaluation Board Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 AD7877 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03796–0–11/04(A) Rev. A | Page 44 of 44