Data Sheet Touch Screen Controller AD7877 FEATURES FUNCTIONAL BLOCK DIAGRAM 7 AD7877 X+ 12 X– 10 Y+ 13 Y– 11 X– Y– GND X+ Y+ VREF AUX1/GPIO1 DUAL 3-1 MUX 6 AUX2/GPIO2 5 REF– AUX3/GPIO3 4 BAT1 3 9 TO 1 INPUT MUX BATTERY MONITOR IN SEQUENCER BAT2 2 CLOCK STOP ACQ LOGIC 20 STOPACQ RESULTS REGISTERS BATTERY MONITOR LIMIT COMPARATOR LIMIT REGISTERS TEMPERATURE SENSOR 14 AGND 15 DGND VREF 31 ALERT STATUS/ MASK REGISTER 2.5V REF AOUT 30 ARNG 29 BUF CONTROL REGISTERS DAC REGISTER 8-BIT DAC ALERT LOGIC GPIO REGISTERS CONTROL LOGIC AND SERIAL PORT Personal digital assistants Smart hand-held devices Touch screen monitors Point-of-sale terminals Medical devices Cell phones Pagers REF+ 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD 18 19 23 26 27 28 CS DIN DAV DCLK DOUT VDRIVE 22 ALERT 21 GPIO4 TO GPIO1-3 PEN INTERRUPT AND WAKE-UP ON TOUCH 17 PENIRQ 03796-001 APPLICATIONS VCC ADC DATA 4-wire touch screen interface LCD noise reduction feature (STOPACQ pin) Automatic conversion sequencer and timer User-programmable conversion parameters On-chip temperature sensor: −40°C to +85°C On-chip 2.5 V reference On-chip 8-bit DAC 3 auxiliary analog inputs 1 dedicated and 3 optional GPIOs 2 direct battery measurement channels (0.5 V to 5 V) 3 interrupt outputs Touch-pressure measurement Wake up on touch function Specified throughput rate of 125 kSPS Single supply, VCC of 2.7 V to 5.25 V Separate VDRIVE level for serial interface Shutdown mode: 1 µA maximum 32-lead, LFCSP, 5 mm × 5 mm package 25-ball,WLCSP, 2.5 mm × 2.8 mm package Qualified for automotive applications Figure 1. GENERAL DESCRIPTION The AD7877 is a 12-bit, successive approximation ADC with a synchronous serial interface and low on resistance switches for driving touch screens. The AD7877 operates from a single 2.7 V to 5.25 V power supply (functional operation to 2.2 V), and features throughput rates of 125 kSPS. The AD7877 features direct battery measurement on two inputs, temperature and touch-pressure measurement. The AD7877 also has an on-board reference of 2.5 V. When not in use, it can be shut down to conserve power. An external reference can also be applied and varied from 1 V to +VCC, with an analog input range of 0 V to VREF. The device includes a shutdown mode that reduces its current consumption to less than 1 µA. Rev. E To reduce the effects of noise from LCDs, the acquisition phase of the on-board ADC is controlled via the STOPACQ pin. Userprogrammable conversion controls include variable acquisition time and first conversion delay. Up to 16 averages can be taken per conversion. There is also an on-board DAC for LCD backlight or contrast control. The AD7877 runs in either slave or master mode using a conversion sequencer and timer. It is ideal for battery-powered systems such as personal digital assistants with resistive touch screens and other portable equipment. The part is available in a 32-lead lead frame chip scale package (LFCSP), and a 25-ball wafer level chip scale package (WLCSP). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7877 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Registers ............................................................................ 20 Applications ....................................................................................... 1 Control Register 1 ...................................................................... 20 Functional Block Diagram .............................................................. 1 Control Register 2 ...................................................................... 21 General Description ......................................................................... 1 Sequencer Registers ................................................................... 22 Revision History ............................................................................... 2 Interrupts ..................................................................................... 24 Specifications..................................................................................... 3 Synchronizing the AD7877 to the Host CPU......................... 25 Timing Specifications .................................................................. 5 8-Bit DAC ........................................................................................ 26 Timing Diagrams.......................................................................... 5 Serial Interface ................................................................................ 28 Absolute Maximum Ratings ............................................................ 6 Writing Data ............................................................................... 28 ESD Caution .................................................................................. 6 Write Timing ............................................................................... 29 Pin Configurations and Function Descriptions ........................... 7 Reading Data ............................................................................... 29 Typical Performance Characteristics ............................................. 9 VDRIVE Pin ..................................................................................... 29 Terminology .................................................................................... 13 General-Purpose I/O Pins ............................................................. 30 Circuit Information ........................................................................ 14 GPIO Configuration .................................................................. 30 Touch Screen Principles ............................................................ 14 Grounding and Layout .................................................................. 32 Measuring Touch Screen Inputs ............................................... 15 PCB Design Guidelines for Chip Scale Packages ................... 32 Touch-Pressure Measurement .................................................. 16 Register Maps .................................................................................. 33 STOPACQ Pin ............................................................................ 16 Detailed Register Descriptions ..................................................... 35 Temperature Measurement ....................................................... 17 GPIO Registers ........................................................................... 42 Battery Measurement ................................................................. 18 Outline Dimensions ....................................................................... 44 Auxiliary Inputs .......................................................................... 19 Ordering Guide .......................................................................... 45 Limit Comparison ...................................................................... 19 Automotive Products ................................................................. 45 REVISION HISTORY 12/14—Rev. D to Rev. E Added Figure 50; Renumbered Sequentially .............................. 44 Updated Outline Dimensions ....................................................... 44 Changes to Ordering Guide .......................................................... 45 12/11—Rev. C to Rev. D Change to Features Section ............................................................. 1 Updated Outline Dimensions ....................................................... 44 Changes to Ordering Guide .......................................................... 44 Added Automotive Products Section........................................... 44 9/09—Rev. B to Rev. C Changes to Offset Error and Gain Error Parameters .................. 3 Added VBAT to GND Parameter ...................................................... 6 Changes to Pin 23 Description ....................................................... 7 Changes to Power Management (Control Register 2, Bits[7:6]) Section ............................................................................ 22 Changes to Bit 7 Description (Table 17) ...................................... 36 Updated Outline Dimensions ....................................................... 44 Changes Ordering Guide ............................................................... 44 6/06—Rev. A to Rev. B Added Wafer Level Chip Scale Package .......................... Universal Changes to Table 3.............................................................................6 Changes to Figure 21...................................................................... 11 Change to Figure 25 ....................................................................... 12 Changes to Figure 38 and Figure 39 ............................................ 23 Change to Figure 40 ....................................................................... 24 Changes to Data Available Output (DAV) Section .................... 24 Updated Outline Dimensions ....................................................... 42 Changes to Ordering Guide .......................................................... 42 11/04—Rev. 0 to Rev. A Changes to Absolute Maximum Ratings .......................................6 Changes to Figure 4 ...........................................................................7 Changes to Table 4.............................................................................7 Changes to Grounding and Layout section ................................ 32 Changes to Figure 42...................................................................... 32 Changes to Ordering Guide .......................................................... 43 7/04—Revision 0: Initial Version Rev. E | Page 2 of 45 Data Sheet AD7877 SPECIFICATIONS VCC = 2.7 V to 3.6 V, VREF = 2.5 V internal or external, fDCLK = 2 MHz, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter DC ACCURACY Resolution No Missing Codes Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1 Negative DNL Positive DNL Offset Error1 Gain Error1 Noise Power Supply Rejection Internal Clock Frequency SWITCH DRIVERS On Resistance1 Y+, X+ Y−, X− ANALOG INPUTS Input Voltage Ranges DC Leakage Current Input Capacitance Accuracy REFERENCE INPUT/OUTPUT Internal Reference Voltage Internal Reference Tempco VREF Input Voltage Range DC Leakage Current VREF Input Impedance TEMPERATURE MEASUREMENT Temperature Range Resolution Differential Method 2 Single Conversion Method 3 Accuracy Differential Method2 Single Conversion Method3 BATTERY MONITOR Input Voltage Range Input Impedance Accuracy Min Typ 12 11 12 Max Unit ±2 Bits Bits LSB −0.99 +2 ±5 ±3 70 70 2 LSB LSB LSB LSB µV rms dB MHz 14 14 Ω Ω 0 VREF ±0.1 30 0.3 2.44 2.55 ±50 1 VCC ±1 1 −40 +85 V µA pF % V ppm/°C V µA GΩ Test Conditions/Comments LSB size = 610 µV Minimum LSB size = 610 µV Specified for 11bits Specified for 11 bits; external reference All channels, internal VREF CS = GND or VCC; typically 25 Ω when the on-board reference is enabled °C 1.6 0.3 °C °C ±4 ±2 °C °C 0°C to 70°C Calibrated at 25°C V kΩ % @ VREF = 2.5 V Sampling, 1 GΩ when the battery monitor is off External/internal reference, see Figure 26 0.5 5 14 1 3.2 Rev. E | Page 3 of 45 AD7877 Parameter DAC Resolution Integral Nonlinearity Differential Nonlinearity Voltage Mode Output Voltage Range Slew Rate Output Settling Time Capacitive Load Stability Output Impedance Short-Circuit Current Current Mode Output Current Range Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Throughput Rate POWER REQUIREMENTS VCC (Specified Performance) VDRIVE ICC Converting Mode Static Shutdown Mode Data Sheet Min Typ Max Unit Test Conditions/Comments 8 ±1 ±1 Bits Bits 0 − VCC/2 0 − VCC −0.4, +0.5 12 50 75 21 V V V/µs µs pF kΩ mA DAC register Bit 2 = 0, Bit 0 = 0 DAC register Bit 2 = 0, Bit 0 = 1 µA DAC register, Bit 2 = 1; full-scale current is set by RRNG Power-down mode 0 Guaranteed monotonic by design 15 100 1000 Open 0.7 VDRIVE 0.3 VDRIVE ±1 10 VDRIVE − 0.2 0.4 ±10 10 0 to 3/4 scale, RLOAD = 10 kΩ, CLOAD = 50 pF RLOAD = 10 kΩ Power-down mode V V µA pF Typically 10 nA, VIN = 0 V or VCC V V µA pF ISOURCE = 250 µA, VCC/VDRIVE = 2.7 V to 5.25 V ISINK = 250 µA Straight (natural) binary 8 125 2.7 1.65 240 650 900 150 µs kSPS CS high to DAV low 3.6 VCC V V Functional from 2.2 V to 5.25 V 380 900 µA µA µA µA 1 µA See the Terminology section. Difference between Temp0 and Temp1 measurement. No calibration necessary. 3 Temperature drift is −2.1 mV/°C. 4 Sample tested @ 25°C to ensure compliance. 1 2 Rev. E | Page 4 of 45 Digital inputs = 0 V or VCC ADC on, internal reference off, VCC = 3.6 V ADC on, internal reference on, VCC = 3.6 V ADC on, internal reference on, DAC on ADC on, but not converting, internal reference off, VCC = 3.6 V Data Sheet AD7877 TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted, VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 2. Parameter fDCLK 1 t1 t2 t3 t4 t5 t6 2 t7 2 t8 3 t9 Limit at TMIN, TMAX 10 20 16 20 20 12 12 16 16 16 0 Unit kHz min MHz max ns min ns min ns min ns min ns min ns max ns max ns max ns min Description CS falling edge to first DCLK rising edge DCLK high pulse width DCLK low pulse width DIN setup time DIN hold time CS falling edge to DOUT, three-state disabled DCLK falling edge to DOUT valid CS rising edge to DOUT high impedance CS rising edge to DCLK ignored Mark/space ratio for the DCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 1 2 TIMING DIAGRAMS CS t1 t2 1 DCLK 2 t9 t3 3 15 16 t5 t4 MSB LSB t7 DOUT t8 MSB LSB Figure 2. Detailed Timing Diagram 200µA TO OUTPUT PIN IOL 1.6V CL 50pF 200µA IOH Figure 3. Load Circuit for Digital Output Timing Specifications Rev. E | Page 5 of 45 03796-004 t6 03796-003 DIN AD7877 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND VBAT to GND Input Current to Any Pin Except Supplies 1 ESD Rating (IEC 1000-4-2, Air Discharge) Tablet Pins (X+, X−, Y+, Y−) Other Pins Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Package Power Dissipation θJA Thermal Impedance IR Reflow Peak Temperature Pb-Free Parts Only Lead Temperature (Soldering 10 sec) 1 Rating −0.3 V to +7 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC +5 V 10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 4 kV 2 kV −40°C to +85°C −65°C to +150°C 150°C 450 mW 135.7°C/W 220°C 260°C (±0.5°C) 300°C Transient currents of up to 100 mA do not cause SCR latch-up. Rev. E | Page 6 of 45 Data Sheet AD7877 NC VREF AOUT ARNG VDRIVE DOUT DCLK NC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 PIN 1 NC NC 1 24 BAT2 2 23 DAV BAT1 3 22 ALERT 21 GPIO4 20 STOPACQ AUX1/GPIO1 6 19 DIN VCC 7 18 CS NC 8 17 PENIRQ AD7877 TOP VIEW (Not to Scale) DOUT VDRIVE ARNG AOUT ALERT GPIO4 DAV VREF BAT2 STOP ACQ DIN AUX2/ GPI02 BAT1 AUX3/ GPI03 CS PENIRQ AGND VCC AUX1/ GPI01 DGND Y+ X+ Y– X– 16 NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO GROUND PLANE. 03796-051 15 NC 14 DGND 13 AGND 12 Y+ 11 X+ 10 X– NC 9 Y– AUX2/GPIO2 5 AD7877 WLCSP TOP VIEW Not to Scale 03796-002 AUX3/GPIO3 4 DCLK Figure 5. WLCSP Pin Configuration Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 8, 9, 16, 24, 25, 32 2 3 4 5 6 7 10 11 12 13 14 Mnemonic NC Description No Connect. BAT2 BAT1 AUX3/GPIO3 AUX2/GPIO2 AUX1/GPIO1 VCC X− Y− X+ Y+ AGND 15 DGND 17 18 PENIRQ CS 19 DIN 20 STOPACQ 21 22 GPIO4 ALERT 23 DAV 26 27 DCLK DOUT Battery Monitor Input. ADC Input Channel 7. Battery Monitor Input. ADC Input Channel 6. Auxiliary Analog Input. ADC Input Channel 5. Can be reconfigured as GPIO pin. Auxiliary Analog Input. ADC Input Channel 4. Can be reconfigured as GPIO pin. Auxiliary Analog Input. ADC Input Channel 3. Can be reconfigured as GPIO pin. Power Supply Input. The VCC range for the AD7877 is from 2.2 V to 5.25 V. Touch Screen Position Input. Touch Screen Position Input. ADC Input Channel 2. Touch Screen Position Input. ADC Input Channel 0. Touch Screen Position Input. ADC Input Channel 1. Analog Ground. Ground reference point for all analog circuitry on the AD7877. All analog input signals and any external reference signal should be referred to this voltage. Digital Ground. Ground reference for all digital circuitry on the AD7877. Refer all digital input signals to this voltage. Pen Interrupt. Digital active low output (has a 50 kΩ internal pull-up resistor). Chip Select Input. Active low logic input. This input provides the dual function of initiating conversions on the AD7877 and enabling the serial input/output register. SPI® Serial Data Input. Data to be written to the AD7877 registers are provided on this input and clocked into the register on the rising edge of DCLK. Stop Acquisition Pin. A signal applied to this pin can be monitored by the AD7877, so that acquisition of new data by the ADC is halted while the signal is active. Used to reduce the effect of noise from an LCD screen on the touch screen measurements. Dedicated General-Purpose Logic Input/Output Pin. Digital Active Low Output. Interrupt output that goes low if a GPIO data bit is set, or if the AUX1, TEMP1, BAT1, or BAT2 measurements are out of range. Data Available Output. Active low logic output. Asserts low when new data is available in the AD7877 results registers. External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part. Serial Data Output. Logic output. The conversion result from the AD7877 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high. Rev. E | Page 7 of 45 AD7877 Data Sheet Pin No. 28 Mnemonic VDRIVE 29 30 31 ARNG AOUT VREF Description Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial interface of the AD7877. When the DAC is in current output mode, a resistor from ARNG to GND sets the output range. Analog Output Voltage or Current from DAC. Reference Output for the AD7877. The internal 2.5 V reference is available on this pin for use external to the device. The reference output must be buffered before it is applied elsewhere in a system. To reduce system noise effects, it is strongly recommended to place a capacitor of 100 nF between the VREF pin and GND. Alternatively, an external reference can be applied to this input. The voltage range for the external reference is 1.0 V to VCC. For the specified performance, it is 2.5 V on the AD7877. Rev. E | Page 8 of 45 Data Sheet AD7877 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 125 kHz, fDCLK = 16 × fSAMPLE = 2 MHz, unless otherwise noted. 800 200 ADC, REF, AND DAC 180 160 CURRENT (nA) CURRENT (A) 700 ADC AND REF 600 140 120 –30 –10 0 30 TEMPERATURE (C) 50 70 80 –50 90 Figure 6. Supply Current vs. Temperature 03796-032 500 –50 03796-030 100 –30 –10 10 30 TEMPERATURE (C) 50 70 90 Figure 9. Full Power-Down IDD vs. Temperature 1000 0.6 0.5 0.4 900 DELTA FROM 25C (LSB) ADC, REF, AND DAC 700 ADC AND REF 600 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 03796-031 500 400 2.0 0.3 2.3 2.6 2.9 3.2 3.5 3.8 VCC (V) 4.1 4.4 4.7 –0.5 –0.6 –50 5.0 Figure 7. Supply Current vs. VCC –10 10 30 TEMPERATURE (C) 50 70 90 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 INL (LSB) 0.1 0 –0.1 –0.2 0.2 0 –0.2 –0.4 –0.3 –0.5 –30 –10 10 30 TEMPERATURE (C) 50 70 03796-044 –0.6 –0.4 03796-039 DELTA FROM 25C (LSB) –30 Figure 10. Change in ADC Offset vs. Temperature 0.6 –0.6 –50 03796-040 CURRENT (A) 800 –0.8 –1.0 90 Figure 8. Change in ADC Gain vs. Temperature 0 500 1000 1500 2000 2500 CODE Figure 11. ACD INL Plot Rev. E | Page 9 of 45 3000 3500 4000 AD7877 Data Sheet 1.0 16 0.8 14 REFERENCE CURRENT (A) 0.6 0.2 0 –0.2 –0.4 –0.6 0 500 1000 1500 2000 2500 CODE 3000 3500 6 4 0 –50 4000 Figure 12. ADC DNL Plot –30 –10 10 30 TEMPERATURE (C) 50 70 90 Figure 15. External Reference Current vs. Temperature 22 2.520 20 2.515 2.510 18 X– TO GND 2.505 16 VREF (V) RON (Ω) 8 03796-046 –1.0 10 2 03796-045 –0.8 12 Y– TO GND 14 Y+ TO VCC 2.495 2.490 12 2.485 03796-048 10 X+ TO VCC 8 2.7 2.500 3.1 3.5 3.9 4.3 4.7 5.1 2.480 5.5 2.475 –50 VCC (V) Figure 13. Switch On Resistance vs. VCC (X+, Y+: VCC to Pin; X−, Y−: Pin to GND) 03796-033 DNL (LSB) 0.4 –30 –10 10 30 TEMPERATURE (C) 50 70 90 Figure 16. Internal VREF vs. Temperature 22 2.508 20 X– TO GND 2.506 18 VREF (V) Y– TO GND 14 Y+ TO VCC X+ TO VCC –20 0 20 40 60 2.498 2.496 2.6 80 TEMPERATURE (°C) Figure 14. Switch On Resistance vs. Temperature (X+, Y+: VCC to Pin; X−, Y−: Pin to GND) 03796-034 10 8 –40 2.502 2.500 12 03796-049 RON (Ω) 2.504 16 2.9 3.2 3.5 3.8 4.1 VCC (V) 4.4 Figure 17. Internal VREF vs. VCC Rev. E | Page 10 of 45 4.7 5.0 Data Sheet AD7877 3145 6 3135 3115 INTERNAL VREF (V) ADC CODE (Decimal) 3125 3105 3095 3085 3075 NO CAP 0.711µs SETTLING TIME 2.5 3065 3045 –50 –10 –30 10 30 TEMPERATURE (°C) 50 70 03796-047 03796-041 100nF CAP 54.64µs SETTLING TIME 3055 0 –20 90 0 20 40 60 80 100 120 TURN-ON TIME (µs) Figure 18. ADC Code vs. Temperature (2.7 V Supply) Figure 21. Internal VREF vs. Turn-On Time 1183 10 1182 INPUT TONE AMPLITUDE (dB) –10 1180 1179 1178 1176 2.7 03796-042 1177 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 SNR 70.25dB THD 78.11dB –30 –50 –70 –90 –110 –130 03796-035 TEMP1 CODE 1181 –150 3.6 0 Figure 19. Temp1 vs. VCC 10k 20k FREQUENCY 30k 40k Figure 22. Typical FFT Plot for the Auxiliary Channels of the AD7877 at 90 kHz Sample Rate and 10 kHz Input Frequency 982 3.50 3.25 981 DAC O/P SOURCE ABILITY 3.00 2.75 980 DAC O/P LEVEL (V) 979 978 977 2.00 1.75 1.50 1.25 1.00 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 0.50 03796-036 975 2.7 2.25 0.75 976 03796-043 TEMP0 CODE 2.50 DAC O/P SINK ABILITY 0.25 0 3.6 0 Figure 20. Temp0 vs. VCC 1 2 3 4 5 6 7 SOURCE/SINK CURRENT (mA) 8 9 Figure 23. DAC Source and Sink Current Capability Rev. E | Page 11 of 45 10 AD7877 Data Sheet : 144mV 03796-037 VDD = 3V TEMPERATURE = 25C 1 CH1 200mV CH2 100mV M2.00s CH1 03796-050 @: 1.296V –2 780mV Figure 24. DAC Output Settling Time (Zero Scale to Half Scale) 400 DAC SINK CURRENT 300 200 0 0 25 50 75 100 125 150 175 200 225 03796-038 DAC SINK CURRENT (µA) 500 NOTE: MAXIMUM DAC SINK CURRENT IS SET ACCORDING TO THE EQUATION: IMAX = VCC /(RRNG × 6) 0 ERROR (%) 1 Figure 26. Typical Accuracy for Battery Channel (25°C) 600 100 –1 250 INPUT CODE (Decimal) Figure 25. DAC Sink Current vs. Input Code with RRNG = 1 kΩ Rev. E | Page 12 of 45 2 Data Sheet AD7877 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at 1 LSB below the first code transition, and full scale at 1 LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00…000) to (00…001) from the ideal (AGND + 1 LSB). Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal (VREF − 1 LSB) after the offset error has been adjusted out. On Resistance A measure of the ohmic resistance between the drain and the source of the switch drivers. Rev. E | Page 13 of 45 AD7877 Data Sheet CIRCUIT INFORMATION The core of the AD7877 is a high speed, low power, 12-bit analog-to-digital converter (ADC) with input multiplexer, on-chip track-and-hold, and on-chip clock. The results of conversions are stored in 11 results registers, and the results from one auxiliary input and two battery inputs can be compared with high and low limits stored in limit registers to generate an out-of-limit ALERT. The AD7877 also contains low resistance analog switches to switch the X and Y excitation voltages to the touch screen, a STOPACQ pin to control the ADC acquisition period, 2.5 V reference, on-chip temperature sensor, and 8-bit DAC to control LCD contrast. The high speed SPI serial bus provides control of, and communication with, the device. Operating from a single supply from 2.2 V to 5 V, the AD7877 offers throughput rates of up to 125 kHz. The device is available in a 5 mm × 5 mm, 32-lead, lead frame chip scale package (LFCSP), and in a 2.5 mm × 2.8 mm, wafer level chip scale package (WLCSP), with a 5 × 5 ball grid array. The data acquisition system of the AD7877 has a number of advanced features: • Input channel sequenced automatically or selected by the host. • STOPACQ feature to reduce noise from LCD. • Averaging of from 1 to 16 conversions for noise reduction. • Programmable acquisition time. • Power management. • Programmable ADC power-up delay before first conversion. • Choice of internal or external reference. • Conversion at preprogrammed intervals. CONDUCTIVE ELECTRODE ON BOTTOM SIDE PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON BOTTOM SIDE Y+ X– Y– X+ CONDUCTIVE ELECTRODE ON TOP SIDE PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON TOP SIDE LCD SCREEN Figure 27. Basic Construction of a Touch Screen The Y layer has conductive electrodes running along the top and bottom edges, allowing the application of an excitation voltage down the Y layer from top to bottom. Provided that the layers are of uniform resistivity, the voltage at any point between the two electrodes is proportional to the horizontal position for the X layer and the vertical position for the Y layer. When the screen is touched, the two layers make contact. If only the X layer is excited, the voltage at the point of contact, and therefore the horizontal position, can be sensed at one of the Y layer electrodes. Similarly, if only the Y layer is excited, the voltage, and therefore the vertical position, can be sensed at one of the X layer electrodes. By switching alternately between X and Y excitation and measuring the voltages, the X and Y coordinates of the contact point can be found. In addition to measuring the X and Y coordinates, it is also possible to estimate the touch pressure by measuring the contact resistance between the X and Y layers. The AD7877 is designed to facilitate this measurement. TOUCH SCREEN PRINCIPLES A 4-wire touch screen consists of two flexible, transparent, resistive-coated layers that are normally separated by a small air gap. The X layer has conductive electrodes running down the left and right edges, allowing the application of an excitation voltage across the X layer from left to right. 03796-005 The AD7877 is a complete, 12-bit data acquisition system for digitizing positional inputs from a touch screen in PDAs and other devices. In addition, it can monitor two battery voltages, ambient temperature, and three auxiliary analog voltages, with high and low limit comparisons on three of the inputs, and has up to four general-purpose logic I/O pins. Figure 28 shows an equivalent circuit of the analog input structure of the AD7877, showing the touch screen switches, the main analog multiplexer, the ADC with analog and differential reference inputs, and the dual 3-to-1 multiplexer that selects the reference source for the ADC. Rev. E | Page 14 of 45 Data Sheet AD7877 VCC The voltage seen at the input to the ADC in Figure 29 is VIN = VCC × X+ X– REF INT/EXT Y+ Y– X– Y– GND X+ Y+ VREF DUAL 3-1 MUX 9 TO 1 I/P MUX AUX1/GPIO2 AUX2/GPIO3 AUX3/GPIO4 REF– IN+ BAT1 REF+ 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD TEMPERATURE SENSOR The disadvantages of the single-ended method are as follows: • It can be used only if VCC is close to VREF. If VCC is greater than VREF, some positions on the screen are outside the range of the ADC. If VCC is less than VREF, the full range of the ADC is not used. • The ratio of VCC to VREF must be known. If VREF and/or VCC vary relative to one another, this can introduce errors. • Voltage drops across the switches can introduce errors. Touch screens can have a total end-to-end resistance ranging from 200 Ω to 900 Ω. Taking the lowest screen resistance of 200 Ω and a typical switch resistance of 14 Ω can reduce the apparent excitation voltage to 200/228 × 100 = 87% of its actual value. In addition, the voltage drop across the low-side switch adds to the ADC input voltage. This introduces an offset into the input voltage, thus, it can never reach zero. Figure 28. Analog Input Structure The AD7877 can be set up to automatically convert either specific input channels or a sequence of channels. The results of the ADC conversions are stored in the results registers. See the Serial Interface section for details. When measuring the ancillary analog inputs (AUX1 to AUX3, BAT1 and BAT2), the ADC uses the internal reference, or an external reference applied to the VREF pin, and the measurement is referred to GND. MEASURING TOUCH SCREEN INPUTS When measuring the touch screen inputs, it is possible to measure using the internal (or external) reference, or to use the touch screen excitation voltage as the reference and perform a ratiometric, differential measurement. The differential method is the default and is selected by clearing the SER/DFR bit (Bit 11) in Control Register 1. The single-ended method is selected by setting this bit. Single-Ended Method Figure 29 illustrates the single-ended method for the Y position. For the X position, the excitation voltage is applied to X+ and X− and the voltage measured at Y+. The single-ended method is adequate for applications that use a fairly blunt and imprecise instrument for an input device, such as a finger. Ratiometric Method The ratiometric method illustrated in Figure 30 shows the negative input of the ADC reference tied to Y− and the positive input connected to Y+. Thus, the screen excitation voltage provides the reference for the ADC. The input of the ADC is connected to X+ to determine the Y position. VCC VCC Y+ (1) The advantage of the single-ended method is that the touch screen excitation voltage can be switched off once the signal is acquired. Because a screen can draw over 1 mA, this is a significant consideration for a battery-powered system. 03796-006 BAT2 RY − RYTOTAL Y+ VREF X+ X+ INPUT (VIA MUX) INPUT (VIA MUX) REF+ ADC REF+ TOUCH SCREEN ADC REF– Y– GND GND 03796-008 REF– Y– 03796-007 TOUCH SCREEN Figure 30. Ratiometric Conversion of Touch Screen Inputs Figure 29. Single-Ended Conversion of Touch Screen Inputs Rev. E | Page 15 of 45 AD7877 Data Sheet For greater accuracy, the ratiometric method has two significant advantages: TOUCH RESISTANCE The reference to the ADC is provided from the actual voltage across the screen; therefore, when the voltage drops across the switches, it has no effect. Because the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. However, it must not change after the signal has been acquired. X– Y– Y+ X+ MEASURE Z1 POSITION TOUCH RESISTANCE The disadvantage of the ratiometric method is that the screen must be powered up at all times because it provides the reference voltage for the ADC. Y– X– Y+ X+ TOUCH RESISTANCE TOUCH-PRESSURE MEASUREMENT The pressure applied to the touch screen via a pen or finger can also be measured with the AD7877 using some simple calculations. The contact resistance between the X and Y plates is measured providing a good indication of the size of the depressed area and, therefore, the applied pressure. The area of the spot that is touched is proportional to the size of the object touching it. The size of this resistance (RTOUCH) can be calculated using two different methods. First Method The first method requires the user to know the total resistance of the X-plate tablet (RX). Three touch screen conversions are required: Measurement of the X position, XPOSITION (Y+ input). Measurement of the Y− input with the excitation voltage applied to Y+ and X− (Z1 measurement). Measurement of the X+ input with the excitation voltage applied to Y+ and X− (Z2 measurement). These three measurements are illustrated in Figure 31. The AD7877 has two special ADC channel settings that configure the X and Y switches for Z1 and Z2 measurement and store the results in the Z1 and Z2 results registers. The Z1 measurement is ADC Channel 1010b, and the result is stored in the register with Read Address 11010b. The Z2 measurement is ADC Channel 0010b, and the result is stored in the register with Read Address 10010b. Y– X– MEASURE Z2 POSITION Figure 31. Three Measurements Required for Touch Pressure Second Method The second method requires the user to know the resistance of the X-plate and Y-plate tablets. Three touch screen conversions are required, a measurement of the X position (XPOSITION), Y position (YPOSITION), and Z1 position. The following equation also calculates the touch resistance: RTOUCH = RXPlate × (XPOSITION /4096) × [(4096/Z1) − 1] − RYPlate × [1 − (YPOSITION/4096)] (3) STOPACQ PIN As previously explained in the Touch Screen Principles section, touch screens are composed of two resistive layers, normally placed over an LCD screen. Because these layers are in close proximity to the LCD screen, noise can be coupled from the screen onto these resistive layers, causing errors in the touch screen positional measurements. For example, a jitter might be noticeable in the cursor on-screen. In most LCD touch screen systems, a signal, such as an LCD invert signal or other control signal, is present, and noise is usually coupled onto the touch screen during the active period of this signal (see Figure 32). The touch resistance can then be calculated using the following equation: RTOUCH = (RXPlate) × (XPOSITION /4096 × [Z2/Z1) − 1] MEASURE X POSITION LCD SIGNAL (2) TOUCH SCREEN SIGNAL NOISY PERIOD NOISY PERIOD Figure 32. Effect of LCD Noise on Touch Screen Measurements Rev. E | Page 16 of 45 03796-010 Y+ 03796-009 X+ Data Sheet AD7877 The LCD control signal should be applied to the STOPACQ pin. To ensure that acquisition never occurs during the noisy period when the LCD signal is active, the AD7877 monitors this signal. No acquisitions take place when the control signal is active. Any acquisition that is in progress when the signal becomes active is aborted and restarts when the signal becomes inactive again. To accommodate signals of different polarities on the STOPACQ pin, a user-programmable register bit is used to indicate whether the signal is active high or low. The POL bit is Bit 3 in Control Register 2, Address 0x02. Setting POL to 1 indicates that the signal on STOPACQ is active high; setting POL to 0 indicates that it is active low. POL defaults to 0 on power-up. To disable monitoring of STOPACQ, the pin should be tied low if POL = 1, or tied high if POL = 0. Under no circumstances should the pin be left floating. The signal on STOPACQ has no effect while the ADC is in conversion mode, or during the first conversion delay time. (See the Control Registers section for details on the first conversion delay.) When enabled, the STOPACQ monitoring function is implemented on all input channels to the ADC: AUX1, AUX2, BAT1, BAT2, TEMP1, and TEMP2, as well as on the touch screen input channels. TEMPERATURE MEASUREMENT Two temperature measurement options are available on the AD7877: the single conversion method and the differential conversion method. The single conversion method requires only a single measurement on ADC Channel 1000b. Whereas differential conversion requires two measurements, one on ADC Channel 1000b and a second on ADC Channel 1001b. The results are stored in the results registers with Address 11000b (TEMP1) and Address 11001b (TEMP2). The AD7877 does not provide an explicit output of the temperature reading; the system must perform some external calculations. Both methods are based on an on-chip diode measurement. measured. This method provides a resolution of approximately 0.3°C and a predicted accuracy of ±2.5°C. The temperature limit comparison is performed on the result in the TEMP1 results register, which is simply the measurement of the diode forward voltage. The values programmed into the high and low limits should be referenced to the calibrated diode forward voltage to make accurate limit comparisons. An example is shown in the Limit Comparison section. Differential Conversion Method The differential conversion method is a 2-point measurement. The first measurement is performed with a fixed bias current into a diode (when the TEMP1 channel is selected), and the second measurement is performed with a fixed multiple of the bias current into the same diode (when the TEMP2 channel is selected). The voltage difference in the diode readings is proportional to absolute temperature and is given by the following formula: ∆VBE = (kT/q) × (ln N) (4) where: VBE represents the diode voltage. N is the bias current multiple (typical value for AD7877 = 120). k is Boltzmann’s constant. q is the electron charge. This method provides a resolution of approximately 1.6°C, and a guaranteed accuracy of ±4°C without calibration. Determination of the N value on a part-by-part basis improves accuracy. Assuming a current multiple of 120, which is a typical value for the AD7877, taking Boltzmann’s constant, k = 1.38054 × 10−23 electrons V/°K, the electron charge q = 1.602189 × 10−19, then T, the ambient temperature in Kelvin, would be calculated as follows: ∆VBE = (kT/q) × (ln N) T°k = (∆VBE × q)/(k × ln N) = (∆VBE × 1.602189 × 10−19)/(1.38054 × 10−23 × 4.65) T°C = 2.49 × 120 × ∆VBE − 273 ∆VBE is calculated from the difference in readings from the first conversion to the second conversion. The user must perform the calculations to get ∆VBE, and then calculate the temperature value in degrees. Figure 33 shows a block diagram of the temperature measurement circuit. TEMP1 Single Conversion Method The single conversion method makes use of the fact that the temperature coefficient of a silicon diode is approximately −2.1 mV/°C. However, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. It is, therefore, necessary to calibrate by measuring the diode voltage at a known temperature to provide a baseline from which the change in forward voltage with temperature can be Rev. E | Page 17 of 45 I TEMP2 I20 × I MUX VBE ADC 03796-011 It is only during the sample or acquisition phase of the ADC operation of the AD7877 that noise from the LCD screen has an effect on the ADC measurements. During the hold or conversion phase, the noise has no effect, because the voltage at the input of the ADC has already been acquired. Therefore, to minimize the effect of noise on the touch screen measurements, the ADC acquisition phase should be halted. Figure 33. Block Diagram of Temperature Measurement Circuit AD7877 Data Sheet Temperature Calculations BATTERY MEASUREMENT If an explicit temperature reading in °C is required, then this is calculated as follows for the single measurement method: The AD7877 can monitor battery voltages from 0.5 V to 5 V on two inputs, BAT1 and BAT2. Figure 34 shows a block diagram of a battery voltage monitored through the BAT1 pin. The voltage to the VCC pin of the AD7877 is maintained at the desired supply voltage via the dc/dc regulator while the input to the regulator is monitored. This voltage on BAT1 is divided down by 2 internally, so that a 5 V battery voltage is presented to the ADC as 2.5 V. To conserve power, the divider circuit is on only during the sampling of a voltage on BAT1. The BAT2 input circuitry is identical. 1. Calculate the scale factor of the ADC in degrees per LSB: Degrees per LSB = ADC LSB size/−2.1 mV = (VREF/4096)/−2.1 mV 2. Save the ADC output, DCAL, at the calibration temperature, TCAL. 3. Take ADC reading, DAMB, at the temperature to be measured, TAMB. 4. Calculate the difference in degrees between TCAL and TAMB using The BAT1 input is ADC Channel 0110b and the result is stored in Register 10110b. The BAT2 input is ADC Channel 0111b and the result is stored in Register 10111b. ∆T = (DAMB − DCAL) × degrees per LSB 5. DC-DC CONVERTER BATTERY 0.5V TO 5V Add ∆T to TCAL VCC BAT1 Example: 5kΩ The internal 2.5 V reference is used. VREF SW 0.25V–2.5V ADC Degrees per LSB = (2.5/4096)/−2.1 × 10−3 = −0.291 2. The ADC output is 983 decimal at 25°C, equivalent to a diode forward voltage of 0.6 V. 3. The ADC output at TAMB is 880. 4. ∆T = (880 − 983) × −0.291 = 30° 5. TAMB = 25 + 30 = 55°C 03796-012 5kΩ 1. Figure 34. Block Diagram of Battery Measurement Circuit To calculate the temperature explicitly using the differential method: 1. Calculate the LSB size of the ADC in V: LSB = VREF/4096 2. Subtract TEMP1 from TEMP2 and multiply by LSB size to get ∆VBE. 3. Multiply by 2490 and subtract 273 to obtain the temperature in °C. Figure 34 shows the ADC using the internal reference of 2.5 V. The maximum battery voltage that the AD7877 can measure changes when a different reference voltage is used. The maximum voltage that is measurable is VREF × 2, because this voltage gives a full-scale output from the ADC. If a smaller reference is used, such as 2 V, then the maximum measurable battery voltage is 4 V. If a larger reference is used, such as 3.5 V, then the maximum measurable battery voltage is 7 V. The internal reference is particularly suited for use when measuring lithium-ion batteries, wherein the minimum voltage is about 2.7 V and the maximum voltage is about 4.2 V. A proper choice of external reference ensures that other voltage ranges can be accommodated. Example: The internal 2.5 V reference is used. 1. LSB size = 2.5 V/4096 = 6.1 × 10−4 V(610 µV) 2. TEMP1 = 880 and TEMP2 = 1103: ∆VBE = (1103 − 880) × 6.1× 10−4 = 0.136 V 3. T = 0.136 × 2490 − 273 = 65°C Rev. E | Page 18 of 45 Data Sheet AD7877 AUXILIARY INPUTS The AD7877 has three auxiliary analog inputs, AUX1 to AUX3. These channels have a full-scale input range from 0 V to VREF. The ADC channel addresses for AUX1 to AUX3 are 0011b, 0100b, and 0101b, and the results are stored in Register 10011b, Register 10100b, and Register 10101b. These pins can also be reconfigured as general-purpose logic inputs/outputs, as described in the GPIO Configuration section. Instead, it is necessary to calibrate the temperature measurement, calculate the TEMP1 readings at the high and low limit temperatures, and then program those values into the limit registers, as follows: 1. LSB per degree = −2.1 mV/(VREF/4096). 2. Save the calibration reading DCAL at the calibration temperature, TCAL. 3. Subtract TCAL from limit temperatures THIGH and TLOW to get the difference in degrees between the limit temperatures and the calibration temperature. 4. Multiply this value by LSB per degree to obtain the value in LSBs. 5. Add these values to the digital value at the calibration temperature to get the digital high and low limit values. LIMIT COMPARISON The AUX1 measurement, the two battery measurements, and the TEMP1 measurement can all be compared with high and low limits, and an out-of-limit result that generates an alarm output at the ALERT pin. The limits are stored in registers with addresses from 00100b to 01011b. After a measurement from any one of the four channels is converted, it is compared with the corresponding high and low limits. An out-of-limit result sets one of the status bits in the alert status/enable register. For details on these and other registers, see the Register Maps and Detailed Register Descriptions sections. For details on writing and reading data, see the Serial Interface section. As described in the Single Conversion Method section, the temperature comparison is made using the result of the TEMP1 measurement, that is, the diode forward voltage. Because the temperature coefficient of the diode is known but the actual forward voltage can have a wide tolerance, it is not possible to program the high and low limit registers with predetermined values. Calculate Example: The internal 2.5 V reference is used. 1. THIGH = +65°C and TLOW = −10°C. 2. LSB per degree = −2.1 × 10−3/(2.5/4096) = −3.44. 3. DCAL = 983 decimal at 25°C. 4. DHIGH = (65 − 25) × −3.44 + 983 = 845. 5. DLOW = (−10 − 25) × −3.44 + 983 = 1103. Rev. E | Page 19 of 45 AD7877 Data Sheet CONTROL REGISTERS Control Register 1 contains the ADC channel address, the SER/DFR bit (to choose single or differential methods of touch screen measurement), the register read address, and the ADC mode bits. Control Register 1 should always be the last register to be programmed prior to starting conversions. Its power-on default value is 0x00. To change any parameter after conversion has begun, the part should first be put into Mode 00, the changes made, and then Control Register 1 reprogrammed, ensuring that it is always the last register to be programmed before conversions begin. SER/ DFR 0 CHNL CHNL CHNL CHNL ADD ADD ADD ADD 3 2 1 0 RD ADD 4 RD ADD 3 RD ADD 2 RD ADD 1 RD ADD 0 ADC ADC MODE MODE 1 0 03796-013 11 Figure 35. Control Register 1 Control Register 2 sets the timer, reference, polarity, first conversion delay, averaging, and acquisition time. Its power-on default value is 0x00. See the Detailed Register Descriptions section for more information on the control registers. AVG 1 0 AVG 0 ACQ 1 ACQ 0 PM 1 PM 0 FCD 1 FCD 0 POL REF TMR 1 TMR 0 Figure 36. Control Register 2 CONTROL REGISTER 1 ADC Mode (Control Register 1, Bits[1:0]) These bits select the operating mode of the ADC. The AD7877 has three operating modes. These are selected by writing to the mode bits in Control Register 1. If the mode bits are 00, no conversion is performed. Table 5. Control Registera 1 Mode Selection MODE1 0 0 MODE0 0 1 1 1 0 1 Function Do not convert (default) Single-channel conversion, AD7877 in slave mode Sequence 0, AD7877 in slave mode Sequence 1, AD7877 in master mode If the mode bits are 01, a single conversion is performed on the channel selected by writing to the channel bits of Control Register 1 (Bit 7 to Bit 10). At the end of the conversion, if the TMR bits in Control Register 2 are set to 00, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a value other than 00 causes the conversion to be repeated, as described in the Timer (Control Register 2, Bits[1:0]) section. The flowchart in Figure 38 shows how the AD7877 operates in Mode 01. 03796-014 11 The AD7877 can also be programmed to convert a sequence of selected channels automatically. The two modes for this type of conversion are slave mode and master mode. For slave mode operation, the channels to be digitized are selected by setting the corresponding bits in Sequencer Register 0. Conversion is initiated by writing 10b to the mode bits of Control Register 1. The ADC then digitizes the selected channels and stores the results in the corresponding results registers. At the end of the conversion, if the TMR bits in Control Register 2 are set to 00, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a code other than 00 causes the conversion sequence to be repeated. The flowchart in Figure 39 shows how the AD7877 operates in Mode 10. For master mode operation, the channels to be digitized are written to Sequencer Register 1. Master mode is then selected by writing 11 to the mode bits in Control Register 1. In this mode, the wake-up on touch feature is active, so conversion does not begin immediately. The AD7877 waits until the screen is touched before beginning the sequence of conversions. The ADC then digitizes the selected channels, and the results are written to the results registers. The AD7877 waits for the screen to be touched again, or for a timer event if the screen remains touched, before beginning another sequence of conversions. The flowchart in Figure 40 shows how the AD7877 operates in Mode 11. ADC Channel (Control Register 1, Bits[10:7]) The ADC channel is selected by Bits [10:7] of Control Register 1 (CHADD3 to CHADD0). In addition, the SER/DFR bit, Bit 11, selects between single-ended and differential conversion. A complete list of channel addresses is given in Table 6. For Mode 0 (single-channel) conversion, the channel is selected by writing the appropriate CHADD3 to CHADD0 code to Control Register 1. For sequential channel conversion, channels to be converted are selected by setting bits corresponding to the channel number in Sequencer Register 1 for slave mode sequencing or Sequencer Register 2 for master mode sequencing. For both single-channel and sequential conversion, normal (single-ended) conversion is selected by clearing the SER/DFR bit in Control Register 1. Ratiometric (differential) conversion is selected by setting the SER/DFR bit. Rev. E | Page 20 of 45 Data Sheet AD7877 Table 6. Codes for Selecting Input Channel and Normal or Ratiometric Conversion Channel 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 - SER/DFR CHADD(3:0) 0000 0001 0010 0 01 1 0 1 00 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 10 1 1 1100 1101 1110 1111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Analog Input X+ (Y position) Y+ (X position) Y− (Z2) AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) X+ (Y position) Y+ (X position) Y− (Z2) AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) X Switches Y Switches Off On On Off X+ off, X− on Y+ on, Y− off Off Off Off Off Off Off Off Off Off Off Off Off Off Off X+ OFF, X− ON Y+ on Y− off Invalid address Invalid address Invalid address Invalid address Invalid address Off On On Off X+ off, X− on Y+ on, Y− off Off Off Off Off Off Off Off Off Off Off Off Off Off Off X+ off, X− on Y+ on, Y− off Invalid address Invalid address Invalid address Invalid address Invalid address +REF Y+ X+ Y+ VREF VREF VREF VREF VREF VREF VREF Y+ −REF Y− X− X− GND GND GND GND GND GND GND X− VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF GND GND GND GND GND GND GND GND GND GND GND CONTROL REGISTER 2 Int/Ext Reference (Control Register 2, Bit[2]) Timer (Control Register 2, Bits[1:0]) If the REF bit in Control Register 2 is 0 (default value), the internal reference is selected. Buffer any connection made to VREF while the internal reference is selected (for example, to supply a reference to other circuits). An external power supply should not be connected to this pin while REF is equal to 0, because it might overdrive the internal reference. Because the internal reference is 2.5 V, it operates only with supply voltages down to 2.7 V. Below this value, use an external reference. The TMR bits in Control Register 2 enable the ADC to repeatedly perform a conversion or conversion sequence either once only or at intervals of 512 μs, 1.024 ms, or 8.19 ms. In slave mode, the timer starts as soon as the conversion sequence is finished. In master mode, the timer starts at the end of a conversion sequence only if the screen remains touched. If the touch is released at any stage, then the timer stops and, the next time the screen is touched, a conversion sequence begins immediately. Table 7. Control Register 2 Timer Selection TMR1 0 0 1 1 TMR0 0 1 0 1 Function Convert only once (default) Every 1024 clocks (512 μs) Every 2048 clocks (1.024 ms) Every 16,384 clocks (8.19 ms) If the REF bit is 1, the VREF pin becomes an input and the internal reference is powered down. This overrides any setting of the PM bits with regard to the reference. An external reference can then be applied to the REF pin. Rev. E | Page 21 of 45 AD7877 Data Sheet STOPACQ Polarity (Control Register 2, Bit[3]) Acquisition Time (Control Register 2, Bits[9:8]) This bit should be set according to the polarity of the signal applied to the STOPACQ pin. If that signal is active high, that is, no acquisitions should occur during the high period of the signal, then the POL bit should be set to 1. If the signal is active low, then the POL bit should be 0. The default value for POL is 0. The ACQ bits in Control Register 2 allow the selection of acquisition times for the ADC of 2 μs (default), 4 μs, 8 μs, or 16 μs. The user can program the ADC with an acquisition time suitable for the type of signal being sampled. For example, signals with large RC time constants can require longer acquisition times. First Conversion Delay (Control Register 2, Bits[5:4]) The first conversion delay (FCD) bits in Control Register 2 program a delay of 500 ns (default), 128 μs, 1.024 ms, or 8.19 ms before the first conversion, to allow the ADC time to power up. This delay also occurs before conversion of the X and Y coordinate channels, to allow extra time for screen settling, and after the last conversion in a sequence, to precharge PENIRQ. If the signal on the STOPACQ pin is being monitored and goes active during the FCD, it is ignored until after the FCD period. Table 8. First Conversion Delay Selection FCD 0 1 0 1 Function 1 clock delay (500 ns) 256 clock delays (128 μs) 2048 clock delays (1.024 ms) 16,384 clock delays (8.19 ms) The power management (PM) bits in Control Register 2 allow the power management features of the ADC to be programmed. If the PM bits are 00, the ADC is powered down permanently. This overrides any setting of the mode bits in Control Register 1. If the PM bits are 01, the ADC and the reference both power down when the ADC is not converting. If the PM bits are 10, the ADC and reference are powered up continuously. If the PM bits are 11, the ADC, but not the reference, powers down when the ADC is not converting. If the AD7879 is in full power mode (PM=10), the master sequencer should not be used. PM bits must be set to 01 or 11 when using the master sequencer. Table 9. Power Management Selection PM0 0 1 1 1 0 1 ACQ0 0 1 0 1 Function 4 clock periods (2 μs) 8 clock periods (4 μs) 16 clock periods (8 μs) 32 clock periods (16 μs) Averaging (Control Register 2, Bits[11:10]) Signals from touch screens can be extremely noisy. The AVG bits in Control Register 2 allow multiple conversions to be performed on each input channel and averaged to reduce noise. A single conversion can be selected (no averaging), which is the default, or 4, 8, or 16 conversions can be averaged. Only the final averaged result is written into the results register. Table 11. Averaging Selection Power Management (Control Register 2, Bits[7:6]) PM1 0 0 ACQ1 0 0 1 1 Function Power down continuously (default) Power down ADC and reference when ADC is not converting (powers up with FCD at start of a conversion) Powered up continuously Power down ADC when ADC is not converting (powers up with FCD at start of conversion) AVG1 0 0 1 1 AVG0 0 1 0 1 Function ADC performs 1 average per channel ADC performs 4 averages per channel ADC performs 8 averages per channel ADC performs 16 averages per channel SEQUENCER REGISTERS There are two sequencer registers on the AD7877. Sequencer Register 0 controls the measurements performed during a slave mode sequence. Sequencer Register 1 controls the measurements performed during a master mode sequence. To include a measurement in a slave mode or master mode sequence, the relevant bit must be set in Sequencer Register 0 or Sequencer Register 1. Setting Bit 11 includes a measurement on ADC Channel 0 in the sequence, which is the Y positional measurement. Setting Bit 10 includes a measurement on ADC Channel 1 (X+ measurement), and so on, through Bit 1 for Channel 10. Figure 37 illustrates the correspondence between the bits in the sequencer registers and the various measurements. Bit 0 in both sequencer registers is not used. See also the Detailed Register Descriptions section. 11 0 Y+ X+ Z2 AUX 1 AUX 2 AUX 3 BAT 1 BAT 2 TEMP TEMP 1 2 Figure 37. Sequencer Register Rev. E | Page 22 of 45 Z1 NOT USED 03796-015 FCD1 0 0 1 1 Table 10. Acquisition Time Selection Data Sheet AD7877 HOST PROGRAMS AD7877 IN MODE 10 HOST PROGRAMS AD7877 IN MODE 01 VALID SEQUENCE 0? NO GO TO MODE 00 IS FCD REQUIRED? NO YES SELECT NEXT CHANNEL YES START FCD TIMER IS FCD REQUIRED? IS FCD FINISHED? YES NO START FCD TIMER YES YES NO IS FCD FINISHED? IS STOPACQ SIGNAL ACTIVE? NO YES NO IS STOPACQ SIGNAL ACTIVE? YES START ACQUISITION TIMER NO START ACQUISITION TIMER IS STOPACQ SIGNAL ACTIVE? YES YES IS STOPACQ SIGNAL ACTIVE? NO NO NO IS ACQUISITION TIME FINISHED? IS ACQUISITION TIME FINISHED? YES YES CONVERT SELECTED CHANNEL CONVERT SELECTED CHANNEL IS AVERAGING FINISHED? NO IS AVERAGING FINISHED? NO NO YES YES WRITE RESULT TO REGISTERS WRITE RESULT TO REGISTERS LIMIT COMPARISON LIMIT COMPARISON OUT-OF-LIMIT? OUT-OF-LIMIT? NO YES UPDATE ALERT ENABLE/STATUS REGISTER YES UPDATE ALERT ENABLE/STATUS REGISTER ALERT SOURCE ENABLED? NO ALERT SOURCE ENABLED? NO YES NO ASSERT ALERT OUTPUT1 YES ASSERT ALERT OUTPUT1 LAST CHANNEL IN SEQUENCE? NO YES GO TO MODE 00 YES ONCE-ONLY MODE? GO TO MODE 00 NO NO START TIMER START TIMER 1SEE TIMER FINISHED? YES SEQUENCER REGISTERS SECTION. NO TIMER FINISHED? YES 03796-016 NO ONCE-ONLY MODE? 1SEE SEQUENCER REGISTERS SECTION. 03796-017 YES Figure 39. Slave Mode Sequencer Operation Figure 38. Single Channel Operation Rev. E | Page 23 of 45 AD7877 Data Sheet HOST PROGRAMS AD7877 IN MODE 11 GO TO MODE 00 INTERRUPTS Data Available Output (DAV) VALID SEQUENCE 1? NO The data available output (DAV) indicates that new ADC data is available in the results registers. While the ADC is idle or is converting, DAV is high. Once the ADC has finished converting and new data has been written to the results registers, DAV goes low. Taking DAV low to read the registers resets DAV to a high condition. DAV is also reset, if a new conversion is started by the AD7877 because the timer expired. The host should attempt to read the results registers only when DAV is low. YES IS SCREEN TOUCHED? NO YES SELECT NEXT CHANNEL IS FCD REQUIRED? NO YES START FCD TIMER CS IS FCD FINISHED? NO YES DAV tCONV IS STOPACQ SIGNAL ACTIVE? AD7877 STATUS NO START ACQUISITION TIMER YES NEW DATA HOST READS AVAILABLE RESULTS IDLE DAV is useful as a host interrupt in master mode. In this mode, the host can program the AD7877 to automatically perform a sequence of conversions, and can be interrupted by DAV at the end of each conversion sequence. NO NO YES CONVERT SELECTED CHANNEL When the on-board timer is programmed to perform automatic conversions, a limited time is available to the host to read the results registers before another sequence of conversions begins. The DAV signal is reset high when the timer expires, and the host should not access the results registers while DAV is high. NO IS AVERAGING FINISHED? ADC CONVERTING Figure 41. Operation of DAV Output IS STOPACQ SIGNAL ACTIVE? IS ACQUISITION TIME FINISHED? IDLE SETUP BY HOST 03796-019 YES YES WRITE RESULT TO REGISTERS LIMIT COMPARISON OUT-OF-LIMIT? Figure 42 shows the worst-case timings for reading the results registers after DAV has gone low. The timer is set at a minimum, and the conversion sequence includes all 11 possible ADC channels. t1 is the time taken for acquisition and conversion on one ADC channel. t2 shows the minimum timer delay, that is, 1024 clock periods. t3 is the time taken to read all 11 result registers. If the host wants to read all 11 registers, then it must do so before the timer expires. t4 is the maximum time allowable between DAV going low and the host beginning to read the results registers. If t4 is exceeded, then all registers cannot be read before the start of a new conversion, and incorrect data could be read by the host. NO YES UPDATE ALERT ENABLE/STATUS REGISTER ALERT SOURCE ENABLED? NO YES ASSERT ALERT OUTPUT1 NO LAST CHANNEL IN SEQUENCE? YES YES ONCE-ONLY MODE? NO IS SCREEN STILL TOUCHED? AD7877 STATUS NO t1 t2 CHANNEL 11 CONVERSION AND ACQUISITION TIMER INTERVAL CHNL 1 DAV YES START TIMER CS YES NO 1SEE IS SCREEN STILL TOUCHED? t3 NO SEQUENCER REGISTERS SECTION. Figure 42. Timing for Reads after DAV Goes Low 03796-018 YES t4 DOUT Figure 40. Master Mode Sequencer Operation Rev. E | Page 24 of 45 03796-020 TIMER FINISHED? Data Sheet AD7877 NOT SCREEN TOUCHED t2 = 512 µs with timer set to 1024 (TMR bits = 01b) tWRITE = tREAD = 16 CLK period × tDCLK = 800 ns PENIRQ DETECTS TOUCH PENIRQ t3 = maximum time taken to write read address and read 11 registers = 800 ns (write) + [800 ns (read) × 11] = 9.6 µs. ADC STATUS t4MAX = t2 − t3 = 512 µs − 9.6 µs = 502.4 µs Pen Interrupt (PENIRQ) Y+ VCC VCC 50kΩ PENIRQ X+ X– RELEASE NOT DETECTED ADC IDLE NOT TOUCHED PENIRQ DETECTS RELEASE ADC CONVERTING ADC IDLE Figure 44. PENIRQ Operation for ADC Idle and ADC Converting SYNCHRONIZING THE AD7877 TO THE HOST CPU The two suggested methods for synchronizing the AD7877 to its host CPU are slave mode, in which the mode bits can be either 01b or 10b, and master mode, in which the mode bits are 11b. In slave mode, PENIRQ can be used as an interrupt to the host. When PENIRQ goes low to indicate that the screen has been touched, the host is awakened. The host can then program the AD7877 to begin converting in either Mode 01b or Mode 10b, and can read the result registers after the conversions are completed. TOUCH SCREEN 03796-021 PENIRQ ENABLE Y– TOUCHED PENIRQ DETECTS TOUCH PENIRQ ADC STATUS PENIRQ DETECTS RELEASE ADC IDLE NOT SCREEN TOUCHED The pen interrupt request output (PENIRQ) goes low whenever the screen is touched. The pen interrupt equivalent output circuitry is outlined in Figure 43. This is a digital logic output with an internal pull-up resistor of 50 kΩ, which means it does not need an external pull-up. The PENIRQ output idles high. The PENIRQ circuitry is always enabled, except during conversions. NOT TOUCHED TOUCHED 03796-022 If fDCLK = 20 MHz (maximum), then tDCLK = 50 ns. Figure 43. PENIRQ Output Equivalent Circuit When the screen is touched, PENIRQ goes low. This generates an interrupt request to the host. When the screen touch ends, and if the ADC is idle, PENIRQ immediately goes high. If the ADC is converting, PENIRQ goes high once the ADC becomes idle. The PENIRQ operation for these two conditions is shown in Figure 44. In master mode, DAV can also be used as an interrupt to the host. However, the host should first initialize the AD7877 in Mode 11b. The host can then go into sleep mode to conserve power. The wake-up on touch feature of the AD7877 is active in this mode, therefore, when the screen is touched, the programmed sequence of conversions begins automatically. When the DAV signal asserts, the host reads the new data available in the AD7877 results registers and returns to sleep mode. This method can significantly reduce the load on the host. Rev. E | Page 25 of 45 AD7877 Data Sheet 8-BIT DAC The AD7877 features an on-chip 8-bit DAC for LCD contrast control. The DAC can be configured for voltage output by clearing Bit 2 of the DAC register (Address 1110b), or for current output by setting this bit. In current mode, it is quite easy to calculate the resistor values to give the required adjustment range in VOUT using the following steps: The output voltage range can be set to 0 to VCC/2 by clearing Bit 0 of the DAC register, or to 0 to VCC by setting this bit. In current mode, the output range is selectable by an external resistor, RRNG, connected between the ARNG pin and GND. This sets the full-scale output current according to the following equations: IFS = VCC/(RRNG × 6) (5) In current mode, the DAC sinks current, that is, positive current flows into ground. The maximum output current is 1000 μA. The DAC is updated by writing to Address 1110b of the DAC register. The 8 MSBs of the data-word are used for DAC data. The most effective way to control LCD contrast with the DAC is to use it to control the feedback loop of the dc-to-dc converter that supplies the LCD bias voltage, as shown in Figure 45. The bias voltage for graphic LCDs is typically in the range of 20 V to 25 V, and the dc-to-dc converter usually has a feedback loop that attenuates the output voltage and compares it with an internal reference voltage. DC-DC CONVERTER RRNG 1 IOUT 2. Decide on the current around the feedback loop. For reasonable accuracy of the output voltage, this current should be at least 100 times the input bias current of the dc-to-dc converter’s comparator 3. Calculate R3 using the following equation: VFB R12 R3 VREF TO LCD 4. Calculate R2 for the minimum value of VOUT, when the DAC has no effect R2 = R3(VOUT(MIN) − VREF)/VREF 5. Because the voltage across R3 does not change, subtract VREF from VOUTMAX and VOUTMIN to get the maximum and minimum voltages across R2 6. Calculate the change in feedback current between minimum and maximum output voltages ΔI = VR2(MAX)/R2 − VR2(MIN)/R2 This is the required full-scale current of the DAC. 7. Calculate RRNG from Equation 5 Example: VOUT 1. VCC = 5 V VOUT(MIN) is 20 V and VOUT(MAX) is 25 V VREF is 1.25 V 2. Allow 100 μA around the feedback loop. 3. R3 = 1.25 V/100 μA = 12.5 kΩ Use the nearest preferred value of 12 kΩ and recalculate the feedback current as COMP GND NOTES: 1R RNG IS REQUIRED ONLY IF DAC IS IN CURRENT MODE. 2R1 IS REQUIRED ONLY IF DAC IS IN VOLTAGE MODE. 03796-023 ARNG R2 AOUT 8-BIT DAC Find the required maximum and minimum values of VOUT from the LCD manufacturer’s data R3 = VFB/IFB = VREF/IFB therefore, RRNG = VCC/(IFS × 6) AD7877 1. Figure 45. Using the DAC to Adjust LCD Contrast The circuit operates as follows. If the DAC is in current mode when the DAC output is zero, it has no effect on the feedback loop. Regardless of what the DAC does, the feedback loop maintains the voltage across R4, VFB, equal to VREF, and the output voltage, VOUT, is VREF × (R2 + R3)/R3 As the DAC output is increased, it increases the feedback current, so the voltage across R2 and, therefore, the output voltage also increase. Note that the voltage across R3 does not change. This is important for calculation of the adjustment range. IFB = 1.25 V/12 kΩ = 104 μA 4. R2 = (20 V − 1.25 V)/104 μA = 180 kΩ 5. ΔI = 23.75 V/180 kΩ − 18.75 V/180 kΩ = 28 μA 6. RRNG = 5 V/(6 × 28 μA) = 30 kΩ In voltage mode, the circuit operation depends on whether the maximum output voltage of the DAC exceeds the dc to dc converter VREF. Rev. E | Page 26 of 45 Data Sheet AD7877 When the DAC output voltage is zero, it sinks the maximum current through R1. The feedback current and, therefore, VOUT are at their maximum. As the DAC output voltage increases, the sink current and, thus, the feedback current decrease, and VOUT falls. If the DAC output exceeds VREF, it starts to source current, and VOUT has to further decrease to compensate. When the DAC output is at full scale, VOUT is at its minimum. 5. R1 = VFS/∆. 6. Calculate R3 from R1 and R using R3 = (R1 × RP)/(R1 − RP) Example: 1. VCC = 5 V and VFS = VCC. VOUT(MIN) is 20 V and VOUT(MAX) is 25 V. VREF is 1.25 V. Allow 100 µA around the feedback loop. Note that the effect of the DAC on VOUT is opposite in voltage mode to that in current mode. In current mode, increasing DAC code increases the sink current, so VOUT increases with increasing DAC code. In voltage mode, increasing DAC code increases the DAC output voltage, reducing the sink current. 2. RP = 1.25 V/100 µA = 12.5 kΩ. 3. R2 = 12.5 kΩ × (25 Ω − 1.25 Ω)/1.25 Ω = 237 kΩ. Calculate the resistor values as follows: 4. ∆I = 25 V/240 kΩ − 20 V/240 kΩ = 21 µA. 1. Decide on the feedback current as before. 5. R1 = 5 V/21 µA = 238 kΩ. 2. Calculate the parallel combination of R1 and R3 when the DAC output is zero RP = VREF/IFB 3. Use the nearest preferred value of 250 kΩ. 6. R3 = (180 kΩ × 12.5 kΩ)/(180 kΩ − 12.5 kΩ) = 13.4 kΩ. Use nearest preferred value of 13 kΩ. Calculate R2 as before, but use RP and VOUT(MAX) The actual adjustment range using these values is 21 V to 26 V. R2 = RP(VOUT(MAX) − VREF)/VREF 4. Use the nearest preferred value of 240 kΩ. Calculate the change in feedback current between minimum and maximum output voltages as before using ∆I = VR2(MAX)/R2 − VR2(MIN)/R2 This is equal to the change in current through R1 between zero output and full scale, which is also given by ∆I = current at zero − current at full scale = V/R1 − (VREF − V)/R1 = V/R1 Rev. E | Page 27 of 45 AD7877 Data Sheet SERIAL INTERFACE Register Address 1111b is not a physical register, but enables an extended writing mode that allows writing to the GPIO configuration registers. When the register address is 1111b, the next four bits of the data-word are the address of a GPIO configuration register and the eight LSBs are the GPIO configuration data. For details on the configuration of the GPIO pins, see the General-Purpose I/O Pins section. The AD7877 is controlled via a 3-wire serial peripheral interface (SPI). The SPI has a data input pin (DIN) for inputting data to the device, a data output pin (DOUT) for reading data back from the device, and a data clock pin (DCLK) for clocking data into and out of the device. A chip-select pin (CS) enables or disables the serial interface. WRITING DATA Register Address 0001b is a physical register, Control Register 1, but this is a special register. It contains data for setting up the ADC channel and operating mode, but Bit 20 to Bit 6 compose the register address for reading. These define the register that is read back during the next read operation. Control Register 1 should be the last register in the AD7877 to be programmed before starting a conversion. The three types of data-words used for writing are shown in Figure 46. Data is written to the AD7877 in 16-bit words. The first four bits of the word are the register address that directs the AD7877 to the register to write to. The next 12 bits are data. How the AD7877 handles the data bits depends on the register address. Register Address 0000b is a dummy address, which does nothing. Register Addresses 0010b to Register Address 1110b are 12-bit registers that perform various functions as described in the register map. 16-BIT DATA-WORD D15 D14 D13 D12 D11 D10 D9 WADD3 WADD2 WADD1 WADD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 RADD0 MODE 1 MODE 0 WRITING TO A REGISTER D8 D7 4-BIT REGISTER WRITE ADDRESS 12 BITS DATA EXTENDED WRITE OPERATION TO GPIO REGISTERS 1 1 1 1 EADD3 EXTENDED WRITE ADDRESS EADD2 EADD1 EADD0 D7 D6 D5 4-BIT EXTENDED ADDRESS 8 BITS GPIO DATA WRITING TO CONTROL REGISTER 1 TO SET ADC CHANNEL, MODE, AND READ REGISTER ADDRESS 0 0 0 0 SER/DFR CHADD3 CHADD2 CHADD1 CHADD0 CONTROL REGISTER 1 ADDRESS RADD4 ADC CHANNEL ADDRESS RADD3 RADD2 RADD1 5-BIT READ REGISTER ADDRESS OPERATING MODE 03796-024 NORMAL (SINGLE-ENDED)/ RATIOMETRIC (DIFFERENTIAL) CONVERSION Figure 46. Designation of Data-Word Bits in AD7877 Write Operations CS 1 16 1 16 DCLK 0000 + 12-BIT DATA3 0000 + 12-BIT DATA3 HIGH-Z D15 DOUT1 D0 HIGH-Z D15 REGISTER n DATA4 D0 REGISTER n + 1 DATA4 4-BIT ADDRESS + 12-BIT DATA D15 D0 NOTES: 1DATA IS CLOCKED OUT ON THE FALLING EDGE OF DCLK. 2INPUT DATA IS SAMPLED ON THE RISING EDGE OF DCLK. 3FOR 8-BIT REGISTERS, 8 LEADING ZEROS PRECEDE 8 BITS OF DATA. 4REGISTER READ ADDRESS INCREMENTS AUTOMATICALLY, PROVIDED THAT A NEW ADDRESS IS NOT WRITTEN TO CONTROL REGISTER 1. Figure 47. Overall Read/Write Timing Rev. E | Page 28 of 45 03796-025 DIN2 Data Sheet AD7877 WRITE TIMING No serial interface operations can take place when CS is high. To write to the AD7877, CS must be taken low. To write to the device, a burst of 16 clock pulses is input to DCLK while the write data is input to DIN. Data is clocked in on the rising edge of DCLK. If multiple write operations are to be performed, CS must be taken high after the end of each write operation before another write operation can be performed by taking CS low again. READING DATA Data is available on the DOUT pin following the falling edge of CS, when the device is being clocked. The MSB is clocked out on the falling edge of CS, with subsequent data bits clocked out on the falling edge of DCLK. After CS is taken low and the device is clocked, the AD7877 outputs data from the register whose read address is currently stored in Control Register 1. Once this data has been output, the address increments automatically. CS must be taken high between reads. When CS is taken low again, reading continues from the register whose read address is in Control Register 1, provided that a write operation does not change the address. If the register read address reaches 11111b, it is then reset to zero. This feature allows all registers to be read out in sequence without having to explicitly write all their addresses to the device. Note that because data-words are 16 bits long, but the data registers are only 12 bits long, or 8 bits in the case of GPIO registers, the first four bits of a readback data-word are zeros, or the first 8 bits in the case of a GPIO register. VDRIVE PIN The supply voltage to all pins associated with the serial interface (DAV, DIN, DOUT, DCLK, CS, PENIRQ, and ALERT) is separate from the main VCC supply and is connected to the VDRIVE pin. This allows the AD7877 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7877, in fact, as low as 1.7 V. Rev. E | Page 29 of 45 AD7877 Data Sheet GENERAL-PURPOSE I/O PINS The AD7877 has one dedicated general-purpose logic input/ output pin (GPIO4), and any or all of the three auxiliary analog inputs can also be reconfigured as GPIOs. Associated with the GPIOs are two 8-bit control registers and one 8-bit data register that are accessed using the extended write mode. As described in the Reading Data section, GPIO registers are written to using the extended writing mode. The first four bits of the data-word must be 1111b to access the extended writing map, and the next four bits are the GPIO register address. This leaves 8 bits for the GPIO register data, because all GPIO registers are 8 bits. The GPIO control registers are located at the 0000b and 0001b extended writing map addresses, and the GPIO data register is at Address 0010b. GPIO registers are read in the same way as other registers, by writing a 5-bit address to Control Register 1. The GPIO registers are located at Read Addresses 11011b to Read Address 11101b. If POL = 1 and DIR = 0, a 1 in the GPIO data register bit puts a 1 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 0 on the GPIO output pin. If POL = 0 and DIR = 1, a 1 at the input pin sets the corresponding GPIO data bit to 0. A 0 at the input pin clears the corresponding GPIO data bit to 1. If POL = 0 and DIR = 0, a 1 in the GPIO data register bit puts a 0 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 1 on the GPIO output pin. ALERT Enable (ALEN) GPIOs can operate as interrupt sources to trigger the ALERT output. This is controlled by the ALERT enable (ALEN) bits in the GPIO configuration registers. When ALEN = 1, the corresponding GPIO can trigger an ALERT. When ALEN = 0, the corresponding GPIO cannot cause the ALERT output to assert. Each GPIO pin is configured by four bits in one of the GPIO control registers and has a data bit in the GPIO data register. The GPIO configuration bits are described in the following sections and in Table 12. Also see the Detailed Register Descriptions section. ALERT is asserted low if any GPIO data register bit is set when the GPIO is configured as an input. The GPIO data bit is set if a 1 appears on the GPIO input pin when POL = 1, or if a 0 appears on the GPIO input pin when POL = 0. ALERT is triggered only when the GPIO is configured as an input, that is, when DIR = 1. ALERT can never be triggered by a GPIO that is configured as an output, that is, DIR = 0. Enable (EN) ALERT Output These bits enable or disable the GPIO pins. When EN = 0, the corresponding GPIO pin is configured as the alternate function (AUX input). The other GPIO configuration bits have no effect, if the particular GPIO is not enabled. When EN = 1, the pin is configured as a GPIO pin. GPIO4, which does not have an alternate function, does not have an EN bit; it is always enabled. The ALERT pin is an alarm or interrupt output that goes low if any one of a number of interrupt sources is asserted. The results of high and low limit comparisons on the AUX1, BAT1, BAT2, and TEMP1 channels are interrupt sources. An out-of-limit comparison sets a status bit in the alert status/mask register (Address 00011b).There are separate status bits for both the high and low limits on each channel to indicate which limit was exceeded. The interrupt sources can be masked out by clearing the corresponding enable bit in this register. There is one enable bit per channel. GPIO CONFIGURATION Direction—DIR These bits set the direction of the GPIO pins. When DIR = 0, the pin is an output. Setting or clearing the relevant bit in the GPIO data register outputs a value on the corresponding GPIO pin. The output value depends on the POL bit. When DIR = 1, the pin is an input. An input value on the relevant GPIO pin sets or clears the corresponding bit in the GPIO data register, depending on the POL bit. A GPIO data register bit is read-only when DIR = 1 for that GPIO. Polarity (POL) When POL = 0, the GPIO pin is active low. When POL = 1, the GPIO pin is active high. How this bit affects the GPIO operation also depends on the DIR bit. ALERT is also asserted if an input on a GPIO pin sets a bit in the GPIO data register, as explained in the ALERT Enable (ALEN) section. GPIO interrupts can be disabled by clearing the corresponding ALEN bit in the GPIO control registers. The interrupt source can be identified by reading the GPIO data register and the alert status/enable register. ALERT remains asserted until the source of the interrupt has been masked out or removed. If POL = 1 and DIR = 1, a 1 at the input pin sets the corresponding GPIO data register bit to 1. A 0 at the input pin clears the corresponding GPIO data bit to 0. Rev. E | Page 30 of 45 Data Sheet AD7877 If the ALERT source is a GPIO, then masking out the interrupt by clearing the corresponding ALEN bit to 0 or removing the source of the interrupt on the GPIO pin causes ALERT to go high again. If the ALERT source is an out-of-limit measurement, writing a 0 to the corresponding status bit in the alert status/enable register causes ALERT to go high. However, the status bit is set to 1 again on the next measurement cycle, if the measurement remains out of limit. The ALERT source can also be masked by clearing the relevant bit in the alert status/enable register to 0. Table 12. GPIO Configuration EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 DIR X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 POL X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ALEN X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data Bit X 0 1 0 1 0 1 0 1 12 02 12 02 02 12 02 12 Pin Voltage X 11 01 11 01 01 11 01 11 0 1 0 1 0 1 0 1 ALERT X 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 A change in the data register causes a change in the output voltage on the pin. A change in input voltage on the pin causes a change in the data register bit. Rev. E | Page 31 of 45 AD7877 Data Sheet GROUNDING AND LAYOUT The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. It is recommended that the ground pins, AGND and DGND, be shorted together as close as possible to the device itself on the user’s PCB. For more information on grounding and layout considerations for the AD7877, refer to the AN-577 Application Note, Layout and Grounding Recommendations for Touch Screen Digitizers. Using thermal vias on the printed circuit board thermal pad improves the thermal performance of the package. If vias are used, incorporate them in the thermal pad at a 1.2 mm pitch grid. Keep the via diameter between 0.3 mm and 0.33 mm. The via barrel should be plated with 1 oz. copper to plug the via. PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGES The lands on the chip scale package (CP-32) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. To ensure that the solder joint size is maximized, center the land on the pad. The user should connect the printed circuit board thermal pad to AGND. TO LCD BACKLIGHT VIN OUT FB DC-DC CONVERTER RRNG 25 ARNG DOUT DCLK NC 1 NC 2 BAT2 NC 24 3 BAT1 4 AUX3/GPIO3 5 AUX2/GPIO2 STOPACQ 20 MISO 6 AUX1/GPIO1 DIN 19 MOSI 7 VCC 8 NC HOST DAV 23 INT1 ALERT 22 AD7877 GPIO4 21 INT2 GPIO DGND 9 10 11 12 13 14 15 PENIRQ 17 SCLK CS PENIRQ NC AGND CS 18 Y+ 1.0F–10F (OPTIONAL) 26 X+ 16 HSYNC SIGNAL FROM LCD NC = NO CONNECT TOUCH SCREEN Figure 48. Typical Application Circuit Rev. E | Page 32 of 45 03796-026 TEMPERATURE MEASUREMENT DIODE 27 Y– MAIN BATTERY 0.1F 28 X– VOLTAGE REGULATOR 29 SPI INTERFACE FROM AUDIO REMOTE CONTROL FROM HOTSYNC INPUTS 30 NC SECONDARY BATTERY 31 VDRIVE NC 32 VREF 0.1F AOUT VCC Data Sheet AD7877 REGISTER MAPS Table 13. Write Register Map WADD3 0 0 Register Address Binary WADD2 WADD1 WADD0 0 0 0 0 0 1 Hex 0 1 Register Name None Control Register 1 0 0 1 0 2 Control Register 2 0 0 1 1 3 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 4 5 6 7 8 9 A B C 1 1 0 1 D 1 1 1 1 1 1 0 1 E F Alert status/enable register AUX1 high limit AUX1 low limit BAT1 high limit BAT1 low limit BAT2 high limit BAT2 low limit TEMP1 low limit TEMP1 high limit Sequencer Register 0 Sequencer Register 1 DAC register Extended write Description Unused; writing to this address has no effect Contains ADC channel address, register read address, and ADC mode Contains ADC averaging, acquisition time, power management, first conversion delay, STOPACQ polarity, and reference and timer settings Contains status of high/low limit comparisons for TEMP1, BAT1, BAT2, and AUX1, and enable bits to allow these channels to become interrupt sources User-programmable AUX1 upper limit User-programmable AUX1 lower limit User-programmable BAT1 upper limit User-programmable BAT1 lower limit User-programmable BAT2 upper limit User-programmable BAT2 lower limit User-programmable TEMP1 lower limit User-programmable TEMP1 upper limit Contains channel selection data for slave mode (software) sequencing Contains channel selection data for master mode (hardware) sequencing Contains DAC data and setup information Not a physical register; enables writing to extended writing map Table 14. Extended Writing Map EADD3 0 Register Address Binary EADD2 EADD1 EADD0 0 0 0 Hex 0 0 0 0 1 1 0 0 1 0 2 Register Name GPIO Control Register 1 GPIO Control Register 2 GPIO data Description Contains polarity, direction, enabling, and interrupt enabling settings for GPIO1 and GPIO2 Contains polarity, direction, enabling, and interrupt enabling settings for GPIO3 and GPIO4 Contains GPIO1 to GPIO4 data Rev. E | Page 33 of 45 AD7877 Data Sheet Table 15. Read Register Map RADD4 0 0 0 0 RADD3 0 0 0 0 Register Address Binary RADD2 RADD1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Register Name None Control Register 1 Control Register 2 Alert status/enable register AUX1 high limit AUX1 low limit BAT1 high limit BAT1 low limit BAT2 high limit BAT2 low limit TEMP1 low limit TEMP1 high limit Sequencer Register 0 Sequencer Register 1 DAC register None X+ Y+ Y− (Z2) 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 13 14 15 16 17 18 19 1A AUX1 AUX2 AUX3 BAT1 BAT2 TEMP1 TEMP2 X+ (Z1) 1 1 0 1 1 1B 1 1 1 0 0 1C 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1D 1E 1F GPIO Control Register 1 GPIO Control Register 2 GPIO data None None RADD0 0 1 0 1 Hex 00 01 02 03 Rev. E | Page 34 of 45 Description Reads back all zeros See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 See Table 13 Factory use only Measurement at X+ input for Y position Measurement at Y+ input for X position Measurement at Y− input for touch-pressure calculation Z2 Auxiliary Input 1 measurement Auxiliary Input 2 measurement Auxiliary Input 3 measurement Battery Input 1 measurement Battery Input 2 measurement Single-ended temperature measurement Differential temperature measurement Measurement at X+ input for touch-pressure calculation Z1 See Table 14 See Table 14 See Table 14 Factory use only Factory use only Data Sheet AD7877 DETAILED REGISTER DESCRIPTIONS Register Name: Control Register 1 Write Address: 0001 Read Address: 00001 Default Value: 0x000 Type: Read/write Table 16. Bit 0 1 Name MODE0 MODE1 Read/Write R/W R/W 2 3 4 5 6 7 8 9 10 RD0 RD1 RD2 RD3 RD4 CHADD0 CHADD1 CHADD2 CHADD3 R/W R/W R/W R/W R/W R/W R/W R/W R/W 11 SER/DFR R/W Description LSB of ADC mode code MSB of ADC mode code 00 = no conversion 01 = single conversion 10 = conversion sequence (slave mode) 11 = conversion sequence (master mode) LSB of register read address; to read a register, its address must first be written to Control Register 1 Bit 1 of register read address; to read a register, its address must first be written to Control Register 1 Bit 2 of register read address; to read a register, its address must first be written to Control Register 1 Bit 3 of register read address; to read a register, its address must first be written to Control Register 1 MSB of register read address; to read a register, its address must first be written to Control Register 1 LSB of ADC channel address Bit 1 of ADC channel address Bit 2 of ADC channel address MSB of ADC channel address 0000 = X+ input (Y position) 0001 = Y+ input (X position) 0010 = Y− (Z2) input (used for touch-pressure calculation) 0011 = Auxiliary Input 1 (AUX1) 0100 = Auxiliary Input 2 (AUX2) 0101 = Auxiliary Input 3 (AUX3) 0110 = Battery Monitor Input 1 (BAT1) 0111 = Battery Monitor Input 2 (BAT2) 1000 = Temperature Measurement 1 (used for single conversion) 1001 = Temperature Measurement 2 (used for differential measurement method) 1010 = X+ (Z1) input (used for touch-pressure calculation) Selects normal (single-ended) or ratiometric (differential) conversion 0 = ratiometric (differential) 1 = normal (single-ended) Rev. E | Page 35 of 45 AD7877 Data Sheet Register Name: Control Register 2 Write Address: 0010 Read Address: 00010 Default Value: 0x000 Type: Read/write Table 17. Bit 0 1 Name TMR0 TMR1 Read/Write R/W R/W 2 REF R/W 3 POL R/W 4 5 FCD0 FCD1 R/W R/W 6 7 PM0 PM1 R/W R/W 8 9 ACQ0 ACQ1 R/W R/W 10 11 AVG0 AVG1 R/W R/W Description LSB of conversion interval timer MSB of conversion interval timer 00 = convert only once 01 = every 1024 clock periods (512 µs) 10 = every 2048 clock periods (1.024 ms) 11 = every 16,384 clock periods (8.19 ms) Selects internal or external reference 0 = internal reference 1 = external reference Indicates polarity of signal on STOPACQ pin 0 = active low 1 = active high LSB of first conversion delay MSB of first conversion delay This delay occurs before the first conversion after powering up the ADC, before converting the X and Y coordinate channels to allow settling, and after the last conversion to allow PENIRQ precharge 00 = 1 clock period delay (500 ns) 01 = 256 clock periods delay (128 µs) 10 = 2048 clock periods delay (1.024 ms) 11 = 16,384 clock periods delay (8.19 ms) LSB of ADC power management code MSB of ADC power management code 00 = ADC and reference powered down continuously For the following codes, regardless of PM bits, the reference is always powered down if the REF bit is 1: 01 = ADC and reference powered down when not converting 10 = ADC and reference powered up continuously (master sequencer does not work if PM = 10) 11 = ADC powered down when not converting, reference powered up LSB of ADC acquisition time MSB of ADC acquisition time 00 = 4 clock periods (2 µs) 01 = 8 clock periods (4 µs) 10 = 16 clock periods (8 µs) 11 = 32 clock periods (16 µs) LSB of ADC averaging code MSB of ADC averaging code 00 = no averaging (1 conversion per channel) 01 = 4 measurements per channel averaged 10 = 8 measurements per channel averaged 11 = 16 measurements per channel averaged Rev. E | Page 36 of 45 Data Sheet AD7877 Register Name: Alert Status/Enable Register Write Address: 0011 Read Address: 00011 Default Value: 0x000 Type: Read/write Table 18. Bit 0 1 2 3 4 5 6 7 Name AUX1LO BAT1LO BAT2LO TEMP1LO AUX1HI BAT1HI BAT2HI TEMP1HI Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 1, the AUX1 channel is below its low limit When this bit is 1, the BAT1 channel is below its low limit When this bit is 1, the BAT2 channel is below its low limit When this bit is 1, the TEMP1 channel is above its low limit When this bit is 1, the AUX1 channel is above its high limit When this bit is 1, the BAT1 channel is above its high limit When this bit is 1, the BAT2 channel is above its high limit When this bit is 1, the TEMP1 channel is below its high limit 8 AUX1EN R/W Setting this bit enables AUX1 as an interrupt source to the ALERT output 9 BAT1EN R/W Setting this bit enables BAT1 as an interrupt source to the ALERT output 10 BAT2EN R/W Setting this bit enables BAT2 as an interrupt source to the ALERT output 11 TEMP1EN R/W Setting this bit enables TEMP1 as an interrupt source to the ALERT output Register Name: AUX1 High Limit Register Name: BAT1 Low Limit Write Address: 0100 Write Address: 0111 Read Address: 00100 Read Address: 00111 Default Value: 0x000 Default Value: 0x000 Type: Read/write Type: Read/write This register contains the 12-bit high limit for Auxiliary Input 1. Register Name: AUX1 Low Limit Write Address: 0101 Read Address: 00101 Default Value: 0x000 Type: Read/write This register contains the 12-bit low limit for Battery Monitoring Input 1. Register Name: BAT2 High Limit Write Address: 1000 Read Address: 01000 Default Value: 0x000 This register contains the 12-bit low limit for Auxiliary Input 1. Type: Read/write Register Name: BAT1 High Limit This register contains the 12-bit high limit for Battery Monitoring Input 2. Write Address: 0110 Read Address: 00110 Default Value: 0x000 Type: Read/write This register contains the 12-bit high limit for Battery Monitoring Input 1. Rev. E | Page 37 of 45 AD7877 Data Sheet Register Name: BAT2 Low Limit Register Name: TEMP1 High Limit Write Address: 1001 Write Address: 1011 Read Address: 01001 Read Address: 01011 Default Value: 0x000 Default Value: 0x000 Type: Read/write Type: Read/write This register contains the 12-bit low limit for Battery Monitoring Input 2. This register contains the 12-bit high limit for temperature measurement. Register Name: TEMP1 Low Limit Write Address: 1010 Read Address: 01010 Default Value: 0x000 Type: Read/write This register contains the 12-bit low limit for temperature measurement. Rev. E | Page 38 of 45 Data Sheet AD7877 Register Name: Sequencer Register 0 Write Address: 1100 Read Address: 01100 Default Value: 0x000 Type: Read/write Table 19. Bit 0 1 2 Name Not Used Z1_SS TEMP2_SS Read/Write R/W R/W R/W 3 TEMP1_SS R/W 4 5 6 7 8 9 10 11 BAT2_SS BAT1_SS AUX3_SS AUX2_SS AUX1_SS Z2_SS XPOS_SS YPOS_SS R/W R/W R/W R/W R/W R/W R/W R/W Description This bit is not used Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a slave mode sequence Setting this bit includes a temperature measurement using differential conversion in a slave mode sequence Setting this bit includes a temperature measurement using single-ended conversion in a slave mode sequence Setting this bit includes measurement of Battery Monitor Input 2 in a slave mode sequence Setting this bit includes measurement of Battery Monitor Input 1 in a slave mode sequence Setting this bit includes measurement of Auxiliary Input 3 in a slave mode sequence Setting this bit includes measurement of Auxiliary Input 2 in a slave mode sequence Setting this bit includes measurement of Auxiliary Input 1 in a slave mode sequence Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a slave mode sequence Setting this bit includes measurement of the X position (Y+ input) in a slave mode sequence Setting this bit includes measurement of the Y position (X+ input) in a slave mode sequence Register Name: Sequencer Register 1 Write Address: 1101 Read Address: 01101 Default Value: 0x000 Type: Read/write Table 20. Bit 0 1 2 Name Not Used Z1_MS TEMP2_MS Read/Write R/W R/W R/W 3 TEMP1_MS R/W 4 5 6 7 8 9 10 11 BAT2_MS BAT1_MS AUX3_MS AUX2_MS AUX1_MS Z2_MS XPOS_MS YPOS_MS R/W R/W R/W R/W R/W R/W R/W R/W Description This bit is not used Setting this bit includes the Z1 touch-pressure measurement (X+ input) in a master mode sequence Setting this bit includes a temperature measurement using differential conversion in a master mode sequence Setting this bit includes a temperature measurement using single-ended conversion in a master mode sequence Setting this bit includes measurement of Battery Monitor Input 2 in a master mode sequence Setting this bit includes measurement of Battery Monitor Input 1 in a master mode sequence Setting this bit includes measurement of Auxiliary Input 3 in a master mode sequence Setting this bit includes measurement of Auxiliary Input 2 in a master mode sequence Setting this bit includes measurement of Auxiliary Input 1 in a master mode sequence Setting this bit includes the Z2 touch-pressure measurement (Y− input) in a master mode sequence Setting this bit includes measurement of the X position (Y+ input) in a master mode sequence Setting this bit includes measurement of the Y position (X+ input) in a master mode sequence Rev. E | Page 39 of 45 AD7877 Data Sheet Register Name: DAC Register Write Address: 1110 Read Address: 01110 Default Value: 0x008 Type: Read/write Table 21. Bit 0 Name RANGE Read/Write R/W 1 2 Not Used V/I R/W R/W 3 PD R/W 4 5 6 7 8 9 10 11 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 Description Output range of the DAC in voltage mode 0 = 0 to VCC/2 1 = 0 to VCC This bit is not used Voltage output and current output 0 = voltage 1 = current DAC power-down 0 = DAC on 1 = DAC powered down LSB of DAC data Bit 1 of DAC data Bit 2 of DAC data Bit 3 of DAC data Bit 4 of DAC data Bit 5 of DAC data Bit 6 of DAC data MSB of DAC data Register Name: Y Position Register Name: Z2 Write Address: N/A Write Address: N/A Read Address: 10000 Read Address: 10010 Default Value: 0x000 Default Value: 0x000 Type: Read only Type: Read only This register contains the 12-bit result of the measurement at the X+ input with Y layer excited (Y position measurement). Register Name: X Position Write Address: N/A Read Address: 10001 Default Value: 0x000 Type: Read only This register contains the 12-bit result of the measurement at the Y− input with excitation voltage applied to Y+ and X− (used for touch-pressure calculation). Register Name: AUX1 This register contains the 12-bit result of the measurement at the Y+ input with X layer excited (X position measurement). Write Address: N/A Read Address: 10011 Default Value: 0x000 Type: Read only This register contains the 12-bit result of the measurement at Auxiliary Input 1. Rev. E | Page 40 of 45 Data Sheet AD7877 Register Name: AUX2 Register Name: TEMP1 Write Address: N/A Write Address: N/A Read Address: 10100 Read Address: 11000 Default Value: 0x000 Default Value: 0x000 Type: Read only Type: Read only This register contains the 12-bit result of the measurement at Auxiliary Input 2. This register contains the 12-bit result of a temperature measurement using single-ended conversion. Register Name: AUX3 Register Name: TEMP2 Write Address: N/A Write Address: N/A Read Address: 10101 Read Address: 11001 Default Value: 0x000 Default Value: 0x000 Type: Read only Type: Read only This register contains the 12-bit result of the measurement at Auxiliary Input 3. This register contains the 12-bit result of a temperature measurement using a differential conversion. Register Name: BAT1 Register Name: Z1 Write Address: N/A Write Address: N/A Read Address: 10110 Read Address: 11010 Default Value: 0x000 Default Value: 0x000 Type: Read only Type: Read only This register contains the 12-bit result of the measurement at Battery Monitor Input 1. Register Name: BAT2 Write Address: N/A Read Address: 10111 Default Value: 0x000 Type: Read only This register contains the 12-bit result of a measurement at the X+ input with excitation voltage applied to Y+ and X− (used for touch-pressure calculation). This register contains the 12-bit result of the measurement at Battery Monitor Input 2. Rev. E | Page 41 of 45 AD7877 Data Sheet GPIO REGISTERS GPIO registers are written to using an extended 8-bit address. The first four bits of the data-word are always 1111b to access the extended writing map. The next four bits are the register address. This leaves 8 bits for the GPIO data. GPIO registers are read like all other registers, by writing a 5-bit address to Control Register 1, then reading DOUT. See the GPIO Configuration section for information on configuring the GPIOs. Register Name: GPIO Control Register 1 Write Address: [1111] 0000 Read Address: 11011 Default Value: 0x000 Type: Read/write Table 22. Bit Name Read/Write Description 0 GPIO2_ALEN R/W If this bit is 1, GPIO2 is an interrupt source for the ALERT output; clearing this bit masks out GPIO2 as an interrupt source for the ALERT output 1 GPIO2_DIR R/W 2 GPIO2_POL R/W 3 GPIO2_EN R/W 4 GPIO1_ALEN R/W This bit sets the direction of GPIO2 0 = output 1 = input This bit determines if GPIO2 is active high or low 0 = active low 1 = active high This bit selects the function of AUX2/GPIO2 0 = AUX2 1 = GPIO2 If this bit is 1, GPIO1 is an interrupt source for the ALERT output; clearing this bit masks out GPIO1 as an interrupt source for the ALERT output 5 GPIO1_DIR R/W 6 GPIO1_POL R/W 7 GPIO1_EN R/W This bit sets the direction of GPIO1 0 = output 1 = input This bit determines if GPIO1 is active high or low 0 = active low 1 = active high This bit selects the function of AUX1/GPIO1 0 = AUX1 1 = GPIO1 Rev. E | Page 42 of 45 Data Sheet AD7877 Register Name: GPIO Control Register 2 Write Address: [1111] 0001 Read Address: 11100 Default Value: 0x000 Type: Read/write Table 23. Bit Name Read/Write Description 0 GPIO4_ALEN R/W If this bit is 1, GPIO4 is an interrupt source for the ALERT output; clearing this bit masks out GPIO3 as an interrupt source for the ALERT output 1 GPIO4_DIR R/W 2 GPIO4_POL R/W 3 Not Used This bit sets the direction of GPIO4 0 = output 1 = input This bit determines if GPIO4 is active high or low 0 = active low 1 = active high This bit is not used 4 GPIO3_ALEN R/W If this bit is 1, GPIO3 is an interrupt source for the ALERT output; clearing this bit masks out GPIO4 as an interrupt source for the ALERT output 5 GPIO3_DIR R/W 6 GPIO3_POL R/W 7 GPIO3_EN R/W This bit sets the direction of GPIO3 0 = output 1 = input This bit determines if GPIO3 is active high or low 0 = active low 1 = active high This bit selects the function of AUX3/GPIO3 0 = AUX3 1 = GPIO3 Register Name: GPIO Data Register Write Address: [1111] 0010 Read Address: 11101 Default Value: 0x000 Type: Read/write Table 24. Bit 0 1 2 3 4 5 6 7 Name Not used Not used Not used Not used GPIO4_DAT GPIO3_DAT GPIO2_DAT GPIO1_DAT Read/Write R/W R/W R/W R/W Description This bit is not used This bit is not used This bit is not used This bit is not used GPIO4 data bit GPIO3 data bit GPIO2 data bit GPIO1 data bit Rev. E | Page 43 of 45 AD7877 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 0.60 MAX 0.60 MAX 25 32 24 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 12° MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 8 16 0.50 0.40 0.30 TOP VIEW 9 BOTTOM VIEW 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters 0.30 0.25 0.18 32 25 1 24 0.50 BSC TOP VIEW 0.80 0.75 0.70 SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 8 17 0.50 0.40 0.30 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 50. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm x 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters Rev. E | Page 44 of 45 PIN 1 INDICATOR 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 10-02-2013-A 4.75 BSC SQ PIN 1 INDICATOR 1 Data Sheet AD7877 2.825 2.765 2.705 5 4 3 2 1 A BALL A1 IDENTIFIER 2.605 2.545 2.485 B 2.00 REF C D E 0.50 BSC TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) SEATING PLANE (BALL SIDE UP) SIDE VIEW COPLANARITY 0.05 0.360 0.320 0.280 0.280 0.240 0.200 10-31-2012-A 0.650 0.590 0.530 0.240 0.220 0.200 Figure 51. 25-Ball Wafer Level Chip Scale Package [WLCSP] 2.5 mm × 2.8 mm Body (CB-25-1) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD7877ACPZ-REEL AD7877ACPZ-REEL7 AD7877ACPZ-500RL7 AD7877ACBZ-REEL AD7877ACBZ-REEL7 AD7877WACPZ-REEL7 EVAL-AD7877EBZ 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 25-Ball WLCSP 25-Ball WLCSP 32-Lead LFCSP_WQ Evaluation Board Package Option CP-32-2 CP-32-2 CP-32-2 CB-25-1 CB-25-1 CP-32-7 Z = RoHS Compliant Part. W = Qualified for Automotive Applications AUTOMOTIVE PRODUCTS The AD7877WACPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2004–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03796-0-12/14(E) Rev. E | Page 45 of 45