24AA174 16K 1.8V Cascadable I2C™ Serial EEPROM with OTP Security Page PACKAGE TYPES FEATURES The Microchip Technology Inc. 24AA174 is a cascadable 16K bit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface and provides a specially addressed OTP (one-time programmable) 16 byte security block. Low voltage design permits operation down to 1.8 volts (end-of-life voltage for most popular battery technologies) with standby and active currents of only 5 µA and 1 mA respectively. The 24AA174 also has a page-write capability for up to 16 bytes of data. The 24AA174 is available in the standard 8-pin DIP and 8-lead surface mount SOIC packages. 8-lead SOIC A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA 24AA174 DESCRIPTION PDIP 24AA174 • Single supply with operation down to 1.8V • 16 bytes OTP Secure Memory • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V - 5 µA standby current typical at 3.0V • Organized as eight blocks of 256 bytes (8 x 256 x 8) • 2-wire serial interface bus, I2C compatible • Functional address inputs for cascading up to 8 devices • Schmitt trigger, filtered inputs for noise suppression • Output slope control to eliminate ground bounce • 100 kHz (1.8V) and 400 kHz (5V) compatibility • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 16 bytes • 2 ms typical write cycle time for page-write • Hardware write protect for entire memory • Can be operated as a serial ROM • Factory programming (QTP) available • ESD protection > 4,000V • 1,000,000 Erase/Write cycles guaranteed • Data retention > 200 years • 8 pin DIP, 8-lead SOIC packages • Available for commercial temperature range - Commercial (C): 0°C to +70°C BLOCK DIAGRAM A0 A1 A2 I/O CONTROL LOGIC WP MEMORY CONTROL LOGIC HV GENERATOR XDEC EEPROM ARRAY (8 x 256 x 8) PAGE LATCHES SDA SCL YDEC VCC VSS SENSE AMP R/W CONTROL The three select pins, A0, A1, and A2, function as chip select inputs and allow up to eight devices to share a common bus, for up to 128K bits total system EEPROM. I2C is a trademark of Philips Corporation. 1999 Microchip Technology Inc. DS21102F-page 1 24AA174 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name Function VSS SDA SCL WP VCC A0, A1, A2 VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ................ -0.3V to Vcc +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied................. -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins ..................................................≥ 4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Ground Serial Address/Data I/O Serial Clock Write Protect Input +1.8V to 5.5V Power Supply Chip Address Inputs DC CHARACTERISTICS VCC = +1.8V to 5.5V Commercial (C): Tamb = 0˚C to +70˚C Parameter Symbol Min Max Units WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) VIH VIL VHYS VOL ILI ILO CIN, COUT .7 VCC — .05 VCC — -10 -10 — — .3 VCC — .40 10 10 10 V V V V µA µA pF ICC Write ICC Read ICCS — — — — 3 1 30 100 mA mA µA µA Operating current Standby current Note: Conditions (Note) IOL = 3.0 mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note1) Tamb = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC WP=VSS This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS21102F-page 2 STOP 1999 Microchip Technology Inc. 24AA174 TABLE 1-3: AC CHARACTERISTICS Standard Mode Parameter Symbol V CC= 4.5 - 5.5V Fast Mode Min Max Min Max Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time TSU:STA 4700 — 600 — ns THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns TOF — 250 250 ns TSP — 50 20 +0.1 CB — (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB ≤ 100 pF 50 ns (Note 3) TWR — — 1M 10 — — 1M 10 — ms Cycles Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition Byte or Page mode 25°C, Vcc = 5.0V, Block Mode (Note 4) 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-2: BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT THD:STA SDA IN TSP TSU:STO TBUF TAA TAA SDA OUT 1999 Microchip Technology Inc. DS21102F-page 3 24AA174 2.0 FUNCTIONAL DESCRIPTION The 24AA174 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA174 works as slave. Both, master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (see Figure 3-1). 3.1 3.4 The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Bus not Busy (A) Data Valid (D) The 24AA174 does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA174) will leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (D) (C) (A) SCL SDA DS21102F-page 4 DATA ALLOWED TO CHANGE STOP CONDITION 1999 Microchip Technology Inc. 24AA174 3.6 Device Addressing A control byte is the first byte received following the start condition from the master device. The first bit is always a one. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used to select which of the eight devices are to be accessed. The A1 bit must be the inverse of the A1 device select pin. The next three bits of the control byte are the block select bits (B2, B1, B0). They are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24AA174 looks for the slave address for the device selected. Depending on the state of the R/W bit, the 24AA174 will select a read or write operation. Operation Read Write Control Code 1 1 FIGURE 3-2: Block Select A2 A1 A0 Block Address A2 A1 A0 Block Address CONTROL BYTE ALLOCATION START READ/WRITE SLAVE ADDRESS 1 A2 A1 A0 MSB B2 R/W A B1 B0 LSB R/W 1 0 4.0 WRITE OPERATION 4.1 Byte Write Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24AA174. After receiving another acknowledge signal from the 24AA174 the master device will transmit the data word to be written into the addressed memory location. The 24AA174 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24AA174 will not generate acknowledge signals (see Figure 4-1). 4.2 The write control byte, word address and the first data byte are transmitted to the 24AA174 in the same way as in a byte write. But instead of generating a stop condition the master transmits up to 16 data bytes to the 24AA174 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (see Figure 4-2). Note: 1999 Microchip Technology Inc. Page Write Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or Ôpage sizeÕ) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. DS21102F-page 5 24AA174 FIGURE 4-1: BYTE WRITE BUS ACTIVITY: MASTER SDA LINE S T A R T BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: 5.0 S T O P DATA S 1 A2 A1 A0 B2 B1 B0 BUS ACTIVITY: FIGURE 4-2: WORD ADDRESS CONTROL BYTE P A C K A C K A C K PAGE WRITE S T A R T S WORD ADDRESS (n) CONTROL BYTE DATA n DATA n + 1 S T O P DATA n + 15 A2 A1 A0 B2 B1 B0 P A C K ACKNOWLEDGE POLLING A C K A C K A C K FIGURE 5-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. A C K ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation 6.0 WRITE PROTECTION The 24AA174 can be used as a serial ROM when the WP pin is connected to VCC. Programming will be inhibited and the entire memory will be write-protected. DS21102F-page 6 1999 Microchip Technology Inc. 24AA174 7.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 7.1 Current Address Read The 24AA174 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24AA174 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA174 discontinues transmission (Figure 8-1). 7.2 Random Read 7.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24AA174 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24AA174 to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24AA174 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows an entire device memory contents to be serially read during one operation. 7.4 Noise Protection The 24AA174 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24AA174 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24AA174 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA174 discontinues transmission (Figure 8-2). 1999 Microchip Technology Inc. DS21102F-page 7 24AA174 8.0 PIN DESCRIPTIONS 8.1 SDA Serial Address/Data Input/Output Note: Up to eight 24AA174s may be connected to the same bus. These pins must be connected to either VSS or VCC. This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400 kHz). 8.5 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 8.3 8.6 WP Security Access Write The S.A.W. data is written to the device using a normal page write following the proper control access sequence. Upon receiving the final stop bit, the internal write sequence will commence. At the completion of the internal write sequence a fuse will be set disabling the write function for the 16 byte security page. This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 000-7FF). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. 8.7 This feature allows the user to use the 24AA174 as a serial ROM when WP is enabled (tied to VCC). 8.4 Security Access Control The security row is enabled by sending the control sequence with the I2C slave address of 0110. Bit 0 of the control byte must be set to a one for a READ OPERATION or a zero for the OTP WRITE OPERATION. The SECURITY ACCESS DATA is always read starting at byte 0 for N bytes up to and including byte 15. (See Figure 4-2). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 8.2 The level on A1 is compared to the inverse of the slave address. Security Access Read The security access read is accomplished by executing the normal read sequences, following the security access control sequence with bit 0 set to a one. The security page read starts at data byte 0. A0, A1, A2 These pins are used to configure the proper chip address in multiple-chip applications (more than one 24AA174 on the same bus). The levels on these pins are compared to the corresponding bits in the slave address. The chip is selected if the compare is true. FIGURE 8-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S 1 A2 A1 A0 B2 B1 B0 CONTROL BYTE DATA n P A C K RANDOM READ BUS ACTIVITY MASTER SDA LINE S T A R T CONTROL BYTE WORD ADDRESS (n) S T A R T S 1 A2 A1A0B2B1B0 BUS ACTIVITY DS21102F-page 8 N O A C K BUS ACTIVITY FIGURE 8-2: S T O P CONTROL BYTE S T O P DATA (n) P S A C K A C K A C K N O A C K 1999 Microchip Technology Inc. 24AA174 FIGURE 8-3: SEQUENTIAL READ BUS ACTIVITY MASTER CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X P SDA LINE A C K BUS ACTIVITY A C K A C K A C K N O A C K FIGURE 8-4: SECURITY CONTROL BYTE ALLOCATION START Operation Control Code Block Select R/W Read 0110 000 1 Write 0110 000 0 READ/WRITE SLAVE ADDRESS 0 1 1 0 0 R/W 0 MSB FIGURE 8-5: A 0 LSB SECURITY PAGE READ BUS MASTER ACTIVITY S T A R T SDA LINE S 0 1 1 0 CONTROL BYTE 0 BUS ACTIVITY CONTROL BYTE S 0 1 1 0 R/W A C K BUS ACTIVITY MASTER S T A R T WORD ADDRESS (n) DATA 1 1 R/W A C K A C K DATA 2 DATA 0 A C K DATA 3 S T O P DATA 15 P SDA LINE FIGURE 8-6: A C K A C K A C K A C K BUS ACTIVITY N O A C K SECURITY PAGE WRITE BUS MASTER ACTIVITY S T A R T SDA LINE S 0 1 1 0 CONTROL BYTE BUS ACTIVITY 1999 Microchip Technology Inc. WORD ADDRESS (n) DATA (n) DATA n + 1 S T O P DATA n + 15 0 R/W A C K P A C K A C K A C K N O A C K DS21102F-page 9 24AA174 NOTES: DS21102F-page 10 1999 Microchip Technology Inc. 24AA174 24AA174 Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24AA174 – /P Package: Temperature Range: Device: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead Blank = 0˚C to +70˚C 24AA174 24AA174T 16K I2C Serial EEPROM 16K I2C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 4/99 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 München, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 03/15/99 Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO). Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21102F-page 12 1999 Microchip Technology Inc.