Revised November 1999 74ABT126 Quad Buffer with 3-STATE Outputs General Description Features The ABT126 contains four independent non-inverting buffers with 3-STATE outputs. ■ Non-inverting buffers ■ Output sink capability of 64 mA, source capability of 32 m ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability ■ Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT126CSC 74ABT126CSJ 74ABT126CMTC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body M14D MTC14 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Descriptions An, Bn Inputs On Outputs Function Table Inputs An Output Bn On H L L H H H L X Z H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial © 1999 Fairchild Semiconductor Corporation DS011692 www.fairchildsemi.com 74ABT126 Quad Buffer with 3-STATE Outputs January 1995 74ABT126 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 100 mV/ns Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. DC Latchup Source Current −300 mA (Across Comm Operating Range) Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. 10V DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA 2.0 V Min IOH = −32 mA V Min IOL = 64 mA µA Max Output LOW Voltage IIH Input HIGH Current V Conditions VIH VOL 2.0 Units 0.55 1 1 Recognized HIGH Signal Recognized LOW Signal µA Max µA Max V 0.0 VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current −1 VID Input Leakage Test IOZH Output Leakage Current 10 µA 0 − 5.5V VOUT = 2.7V; OEn = 2.0V IOZL Output Leakage Current −10 µA 0 − 5.5V VOUT = 0.5V; OEn = 2.0V −1 4.75 VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA, All Other Pin Grounded IOS Output Short-Circuit Current −275 mA Max ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 15 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max OEn = VCC; ICCT Additional ICC/Input Outputs Enabled 1.5 mA Outputs 3-STATE 1.5 mA Outputs 3-STATE 50 µA -100 VOUT = 0.0V All Others at VCC or Ground VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or Ground ICCD Dynamic ICC No Load mA/ (Note 3) 0.1 MHz Outputs Open Max OEn = GND, (Note 4) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD < 0.8 mA/MHz. www.fairchildsemi.com 2 Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Max Min tPLH Propagation Delay Min 1.0 Typ 4.4 1.0 4.4 tPHL Data to Outputs 1.0 4.6 1.0 4.6 tPZH Output Enable 1.0 6.5 1.0 6.5 tPZL Time 1.0 6.5 1.0 6.5 tPHZ Output Disable 1.0 5.8 1.0 5.8 tPLZ Time 1.0 5.5 1.0 5.5 Units Max ns ns ns Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0V COUT (Note 5) Output Capacitance 9.0 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 3 www.fairchildsemi.com 74ABT126 AC Electrical Characteristics 74ABT126 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A www.fairchildsemi.com 4 74ABT126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74ABT126 Quad Buffer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6