Revised March 2005
74ABT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT240CSC
74ABT240CSJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT240CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ABT240CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
OE1, OE2
Description
3-STATE Output
Enable Inputs
I0–I7
Inputs
O0–O7
Outputs
Truth Tables
Inputs
Outputs
In
(Pins 12, 14, 16, 18)
L
L
H
L
H
L
H
X
Z
OE1
Inputs
OE2
Outputs
In
(Pins 3, 5, 7, 9)
L
L
H
L
H
L
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
© 2005 Fairchild Semiconductor Corporation
DS011664
www.fairchildsemi.com
74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
March 1994
74ABT240
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
65qC to 150qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Voltage Applied to Any Output
Data Input
50 mV/ns
Enable Input
20 mV/ns
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-Off State
in the HIGH State
Current Applied to Output
twice the rated IOL (mA)
in LOW State (Max)
DC Latchup Source Current
(Across Comm Operating Range)
150 mA
Over Voltage Latchup (I/O)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
10V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
2.0
Units
VCC
V
Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
IIN
18 mA
VOH
Output HIGH Voltage
2.5
V
Min
IOH
3 mA
2.0
V
Min
IOH
32 mA
V
Min
IOL
64 mA
PA
Max
PA
Max
VOL
Output LOW Voltage
0.55
IIH
Input HIGH Current
1
1
IBVI
Input HIGH Current Breakdown Test
7
IIL
Input LOW Current
1
1
Recognized HIGH Signal
Recognized LOW Signal
PA
Max
V
0.0
VIN
2.7V (Note 3)
VIN
VCC
VIN
7.0V
VIN
0.5V (Note 3)
VIN
0.0V
IID
1.9 PA
VID
Input Leakage Test
IOZH
Output Leakage Current
10
PA
0 5.5V VOUT
2.7V; OEn
2.0V
IOZL
Output Leakage Current
10
PA
0 5.5V VOUT
0.5V; OEn
2.0V
IOS
Output Short-Circuit Current
275
mA
Max
VOUT
0.0V
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
VCC
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.5V; All Others GND
ICCH
Power Supply Current
50
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
PA
Max
4.75
All Other Pins Grounded
100
OEn
VCC;
All Others at VCC or Ground
ICCT
Additional ICC/Input
VCC 2.1V
Outputs Enabled
1.5
mA
VI
Outputs 3-STATE
1.5
mA
Enable Input VI
Outputs 3-STATE
50
PA
Max
Data Input VI
VCC 2.1V
VCC 2.1V
All Others at VCC or Ground
ICCD
Dynamic ICC
No Load
mA/
(Note 3)
0.1
MHz
Outputs Open
Max
OEn
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, ICCD 0.8 mA/MHz.
www.fairchildsemi.com
2
25qC
TA
VCC
Symbol
CL
Parameter
Min
TA
5V
55qC to 125qC
VCC
50 pF
CL
Typ
Max
TA
4.5V–5.5V
Min
40qC to 85qC
VCC
50 pF
4.5V–5.5V
CL
Max
50 pF
Min
Units
Max
tPLH
Propagation Delay
1.0
4.8
0.8
5.5
1.0
4.8
tPHL
Data to Outputs
1.6
4.8
1.0
5.5
1.6
4.8
tPZH
Output Enable
1.1
6.2
0.8
7.5
1.1
6.2
tPZL
Time
1.1
6.2
0.8
7.7
1.1
6.2
tPHZ
Output Disable
1.8
6.4
1.0
7.5
1.8
6.4
tPLZ
Time
1.6
5.8
1.0
7.2
1.6
5.8
ns
ns
ns
Capacitance
Symbol
Parameter
CIN
Input Capacitance
COUT (Note 5)
Output Capacitance
Note 5: COUT is measured at frequency f
Conditions
Typ
Units
5.0
pF
VCC
0V
9.0
pF
VCC
5.0V
TA
25qC
1 MHz, per MIL-STD-883, Method 3012.
3
www.fairchildsemi.com
74ABT240
AC Electrical Characteristics
74ABT240
AC Loading
*Includes jig and probe capacitance
Standard AC Test Load
Test Input Signal Levels
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
Test Input Signal Requirements
AC Waveforms
Propagation Delay,
Pulse Width Waveforms
Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
3-STATE Output HIGH
and LOW Enable and Disable Times
Setup Time, Hold Time
and Recovery Time Waveforms
www.fairchildsemi.com
4
74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
www.fairchildsemi.com
74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
6
74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
7
www.fairchildsemi.com
74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
www.fairchildsemi.com
8