ACECore MIL-STD-1553 Intellectual Property (IP) Core www.ddc-web.com MODEL: BU-69200 FEATURES • Modular and Universally Synthesizable Code for Enhanced Mini-ACE - Industry Standard, Proven Design - Use Enhanced Mini-ACE Hybrid for Prototyping • Includes VHDL Design and VHDL Test Bench Code • BC/RT/Monitor and RT-Only Configurations. • Single Clock Domain, Selectable for 10, 12, 16, or 20 MHz Operation • Fully Synchronous Design • Approximately 20,000 ASIC Gates for BC/RT/MT Instantiation, Highly Optimized Design • Provision for up to 64K Words OffCore Buffer RAM, with Optional RAM Parity Bit • Provision for Off-Core Built-In Self-Test ROM • On-Core Buses are Unidirectional (not tri-state). Tri-State Buses May be Created Using Off-Core Buffers • Instantiate on FPGAs or ASICs • Passed MIL-STD-1553 RT Validation Testing • Compatible with DDC Transceivers • Complete Documentation Provided • Scalable to Higher Bit Rates • Applications: - Space/Rad Hard Applications - High Volume Applications DESCRIPTION The ACECore Intellectual Property (IP) is based on the architecture of DDC's powerful Enhanced Mini-ACE MIL-STD-1553 protocol engine. As such, it provides compatibility with all previous and current generations of DDC components, including AIM-HY, AIM-HY'er, ACE, Mini-ACE, as well as Enhanced Mini-ACE, PCI Enhanced Mini-ACE, and µ-ACE. As a result, the ACECore IP brings a legacy of demonstrated performance in a myriad of air, land, and space applications. Further, this compatibility enables designers to leverage investments in legacy ACE software and to accelerate development efforts using DDC's components early in their design phase. The ACECore provides VHDL core source code, VHDL test bench, and supporting documentation, thus enabling designers to instantiate the architecture in a variety of PLD, FPGA, or ASIC System on a Chip (SoC) implementations. The ACECore can be configured as BC/RT/MT, RT-only, or customized for your requirements. The core provides a high degree of flexibility in terms of processor interface, memory architecture, and self-test functionality. To minimize design risk, the design of the ACECore's manchester encoder/decoder is highly optimized for use with DDC's 5V or 3.3V transceivers. The ACECore's advanced bus controller architecture provides methods to control message scheduling, along with the means to minimize host overhead for asynchronous message insertion, facilitate bulk data transfers and double buffering, and support various message retry and bus switching strategies. The ACECore's remote terminal architecture provides flexibility in meeting all common MIL-STD-1553 protocols. The choice of RT data buffering and interrupt options provides robust support for synchronous and asynchronous messaging, while ensuring data sample consistency and supporting bulk data transfers. The ACECore message monitor (and combined RT/Monitor) enables true message monitoring, with filtering on an RT address/T-R bit/subaddress basis. The ACECore includes provides robust built-in self-tests for protocol, transceivers, and RAM. All trademarks are the property of their respective owners © 2002 Data Device Corporation Specifications PARAMETER ASIC GATE COUNT CORE CONFIGURATIONS PROTOCOLS SUPORTED MEMORY SUPPORT 1553 Message, Control, and Status RAM Protocol Self-Test ROM or RAM CLOCK INPUT Number Of Clock Domains Frequency: Nominal Values Default Mode Option Option Option MIN TYP MAX UNITS 20,000 BC/RT/Monitor, RT-only MIL-STD-1553A/B Notice 2 STANAG-3838 MIL-STD-1760 64K X 16 or 64K X 17 4K X 24 1 16.0 12.0 10.0 20.0 MHz MHz MHz MHz PARAMETER MIN TYP 1553 MESSAGE TIMING BC Intermessage Gap - Non-enhanced (Mini-ACE compatible) BC mode - Enhanced BC Mode BC/RT/MT Response Timeout 18.5 nominal 22.5 nominal 50.5 nominal 128.0 nominal RT Response Time (mid-parity to mid-sync) Transmitter Watchdog Timeout 17.5 21.5 49.5 127 MAX UNITS 9.5 µS 10.0 to 10.5 µS 18.5 22.5 50.5 129.5 91.5 23.5 51.5 131 µS µS µS µS 7 µS µS 4 660.5 SOURCE CODE LANGUAGE VHDL SUPPORT DOCUMENTATION ACECore IP User's Guide Enhanced Mini-ACE User's Guide BC Architecture - Highly Autonomous Message Sequence Control Defined Set of 20 Instructions Control/Status Blocks for Individual Messages Minor and Major Frame Scheduling Asynchronous Message Insertion Conditional Branching and Subroutines General Purpose Queue: Message Status, Time, Immediate and Indirect Data - Fully User-definable Interrupts - Legacy Mode for Compatibility with ACE and Mini-ACE Applications RT Architecture - Supports MIL-STD-1553A/B Notice 2, STANAG-3838 RT, and MIL-STD-1760 Stores Management - Choice of Subaddress Single Message, Double Buffering, or Circular Buffering; or Global Circular Buffering - 32-Entry Interrupt Status Queue - 50% and 100% Circular Buffer Rollover Interrupts - Stack with Descriptors for Individual Messages - Message Status, Time Tag, Command Word, Data Pointer Data Device Corporation www.ddc-web.com - Programmable Command Illegalization - Programmable Busy by Subaddress - Interrupts on All Messages, or Individual Subaddresses and/or Mode Codes - Hardwired or Software-Programmable RT Address - Available with Option for RT AUTO-BOOT with BUSY Bit Set for MIL-STD-1760 Applications - Compatible with ACE and Mini-ACE Applications Monitor Architecture - Selective Message Monitor Filter Based on RT Address, T/R* bit, Subaddress True Message Monitor Command Stack Message Status, Time Tag, Command Word, Data Pointer - Data Stack - All Monitored Words Following (first) Command Word - 50% and 100% Rollover Interrupts for Command and Data Stacks - 32-Entry Interrupt Status Queue - Simultaneous RT/Message Monitor Option BU-69200 REV CODE 1 Autonomous Built-In Self-Test Capability Development Environment/Tools - Protocol Self-Test RAM Self-Test Online Loopback Test Capability to Support Channel A-to-Channel B Wraparound Test - Capability to Test Transmitter Timeout Function - Protocol Self-Test May be Run From External Host - DDC Development Tools: Mentor Graphics Workstation; Renoir Design Entry (Including for Block Diagrams); Leonardo Synthesizer; Model Technology Simulation Tool - Sample Synthesis Scripts - VHDL Test Bench Miscellaneous Host and Memory Interface Configurations - Reset Philosophy: Hardware and Software Mechanisms for Resetting All Flip-Flops - No On-Chip Tri-State Buses. - Shared RAM, Up to 64K X 16 or 64K X 17 (with RAM parity) - 16-bit Address, 16-bit or 8-bit Data Path - "Zero Wait State" Interface (no hardware acknowledge) for Microcontrollers - Support of DMA Configuration, Enabling Core Access of RAM on Host Processor Bus - Supports Use of External Dual Port RAM ACECore Functional Blocks Figure 1 Decoder DDC 3.3V or 5V Dual Transceiver Interrupt Logic INT* Encoder Decoder Encoder Data Device Corporation www.ddc-web.com Protocol State Machines: • BC • RT • Monitor DATA Registers: • Configuration • Interrupts • Self-Test • Other Functions Host Interface Buffers and Logic Shared RAM Interface Built-in Self-Test Logic Shared RAM (up to 64K X 17) Self-Test ROM (4K X 24 optional) ADDRESS CONTROL ® DnC d D ooar B BU-69200 REV CODE 1 BU-69200 X X Base Product BU-69200 = MIL-STD-1553 ACECore Intellectual Property Architecturally Compatible Products • • • • • • • AIM AIM HIGHER ACE Mini-ACE™ Enhanced Mini-ACE™ m-ACE™ (Micro-ACE) Series Mini-ACE™ Mark3 Series The information in this product brief is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. I www.ddc-web.com Call DDC or visit www.ddc-web.com for a quote today: 105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7234 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 REV 1 - 08/02 - RM ® FI REG U ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 PRINTED IN THE U.S.A.