ETC 5962F8957701QZXA

UT1553 BCRTM
p Register-oriented architecture to enhance
FEATURES
p Comprehensive MIL-STD-1553 dual-redundant Bus
p
p
p
p
p
programmability
p DMA memory interface with 64K addressability
p Internal self-test
p Radiation-hardened option available for 84-lead
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
MIL-STD-1773 compatible
Multiple message processing capability in BC
Time tagging and message logging in RT and M modes
Automatic polling and intermessage delay in
BC mode
Programmable interrupt scheme and internally
generated interrupt history list
flatpack package only
p Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p Available in 84-pin pingrid array, 84-lead flatpack, 84lead leadless chip-carrier
p Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
REGISTERS
CONTROL
MASTER
RESET
12MHz
STATUS
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
CURRENT BC (or M) BLOCK/
RT DESCRIPTOR SPACE
POLLING COMPARE
INTERRUPT
HANDLER
CLOCK &
RESET
LOGIC
1553
DATA
CHANNEL
A
1553
DATA
CHANNEL
B
TIMERON
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
CURRENT COMMAND
PARALLELTO-SERIAL
CONVERSION
ADDRESS
GENERATOR
INTERRUPT LOG
LIST POINTER
BC PROTOCOL
&
MESSAGE
HANDLER
HIGH-PRIORITY
INTERRUPT ENABLE
BUS
TRANSFER
LOGIC
16
SERIAL-TOPARALLEL
CONVERSION
TIMEOUT
BUILT-IN-TEST WORD
HIGH-PRIORITY
INTERRUPT STATUS
16
STANDARD INTERRUPT
ENABLE
16
RT/MONITOR
PROTOCOL &
MESSAGE
HANDLER
16
DMA/CPU
CONTROL
16
RT ADDRESS
BUILT-IN-TEST
START COMMAND
16
BUILTINTEST
RESET COMMAND
RT TIMER
RESET COMMAND
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
DMA ARBITRATION
REGISTER CONTROL
ADDRESS
MONITOR ADDRESS
SELECT (16-31)
DUAL-PORT MEMORY CONTROL
16
Figure 1. BCRTM Block Diagram
16
DATA
BCRTM-1
Table of Contents
1.0
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
2.0
PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0
INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.0
SYSTEM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.2
5.3
5.4
5.6
6.0
6.2
6.3
7.0
RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
7.4
7.5
8.0
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
REMOTE TERMINAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MONITOR ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
8.2
8.3
BCRTM-2
Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.0
EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . . . . . 36
10.0
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . 40
11.0
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.0
AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.0
PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.0 INTRODUCTION
The monolithic CMOS UT1553 BCRTM provides the
system designer with an intelligent solution to
MIL-STD-1553B multiplexed serial data bus design
problems. The UT1553B BCRTM is a single-chip device
that implements all three of defined MIL-STD-1553B
functions - Bus Controller, Remote Terminal, and Monitor.
Designed to reduce host CPU overhead, the BCRTM’s
powerful state machines automatically execute message
transfers, provide interrupts, and generate status
information. Multiple registers offer many programmable
functions as well as extensive information for host use. In
the BC mode, the BCRTM uses a linked-list message
scheme to provide the host with message chaining
capability. The BCRTM enhances memory use by
supporting variable-size, relocatable data blocks. In the RT
mode, the BCRTM implements time-tagging and message
history functions. It also supports multiple (up to 128)
message buffering and variable length messages to any
subaddress.In the Monitor (M) mode, the BCRTM’s
powerful linked list command block structure allows it to
process a series of monitored 1553 messages without the
intervention of the host. The BCRTM can store as much bus
traffic as can be contained in its 64K memory space. In
addition, the host has the capability of instructing the
BCRTM to monitor and store data for only selected remote
terminals.
The UT1553 BCRTM is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRTM is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTM, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTM can use as little or as much memory (up to
64K) as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTM stores/retrieves, by subaddress, all messages
in the order in which they are transacted.
Sequential Message Status Information
The BCRTM provides message validity, time-tag, and
word-count information, and stores it sequentially in a
separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRTM autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTM can delay a
host-specified time before executing the next message in
sequence.
Automatic Polling
When polling, the BCRTM interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTM
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.
Automatic Retry
The BCRTM can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTM can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
Variable Space Allocation
The BCRTM uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
BCRTM-3
1.3 Features - Monitor (M) Mode
Command History List
The BCRTM’s linked list command block structure permits
the BCRTM to process a series of monitored messages
without host intervention.
Monitor Selected Terminal Address
The host can select the remote terminals to be monitored by
programming the proper bits in the Terminal Address Select
registers (Registers16 and 17). The BCRTM can monitor
any or all remote terminals.
Variable Space Allocation
The BCRTM can use as little or as much memory (up to
64K) as needed
BCRTM-4
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTM stores, by Terminal Address, all 1553
messages in the order in which they are transacted.
Programmable Interrupt Selection
The host can select a wide variety of events that may cause
an interrupting event.
Interrupt History List
The BCRTM stores, chronologically in memory, an
Interrupt History List of each event that causes an interrupt.
2.0 PIN IDENTIFICATION AND DESCRIPTION
BIPHASE OUT
TAZ
TAO
TBZ
TBO
13
14
17
18
(K3)
(L2)
(L4)
(K6)
BIPHASE IN
RAZ
RAO
RBZ
RBO
15
16
19
20
(L3)
(K4)
(K5)
(L5)
TERMINAL
ADDRESS
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
28
29
30
31
32
33
(K8) **
(L9) **
(L10) **
(K9) **
(L11) **
(K10) **
STATUS
SIGNALS
STDINTL
STDINTP
HPINT
TIMERON
COMSTR
SSYSF
BCRTF
CHA/B
TEST
68
69
70
25
27
72
75
26
73
(A6) +
(A4)
(B4) +
(K7)
(L8)
(A2)
(B2)
(J7)
(B3)*
DMAR
DMAG
DMAGO
DMACK
BURST
TSCTL
56
57
67
58
74
55
(A10) +
(A9)
(B5)
(B8) +
(A1)
(B9)
DMA
SIGNALS
RD
WR
CS
AEN
BCRTSEL
LOCK
CONTROL
MRST
SIGNALS
EXTOVR
RRD
RWR
MEMCSI
MEMCSO
**
+
++
*
Pin internally pulled up.
Pin at high impedance when not asserted
Bidirectional pin.
Formerly MEMWIN.
61
60
62
66
11
12
10
24
53
52
59
54
(B7)
(C7)
(A7)
(A5)
(L1) * *
(K2) * *
(J2)
(L7) * *
(A11)
(C10)
(A8) * *
(B10)
(J10)
(K11)
(J11)
(H10)
(H11)
(G9)
(G10)
(G11)
(E9)
(E11)
(E10)
(F11)
(D11)
(D10)
(C11)
(B11)
34
35
36
37
38
39
40
41
44
45
46
47
48
49
50
51
A0 ++
A1 ++
A2 ++
A3 ++
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
ADDRESS+
LINES
(K1)
(J1)
(H2)
(H1)
(G3)
(G2)
(G1)
(F1)
(E1)
(E2)
(F2)
(D1)
(D2)
(C1)
(B1)
(C2)
9
8
7
6
5
4
3
2
83
82
81
80
79
78
77
76
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DATA
++
LINES
(L6)
(F9)
(C6)
(E3)
23
43
64
84
VDD
VDD
VDD
VDD
POWER
(F3)
(J6)
(F10)
(B6)
1
22
42
63
VSS
VSS
VSS
VSS
GROUND
(J5)
(C5)
(A3)
21
65
71
CLK
MCLK
MCLKD2
CLOCK
SIGNALS
() Pingrid array pin identification in parentheses.
LCC, flatpack pin number not in parentheses.
Figure 2. BCRT Functional Pin Description
BCRTM-5
Legend for TYPE and ACTIVE fields:
TUI = TTL input (pull-up)
AL = Active low
AH = Active high
ZL = Active low - inactive state is high impedance
TI = TTL input
TO = TTL output
TTO = Three-state TTL output
TTB = Bidirectional
Notes:
1. Address and data buses are in the high-impedance state when idle.
2. Flatpack pin numbers are same as LCC.
NAME
PIN NUMBER
LCC
PGA
A0
34
A1
TYPE
ACTIVE
J10
TTB
--
Bit 0 (LSB) of the Address bus
35
K11
TTB
--
Bit 1 of the Address bus
A2
36
J11
TTB
--
Bit 2 of the Address bus
A3
37
H10
TTB
--
Bit 3 of the Address bus
A4
38
H11
TTB
--
Bit 4 of the Address bus
A5
39
G9
TTO
--
Bit 5 of the Address bus
A6
40
G10
TTO
--
Bit 6 of the Address bus
A7
41
G11
TTO
--
Bit 7 of the Address bus
A8
44
E9
TTO
--
Bit 8 of the Address bus
A9
45
E11
TTO
--
Bit 9 of the Address bus
A10
46
E10
TTO
--
Bit 10 of the Address bus
A11
47
F11
TTO
--
Bit 11 of the Address bus
A12
48
D11
TTO
--
Bit 12 of the Address bus
A13
49
D10
TTO
--
Bit 13 of the Address bus
A14
50
C11
TTO
--
Bit 14 of the Address bus
A15
51
B11
TTO
--
Bit 15 (MSB) of the Address bus
BCRTM-6
DESCRIPTION
DATA BUS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
D0
9
K1
TTB
--
Bit 0 (LSB) of the Data bus
D1
8
J1
TTB
--
Bit 1 of the Data bus
D2
7
H2
TTB
--
Bit 2 of the Data bus
D3
6
H1
TTB
--
Bit 3 of the Data bus
D4
5
G3
TTB
--
Bit 4 of the Data bus
D5
4
G2
TTB
--
Bit 5 of the Data bus
D6
3
G1
TTB
--
Bit 6 of the Data bus
D7
2
F1
TTB
--
Bit 7 of the Data bus
D8
83
E1
TTB
--
Bit 8 of the Data bus
D9
82
E2
TTB
--
Bit 9 of the Data bus
D10
81
F2
TTB
--
Bit 10 of the Data bus
D11
80
D1
TTB
--
Bit 11 of the Data bus
D12
79
D2
TTB
--
Bit 12 of the Data bus
D13
78
C1
TTB
--
Bit 13 of the Data bus
D14
77
B1
TTB
--
Bit 14 of the Data bus
D15
76
C2
TTB
--
Bit 15 (MSB) of the Data bus
TYPE
ACTIVE
TERMINAL ADDRESS INPUTS
NAME
PIN NUMBER
LCC
PGA
RTA0
28
K8
TUI
--
Remote Terminal Address Bit 0 (LSB). The entire
RT address is strobed in at Master Reset. Verify it
by reading the Remote Terminal Address Register.
All the Remote Terminal Address bits are internally
pulled up.
RTA1
29
L9
TUI
--
Remote Terminal Address Bit 1. This is bit 1 of
the Remote Terminal Address.
RTA2
30
L10
TUI
--
Remote Terminal Address Bit 2. This is bit 2 of
the Remote Terminal Address.
RTA3
31
K9
TUI
--
Remote Terminal Address Bit 3. This is bit 3 of
the Remote Terminal Address.
RTA4
32
L11
TUI
--
Remote Terminal Address Bit 4. This is bit 4
(MSB) of the Remote Terminal Address.
RTPTY
33
K10
TUI
--
Remote Terminal (Address) Parity. This is an odd
parity input for the Remote Terminal Address.
DESCRIPTION
BCRTM-7
CONTROL SIGNALS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
RD
61
B7
TI
AL
Read. The host uses this in conjunction with CS to read an
internal BCRTM register.
WR
60
C7
TI
AL
Write. The host uses this in conjunction with CS to write to an
internal BCRTM register.
CS
62
A7
TI
AL
Chip Select. This selects the BCRTM when accessing
the BCRTM’s internal register.
AEN
66
A5
TI
AH
Address Enable. The host CPU uses AEN to indicate to the
BCRTM that the BCRTM’s address lines can be asserted;
this is a precautionary signal provided to avoid address bus
crash. If not used, it must be tied high.
BCRTSEL
11
L1
TUI
--
LOCK
12
K2
TUI
AH
EXTOVR
24
L7
TUI
AL
MRST
10
J2
TI
AL
MEMCSO
54
B10
TO
AL
MEMCSI
59
A8
TUI
AL
Memory Chip Select In. Used in the pseudo-dual-port
RAM mode only, MEMCSI is received from the host and
is propagated through to the MEMCSO.
RRD
53
A11
TO
AL
RAM Read. In the pseudo-dual-port RAM mode, the host
uses this signal in conjunction with MEMCSO to read
from external RAM through the BCRTM. It is also the
signal the BCRTM uses to read from memory. It is
asserted following receipt of DMAG. When the BCRTM
performs multiple reads, this signal is pulsed.
RWR
52
C10
TO
AL
RAM Write. In the pseudo-dual-port RAM mode, the
CPU and BCRTM use this to write to external RAM. This
signal is asserted following receipt of DMAG. For multiple writes, this signal is pulsed.
BCRTM-8
BC/RT Select. This selects between either the Bus Controller or Remote Terminal mode. The BC/RT Mode
Select bit in the Control Register overrides this input if
the LOCK pin is not high. This pin is internally
pulled high.
Lock. When set, this pin prevents internal changes
to both the RT address and BC/RT mode select functions.
This pin is internally pulled high.
External Override. Use this in multi-redundant applications. Upon receipt, the BCRTM aborts all current activity. EXTOVR should be connected to COMSTR output of
the adjacent BCRTM when used. This pin is internally
pulled high.
Master Reset. This resets all internal state machines,
encoders, decoders, and registers. The minimum pulse
width for a successful Master Reset is 500ns.
Memory Chip Select Out. This is the regenerated
MEMCSI input for external RAM during the pseudodual-port RAM mode. The BCRTM also uses it to select
external memory during memory accesses.
STATUS SIGNALS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
STDINTL
68
A6
TTO
ZL
Standard Interrupt Level. This is a level interrupt. It is
asserted when one or more events enabled in either the
Standard Interrupt Enable Register, RT Descriptor, or BC
Command Block occur. Resetting the Standard Interrupt
bit in the High-Priority Interrupt Status/Reset Register
clears the interrupt.
STDINTP
69
A4
TO
AL
Standard Interrupt Pulse. STDINTP pulses when an interrupt is logged.
HPINT
70
B4
TTO
ZL
High Priority Interrupt. The High-Priority Interrupt level
is asserted upon occurrence of events enabled in the High
Priority Interrupt Enable Register. The corresponding
bit(s) in the High-Priority Interrupt Status/Reset Register
reset HPINT.
TIMERON
25
K7
TO
AL
COMSTR
27
L8
TO
AL
SSYSF
72
A2
TI
AH
BCRTF
75
B2
TO
AH
CHA/B
26
J7
TO
--
TEST
73
B3
TO
AL
(RT)Timer On. This is a 760-microsecond fail-safe transmitter enable timer. Started at the beginning of a transmission. TIMERON goes inactive 760 microseconds later or
is reset automatically with the receipt of a new command.
Use it in conjunction with CHA/B output to provide a fail
safe timer for channel A and B transmitters.
(RT) Command Strobe. The BCRTM asserts this
signal after receiving a valid command. The BCRTM deactivates it after servicing the command.
Subsystem Fail. Upon receipt, this signal propagates
directly to the RT 1553 status word and the BCRTM
Status Register.
BCRT Fail. this indicates a Built-In-Test (BIT) failure.
In the RT mode, the Terminal Flag bit in 1553 status word
is also set.
Channel A/B. This indicates the active or last active
channel.
TEST. This pin is used as a factory test pin. (Formerly
MEMWIN.)
BIPHASE INPUTS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
RAO
16
K4
TI
--
Receive Channel A One. This is the Manchester-en-coded
true signal input from Channel A of the bus receiver
RAZ
15
L3
TI
--
Receive Channel A Zero. This is Manchester-encoded
complementary signal input from Channel A of the bus
receiver
RBO
20
L5
TI
--
Receive Channel B One. This is the Manchester-en-coded
true signal input from Channel B of the bus receiver.
RBZ
19
K5
TI
--
Receive Channel B Zero. This is the Manchester-en-coded
complementary signal input from Channel B of the bus
receiver
BCRTM-9
BIPHASE OUTPUTS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
TAO
14
L2
TO
--
Transmit Channel A One. This is the Manchester-encoded
true output to be connected to the Channel A bus transmitter
input. This signal is idle low.
TAZ
13
K3
TO
--
Transmit Channel A Zero. This is the Manchester-encoded
complementary output to be connected to the Channel A bus
transmitter input. This signal is idle low.
TBO
18
K6
TO
--
Transmit Channel B One. This is the Manchesterencoded true output to be connected to the Channel B bus
transmitter input. This signal is idle low.
L4
TO
--
Transmit Channel B Zero. This is the Manchester-encoded
complementary output to be connected to the Channel B bus
transmitter input. This signal is idle low.
TYPE
ACTIVE
DESCRIPTION
TBZ
17
DMA SIGNALS
NAME
PIN NUMBER
LCC
PGA
DMAR
56
A10
TTO
ZL
DMA Request. The BCRTM issues this signal when access to
RAM is required. It goes inactive after receiving a DMAG
signal.
DMAG
57
A9
TI
AL
DMA Grant. This input to the BCRTM allows the
BCRT to access RAM. It is recognized 45ns before the rising
edge of MCLKD2.
DMAGO
67
B5
TO
AL
DMA Grant Out. If DMAG is received but not needed, it
passes through to this output.
DMACK
58
B8
TTO
ZL
DMA Acknowledge. The BCRTM asserts this signal to confirm
receipt of DMAG, it stays low until memory access is complete.
BURST
74
A1
TO
AH
Burst (DMA Cycle). This indicates that the current
DMA cycle transfers at least two words; worst case is five words
plus a “dummy” word.
TSCTL
55
B9
TO
AL
BCRTM-10
Three-State Control. This signal indicates when the
BCRTM is actually accessing memory. The host subsystem’s
address and data lines must be in the high-impedance state when
the signals active. This signal assists in placing the external data
and address buffers into the high-impedance state.
CLOCK SIGNALS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
CLK
21
J5
TI
--
Clock. The 12MHz input clock requires a 50%
± 10% duty cycle with an accuracy of ± 0.01%. The accuracy
is required in order to meet the Manchester encoding/
decoding requirements of MIL-STD-1553.
MCLK
65
C5
TI
--
Memory Clock. This is the input clock frequency the BCRTM
uses for memory accesses. The memory cycle time is equal
to two MCLK cycles. Therefore, RAM access time is
dependent upon the chosen MCLK frequency (6MHz
minimum, 12MHz maximum). Please see the BCRTM DMA
timing diagrams in this data sheet.
MCLKD2
71
A3
TO
--
Memory Clock Divided by Two. This signal is the
Memory Clock input divided by two. It assists the
host subsystem in synchronizing DMA events.
TYPE
ACTIVE
POWER AND
NAME
PIN NUMBER
LCC
PGA
DESCRIPTION
VDD
23
L6
PWR
--
+5V
VDD
43
F9
PWR
--
+5V
VDD
64
G13
PWR
--
+5V
VDD
84
C7
PWR
--
+5V
VSS
1
J3
GND
--
Ground
VSS
22
N8
GND
--
Ground
VSS
42
F10
GND
--
Ground
VSS
63
B6
GND
--
Ground
BCRTM-11
3.0 INTERNAL REGISTERS
The BCRTM’s internal registers (see table 1 on pages 1819) enable the CPU to control the actions of the BCRTM
while maintaining low DMA overhead by the BCRTM. All
functions are active high and ignored when low unless stated
otherwise. Functions and parameters are used in both RT
and BC modes except where indicated. Registers are
addressed by the binary equivalent of their decimal number.
For example, Register 1 is addressed as 0001B. Register
usage is defined as follows:
#0 Control Register
Bit
Number
Description
BIT 15
Reserved.
BIT 14
Rt Address 31. When RT31=0, the BCRTM recognizes RT Address 31 as a Broadcast command. When
RT31=1,the BCRTM treats RT Address 31 as a normal terminal address.
BIT 13
Subaddress 31. When SA31=0, the BCRTM recognizes a command word with either subaddress 0 or 31 as being
a valid code. When SA31=1, the BCRTM only recognizes a command word with a subaddress of 0 as a valid
mode code.
BIT 12
Bus Controller Time out. When the BCRTM is a BC and BCTO=0, the BCRTM allows an RT up to 16us to
respond with a status word before it declares a bus time-out. If BCTO=1, the BCRTM allows an RT up to 32us to
respond with a status word before it declares a bus time-out. In the remote terminal mode of operation, this bit
controls to RT to RT response time-out. To support the requirements of MIL-STD-1553B, this bit is set to a
logical zero.
BIT 11
Enable External Override. For use in multi-redundant systems. This bit enables the EXTOVR pin.
BIT 10
BC/RT Select. This function selects between the Bus Controller and Remote Terminal/Monitor operation
modes. It overrides the external BCRTSEL input setting if the Change Lock-Out function is not used. A reset
operation must be performed when changing between BC and RT/M modes. For monitor operation this bit
must be "0". This bit is write-only.
BIT 9
(BC) Retry on Alternate Bus. This bit enables an automatic retry to operate on alternate buses. For example, if
on bus A, with two automatic retries programmed, the automatic retries occur on bus B.
BIT 8
(RT,M) Channel B Enable. When set, this bit enables Channel B operation.
(BC) No significance.
BIT 7
(RT,M) Channel A Enable. When set, this bit enables Channel A operation.
(BC) Channel Select A/B. When set, this bit selects Channel A.
BITs 6-5
(BC) Retry Count. These bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries)
BIT 4
(BC) Retry on Bus Controller Message Error. This bit enables automatic retries on an error the Bus Controller
detects (see the Bus Controller Architecture section, page 29).
BIT 3
(BC) Retry on Time-Out. This bit enables an automatic retry on a response time-out condition.
BIT 2
(BC) Retry on Message Error. This bit enables an automatic retry when the Message Error bit is set in the RT’s
status word response.
BIT 1
(BC) Retry on Busy. This bit enables automatic retry on a received Busy bit in an RT status word response.
BIT 0
Start Enable. In the BC mode, this bit starts/restarts Command Block execution. In the RT or M mode,
It enables the BCRTM to receive a valid command. RT operation does not start until a valid command is
received. When using this function:
•
•
BCRTM-12
Restart the BCRTM after each Master Reset or programmed reset.
This bit is not readable; verify operation by reading bit 0 of the BCRTM’s Status Register.
#1 Status Register (Read Only)
These bits indicate the BCRTM’s current status.
Bit
Number
Description
BIT 15
TEST. This bit reflects the inverse of the TEST output. It changes state simultaneously with the TEST output.
BIT 14
(RT,M) Remote Terminal (or Monitor) Active. Indicates that the BCRTM, in the Remote Terminal (or Monitor)
mode, is presently servicing a command. This bit reflects the inverse of the COMSTR pin.
BIT 13
(RT) Dynamic Bus Control Acceptance. This bit reflects the state of the Dynamic Bus Control
Acceptance bit in the RT status word (see Register 10 on page 16).
BIT 12
(RT) Terminal Flag bit is set in RT status word. This bit reflects the result of writing to Register 10, bit 11
BIT 11
(RT) Service Request bit is set in RT status word.This bit reflects the result of writing to Register 10, bit 10.
BIT 10
(RT) Busy bit is set in RT status word.This bit reflects the result of writing to Register 10, bits 9 or 14.
BIT 9
BIT is in progress.
BIT 8
Reset is in progress. This bit indicates that either a write to Register 12 has just occurred or the BCRTM has
just received a Reset Remote Terminal (#01000) Mode Code. This bit remains set less than 1ms.
BIT 7
BC/(RT) Mode. Indicates the current mode of operation. A reset operation must be performed when changing
between BC and RT modes.
BIT 6
Channel A/B. Indicates either the channel presently in use or the last channel used.
BIT 5
Subsystem Fail Indicator. Indicates receiving a subsystem fail signal from the host subsystem on the
SSYSF input.
BITs 4-1
Reserved.
BIT 0
(BC) Command Block Execution is in progress. (RT) Remote Terminal is in operation. This bit reflects bit 0 of
Register 0.
#2 Current Command Block Register (BC,M)/Remote Terminal Descriptor Space Address Register (RT)
(BC) This register contains the address of the head pointer of the Command Block being executed. Accessing a new Command
Block updates it.
(RT) The host CPU initializes this register to indicate the starting location of the RT Descriptor Space. The host must allocate
320 sequential locations following this starting address. For proper operation, this location must start on an I x 512 decimal
address boundary, where I is an integer multiple.
(M) This register contains the address of the control/status word of the current Monitor Command Block. Accessing a new
Command Block updates it.
#3 Polling Compare Register
In the polling mode, the CPU sets the Polling Compare Register to indicate the RT response word on which the BCRTM should
interrupt. This register is 11 bits wide, corresponding to bit times 9 through 19 of the RT’s 1553 status word response. The
sync, Remote Terminal Address, and parity bits are not included (see the section on Polling, page 32).
BCRTM-13
#4 BIT (Built-In-Test) Word Register
The BCRTM uses the contents of this register when it responds to the Transmit BIT Word Mode Code (#10011). In addition,
the BCRTM writes to the two most significant bits of the BIT Word Register in response to either an Initiate Self-Test Mode
Code (RT mode) or a write to Register 11 (BIT Start Command) to indicate a BIT failure. If the BIT Word needs to be modified,
it can be read out, modified, then rewritten to this register. Note that if the processor writes a “1” to either bit 14 or 15 of this
register, it effectively induces a BIT failure.
Bit
Number
BIT 15
BIT 14
BIT 13-0
Description
Channel B failure.
Channel A failure.
BIT Word. The least significant fourteen bits of the BIT Word are user programmable.
#5 Current Command Register (Read Only)
In the RT or Monitor mode, this register contains the command currently being processed. When not processing a command,
the BCRTM stores the last command or status word transmitted on the 1553B bus in this register. This register is updated only
when bit 0 of Register 0 is set. In the BC mode, this register contains the most current command sent out on the 1553B bus.
#6 Interrupt Log List Pointer Register
Initialized by the CPU, the Interrupt Log List Pointer Register indicates the start of the Interrupt Log List. After each list entry,
the BCRTM updates this register with the address of the next entry in the list. (See page 37.)
#7 High-Priority Interrupt Enable Register (Read/Write)
Setting the bits in this register causes a High-Priority Interrupt when the enabled event occurs. To service the High-Priority
Interrupt, the user reads Register 8 to determine the cause of the interrupt, then writes to Register 8 to clear the appropriate
bits. The BCRTM also provides a Standard Priority Interrupt Scheme that does not require host intervention. If High-Priority
Interrupt service is not possible in a given application, it is advisable to use the Standard Priority features.
Bit
Number
Description
BITs 15-9
Reserved.
BIT 8
Data Overrun Enable. When set, this bit enables an interrupt when DMAG was not received by the BCRTM
within the allotted time needed for a successful data transfer to memory.
BIT 7
(BC) Illogical Command Error Enable. This bit enables a High-Priority Interrupt to be asserted upon the
occurrence of an Illogical Command. Illogical commands include incorrectly formatted RT-RT Command
Blocks.
BIT 6
(RT) Dynamic Bus Control Mode Code Interrupt Enable. When set, an interrupt is asserted when the
Dynamic Bus Control Mode Code is received.
BIT 5
Subsystem Fail Enable. When set, a High-Priority Interrupt is asserted after receiving a Subsystem Fail
(SSYSF) input pin.
BIT 4
End of BIT Enable. This bit indicates the end of the internal BIT routine.
BIT 3
BIT Word Fail Enable. This bit enables an interrupt indicating that the BCRTM detected a BIT failure.
BIT 2
(BC) End of Command Block List Enable (see Command Block Control Word, page 38.) This interrupt can be
superseded by other high-priority interrupts.
BIT 1
Message Error Enable. If enabled, a High-Priority Interrupt is asserted at the occurrence of a message error. If
a High-Priority Interrupt condition occurs, as the result of an enabled message error, the device will halt
operation until the user clears the interrupt by writing a “1” to Bit 1 of the High-Priority Interrupt Status/Reset
Register (Reg. #8). If this interrupt is not cleared, the BCRTM remains in the HALTED state (appearing to be
“locked up”), even if it receives a valid message. This High-Priority Interrupt scheme is necessary in order to
maintain the BCRTM’s state of operation so that the host CPU has this information available at the time of
interrupt service.
BIT 0
Standard Interrupt Enable. Setting this bit enables the STDINTL pin, but does not cause a high-priority
interrupt. If low, only the STDINTL pin is asserted when a Standard Interrupt occurs.
BCRTM-14
#8 High-Priority Interrupt Status/Reset Register
When a High-Priority Interrupt is asserted, this register indicates the event that caused it. To clear the interrupt signal and reset
the bit, write a “1” to the appropriate bit. See the corresponding bit definitions of Register 7, High-Priority Interrupt Enable
Register.
Bit
Number
Description
BITs 15-9
Reserved.
BIT 8
Data Overrun.
BIT 7
Illogical Command.
BIT 6
Dynamic Bus Control Mode Received
BIT 5
Subsystem Fail.
BIT 4
End of BIT.
BIT 3
BIT Word Fail.
BIT 2
End of Command Block.
BIT 1
Message Error.
BIT 0
Standard Interrupt. The BCRTM sets this bit when any Standard Interrupt occurs, providing bit 0 of Register 7
is enabled.(Reset STDINTL output.)
#9 Standard Interrupt Enable Register
This register enables Standard Interrupt logging for any of the following enabled events (Standard Interrupt logging can also
occur for events enabled in the BC Command Block or RT Subaddress/Mode Code Descriptor):
Bit
Number
Description
BITs 15-6
Reserved.
BIT 5
(RT) Illegal Broadcast Command. When set, this bit enables an interrupt indicating that an Illegal Broadcast
Command has been received.
BIT 4
(RT) Illegal Command. When set, this bit enables an interrupt indicating that an illegal command has been
received.
BIT 3
(BC) Polling Comparison Match. This enables an interrupt indicating that a polling event has occurred. The user
must also set bit 12 in the BC Command Block Control Word for this interrupt to occur.
BIT 2
(BC) Retry Fail. This bit enables an interrupt indicating that all the programmed number of retries have failed.
BIT 1
(BC, RT,M) Message Error Event. This bit enables a standard interrupt for message errors.
BIT 0
(BC,M) Command Block Interrupt and Continue. This bit enables an interrupt indicating that a Command
Block, with the Interrupt and Continue Function enabled, has been executed.
BCRTM-15
#10 Remote Terminal Address Register
This register sets the Remote Terminal Address via software. The Change Lock-Out Enable feature, when set, prevents the
Remote Terminal Address or the BCRTM Mode Selection from changing.
Bit
Number
Description
BIT 15
(RT) Instrumentation. Setting this bit sets the RT status word Instrumentation bit.
BIT 14
(RT) Busy. Setting this bit sets the RT status word Busy bit. It does not inhibit data transfers to the subsystem.
BIT 13
(RT) Subsystem Fail. Setting this bit sets the RT status word Subsystem Flag bit. In the RT mode, the Subsystem
Fail is also logged into the Message Status Word.
BIT 12
(RT) Dynamic Bus Control Acceptance. Setting this bit sets the RT status word Dynamic Bus Control
Acceptance bit when the BCRTM receives the Dynamic Bus Control Mode Code from the currently active Bus
Controller. Host intervention is required for the BCRTM to take over as the active Bus Controller.
BIT 11
(RT) Terminal Flag. Setting this bit sets the RT status word Terminal Flag bit; the Terminal Flag bit in the RT
status word is also internally set if the BIT fails.
BIT 10
(RT) Service Request. Setting this bit sets the RT status word Service Request bit.
BIT 9
(RT) Busy Mode Enable. Setting this bit sets the RT status word Busy bit and inhibits all data transfers to the
subsystem.
BIT 8
BC/RT Mode Select. This bit’s state reflects the external pin BCRTSEL. It does not necessarily reflect the state
of the chip, since the BC/RT Mode Select is software-programmable via bit 10 of Register 0. This bit is
read-only.
BIT 7
Change Lock-Out. This bit’s state reflects the external pin LOCK. When set, this bit indicates that changes to the
RT address or the BC/RT Mode Select are not allowed using internal registers. This bit is read-only.
BIT 6
Remote Terminal Address Parity Error. This bit indicates a Remote Terminal Address Parity Error. It appears
after the Remote Terminal Address is latched if a parity error exists.
BIT 5
Remote Terminal Address Parity. This is an odd parity input bit used with the Remote Terminal Address. It
ensures accurate recognition of the Remote Terminal Address.
BITs 4-0
Remote Terminal Address (Bit 0 is the LSB). This reflects the RTA4-0 inputs at Master Reset. Modify the
Remote Terminal Address by writing to these bits.
#11 BIT Start Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates the internal BIT routine, which lasts 100µs. Verify
using the BIT-in-Progress bit in the Status Register. A programmed reset (write to Register 12) must precede a write to this
register to initiate the internal BIT.A failure of the BIT will be indicated in Register 4 and the BCRTF pin.
The BCRTM’s self-test performs an internal wrap-around test between its Manchester encoder and its two Manchester decoders.
If the BCRTM detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of Register
4 (BIT Word Register) for Channel A and/or bit 15 for Channel B. When in the Remote Terminal mode, while the BCRTM is
performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test.
#12 Programmed Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates a reset sequence of the encoder/decoder and
protocol sections of the BCRTM which lasts less than 1 microsecond. This is identical to the reset used for the Reset Remote
Terminal Mode Code except that command processing halts. For a total reset (i.e., including registers), see the MRST signal
description.
BCRTM-16
#13 RT Timer Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location resets the RT Time Tag timer to zero.
The BCRTM’s Remote Terminal Timer time-tags message transactions. The time tag is generated from a free-running eightbit timer of 64µs resolution. This timer can be reset to zero simply by writing to Register 13. When the timer is reset, it
immediately starts running.
#14 Activity Status/Operational Mode Register
BIT 15
Bus Monitor Select. This bit should be cleared for RT mode operation. The host sets this bit to enable the
BCRTM’s Monitor mode of operation. Bit 10 of Register 0 must also be "0" to enable the Monitor mode.
BIT 14
Monitor All Terminals. When this bit is set, the BCRTM monitors all remote terminal activity.If this bit is not set,
then bit 13 must be set. This bit should be cleared for RT Mode operation.
BIT 13
Monitor Declared Terminals. When this bit is set, the BCRTM monitors all remote terminal bus activity. If this
bit is not set, then bit 13 must be set.This bit should be cleared for RT mode operation.
BITs 12-0
Reserved
#15 Reserved Register
This register is reserved for BCRTM use only and the host should not access it.
#16 Monitor Selected Remote Terminal Address 15-0
BITs 15-0
Monitor Selected Remote Terminal Addresses 15-0. By setting the appropriate bit in this register, the host can
determine which or the Remote terminals, from RT 0 through RT 15, the BCRTM will monitor. For example,
by setting bit 5 in this register, the host instructs the BCRTM to only monitor the bus activity for remote terminal
5. These bits are not mutually exclusive, therefore, the host can monitor any number of different remote terminals
by selecting the proper combination of bits.
#17 Monitor Selected Remote Terminal Address 31-16
BITs 15-0
Monitor Selected Remote Terminal Addresses 31-16. By setting the appropriate bit in this register, the host can
determine which or the Remote terminals, from RT 16 through RT 31, the BCRTM will monitor. For example,
by setting bit 21 in this register, the host instructs the BCRTM to only monitor the bus activity for remote terminal
21. These bits are not mutually exclusive, therefore, the host can monitor any number of different remote
terminals by selecting the proper combination of bits on this register and Register 16.
BCRTM-17
#0
BC/RT CONTROL REGISTER
15
14
UNUSED
7
CHNSEL
BUSAEN
#1
4
3
2
1
0
RTYBCME
RTYTO
RTYME
RTYBSY
STEN
12
DYNBUS
RT FLAG
11
BUSY
9
8
BIT
RESET
4
3
2
1
0
UNUSED
UNUSED
UNUSED
UNUSED
CMBKPG
(BC) CURRENT COMMAND BLOCK REGISTER
(RT) REMOTE TERMINAL DESCRIPTOR SPACE ADDRESS REGISTER
15
14
13
12
11
A14
A13
A12
A11
10
A10
9
8
A9
A8
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
POLLING COMPARE REGISTER
15
14
13
12
11
X
X
X
X
7
6
5
4
3
SWBT12
SWBT13
SWBT14
BRDCST
BUSY
BIT WORD REGISTER
15
14
CHAFAIL
13
12
D13
D12
11
D11
10
MSGERR
2
SS FLAG
10
D10
9
8
INSTR
SRQ
1
0
DBC
TF
9
8
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
CURRENT COMMAND REGISTER
15
14
13
D14
D13
12
11
10
D12
D11
D10
9
8
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
INTERRUPT LOG LIST POINTER REGISTER
15
14
13
12
11
10
A11
A10
A14
A13
A12
9
8
A9
A8
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
BCRTM HIGH-PRIORITYINTERRUPT ENABLE REGISTER
15
14
13
12
11
UNUSED
7
6
ILLCMD
DYNBUS
UNUSED
5
SSFAIL
UNUSED
UNUSED
UNUSED
7
6
ILLCMD
DYNBUS
UNUSED
5
SSFAIL
10
9
8
UNUSED
UNUSED
DATOVR
4
3
2
1
0
ENDBIT
BITFAIL
EOL
MSGERR
STDINT
BCRTM HIGH-PRIORITYINTERRUPT STATUS/RESET REGISTER
15
14
13
12
11
UNUSED
UNUSED
4
ENDBIT
UNUSED
3
BITFAIL
Table 1. BCRTM Registers
BCRTM-18
10
SRQ
5
UNUSED
#8
8
BUSBEN
SSFAIL
A15
#7
9
RTYALTB
6
D15
#6
13
10
BC/RT
BUSA/B
CHBFAIL
#5
RTACT
11
EXTOVR
7
X
#4
5
RTYCNT
12
BCTO
BC/RT
A15
#3
13
UNUSED
6
BC/RT STATUS REGISTER
15
14
TEST
#2
UNUSED
10
9
8
UNUSED
UNUSED
DATOVR
2
1
0
EOL
MSGERR
STDINT
#9
STANDARD INTERRUPT ENABLE REGISTER
15
14
13
12
UNUSED
#10
#12
#13
#14
11
10
9
8
UNUSED
UNUSED
UNUSED
UNUSED
6
5
4
3
UNUSED
ILLBCMD
ILLCMD
POLMTCH
REMOTE TERMINAL ADDRESS REGISTER
15
14
13
BUSY2
SS FLAG
12
DBC
2
RTYFAIL
1
0
MSGERR
CMDBLK
11
10
9
8
RT FLAG
SRQ
BUSY1
BC/RT
7
6
5
4
3
2
1
0
LOCK
PARERR
RTAPAR
RTA4
RTA3
RTA2
RTA1
RTA0
BUILT-IN-TEST START REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PROGRAMMED RESET REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
REMOTE TERMINAL TIMER RESET REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
12
11
10
9
8
X
X
X
X
X
BUS MONITOR CONTROL REGISTER
15
14
13
MAT
MDT
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
MONITOR SELECTED REMOTE TERMINAL ADDRESES 0-15
15
14
13
12
11
TA15
#17
UNUSED
7
BMS
#16
UNUSED
UNUSED
INSTR
#11
UNUSED
TA14
TA13
TA12
TA11
10
9
8
TA10
TA9
TA8
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
MONITOR SELECTED REMOTE TERMINAL ADDRESES 16-31
15
14
13
12
11
10
9
8
TA31
TA30
TA29
TA28
TA27
TA26
TA25
TA24
7
6
5
4
3
2
1
0
T23
T22
T21
T20
T19
TA18
TA17
TA16
X = DON’T CARE
Table 1. BCRTM Registers (continued from page 18)
BCRTM-19
4.0 SYSTEM OVERVIEW
The BCRTM can be configured for a variety of processor
and memory environments. The host processor and the
BCRTM communicate via a flexible, programmable
interrupt structure, internal registers, and a user-definable
shared memory area. The shared memory area (up to 64K)
is completely user-programmable and communicates
BCRTM control information -- message data, and status/
error information.
Built-in memory management functions designed
specifically for MIL-STD-1553 applications aid processor
off-loading. The host needs only to establish the parameters
within memory so the BCRTM can access this information
as required. For example, in the RT mode, the BCRTM can
store data associated with individual subaddresses
anywhere within its 64K address space. The BCRTM then
can automatically buffer up to 128 incoming messages of
the same subaddress, thus preventing the previous messages
from being overwritten by subsequent messages. This
buffering also extends the intervals required by the host
processor to service the data. Selecting an appropriate
MCLK frequency to meet system memory access time
requirements controls the memory access rate. The
completion of a user-defined task or the occurrence of a
user-selected event is indicated by using the extensive set
of interrupts provided.
In the Monitor (M) mode, the BCRTM’s powerful linked
list command block structure allows it to process a series of
monitored 1553 messages without the intervention of the
host. The BCRTM can store as much bus traffic as can be
contained in its 64K memory space. In addition, the host has
the capability of instructing the BCRTM to monitor and
store data for only selected remote terminals. The host
system is responsible for initializing an area in memory that
tells the BCRTM where to store command word information
and data for each command that the BCRTM receives on
the 1553 bus. This area of memory consists of "Bus Monitor
Command Blocks." An M Command Block is very similar
to the BC Command Block in the BCRTM. The only real
differences are the direction of information flow, and that
there is no Head Pointer in the M Command Block.
5.0 SYSTEM INTERFACE
5.1 DMA Transfers
The BCRTM initiates DMA transfers whenever it executes
command blocks (BC mode) or services commands (RT
mode). DMAR initiates the transfer and is terminated by the
inactive edge of DMACK. The Address Enable (AEN)
input enables the BCRTM to output an address onto the
Address bus.
RAM
CPU MEMORY
CONTROL SIGNALS
RRD
RWR
MEMCSO
BCRTM
RD
WR
MEMCSI
Figure 3a. Pseudo-Dual-Port RAM
Control Signals
BCRTM-20
In the BC mode, the BCRTM can process multiple
messages, assist in scheduling message lists, and provide
host-programmable functions such as auto retry. The
BCRTM is incorporated in systems with a variety of
interrupt latencies by using the Interrupt History List feature
(see Exception Handling and Interrupt Logging, page 37).
The Interrupt History List sequentially stores the events that
caused the interrupt in memory without losing information
if a host processor does not respond immediately to
an interrupt.
The BCRTM requests transfer cycles by asserting the
DMAR output, and initiates them when a DMAG input is
received. A DMACK output indicates that the BCRTM has
control of the Data and Address buses. The TSCTL output
is asserted when the BCRTM is actually asserting the
Address and Data buses.
To support using multiple bus masters in a system, the
BCRTM outputs the DMAGO signal that results from the
DMAG signal passing through the chip when a BCRTM bus
request was not generated (DMAR inactive). You can use
DMAGO in daisy-chained multimaster systems.
5.2 Hardware Interface
The BCRTM provides a simple subsystem interface and
facilitates DMA arbitration. The user can configure the
BCRTM to operate in a variety of memory-processor
environments including pseudo-dual-port RAM and
standard DMA configurations.
For complete circuit description, such as arbitration logic
and I/O, please refer to the appropriate application note.
5.3 CPU Interconnection
Pseudo-Dual-Port RAM Configuration
The BCRTM’s Address and Data buses connect directly to
RAM, with buffers isolating the BCRTM’s buses from those
of the host CPU (figures 3a and 3b). The CPU’s memory
control signals (RD, WR, and MEMCSI) pass through the
BCRTM and connect to memory as RRD, RWR, and
MEMCSO.
Standard DMA Configuration
The BCRTM’s and CPU’s data, address, and control signals
are connected to each other as shown in figures 3c and 3d.
The RWR, RRD, and MEMCSO are activated after DMAG
is asserted.
In either case, the BCRTM’s Address and Data buses remain
in a high-impedance state unless the CS and RD
signals are active, indicating a host register access; or
TSCTL is asserted, indicating a memory access by the
BCRTM. CPU attempts to access BCRTM registers are
ignored during BCRTM memory access. Inhibit DMA
transfers by using the Busy function in the Remote Terminal
Address Register while operating in the Remote
Terminal mode.
The designer can use TSCTL to indicate when the BCRTM
is accessing memory or when the CPU can access memory.
AEN is also available (use is optional), giving the CPU
control over the BCRTM’s Address bus. A DMA Burst
(BURST) signal indicates multiple DMA accesses.
Register Access
Registers 0 through 13 are accessed with the decode of the
four LSBs of the Address bus (A0-A3) and asserting CS.
BUFFERS
16 DATA
RAM
HOST
CPU
16 ADDRESS
CONTROL
BCRTM
(DUAL REDUNDANT)
DUAL
TRANSCEIVER
XFMR
CONTROL/ARBITRATION
TRANSMITTER
TIMEOUT
XFMR
BUS A
1553 BUS
BUS B
Figure 3b. CPU/BCRTM Interface -- Pseudo-Dual-Port RAM Configuration
BCRTM-21
ADDRESS BUS
DMAR DMAG
DMACK
BCRTM
CPU
DATA BUS
RRD RWR
SHARED
MEMORY
AREA
OE
•
WE
•
CS
•
MEMCSO
Figure 3c. DMA Signals
RAM
DATA
ADDRESS
BCRTM
MEMORY
BUFFER
CONTROL
CPU
ARBITRATION
DUAL
TRANSCEIVER
XFMR
XFMR
BUS A
1553 BUS
BUS B
Figure 3d. CPU/BCRTM Interface -- DMA Configuration
BCRTM-22
5.4 RAM Interface
The BCRTM’s RRD, RWR, and MEMCSO signals serve as
read and write controls during BCRTM memory accesses.
The host subsystem signals RD, WR, and MEMCSI
propagate through the BCRTM to become RRD, RWR, and
MEMCSO outputs to support a pseudo-dual-port. During
BCRTM-RAM data transfers, the host subsystem’s memory
signals are ignored until the BCRTM access is complete.
- STARTING ADDRESS
INITIALIZED BY CPU
IN THE RT DESCRIPTOR
SPACE REGISTER
RECEIVE
SUBADDRESS
#1
RECEIVE
SUBADDRESS
#2
RECEIVE
SUBADDRESS
#31
TRANSMIT
SUBADDRESS
#1
TRANSMIT
SUBADDRESS
#2
UNUSED
5.5 Legalization Bus
The BCRTM’s Manchester II encoder/decoder interfaces
directly with the1553 bus transceiver, using the TAO-TAZ
and RAZ-RAO signals for Channel A, and TBO-TBZ and
RBZ-RBO signals for Channel B.
The BCRTM also provides a TIMERON signal output and
an active channel output indicator (CHA/B) to assist in
meeting the MIL-STD-1553B fail-safe timer requirements..
TRANSMIT
UNUSED
MODE CODE
#’S 0 & 16
MODE CODE
#’S 1 & 17
BCRTM
TIMRONB
CHANNEL A
SUBADDRESS #31
CHANNEL B CHA/B
MODE CODE
#’S 15 & 31
Figure 5. Descriptor Space
CHANNEL A
TXINHA
CHANNEL B
DUAL
TRANSCEIVER
TXINHB
ILLEGAL BROADCAST
SUBADDRESS
Figure 4. Dual-Channel Transceiver
ILLEGAL
SUBADDRESS
INTERRUPT WHEN
ADDRESSED
6.0 REMOTE TERMINAL ARCHITECTURE
The Remote Terminal architecture is a descriptorbased configuration of relevant parameters. It is composed
of an RT Descriptor Space (see figure 5) and internal, hostprogrammable registers. The Descriptor Space contains
only descriptors. Descriptors contain programmable
subaddress parameters relating to handling message
transfers. Each descriptor consists of four words: (1) a
Control Word, (2) a Message Status List Pointer, (3) a Data
List Pointer, and (4) an unused fourth word (see figure 6.)
These words indicate how to perform the data transfers
associated with the designated subaddress.
INTERRUPT WHEN
INDEX = 0
15
UNUSED
10
9
8
7
I
I
I
I
6
0
INDEX
MESSAGE STATUS LIST POINTER
DATA LIST POINTER
FOR FUTURE EXPANSION
Figure 6. Remote Terminal Subaddress Descriptor
BCRTM-23
A receive descriptor and a transmit descriptor are associated
with each subaddress. The descriptors reside in memory and
are listed sequentially by subaddress. By using the index
within the descriptor, the BCRTM can buffer incoming and
outgoing messages, which reduces host CPU overhead.
This message buffering also reduces the risk of incoming
messages being overwritten by subsequent incoming
messages.
Each descriptor contains a programmable interrupt structure
for subsystem notification of user-selected message
transfers and indicates when the message buffers are full.
Illegalizing subaddresses, in normal and broadcast modes,
is accomplished by using programmable bits within the
descriptor (see the RT Functional Operation section on
this page).
Message Status information -- including word count, an
internally generated time tag, and broadcast and message
validity information -- is provided for each message. The
Message Status Words are stored in a separate Message
Status Word list according to subaddress. The list’s starting
locations are programmable within the descriptor.
Message data, received or transmitted, is also stored in lists.
The message capacity of the lists and the lists’ locations are
user selectable within the descriptor.
6.1 RT Functional Operation
The RT off-loads the host computer of all routine data
transfers involved with message transfers over the 1553B
bus by providing a wide range of user-programmable
functions. These functions make the BCRTM’s operation
flexible for a variety of applications. The following
paragraphs give each function’s operational descriptions.
6.1.1 RT Subaddress Descriptor Definition
The host sets words within the descriptor (see figure 6). The
BCRTM then reads the descriptor words when servicing a
command corresponding to the specified descriptor. All bitselectable functions are active high and inhibited when low.
A. Control Word. The first word in the descriptor, the Control Word, selects or disables message transfers and selects an index.
Bit
Number
Description
BITs
15-11
Reserved.
BIT 10
Illegal Broadcast Subaddress. Indicates to the BCRTM not to access this subaddress using broadcast
commands. The Message Error bit in the status word is set if the illegal broadcast subaddress is addressed.
Since transmit commands do not apply to broadcast, this bit applies only to receive commands.
BIT 9
Illegal Subaddress. Set by the host CPU, it indicates to the BCRTM that a command with this subaddress is
illegal. If a command uses an illegal subaddress the Message Error bit in the 1553 status word is set. The Illegal
Command Interrupt is also asserted if enabled.
BIT 8
Interrupt Upon Valid Command Received. Indicates that the BCRTM is to assert an interrupt every time a
command addresses this descriptor. The interrupt occurs just prior to post-command descriptor updating.
BIT 7
Interrupt When Index = 0. Indicates that the BCRTM initiates an interrupt when the index is decremented
to zero.
BITs 6-0
Index. These bits are for indexed message buffering. Indexing means transacting a pre-specified number of
messages before notifying the host CPU. After each message transaction, the BCRTM decrements the index by
one until index = 0. Note that the index is decremented for messages that contain message errors.
B. Message Status List Pointer. The host sets the Message Status List Pointer, the second word within the descriptor, and the
BCRTM uses it as a starting address for the Message Status List. It is incremented by one with each Message Status Word
write. If the Control Word Index is already equal to zero, the Message Status List Pointer is not incremented and the previous
Message Status Word is overwritten.
Note: A Message Status Word is written and the pointer is incremented when the BCRTM detects a message error.
C. Data List Pointer. The Data List Pointer is the third word within the descriptor. The BCRTM stores data in RAM beginning
at the address indicated by the Data List Pointer. The Data List Pointer is updated at the end of each successful message with
the next message’s starting address with the following exceptions:
• If the message is erroneous, the Data List Pointer is not updated. The next message overwrites any data
corresponding to the erroneous message.
• Upon receiving a message, if the index is already equal to zero, the Data List Pointer is not incremented and
data from the previous message is overwritten.
D. Reserved. The fourth descriptor word is reserved for future use.
BCRTM-24
6.1.2 Message Status Word
Each message the BCRTM transacts has a corresponding
Message Status Word, which is pointed to by the Message
Status List Pointer of the Descriptor. This word allows the
host CPU to evaluate the message’s validity, determine the
word count, and calculate the approximate time frame in
which the message was transacted (figures 7 and 8).
15
14
13
12
8
7
WORD COUNT
0
TIME TAG
MESSAGE ERROR
MESSAGE WAS BROADCASTED
SUBSYSTEM FAIL INPUT WAS
ASSERTED DURING THIS MESSAGE
Figure 7. Message Status Word
MESSAGE STATUS WORD
LIST
DATA LIST
#1
MESSAGE
#1
#2
#3
MESSAGE
#2
#4
MESSAGE STATUS
LIST POINTER
MESSAGE
#5
#3
DATA LIST
POINTER
MESSAGE
#4
(FROM RT DESCRIPTOR)
MESSAGE
#5
Figure 8. Remote Terminal Data and Message Status List
Message Status Word Definition
Bit
Number
Description
BIT 15
BIT 14
BIT 13
BITs 12-8
BITs 7-0
Subsystem Failed. Indicates SSYSF was asserted before the Message Status Word transfer to memory. This
bit is also set when the user sets bit 13 of Register 10.
Broadcast Message. Indicates that the corresponding message was received in the broadcast mode.
Message Error. Indicates a message is invalid due to improper synchronization, bit count, word count, or
Manchester error.
Word Count. Indicates the number of words in the message and reflects the Word Count field in the command
word. Should the message contain a different number of words than the Word Count field, the Message Error
flag is triggered. If there are too many words, they are withheld from RAM. If the actual word count is less than
it should be, the Message Error bit in the 1553 status word is set.
Time Tag. The BCRTM writes the internally generated Time Tag to this location after message completion.
The resolution is 64µs. (See Register 13). If the timer reads 2, it indicates the message was completed 128 to
191µs after the timer started.
BCRTM-25
6.1.3 Mode Code Descriptor Definition
Mode codes are handled similarly to subaddress
transactions. Both use the four-word descriptors residing in
the RT descriptor space to allow the host to program their
operational mode. Corresponding to each mode code is a
descriptor (see figure 9a). Of the 32 address combinations
for mode codes in MIL-STD-1553B, some are clearly
defined functions while others are reserved for future use.
Sixteen descriptors are used for mode code operations with
each descriptor handling two mode codes: one mode code
with an associated data word and one mode code without
an associated data word. All mode codes can be handled in
accordance with MIL-STD-1553B. The function of the first
word of the Mode Code Descriptor is similar to that of the
Subaddress Descriptor and is defined below. The remaining
three words serve the same purpose as in the
Subaddress Descriptor.
REMOTE TERMINAL
DESCRIPTOR SPACE
STARTING ADDRESS
(RTDSSA) + 256
MODE CODE
#’S 0 & 16
MODE CODE
#’S 1 & 17
MODE CODE
#’S 2 & 18
MODE CODE
#’S 15 & 31
RTDSSA + 320
Note:
Mode code descriptor blocks are also provided for reserved mode
codes but have no associated predefined BCRTM operation.
Figure 9a. (RT) Mode Code Descriptor Space
Control Word
Bit
Number Description
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BITs 6-0
Interrupt on Reception of Mode Code (without Data Word).
Illegalize Broadcast Mode Code (without Data Word).
Illegalize Mode Code (without Data Word).
Reserved.
Illegalize Broadcast Mode Code (with Data Word).
Illegalize Transmit Mode Code (with Data Word).
Illegalize Receive Mode Code (with Data Word).
Interrupt on Reception of Mode Code (with Data Word).
Interrupt if Index = 0.
Index. Functionally equivalent to the index described in the Subaddress Descriptor. It applies to mode codes with
data words only.
INTERRUPT ON RECEPTION OF MODE CODE
(WITHOUT DATA WORD)
ILLEGALIZE BROADCAST MODECODE
(WITHOUT DATA WORD)
ILLEGALIZE MODE CODE
(WITHOUT DATA WORD)
RESERVED
ILLEGALIZE BROADCAST MODECODE
(WITH DATA WORD)
ILLEGALIZE TRANSMIT MODE CODE
(WITH DATA WORD)
ILLEGALIZE RECEIVE MODE CODE
(WITH DATA WORD)
INTERRUPT ON RECEPTION OF MODE CODE
(WITH DATA WORD)
INTERRUPT IF INDEX = 0
15
14
13
12
11
10
9
8
7
6
0
INDEX
MESSAGE STATUS LIST POINTER
DATA LIST POINTER
RESERVED
Figure 9b. (RT) Mode Code Descriptor
BCRTM-26
The descriptors, numbered sequentially from 0 to 15,
correspond to mode codes 0 to 15 without data words and
mode codes 16 to 31 with data words. For example, mode
codes 0 and 16 correspond to descriptor 0 and mode codes
1 and 17 correspond to descriptor 1. The Mode Code
Descriptor Space is appended to the Subaddress Descriptor
Space starting at 0100H (256D) of the 320-word RT
Descriptor Space (see figure 5).
when the test is completed. A failure in BIT will also set the
TF status word bit.
The BCRTM can autonomously support all mode codes
without data words by executing the specific function and
transmitting the 1553 status word. The subsystem provides
the data word for mode codes with data words (see the Data
List Pointer section). For all mode codes, an interrupt can
be asserted by setting the appropriate bit in the control word
upon successful completion of the mode command by
setting the appropriate bit in the control word (see figure 9b).
Inhibit Terminal Flag Bit #00110
The BCRTM inhibits the Terminal Flag from being set in
the status word.
Dynamic Bus Control #00000
This mode code is accepted automatically if the Dynamic
Bus Control Enable bit in the Remote Terminal Address
Register is set. Setting the Dynamic Bus Control
Acceptance bit in the 1553 status word and BCRTM Status
Register confirms the mode code acceptance. A HighPriority Interrupt is also asserted if enabled. If the Dynamic
Bus Control Enable bit is not set, the BCRTM does not
accept Dynamic Bus Control.
Synchronize (Without Data Word) #00001
If enabled in the Mode Code #00001 Descriptor Control
Word, the BCRTM asserts an interrupt when this mode code
is received.
Transmit Status Word #00010
The BCRTM automatically transmits the 1553 status word
corresponding to the last message transacted.
Initiate Self-Test #00011
The BCRTM automatically starts its BIT routine. An
interrupt, if enabled, is asserted when the test is completed.
The BIT Word Register and external pin BCRTF are updated
Transmitter Shutdown #00100
The BCRTM disables the channel opposite the channel on
which the command was received.
Override Transmitter Shutdown #00101
The BCRTM enables the channel previously disabled.
Override Inhibit Terminal Flag Bit #00111
The BCRTM disables the Terminal Flag inhibit.
Reset Remote Terminal #01000
The BCRTM automatically resets the encoder, decoders,
and protocol logic.
Transmit Vector Word #10000
The BCRTM transmits the vector word from the location
addressed by the Data List Pointer in the Mode Code
Descriptor Block.
Synchronize (with Data Word) #10001
On receiving this mode code, the BCRTM simply stores the
associated data word.
Transmit Last Command #10010
The BCRTM transmits the last command executed and the
corresponding 1553 status word.
Transmit BIT Word #10011
The BCRTM transmits BIT information from the BIT
Register.
Selected Transmitter Shutdown #10100
On receiving this mode code, the BCRTM simply stores the
associated data word.
Override Selected Transmitter Shutdown #10101
On receiving this mode code, the BCRTM simply stores the
associated data word.
BCRTM-27
6.2 RT Error Detection
In accordance with MIL-STD-1553B, the remote terminal
handles superseding commands on the same or opposite bus.
When receiving, the Remote Terminal performs a response
time-out function of 56 µs for RT-RT transfers. If the
response time-out condition occurs, a Message Error bit can
be set in the 1553 status word and in the Message Status
Word. Error checking occurs on both of the Manchester
logic and the word formats. Detectable errors include word
count errors, long words, short words, Manchester errors
(including zero crossing deviation), parity errors, and data
discontiguity.
generated internally.Writing to Register 10 enables
the other predefined bits. For illegalized commands,
the BCRTM also sets the Message Error Bit in the
1553 Status Word.
Exception Handling.
If an interrupting condition occurs during the
message, the following occurs:
For High-Priority Interrupts:
HPINT is asserted (if enabled in Register 7).
For message errors, the BCRTM is put in a
hold state until the interrupt is acknowledged
(by writing a “1” to the appropriate bit in
Register 8).
6.3 RT Operational Sequence
The following is a general description of the typical
behavior of the BCRTM as it processes a message in the RT
mode. It is assumed that the user has already written a “1”
to Register 0, bit 0, enabling RT operation.
For Standard Interrupts:
DMA arbitration (BURST)
Interrupt Status Word write
RT Descriptor Block Pointer write
Tail Pointer read (into Register 6)
STDINTP pulses low
STDINTL asserted (if enabled)
Processing continues
Valid Command Received.
COMSTR goes active
•
DMA Descriptor Read. After receiving a valid
command, the BCRTM initiates a burst DMA:
DMA arbitration (BURST)
Control Word read
Message Status List Pointer read
Data List Pointer read
Data Transmitted/Received.
•
Data Word DMA.
If the BCRTM needs to transmit data from memory,
it initiates a DMA cycle for each Data Word shortly
before the Data Word is needed on the 1553B bus:
DMA arbitration
Data Word read (starting at Data List Pointer
address, incremented for each successive
word)
If the BCRTM receives data, it writes each Data
Word to memory after the Data Word is received:
DMA arbitration
Data Word write (starting at Data List Pointer
address, incremented for each successive
word)
Status Word Transmission.
The BCRTM automatically transmits the Status
Word as defined in MIL-STD-1553B.The Message
Error and Broadcast Command Received bits are
BCRTM-28
•
Descriptor Write.
After the BCRTM processes the message, a final
DMA burst occurs to update the descriptor block, if
necessary:
DMA arbitration (BURST)
Message Status Word write
Data List Pointer write
(incremented by word count)
Message Status List Pointer write
(incremented by 1)
Control Word write (index decremented)
Note the following exceptions:
Mode codes without data require no
descriptor update.
Predefined mode codes (18 and 19) which do
not require access to memory for the data
word, do not involve updating the Data List
Pointer.
Messages with errors prevent updates to the
Data List Pointer.
If the message index was zero, neither the
Message Status List Pointer nor the Data List
Pointer is updated.
7.0 BUS CONTROLLER ARCHITECTURE
The BCRTM’s bus controller architecture is based on a
Command Block structure and internal, hostprogrammable registers. Each message transacted over the
MIL-STD-1553B bus has an associated Command Block,
which the CPU sets up (see figures 11 and 12). The
Command Block contains all the relevant message and RT
status information as well as programmable function bits
that allow the user to select functions and interrupts. This
memory interface system is flexible due to a doubly-linked
list data structure
HEAD POINTER
A programmable auto retry function is selectable from the
control word and Control Register.
The auto retry can be activated when any of the following
occurs:
•
Busy Bit set in the status word
•
Message Error (indicated by the RT status response)
•
Response Time-Out
•
Message Error detected by the Bus Controller
One to four retries are programmable on the same or
opposite bus.
CONTROL WORD
COMMAND WORD 1
The Bus Controller also has a programmable intermessage
delay timer that facilitates message transfer scheduling (see
figures 13 and 14). This timer, programmed in the control
word, automatically delays between the start of two
successive commands.
COMMAND WORD 2 (RT-RT ONLY)
DATA LIST POINTER
STATUS WORD 1
STATUS WORD 2 (RT-RT ONLY)
TAIL POINTER
Figure 10. Command Block
In a doubly-linked Command Block structure, pointers
delimit each Command Block to the previous and
successive blocks (see figure 12). The linking feature eases
multiple message processing tasks and supports message
scheduling because of its ability to loop through a series of
transfers at a predetermined cycle time. A data pointer in
the command allows efficient space allocation because data
blocks only have to be configured to the exact word count
used in the message. Data pointers also provide flexibility
in data-bank switching.
A polling function is also provided. The Bus Controller,
when programmed, compares incoming status words to a
host-specified status word and generates an interrupt if the
comparison indicates any matching bits. An Interrupt and
Continue function facilitates the host subsystem’s
synchronization by generating an interrupt when the
specified Command Block’s message is executed.
COMMAND BLOCK #1
HP
TP
#2
COMMAND BLOCK
HP
DATA WORD #1
DATA LIST POINTER
DATA WORD #2
X
TP
#3
LAST DATA WORD
HP
X IS BETWEEN 1 & 32
Figure 11. Data Placement
TP
A control word with bit-programmable functions and a
Message Error bit are in each Command Block. This allows
selecting individual functions for each message and
provides message validity information. The BCRTM’s
register set provides additional global parameters and
address pointers.
HP
#4
TP
Figure 12. Command Block Chaining
BCRTM-29
7.1 BC Functional Operation
The Bus Controller off-loads the host computer of many
functions needed to coordinate 1553B bus data transfers.
Special architectural features provide message- by-message
flexibility. In addition, a programmable interrupt scheme,
programmable intermessage timing delays, and internal
registers enhance the BCRTM’s operation.
The host determines the first Command Block by setting the
initial starting address in the current Command Block
Register. Once set, the BCRTM updates the current
Command Block Register with the next Command Block
15
MESSAGE
ERROR
14
SKIP
13
12
11
INTERRUPT
AND
CONTINUE
POLLING
ENABLE
AUTO
RETRY
ENABLE
Address. The BCRTM then executes the sequential
Command Blocks and counts out message delays (where
programmed) until it encounters the last Command Block
listed (indicated by the End of List bit in the control word).
Interrupts are asserted when enabled events occur (see
section 9.0, Exception Handling and Interrupt Logging).
The functions and their programming instructions are
described below. The registers also contain many
programmable functions and function parameters.
10
9
END
OF
LIST
8
RT-RT
TRANSFER
MONITOR
RT-RT
TRANSFER
7
0
‘TIME DELAY’
Figure 13. Command Word
MESSAGE #1
MESSAGE #2
TDELAY1
MESSAGE #3
TDELAY2
Figure 14. BC Timing Delays
BC Command Block Definition
Each Command Block contains (see figure 10):
A. Head Pointer. Host-written, this location can contain the address of the previous Command Block’s Head Pointer.
The BCRTM does not access this location.
B. Control Word. Host-written, the Control Word contains bit-selectable options and a Message Error bit the
BCRTM provides (see figure 13). The bit definitions follow.
Bit
Number
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BCRTM-30
Description
Message Error. The BCRTM sets this bit when it detects an invalid RT response as defined in
MIL-STD 1553B.
Skip. When set, this bit instructs the BCRTM to skip this Command Block and execute the next.
Interrupt and Continue. If set, a Standard Interrupt is asserted when this block is addressed; operation,
however, continues. Note that this interrupt must also be enabled by setting bit 0 of Register 9.
Polling Enable. Enables the BCRTM’s polling operation.
Auto Retry Enable. When set, the Auto Retry function, governed by the global parameters in the Control
Register, is enabled for this message.
End of List. Set by the CPU, this bit indicates that the BCRTM, upon completion of the current message,
will halt and assert a High-Priority Interrupt. The interrupt must also be
enabled in the High-Priority Interrupt Enable Register.
RT-RT. Set by the CPU, this indicates that this Command Block transacts an RT-RT transfer.
BIT 8
Monitor RT-RT Transfer. Set by the CPU, this function indicates that the BCRTM should receive and store
the message beginning at the location indicated by the data pointer.
Time Delay. The CPU sets this field, which causes the BCRTM to delay the specified time between sequential
message starts (see figures 13 and 14). Regardless of the value in the Time Delay field (including zero), the
BCRTM will at least meet the minimum 4µs intermessage gap time as specified in MIL-STD-1553B. The
timer is enabled by having a non-zero value in this bit field. When using this function, please note:
BITs 7-0
• Timer resolution is 16µs. As an example, if a given message requires 116µs to complete (including the minimum
4ms intermessage gap time) the value in the Time Delay field must be at least 00001000
(8 x 16µs = 128µs) to provide an intermessage gap greater than the 4ms minimum requirement.
• If the timer is enabled and the Skip bit is set, the timer provides the programmed delay before proceeding.
• If the message duration exceeds the timer delay, the message is completed just as if the time were
not enabled.
• If SKIP = 1 and EOL = 1 the HPINT is generated if enabled
• If SKIP = 1 and Interrupt and Continue = 1, the STDINT is generated
C. Command Word One. Initialized by the CPU, this location contains the first command word corresponding to the
Command Block’s message transfer.
D. Command Word Two. Initialized by the CPU, this location is for the second (transmit) command word in RT-RT
transfers. In messages involving only one RT, the location is unused.
E. Data Pointer. Initialized by the CPU, this location contains the starting location in RAM for the command block’s
message (see figure 15).
F. Status Word One. Stored by the BCRTM, this location contains the entire Remote Terminal status response.
G. Status Word Two. Stored by the BCRTM, this location contains the receiving Remote Terminal status word. For
transfers involving one Remote Terminal, the location is unused.
H. Tail Pointer. Initialized by the host CPU, the Tail Pointer contains the next Command Block’s starting address.
Compare Register contents. Program the PCR by setting the
PCR bits corresponding to the RT’s 1553 status word bits
RAM
COMMAND BLOCK #1
to be compared. If they match (i.e., two 1’s in the same bit
position) then, if enabled in both the BC Command Block
DATA WORD #1
Control Word and in the Standard Interrupt Enable Register
DATA POINTER
(Register 9), a polling comparison interrupt is generated.
MESSAGE #1
DATA WORD #2
DATA WORD #3
DATA WORD #1
COMMAND BLOCK #2
DATA WORD #2
MESSAGE #2
DATA WORD #3
DATA POINTER
Example 1. No bit match is present
PCR
00000000001
RT’s 1553 Status Word response
00000100010
Result
No Polling Comparison Interrupt
DATA WORD #4
Example 2. Bit match is present
PCR
00100100000
RT’s 1553 Status Word response
00000100000
Result
Polling Comparison Interrupt
Figure 15. Contiguous Data Storage
7.2 Polling
During a typical polling scenario (see figure 16) the Bus
Controller interrogates remote terminals by requesting them
to transmit their status words. This feature can also alert the
host if a bit is set in any RT status word response during
normal message transactions. The BCRTM enables the host
to initialize a chain of Command Blocks with the command
word’s Polling Enable bit. A programmable Polling
Compare Register (PCR) is provided. In the polling mode,
the Remote Terminal response is compared to the Polling
7.3 BC Error Detection
The Bus Controller checks for errors (see the Exception
Handling and Interrupt Logging and the RT Error Detection
sectons, pages 37 and 28) on each message transaction. In
addition, the BC compares the RT command word addresses
to the incoming status word addresses. The BC monitors for
response time-out and checks data and control words for
proper format according to MIL-STD-1553. Illogical
commands include incorrectly formatted RT-RT
Command Blocks.
BCRTM-31
B. For RT-to-BC Command Blocks:
The BCRTM transmits the Command Word.
RT
RT
RT
• Status Word DMA
The BCRTM receives the RT Status Word.
RESPONSE
Q?
BC
DMA arbitration
Status Word write (to sixth location of
Command Block)
The BCRTM receives the first Data Word.
• Data Word DMA
POLLING RESPONSE REGISTER
(RT STATUS WORD)
POLLING COMPARE WORD
(SET BY CPU)
Figure 16. Polling Operation
7.4 Bus Controller Operational Sequence
The following is a general description of the typical
behavior of the BCRTM as it processes a message in the
BC mode.
The user starts BC operation by writing a “1” to Register
0, Bit 0.
• Command Block DMA - the following occurs
immediately after Bus Controller startup:
DMA arbitration (BURST)
Control Word read
Command Word 1 read (from third location
of Command Block)
Data List Pointer read
A. For BC-to-RT Command Blocks:
The BCRTM transmits the Command Word.
• Data Word DMA
DMA arbitration
Data Word read (starting at Data List Pointer
address, incremented for each successive
word)
The BCRTM transmits the Data Word. Data Word DMAs
and transmissions continue until all Data Words are
transmitted.
• Status Word DMA
The BCRTM receives the RT Status Word.
DMA arbitration
Status Word write (to sixth location of
Command Block)
BCRTM-32
DMA arbitration
Data Word write (starting at Data List
Pointer address, incremented for each
successive word)
Data Word receptions and DMAs continue until all Data
Words are received.
C. For RT(A)-to-RT(B) Command Blocks:
The BCRTM transmits Command Word 1 to RT(B).
• Command Word 2 DMA
DMA arbitration
Command Word 2 read (from fourth location
of Command Block)
The BCRTM transmits Command Word 2 to RT(A).
The BCRTM receives the RT Status Word from RT(A).
• Status Word DMA for RT(A) Status Word
DMA arbitration
Status Word write (to sixth location of
Command Block)
The BCRTM receives the first Data Word
• Data Word DMA (only if the BCRTM is enabled to
monitor the RT-to-RT message).
DMA arbitration
Data Word write (starting at Data List Pointer
address, incremented for each successive
word)
Data Word receptions and DMAs continue until all Data
Words are received.
The BCRTM receives the RT Status Word from RT(B).
• Status Word DMA for RT(B) Status Word
DMA arbitration
Status Word write (to seventh location of
Command Block)
Block)
Data List Pointer read
Exception Handling.
If an interrupting condition occurs during the message,
the following occurs:
The BCRTM proceeds again from point A, B, or C as
shown above.
For High-Priority Interrupts:
HPINT is asserted (if enabled in Register 7). For message
errors, the BCRTM is put in a hold state until the
interrupt is acknowledged (by writing a “1” to the
appropriate bit in Register 8).
For Standard Interrupts:
DMA arbitration (BURST)
Interrupt Status Word write
Command Block Pointer write
Tail Pointer read (into Register 6)
STDINTP pulses low
STDINTL asserted (if enabled)
Processing continues
If Retries are enabled and a Retry condition occurs, the
following DMA occurs:
DMA arbitration (BURST)
Control Word read
Command Word 1 read (from third location
of Command Block)
Data List Pointer read
The BCRTM proceeds from the current Command Block to
the next successive Command Block.
•
If no Message Error has occurred during the current
Command Block, the following occurs:
DMA arbitration (BURST)
Command Block Tail Pointer read (to
determine location of next Command Block.
Note that this occurs only if no Retry).
DMA hold cycle
Control Word read (next Command Block)
Command Word 1 read (next Command
Block)
Data List Pointer read
•
If the BCRTM detects a Message Error while
processing the current Command Block, the following
occurs:
DMA arbitration (BURST)
Control Word write
Command Block Tail Pointer read (to
determine location of next Command Block.
Note that this occurs only if no Retry.)
DMA hold cycle
Control Word read (next Command Block)
Command Word 1 read (next Command
7.5 BC Operational Example (figure 22)
The BCRTM is programmed initially to accomplish the
following:
The first Command Block is for a four-word RT-RT transfer
with the BCRTM monitoring the transfer and storing
the data.
•
Auto-retry is enabled on the opposite bus using only
one retry attempt, if the incoming Status Word is
received with the Message Error bit set.
•
Wait for a time delay of 400 microseconds before
proceeding to the next Command Block.
•
The Data List Pointer contains the address 0400H.
The second Command Block is for a BC-RT transfer of
two words.
•
The End of List bit is set in its Control Word.
•
The Data List Pointer contains the address 0404H.
•
The Polling Enable bit is set and the Polling Compare
Register contains a one in Subsystem Fail position
(Bit 2).
Then:
A. The CPU initializes all the appropriate registers and
Command Blocks, and issues a Start Enable by writing
a “1” to Register 0, Bit 0.
B. The BCRTM, through executing a DMA cycle, reads
the Control Word, Command Words, and the Data List
Pointer. The delay timer starts and message execution
begins by transmitting the receive and transmit
commands stored in the Command Blocks. The
BCRTM then waits to receive the Status Word back
from the transmitting RT.
C. The BCRTM receives the RT Status Word with all status
bits low from the transmitting RT and stores the Status
Word in Command Block 1. The incoming data words
from the transmitting RT follow. The BCRTM stores
them in memory locations 0400H - 0403H.
If the Status Word indicates that the message cannot be
transmitted (Message Error), the response time-out
clock counts to zero and the allotted message time runs
out. An auto-retry can be initiated if programmed to do
so. Nevertheless, the ME bit in the Control Word is set.
BCRTM-33
D. The BCRTM receives the Status Word response from
the receiving RT. The ME bit in the Status Word is set,
indicating the message is invalid. The BCRTM initiates
the auto retry function, (as programmed) on the
alternate bus, re-transmits the Command Words,
receives the correct Status Word, and stores the data
again in locations 0400H - 0403H. This time the Status
Word response
from the receiving RT indicates the message transfer
is successful.
E. The timer delay between the two successive
transactions counts down another 135µs before
proceeding. This is determined as follows:
The message transaction time is approximately130µs
(the only approximation is due to the range in status
response and intermessage gap times specified by MILSTD-1553B). Approximating that with the retry, the
total duration for the two attempts is 265µs.
F. The BCRTM reads the Tail Pointer of Command Block
1 and places it in the Current Command Register. It also
reads the Control Word, Command Word, and Data
List Pointer, and the first data word in the second
Command Block.
G. Since this is a BC-RT transfer, the BCRTM transmits
the receive command followed by two data words from
locations 0404H - 0405H in memory. The BCRTM
reads the second data word from memory while
transmitting the first.
8.0 BUS MONITOR ARCHITECTURE
The BCRTM’s bus monitor architecture is based on a
Command Block structure and internal, host-programmable
registers. Each message transactedover the MIL-STD1553B bus (for a monitored RT address) has an associated
Command Block, which the CPU sets up (see figures 17 and
18). The Command Block contains all the relevant message
and RT status information as well as programmable function
bits that allow the user to select functions and interrupts.
MONITOR CINROL/STATUS
1553 COMMAND WORD 1
1553 COMMAND WORD
DATA LIST POINTER
1553 STATUS WORD 1
1553 STATUS WORD 2
TAIL POINTER
Figure 17 BCRTM Bus Monitor Command Block
In a linked list Command Block structure, pointers delimit
each Command Block to the successive block (see figure 19)
A data pointer9 in theCommand Block allows efficient
space allocation because data blocks do not have to be
placed contiguosly in memory
COMMAND BLOCK #1
DATA WORD #1
H. The BCRTM receives the status response from the RT.
In this case, the Status Word indicates, by the ME bit
being low, that the message is valid. The Status Word
also has the Subsystem Fail bit set.
I.
J.
The Status Word is stored in the Command Block. The
BCRTM, having encountered the end of the list, halts
message transactions and waits for another start signal.
The BCRTM asserts a High-Priority Interrupt
indicating the end of the command list. Due to the
polling comparison match, the BCRTM also asserts a
Standard Priority Interrupt and logs the event in the
Interrupt
Log List.
BCRTM-34
DATA LIST POINTER
DATA WORD #2
X
LAST DATA WORD
X IS BETWEEN 1 & 32
Figure 18. Data Placement
A Monitor control/status word with an eight-bit Time Tag,
an Interrupt When Addressed bit, a Message Error bit, and
a Command Block Activated bit are in each Monitor
Command Block. The user can access these control/status
words to determine which Monitor Command Block, the
host can determine when particular remote terminal
has occured.
8.1 Monitor Functional Operation
The Bus Monitor function is a register-selectable mode of
operation. The host users registers 14, 16, and 17 in
conjunction with Register 0 to program the BCRTM to
monitor any combination of remote terminals or all of the
remote terminals.
COMMAND BLOCK #1
CONTROL WORD
TP
#2
the BCRTM’s memory mangement scheme gives the host a
great deal of flexibility for processing 1553 bus data and is
compatible with may bus monitoring applications. the host
CPU is responsible for processing initializing the Monitor
Control Blocks. The Monitor structure is analogous to the
Bus Controller Command Block scheme. the only real
difference is the direction of information flow.
CONTROL WORD
The number of Monitor Control Blocks that the host
initializes depends on the data latency requirements for
post-processing of 1553 commands. the linked list of
Command Blocks could be connected in a loop fashion, with
the BCRTM accessing the loop at one point and the host
CPU processing the message behind that point. The bit
positions of the BM control/status word are defined as
shown in figure 20.
TP
15
CBA
14
ME
TP
#3
CONTROL WORD
#4
CONTROL WORD
TP
Figure 19. Monitor Command Block
Tail Pointers
13
12
11
10
IOA
BA/B
X
X
9
X
8
X
7
6
5
4
3
2
1
0
TT7
TT6
TT5
TT4
TT3
TT2
TT1
TT0
B0 - B7
B8 - B11
B12 - Bus A/B:
B13 - IWA:
B14 - ME:
B15 - CBA:
Time Tag (64µs resolution)
Not Used
Defines which of the dual redundant 1553 buses on which the BCRTM received
this message
Interrupt When Addressed. The BCRTM issues a standard priority interrupt
when the monitor accesses this Bus Monitor Command block.
Message Error. The BCRTM sets this bit if a 1553 message error occurred while
receiving this message.
Command Block Activated. The BCRTM sets this bit when this Bus Monitor
Command Block is accessed by the BCRTM.
Figure 20: Bus Monitor Control/Status Word
8.2 Monitor Error Detection
in the Monitor mode, the BCRTM chaecks all monitored
messages for errors. Detectable errors include word count
errors, long words, short words, Manchester errors
(including zero crossing deviation), parity errors, and
data contiguity.
Bus Controller, since the status syncis identified to the
command sync. In this case, the BCRTM will put the extra
status word in a new Monitor Command Block, and then
report a Message Error due to the to the incorrect
protocol on the erroneously interpreted status word the
RT transmitted.
Due to the nature of the 1553 protocol, it ca be very difficult
for any monitoring device to interpret some types of errors
on the 1553 bus. For example, suppose an RT (whose RT
Address the BCRTM is monitoring) incorrectly responds to
a Broadcast command. The BCRTM, which is not receiving
or transmitting the message, cannot distinguish between the
erroneous status word and a new command sent from the
8.3 Monitor Operational Sequence
The following is a general description of the operation of
the BCRTM as it processes a monitored BC-to-RT message
in the Monitor mode. DMA operations will vary slightly
depending on the type of message (i.e., RT-to-BC, RT-toRT,
etc.) It is assumed that the user has already written a "1" to
BCRTM-35
Upon completion of the message, the BCRTM initiates
a DMA cycle to update the status word and fetch the
address of the next Monitor Command block:
Register 0, bit 0, and all other registers are in the appropriate
state to enable Monitor operation.
Valid Command Received.
DMA arbitration (BURST)
Control/ Status Word write
Tail Pointer write
COMSTR goes active
•
DMA Command Block Read. After receiving
a valid command, the BCRTM initiates a burst
DMA:
DMA arbitration (BURST)
Control Word read
Command Word Write
Data List Pointer read
Data Received.
•
The exception handling scheme the BCRTM uses is based
on an interrupt structure and provides a high degree of
flexibility in:
•
defining the events that cause an interrupt,
Data Word DMA.
•
The BCRTM initiates a DMA cycle for each Data
Word to store the data in memory, whether the
command was a transmit or receive command to any
valid monitored RT Address.
selecting between High-Priority and Standard
interrupts, and
•
selecting the amount of interrupt history retained.
DMA arbitration
Data Word write (starting at Data List Pointer
address, incremented for each successive
word)
Status Word Received.
•
9.0 E XCEPTION HANDLING AND
INTERRUPT LOGGING
Status Word DMA.
DMA arbitration
Status Word write.
Exception Handling.
If an interrupting condition occurs during the
message, the following occurs:
For High-Priority Interrupts:
HPINT is asserted (if enabled in Register 7).
For message errors, the BCRTM is put in a
hold state until the interrupt is acknowledged
(by writing a “1” to the appropriate bit in
Register 8).
For Standard Interrupts:
DMA arbitration (BURST)
Interrupt Status Word write
Command Block Pointer write
Tail Pointer read (into Register 6)
STDINTP pulses low
STDINTL asserted (if enabled)
Processing continues
Message Completion
BCRTM-36
The interrupt structure consists of internal registers that
enable interrupt generation, control bits in the RT and BC
data structures (see the Remote Terminal Descriptor
Definition section, page 23, and the Bus Controller
Command Block definition, page 31), and an Interrupt Log
List that sequentially stores an interrupt events record in
system memory.
The BCRTM generates the Interrupt Log List (see figure
21) to allow the host CPU to view the Standard Interrupt
occurrences in chronological order. Each Interrupt Log List
entry contains three words. The first, the Interrupt Status
Word, indicates the type of interrupt (entries are only for
interrupts enabled). In the BC mode, the second word is a
Command Block Pointer that refers to the corresponding
Command Block. In the RT mode, the second word is a
Descriptor Pointer that refers to the corresponding
subaddress descriptor. The CPU-initialized third word, a
Tail Pointer, is read by the BCRTM to determine the next
Interrupt Log List address. The list length can be as long or
as short as required. The configuration of the Tail Pointers
determines the list length.
The host CPU initializes the list by setting the tail pointers.
This gives flexibility in the list capacity and the ability to
link the list around noncontagious blocks of memory. The
host CPU sets the list’s starting address using the Interrupt
Log List Register. The BCRTM then updates this register
with the address of the next list entry.
The internal High-Priority Interrupt Status/Reset Register
indicates the cause of a High-Priority Interrupt. The HighPriority Interrupt signal is reset by writing a “1” to the set
bits in this register.
The interrupt structure also uses three BCRTM- driven output
signals to indicate when an interrupt event occurs:
STDINTL
INTERRUPT LOG LIST
POINTER REGISTER
Standard Interrupt Level. This signal is
asserted when one or more of the events
enabled in the Standard Interrupt Enable
Register occurs. Clear the signal by resetting
the Standard Interrupt bit in the High-Priority
Interrupt Status/Reset Register.
ENTRY #1
INTERRUPT STATUS
WORD
COMMAND BLOCK
POINTER
SUBADDRESS/MODE
CODE DESCRIPTOR
POINTER
TAIL POINTER
STDINTP
Standard Interrupt Pulse. This signal is
pulsed for each occurrence of an event
enabled in the Standard Interrupt
Enable Register.
ENTRY #2
HPINT
High-Priority Interrupt. This signal is
asserted for each occurrence of an event
enabled in the High-Priority Interrupt/Enable
Register. Writing to the corresponding bit in
the High-Priority Status/Reset Register
resets it.
ENTRY #3
Figure 21. Interrupt Log List
Interrupt Status Word Definition
All bits in the Interrupt Status Word are active high and have the following functions:
Bit
Number Description
BIT 15
Interrupt Status Word Accessed. The BCRT always sets this bit during the DMA Write of the Interrupt.
Status Word. If the CPU resets this bit after reading the Interrupt Status Word, the bit can help the CPU determine
which entries have been acknowledged.
BIT 14
No Response Time-Out (Message Error condition). Further defines the Message Error condition to indicate that a
Response Time-Out condition has occurred.
BIT 13
(RT) Message Error (ME). Indicates the ME bit was set in the 1553 status word response.
BITs 12-8 Reserved.
BIT 7
(RT) Subaddress Event or Mode Code with Data Word Interrupt. Indicates a descriptor control word has been
accessed with either an Interrupt Upon Valid Command Received bit set or an Interrupt when Index=0 bit set (and
the Index is decremented to 0).
BIT 6
(RT) Mode Code without Data Word Interrupt. Indicates a mode code has occurred with an Interrupt When
Addressed interrupt enabled.
BIT 5
(RT) Illegal Broadcast Command. Applies to receive commands only. This bit indicates that a received command,
due to an illegal mode code or subaddress field, has been received in the broadcast mode. This does not include
invalid commands.
BIT 4
(RT) Illegal Command. This indicates that an illegal command has occurred due to an illegal mode code or
subaddress and T/R field. This does not include invalid commands.
BIT 3
(BC) Polling Comparison Match. Indicates a polling comparison interrupt.
BIT 2
(BC) Retry Fail. Indicates all the programmed retries have failed.
BIT 1
(BC, RT) Message Error. Indicates a Message Error has occurred.
BIT 0
(BC) Interrupt and Continue. This corresponds to the interrupt and continue function described in the Command
Block.
BCRTM-37
BCRTM-38
BCRTM
ACTIVITY
DESCRIPTION
READ LOG LIST TAIL PTR
STORE CMD BLOCKPTR
STORE INTERRUPT STATUS WORD
RECOGNIZE ME BIT
STORE STATUS WORD #2
* STATUS
RTI 2
DATA 4
RTI 2
DATA 3
RTI 2
DATA 2
RTI 2
DATA 1
RTI 2
AUTO RETRY
*
FETCH DATA WORD #2
FETCH DATA WORD#1
FETCH DATA POINTER
FETCH COMMAND WORD
FETCH CONTROL WORD
TIME OUT TO 400 µs
Figure 22. Bus Controller Scenario
400µs
STATUS
RTI 1
344 to
392µs
Notes:
1. Times for DMA Arbitration and BCRTM DMA Activities are not shown to scale
relative to the 1553B message word lengths. This is done to illustrate the operation
of these signals.
2. * = response time of 4 to 12µs.
3. DMA Arbitration represents the DMAR↓ to DMACK↑ sequence.
4. The scenario assumes that all DMA grants (DMAG) are received in the required
period of time.
5. These times depend on the DMAG response time.
FETCH CONTROL WORD
BCRTM DMA
ACTIVITY
STATUS
FETCH DATA POINTER
FETCH COMMAND WORD #1
INTERRUPT
FETCH DATA POINTER
FETCH COMMAND WORD #1
FETCH CONTROL WORD
START BCRTM
INITIALIZE REGISTERS
RTI
BC
CMD #1 CMD #2
BC
FETCH COMMAND WORD #2
BCRTM DMA
ARBITRATION3
FETCH COMMAND WORD #2
MANCHESTER
DATA BUS B
*
STORE STATUS WORD #1
DATA 2
BC
STORE DATA WORD#1
484 to
492µs
STORE DATA WORD #2
DATA 1
BC
RTI 1
* STATUS
DATA 4
RTI 2
STORE DATA WORD#3
DATA 3
RTI 2
STORE DATA WORD#4
DATA 2
RTI 2
STORE STATUS WORD #1
CMD
RTI 2
STATUS DATA 1
RTI 2
STORE DATA WORD#1
BC
*
175 to
STORE DATA WORD#2
400µs
BC
CMD #1 CMD #2
BC
168 to
STORE DATA WORD #3
MANCHESTER
DATA BUS A
BCRTM
ACTIVITY
DESCRIPTION
BCRTM DMA
ACTIVITY
INTERRUPT
BCRTM DMA
ARBITRATION3
MANCHESTER
DATA BUS B
MANCHESTER
DATA BUS A
0µs
TIME OUT TO 400 µS
FETCH TAIL POINTER
STORE STATUS WORD #2
STORE DATA WORD#4
EOL IN CONTROL WORD
SO STOP BCRTM
STORE INTERRUPT STATUS WORD
BIT TIMES
1
2
3
4
5
6
7
5
COMMAND WORD
SYNC
REMOTE TERMINAL
ADDRESS
8
9
10
11
1
12
13
14
15
16
5
SUBADDRESS/
MODE
T/R
17
18
19
5
20
1
DATA WORD
COUNT/MODE CODE
P
DATA WORD
SYNC
DATA
P
PARITY
TERMINAL FLAG
DYNAMIC BUS CONTROL ACCEPTANCE
SUBSYSTEM FLAG
BUSY
RESERVED
BROADCAST COMMANDRECEIVED
SERVICE REQUEST
Note:
T/R - transmit/receive
P - parity
REMOTE TERMINAL
ADDRESS
INSTRUMENTATION
SYNC
MESSAGE ERROR
STATUS WORD
Figure 23. MIL-STD-1553B Word Formats
BCRTM-39
10.0 ABOSOLUTE MAXIMUM RATINGS*
(REFERENCED TO VSS)
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
-0.3 to + 7.0
V
VI/O
Voltage on any pin
-0.3 to VDD + 0.3
V
VI
DC input current
± 10
mA
TSTG
Storage temperature
-65 to + 150
°C
TJMAX
Maximum junction temperature
+ 175
°C
PD
Average power dissipation 1
300
mW
Thermal resistance, junction-to-case
12
° C/Watt
ΘJC
Notes:
1. Does not reflect the added PD due to an output short-circuited.
* Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of thisspecification
is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
4.5 to 5.5
V
TC
Temperature range
-55 to +125
°C
FO
Operating frequency
12 ±.01%
BCRTM-40
MHz
11.0 DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V ± 10%; -55°C < TC < + 125°C)
SYMBOL
PARAMETER
CONDITION
MINIMUM
MAXIMUM
UNIT
VIL
Rad and
Non-Rad
Low-level input voltage
TTL inputs
VIH
Non-Rad
High-level input voltage
TTL inputs
VIH
Rad-Hard
High-level input voltage
TTL inputs 7
IIN
Non-Rad
Input leakage current
TTL inputs
Inputs with pull-up resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
-1
-1
-550
-1
-1
-80
µA
µA
µA
IIN
Rad-Hard
Input leakage current
TTL 7
Inputs with pull-up resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
-10
-10
-900
10
10
-150
µA
µA
µA
VOL 1
Low-level output voltage
TTL outputs
I OL = 3.2mA
0.4
V
1
High-level output voltage
TTL outputs
I OH = -400µA
2.4
VO = VDD or VSS
-10
VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
-110
VOH
IOZ
0.8
Three-state output leakage current
TTL outputs
Short-circuit output current
CIN
Input capacitance
CIO
IDD
QIDD
3
Bidirect I/O capacitance
3
Average operating current
Quiescent
current8
1, 2
3
Output capacitance
2.0
V
2.2
V
6
IOS
COUT
V
1, 4
V
10
µA
110
mA
mA
ƒ = 1MHz @ 0V
10
pF
ƒ = 1MHz @ 0V
15
pF
ƒ = 1MHz @ 0V
20
pF
50
mA
1
35
mA
µA
ƒ = 12MHz, CL = 50pF
+125o C
See Note 5, Tc =
Tc = 25oC, -55oC
Notes:
1. Supplied as a design limit, but not guaranteed or tested.
2. Not more than one output may be shorted at a time for a maximum duration of one second.
3. Measured only for initial qualification, and after process or design changes which may affect input/output capacitance.
4. Includes current through input pull-up. Instantaneous surge currents on the order of 1 ampere can occur during output switching.
Voltage supply should be adequately sized and decoupled to handle a large current surge.
5. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.
6. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions
VIH = VIH(min) +20%, -0%; VIL = VIL(max) +0%, -50%, as specified herein, for TTL-compatible inputs.
Devices may be tested using input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max).
7. To 1.0E6 total dose; above this level, CMOS I/Os required.
8. Guaranteed to pre- and post-irradiation limits.
BCRTM-41
12.0 AC ELECTRICAL CHARACTERISTICS
(OVER RECOMMENDED OPERATING CONDITIONS)
VIH
1
INPUT VIL MAX
tb
ta
IN-PHASE
OUTPUT
OUT-OF-PHASE
OUTPUT
VIH MIN
VIL MAX
1
tc
2
2
2
td
2
VOH MIN
VOL MAX
VOH MIN
VOL MAX
te
VOH MIN
BUS
VOL MAX
tf
tg
th
SYMBOL
ta
PARAMETER
INPUT↑ to response↑
INPUT↓ to response↓
tb
tc
td
INPUT↑ to response↓
INPUT↓ to response↑
INPUT↓ to data valid
INPUT↓ to high Z
INPUT↑ to high Z
INPUT↑ to data valid
te
tf
tg
th
Notes:
1. Timing measurements made at (VIH MIN + VIL MAX)/2.
2. Timing measurements made at (VOL MAX + VOH MIN)/2.
3. Based on 50pF load.
4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization.
Figure 24. Typical Timing Measurements
5V
IREF (source)
90%
3V
90%
VREF
•
50pF
10%
10%
0V
IREF (sink)
Output Loading
< 2ns
< 2ns
Input Pulses
Note:
50pF including scope probe and test socket
Figure 25. AC Test Loads and Input Waveforms
BCRTM-42
DMA GRANT RECOGNIZED ON THIS EDGE
MCLKD2
tSHL1
DMAR
DMAG
tPW2
DMACK
TSCTL
MEMCSO
ADDRESS
DATA
RWR/RRD 2
AEN
BURST
tPHL1
tOOZL1
tPZL1
tPHL2
tHLH2
tPHL3
tPHL4
SYMBOL
tSHL16
tPHL1
tPHL21
tPZL16
tHLH2
tPHL3
tPW21
tOOZL1
tPHL4
tPHL4
Notes:
PARAMETER
DMACK↓ to DMAR High Impedance RAD
NON-RAD
3
DMAG↓ to DMACK↓
DMAG↓ to TSCTL↓
TSCTL↓ to ADDRESS valid RAD
NON-RAD
RWR/RRD↑ to DMACK↑
TSCTL↓ to RWR/RRD↓
DMAG↓ to DMAG↑
DMAR↓ to BURST↑
DMAR↓ to DMAG↓ 5
DMAR↓ to DMAG↓ 4
MIN
-2
0
40
40
UNITS
ns
ns
ns
ns
ns
ns
THMC1-10
MCLK-20
MCLK
THMC1+10
MCLK+20
6xMCLK
ns
ns
ns
-10
0
0
10
3.5 (1.9)
1.9 (0.8)
ns
µs
µs
-5
10
0
2x-2MCLK
MAX
+5
10
45
4xMCLK
1. Guaranteed by test.
2. See figures 27 & 28 for detailed DMA read and write timing.
3. DMAG must be asserted at least 45ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2 cycle.
If DMAG is not asserted at least 45ns prior to the rising edge of MCLKD2, DMAG is not recognized until the following MCL
KD2 cycle.
4. Provided MCLK = 12MHz. Number in parentheses indicates the longest DMAR↓ to DMAG↓ allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
5. Provided MCLK = 6MHz. Number in parentheses indicates the longest DMAR↓ DMAG↓ allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
6. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
MCLK = period of the memory clock cycle.
BURST signal is for multiple-word DMA accesses.
THMC1 is equivalent to the positive phase of MCLK (see figure 27).
Figure 26. BURST DMA Timing
BCRTM-43
tIOHL1
tPLH1
THMC1
THMC2
MCLK
MCLKD2
TSCTL
MEMCSO
tPLH2
tHLZ2
ADDRESS
DATA
RRD
tHLZ1
tSHL1
t SLH1
SYMBOL
tSHL1
tPW1
tHLZ
tHLZ2
tSLHI
MIN
ADDRESS valid to RRD↓ (ADDRESS set-up) RAD
)
NON-RAD
2
tPLH1
tPLH2
PARAMETER
1
tIOHL1
RRD↓ to RRD↑
RRD↑ to ADDRESS High Impedance
RRD↑ to DATA High Impedance
DATA valid to RRD↑
MCLK↑ to MCLKD2↑
MCLK↑ to TSCTL/MEMCSO↓
1
MCLK↑ to RRD↓
(ADDRESS hold)
(DATA hold)
(DATA set-up)
-5
10
+5
10
MCLK-10 MCLK+5
THMC1+10 THMC1+10
5
40
0
0
0
Note:
1. Guaranteed by test.
2. Pre- and Post-Irradiation Limits.
Figure 27. BCRTM DMA Read Timing (One-Word Read)
BCRTM-44
MAX
40
40
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
tIOHL1
tPLH1
THMC1
THMC2
MCLK
MCLKD2
TSCTL
MEMCSO
tPLH2
tHLZ2
ADDRESS
DATA
RWR
tSHL1
SYMBOL
tSHL12
tOOZL11,2
tHLZ1
tHLZ2
tPW1
tPLH1
tPLH2
tIOHL1
1
1
PARAMETER
ADDRESS valid to RWR↓
RWR↓ to DATA valid NON-RAD
RAD
tOOZL1
tHLZ1
tPW1
MIN
MAX
(ADDRESS setup) THMC2-10 THMC2+5
0
-5
30
30
RWR↑ to DATA High Impedance
(DATA hold)
THMC1-10 THMC1+10
RWR↑ to ADDRESS High Impedance (ADDRESS hold) THMC1-10 THMC1+10
RWR↓ to RWR↑
MCLK-10 MCLK+5
MCLK↑ to MCLKD2↑
0
40
MCLK↑ to TSCTL/MEMCSO↓
0
40
MCLK↑ to RWR↓
0
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. Guaranteed by test
2. Pre- and Post-Irradiation Limits.
Figure 28. BCRTM DMA Write Timing (One-Word Write)
BCRTM-45
tOOZH2
tOOZH1
tHLH1
ADDRESS
DATA
RD+CS
tHLH2
tPW1
SYMBOL
tOOZH22
tHLH2
tOOZH1 2
tHLH1
tPW1
tPW2
PARAMETER
ADDRESS valid to DATA valid
RD+CS↑ to DATA High Impedance
RD+CS↓ to DATA Valid
RD+CS↑ to ADDRESS High Impedance
RD+CS↓ to RD+CS↑
RD+CS↑ to RD+CS↓
MIN
(DATA hold)
(DATA access)
(ADDRESS hold)
tPW21
Notes:
1. Guaranteed by functional test.
2. User must adhere to both tOOZH1 and tOOZH2 timing constraints to ensure valid data.
5
5
60
80
MAX
80
50
60
-
UNITS
ns
ns
ns
ns
ns
ns
Figure 29. BCRTM Register Read Timing
tSHL1
tPW1
tHLH2
ADDRESS
DATA
WR+CS
tHLH1
tPW2
tSHL2
SYMBOL
tSHL1
tSHL2
tPW1
tHLH1
tHLH2
PARAMETER
ADDRESS valid to WR+CS↓
DATA valid to WR+CS ↓
WR+CS↓ to WR+CS↑
(DATA hold)
WR+CS↑ to DATA High Impedance
WR+CS↑ to ADDRESS High Impedance (ADDRESS hold)
WR+CS↑ to WR+CS↓
tPW21
Note:
1. Guaranteed by functional test.
BCRTM-46
MIN
(ADDRESS setup)
(DATA setup)
Figure 30. BCRTM Register Write Timing
60
5
60
10
10
80
MAX
-
UNITS
ns
ns
ns
ns
ns
ns
tPHL1
RD
RRD
tPHL2
WR
RWR
tPHL3
MEMCSI
MEMCSO
SYMBOL
tPHL1 1
tPLH2 1
tPHL3 1
PARAMETER
RD↓ to RRD↓
WR↓ to RWR↓
MEMCSI↓ to MEMCSO↓
MIN
MAX
UNITS
0
30
ns
0
0
30
30
ns
ns
Figure 31. BCRTM Dual-Port Interface Timing Delays
t PZLI
MANCHESTER C
D
D
DMA
ACTIVITY
SYMBOL
tPZL11,2
PARAMETER
Data word to DMA activity
MIN
0
MAX
UNITS
µs
4
This diagram indicates the relationship between the incoming Manchester code and DMA activity (i.e., DMAR↓ to DMACK↑).
Note:
1. The pulse width = (11µ s -tDMA -tPZL1) where tDMA is the time to complete DMA activity (i.e., DMAR↓ to DMACK↑).
2. Guaranteed by functional test.
Figure 32. DMA Activity Memory Window (RT Mode)
BCRTM-47
tPLH2
MCLK
MCLKD2
DMAR
DMAG
DMAGO
DMACK
tSHL1
tPHL1
SYMBOL
tPHL11
tSHL12
tPLH2
PARAMETER
DMAG↓ to DMAGO ↓
DMACK↓ to DMAR High Impedance RAD
NON-RAD
MCLK↑ to MCLKD2↑
MIN
MAX
UNITS
0
30
5
10
ns
-5
0
0
40
ns
Notes:
1. When DMAG is asserted before DMAR, the DMAG signal passes through the BCRTM as DMAGO.
2. Pre- and Post-Irradiation Limits.
Figure 33. BCRTM Arbitration when DMAG is Asserted before Arbitration
BCRTM-48
ns
Package Selection Guide
RTI
24-pin DIP
(single cavity)
36-pin DIP
(dual cavity)
68-pin PGA
84-pin PGA
144-pin PGA
84-lead LCC
36-lead FP
(dual cavity)
(50-mil ctr)
84-lead FP
132-lead FP
RTMP
RTR
Product
BCRT BCRTM BCRTMP
RTS
XCVR
X
X
X
X
X
X
X
X1
X
X1
X
X
X
X
X
X
X
NOTE:
1. 84LCC package is not available radiation-hardened.
Packaging-1
D
1.565 ± 0.025
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
0.040 REF.
0.080 REF.
(2 Places)
A
L
0.130 ±0.010
0.100 REF.
(4 Places)
E
1.565 ± 0.025
-B-
PIN 1 I.D.
(Geometry Optional)
e
0.100
TYP.
TOP VIEW
-CA
(Base Plane)
b
0.018 ± 0.002
0.030 C A B
0.010 C 2
R
SIDE VIEW
P
N
M
L
K
J
D1/E1
1.400
H
G
F
E
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW
0.003 MIN. TYP.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All package finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
144-Pin Pingrid Array
Packaging-2
1
D/E
1.525 ± 0.015 SQ.
D1/E1
0.950 ± 0.015 SQ.
A
0.110
0.006
A
PIN 1 I.D.
(Geometry
Optional)
e
0.025
SEE DETAIL A
A
LEAD KOVAR
TOP VIEW
C
0.005 + 0.002
- 0.001
L
0.250
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX. REF.
(At Braze Pads)
DETAIL A
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
132-Lead Flatpack (25-MIL Lead Spacing)
Packaging-3
A
0.115 MAX.
D/E
1.150 ± 0.015 SQ.
A1
0.080 ± 0.008
A
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
SIDE VIEW
L/L1
0.050 ± 0.005 TYP.
h
0.040 x 45_
REF. (3 Places)
B1
0.025 ± 0.003
e
0.050
J
0.020 X 455 REF.
e1
0.015 MIN.
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-LCC
Packaging-4
A
D/E
1.810 ± 0.015 SQ.
D1/E1
1.150 ± 0.012 SQ.
A
0.110
0.060
PIN 1 I.D.
(Geometry
Optional)
A
e
0.050
b
0.016 ± 0.002
SEE DETAIL A
A
LEAD KOVAR
C
0.007 ± 0.001
TOP VIEW
L
0.260
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX.
REF.
(At Braze Pads)
BOTTOM VIEW A-A
DETAIL A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-Lead Flatpack (50-MIL Lead Spacing)
Packaging-5
D
1.100 ± 0.020
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
A
L
0.130 ± 0.010
E
1.100 ± 0.020
PIN 1 I.D.
(Geometry Optional)
-B-
-C(Base Plane)
TOP VIEW
e
0.100
TYP.
0.030 C A B
0.010 C 2
SIDE VIEW
L
K
J
H
G
D1/
1.000
F
E
D
1
A
b
0.018 ± 0.002
2
3
4
5
6
7
8 9 10 11
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
0.003 MIN.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
84-Pin Pingrid Array
Packaging-6
1
D
1.100 ± 0.020
A
0.130 MAX.
Q
0.050 ± 0.010
-A-
A
L
0.130 ± 0.010
E
1.100 ± 0.020
-B-
PIN 1 I.D.
(Geometry Optional)
A
-C(Base Plane)
TOP
b
0.010 ± 0.002
∅ 0.030 C A B
∅ 0.010 C 2
e
0.100
TYP.
1
SIDE VIEW
L
K
J
H
G
F
E
D
C
B
A
D1/E1
1.00
1 2 3 4 5 6
PIN 1 I.D.
(Geometry Optional)
7
8
9
10 11
0.003 MIN. TYP.
BOTTOM VIEW A-A
Notes:
1 True position applies to pins at base plane (datum C).
2 True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
68-Pin Pingrid Array
Packaging-7
E
0.750 ± 0.015
L
0.490
MIN.
b
0.015 ± 0.002
D
1.800 ± 0.025
e
0.10
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
c
0.008
+ 0.002
- 0.001
A
0.130 MAX.
END VIEW
Notes:
1 All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)
Packaging-8
Q
0.080 ± 0.010
(At Ceramic Body)
E
0.700 + 0.015
L
0.330
MIN.
b
0.016 + 0.002
D
1.000 ± 0.025
e
0.050
PIN 1 I.D
(Geometry Optional)
TOP
+ 0.002
c
0.007 - 0.001
A
0.100 MAX.
END
Q
0.070 + 0.010
(At Ceramic Body)
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)
Packaging-9
E
0.590 ± 0.012
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.800 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
C
0.010 +- 0.002
0.001
E1
0.600 + 0.010
(At Seating Plane)
A
0.155 MAX.
L/L1
0.150 MIN.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
36-Lead Side-Brazed DIP, Dual Cavity
Packaging-10
E
0.590 ± 0.015
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.200 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
+ 0.002
C
0.010 - 0.001
E1
0.600 + 0.010
(At Seating Plane)
L/L1
0.150 MIN.
A
0.140 MAX.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
24-Lead Side-Brazed DIP, Dual Cavity
Packaging-11
ORDERING INFORMATION
UT1553B BCRT/M Bus Controller/Remote Terminal/Monitor: SMD
5962
*
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(X) = 84 pin PGA (NonRad only)
(Y) = 84 pin FP
(Z) = 84 pin LCC (NonRad only)
Class Designator:
(-) = Blank or No field is QML Q
(V) = Class V
Drawing Number: 8957701
Total Dose:
(F) = 3E5 (300KRad)
(G) = 5E5 (500KRad)
(H) = 1E6 (1MRad)
(R) = 1E5 (100KRad)
(-) = None
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-89577Q1YX).
4. 84 LCC only available with solder lead finish.
UT1553B BCRT/M Bus Controller/Remote Terminal/Monitor
UT1553B/
BCRTM- *
*
*
*
Total Dose:
()
= None
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Screening:
(C) = Military Temperature
(P) = Prototype
Package Type:
(A) = 84pin LCC (solder only)
(G) = 84 pin PGA
(W) = 84 pin FP
UTMC Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Mil Temp range flow per UTMC’s manufacturing flows document. Devices are tested at -55°C, room temperature, and 125°C. Radiation neither tested
nor guaranteed.
4. Prototpe flow per UTMC’s document manufacturing flows and are tested at 25°C only. Radiation characteristics neither tested nor guaranteed. Lead
finish is GOLD only.
5. 84 LCC only available with solder lead finish.