2Mx8/1Mx16/512Kx32, 30A244-00 A 12 - 20ns, Surface Mount 32 Megabit CMOS SRAM DP3S1MX32PY5 ADVANCED INFORMATION PIN-OUT DIAGRAM DESCRIPTION: The DP3S1MX32PY5 is a 1M x 32 SRAM module that utilizes the new and innovative space saving TSOP stacking technology. The module is constructed of two 1M x 16 SRAM’ s that are configured as a 1M x 32. The DP3S1MX32PY5 module features high speed access times with common data inputs and outputs. FEATURES: • Organizations Available: 1M x 32 • Access Times: 10*, 12, 15, 20ns • 3.3 ± 0.3** Volt Power Requirement • Fully Static Operation - No clock or refresh required • TTL-compatible Inputs and Outputs • 80-Pin Surface Mount LP-Stack ™ PIN NAMES A0 - A19 I/O0 - I/O31 CS Address Inputs Data Input/Output Stack Enable WE OE BS0 BS1 Write Enable Output Enable Byte Select I/O0 - I/O7 Byte Select I/O8 - I/O15 BS2 BS3 VDD VSS Byte Select I/O16 - I/O23 Byte Select I/O24 - I/O31 Power (+3.3V) Ground NU. Not Usable FUNCTIONAL BLOCK DIAGRAM * 0°-70° only. ** 5% for 10ns only. 30A244-00 REV. A This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change or discontinue information on this product without prior notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 DP3S1MX32PY5 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION Symbol V DD VIH VIL TA RECOMMENDED OPERATING RANGE 4 Characteristic Min. 10ns 3.135 Supply Voltage 12, 15, 20ns 3.0 Input HIGH Voltage 2.0 Input LOW Voltage -0.32 C 0 Operating Temperature CI -40 CAPACITANCE 5: TA = Symbol Parameter CADR Address Input CCE Chip Enable CBS Byte Select CWE Write Enable COE Output Enable CI/O Data Input/Output 25°C, F = 1.0MHz Max. 20 20 15 20 20 15 Unit Condition pF VIN2 = 0V DC OUTPUT CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit V OH HIGH Voltage IOH= -2mA 2.4 V VOL LOW Voltage IOL=+2mA 0.4 V Typ. 3.3 3.3 +25 +25 Max. 3.465 3.6 V DD+0.33 0.8 +70 +85 AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels Load 1 2 CL 30pF 5pF Unit V V V oC 0V to 3.0V 2ns 1.5V OUTPUT LOAD Parameters Measured except tLZ, tHZ, tOHZ , tOLZ, and tWHZ tLZ, tHZ, tOHZ, tOLZ, and tWHZ +3.3V Figure 1. Output Load ** Including Probe and Jig Capacitance. Symbol TSTC TBIAS VDD V I/O Symbol IIN IOUT ICC ISB1 ISB2 VOL V OH ABSOLUTE MAXIMUM RATINGS 4 Parameter Value Storage Temperature -55 to +125 Temperature Under Bias -55 to +125 Supply Voltage 1 -0.5 to +4.6 Input/Output Voltage 1 -0.5 to +4.6 1200Ω Unit °C °C V V DC OPERATING CHARACTERISTICS: Over operating ranges Characteristics Test Conditions Min. Input V IN = 0V to VDD, VDD = max. -2 Leakage Current Output V I/O = 0V to VDD, -1 Leakage Current V DD = max., CE = VIH Dynamic CE = VIL, VDD = max. Operating Current I OUT = 0mA, f = f max. Full Standby Supply f = 0, VIN ≥ VDD -0.2V or Current (CMOS) V IN ≤ VSS +0.2V, CE ≥ VDD -0.2V Standby Current (TTL) CE = VIH, f = f max. Output Low Voltage I OUT = +2.0mA Output High Voltage I OUT = -2.0mA 2.4 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DOUT CL** 780Ω Max. Unit +2 µA +1 µA 900 mA 8 mA 210 0.4 mA V V 30A244-00 REV. A DP3S1MX32PY5 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION TRUTH TABLE Mode CS OE Read L L Write L X Output Data Standby H = HIGH L H L X H X L = LOW WE BS0 BS1 L L H L H L H L L L L L L H L L L H L L L L H X X X H H X X X X = Don’ t Care BS2 BS3 L L L H L L L L H L X H X L L L L H L L L L H X H X I/O0I/O7 DOUT High-Z DOUT DOUT DOUT D IN High-Z D IN D IN D IN High-Z High-Z High-Z I/O8I/O15 D OUT D OUT High-Z D OUT D OUT DIN DIN High-Z DIN DIN High-Z High-Z High-Z I/O16I/O23 DOUT DOUT DOUT High-Z DOUT DIN DIN DIN High-Z DIN High-Z High-Z High-Z I/O24- Supply I/O31 Current DOUT DOUT DOUT Active DOUT High-Z DIN DIN Active DIN DIN High-Z High-Z Active High-Z High-Z Standby AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges 10ns 12ns 15ns 20ns No. Symbol Parameter Min. 1 2 3 4 5 6 7 8 9 10 11 12 tRC tAA tCO tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Read Cycle Time Address Access Time CE to Output Valid Output Enable to Output Valid Byte Enable Access Time CE to Output in LOW-Z 5, 6 Output Enable to Output in LOW-Z 5, 6 Byte Enable to Output in LOW-Z CE to Output in HIGH-Z 5, 6 Output Enable to Output in HIGH-Z 5, 6 Byte Enable to Output in HIGH-Z Output Hold from Address Change Max. 10 3 1 1 3 Min. Max. 12 10 10 5 5 6 6 6 3 1 1 3 Min. Max. 15 12 12 6 6 7 7 7 3 1 1 3 Min. Max. 20 15 15 8 8 8 8 8 20 20 9 9 3 1 1 9 9 9 3 AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 7, 8: Over operating ranges 10ns 12ns 15ns 20ns No. Symbol Parameter Min. 13 14 15 16 17 18 19 20 21 22 23 tWC tAW tCW tBW tAS tWP tWR tWHZ tDW tDH tOW Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Byte Enable to End of Write Address Set-Up Time * Write Pulse Width (OE High) Write Recovery Time, CE, WE Write Enable to Output in HIGH-Z 5, 6 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write Max. 10 8.5 8.5 8.5 0 7 0 Min. 12 9 9 9 0 8 0 6 6 0 1 Max. Min. 15 11 11 11 0 10 0 7 7 0 1 Max. Min. 20 15 15 15 0 12 0 8 8 0 1 Max. 10 10 0 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns * Valid for both Read and Write Cycles. 30A244-00 REV. A Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 DP3S1MX32PY5 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION READ CYCLE ADDRESS CE OE BS0 - BS3 DATA OUT WRITE CYCLE 1: WE Controlled. ADDRESS WE CE BS0 - BS3 DATA IN DATA OUT 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A244-00 REV. A DP3S1MX32PY5 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION WRITE CYCLE 2: CE Controlled. ADDRESS WE CE BS0 - BS3 DATA IN DATA OUT WRITE CYCLE 3: UB, LB Controlled. ADDRESS WE CE BS0 - BS3 DATA IN DATA OUT 30A244-00 REV. A Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 DP3S1MX32PY5 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION ORDERING INFORMATION NOTES: 1. All voltages are with respect to VSS. 2. -1.5V min. (Pulse Width ≤4ns) for I ≤ 20mA. 3. VIH (max.)=VDD+1.5Vdc (Pulse Width ≤4ns) for I ≤20mA. 4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5. 6. 7. 7. 9. This parameter is guaranteed and not 100% tested. Transition is measured at the point of ±500mV from steady state voltage. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. The outputs are in a high impedance state when WE is LOW. Chip Enable and Write Enable can initiate and terminate WRITE Cycle. MECHANICAL DRAWING Dense-Pac Microsystems, Inc. 7321 Lincoln Way, Garden Grove, California 92841-1431 (714) 898-0007 u (800) 642-4477 u FAX: (714) 897-1772 u http://www.dense-pac.com 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A244-00 REV. A