HANBIT HMS12864F8VL-70

HANBit
HMS12864F8VL
SRAM MODULE 1MByte (128K x 64 bit), 120-Pin SMM, 3.3V
Part No. HMS12864F8VL
GENERAL DESCRIPTION
The HMS12864F8VL is a high-speed static random access memory (SRAM) module containing 131,072 words organized in
a x 64-bit configuration. The module consists of eight 128K x 8 SRAMs mounted on a 120-pin, both-sided, FR4-printed circuit
board.
Byte write enable inputs,(/WE0,/WE1,/WE2,/WE3,/WE4,/WE5,/WE6,/WE7) are used to enable the module’s 8 bits
independently. Output enable(/OE) and write enable(/WE) can set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is
accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from
a single +3.3V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
PIN ASSIGNMENT
P1
w Access times : 70 and 100ns
w High-density 1MByte design
w High-reliability, high-speed design
w Single + 3.3V ±0.3V power supply
w Easy memory expansion with /CE and
/OE functions
w All inputs and outputs are TTL-compatible
w Industry-standard pin-out
w FR4-PCB design
OPTIONS
MARKING
w Timing
70ns access
- 70
100ns access
-100
w Packages
120-pin SMM
F
P2
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
/WE0
/WE1
/WE2
/WE3
/WE4
Vcc
/WE5
/WE6
/WE7
/CS2
Vcc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vss
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Vss
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Vss
A0
A1
A2
A3
A4
Vss
A5
A6
A7
/CS1
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vcc
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vcc
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vcc
A16
A15
A14
A13
A12
Vcc
A11
A10
A9
A8
Vcc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vss
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
Vss
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
Vss
NC
NC
/OE
NC
NC
Vss
NC
NC
NC
NC
Vss
1
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
FUNCTIONAL BLOCK DIAGRAM
DQ0 – DQ63
64
17
A0 - A16
A0-16
A0-16
DQ 32-39
DQ 0-7
U1
/CE
U5
/CE
/OE
/OE
/WE
/WE
/WE0
A0-16
A0-16
DQ 40-47
DQ 8-15
/CE
/CE
U2
/OE
U6
/OE
/WE
/WE
/WE1
A0-16
A0-16
DQ48-55
DQ16-23
/CE
/CE
U3
U7
/OE
/OE
/WE
/WE
/WE2
A0-16
A0-16
DQ56-63
DQ24-31
/CE
/OE
/CE
/CE
U4
/OE
U8
/OE
/WE
/WE
/WE3
2
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN,OUT
-0.5V to Vcc+0.5V
Voltage on Vcc Supply Relative to Vss
VCC
-0.3V to 4.6V
Power Dissipation
PD
8.0W
o
-65 C to +150oC
0oC to +70oC
Voltage on Any Pin Relative to Vss
Storage Temperature
TSTG
Operating Temperature
TA
w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA=0 to 70 o C )
PARAMETER
*
SYMBOL
MIN
TYP.
MAX
Supply Voltage
VCC
3.0V
3.3V
3.6V
Ground
VSS
0
0
0
Input High Voltage
VIH
2.2
-
Vcc+0.3V**
Input Low Voltage
VIL
-0.3*
-
0.6V
VIL(Min.) = -2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA
** VIH(Min.) = Vcc+2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 3.3V ± 10% )
PARAMETER
Input Leakage Current
Output Leakage Current
TEST CONDITIONS
VIN=Vss to Vcc
/CE=VIH or /OE =VIH or /WE=VIL
VOUT=Vss to VCC
SYMBOL
MIN
MAX
UNITS
ILI
-8
8
µA
IL0
-8
8
µA
2.4
Output High Voltage
IOH = -4.0Ma
VOH
Output Low Voltage
IOL = 8.0mA
VOL
V
0.4
V
* Vcc=3.3V, Temp=25 oC
DC AND OPERATING CHARACTERISTICS (2)
DESCRIPTION
Power Supply
Current:Operating
Power Supply
Current:Standby
TEST CONDITIONS
SYMBOL
MAX
UNIT
70
100
ICC
32
32
mA
ISB
2.4
2.4
mA
ISB1
80
80
uA
Min. Cycle, 100% Duty
/CE=VIL, VIN=VIH or VIL,
IOUT=0mA
Min. Cycle, /CE=VIH
f=0MHZ, /CE≥VCC-0.2V,
VIN≥ VCC-0.2V or VIN≤0.2V
3
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
CAPACITANCE (TA =25 oC , f= 1.0Mhz)
DESCRIPTION
Input /Output Capacitance
Input Capacitance
TEST CONDITIONS
SYMBOL
MAX
UNIT
VI/O=0V
CI/O
80
pF
CIN
64
pF
VIN=0V
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 3.3V ± 0.3V, unless otherwise specified)
Test conditions
PARAMETER
VALUE
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
See below
Output Load (B)
Output Load (A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
VL=1.5V
+3.3V
50Ω
DOUT
319Ω
DOUT
Z0=50Ω
30pF
353Ω
5pF*
READ CYCLE
70
PARAMETER
100
SYMBOL
UNIT
MIN
MAX
70
MIN
MAX
Read Cycle Time
tRC
Address Access Time
tAA
70
100
ns
Chip Select to Output
tCO
70
100
ns
Output Enable to Output
tOE
35
50
ns
Output Enable to Low-Z Output
tOLZ
5
5
ns
Chip Enable to Low-Z Output
tLZ
10
10
ns
Output Disable to High-Z Output
tOHZ
0
25
0
30
ns
Chip Disable to High-Z Output
tHZ
0
25
0
30
ns
Output Hold from Address Change
tOH
10
Chip Select to Power Up Time
tPU
ns
Chip Select to Power Down Time
tPD
ns
4
100
15
ns
ns
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
WRITE CYCLE
PARAMETER
70
SYMBOL
MIN
100
MAX
MIN
MAX
UNIT
Write Cycle Time
tWC
70
100
ns
Chip Select to End of Write
tCW
60
80
ns
Address Set-up Time
tAS
0
0
ns
Address Valid to End of Write
tAW
60
80
ns
Write Pulse Width
tWP
55
70
ns
Write Recovery Time
tWR
0
0
ns
Write to Output High-Z
tWHZ
0
Data to Write Time Overlap
tDW
30
40
ns
Data Hold from Write Time
tDH
0
0
ns
End of Write to Output Low-Z
tOW
5
5
ns
25
0
30
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(Address Controlled) ( /CE =/ OE = VIL , /WE = VIH)
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
5
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
tRC
Address
tHZ(3,4,5)
tAA
tCO
/CE
tLZ(4,5)
tOHZ
tOE
/OE
tOH
tOLZ
Data Out
Vcc Supply
Current
High-Z
tPD
tPU
lCC
50%
50%
lSB
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock )
tWC
Address
tAW
tWR(5)
/OE
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ(6)
tOW
Data Out
High-Z
6
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed )
Address
tAW
tCW(3)
tWR(5)
/CE
tAS(4)
tOH
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tWHZ(6,7)
tOW
(10)
(9)
High-
Data Out
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
MODE
I/O PIN
SUPPLY CURRENT
H
X*
X
Not Select
High-Z
l SB, l SB1
L
H
H
Output Disable
High-Z
lCC
L
H
L
Read
DOUT
lCC
L
L
X
Write
DIN
lCC
Note: X means Don't Care
7
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
PACKAGING INFORMATION
FRONT SIDE
REAR SIDE
1.0±0.08 mm
8
HANBit Electronics Co.,Ltd.
HANBit
HMS12864F8VL
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMS12864F8VL-70
1MByte
X 64
120 Pin-SMM
HMS12864F8VL-100
1MByte
X 64
120 Pin-SMM
9
Component
Vcc
SPEED
8EA
3.3V
70ns
8EA
3.3V
100ns
Number
HANBit Electronics Co.,Ltd.