ISSI ® IS61SF6436 64K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • • • • • • • • • • • • Fast access times: 8.5 ns, 9 ns, 10 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 100-Pin TQFP and PQFP package Single +3.3V power supply Two Clock enables and one Clock disable to eliminate multiple bank bus contention. Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state APRIL 2001 DESCRIPTION The ISSI IS61SF6436 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4 controls DQP4 and DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SF6436 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 1 ISSI IS61SF6436 ® BLOCK DIAGRAM MODE CLK Q0 CLK A0' A0 BINARY COUNTER ADV ADSC ADSP A15-A0 Q1 CE A1' A1 64K x 36 MEMORY ARRAY CLR 16 D Q 14 16 ADDRESS REGISTER CE CLK 36 GW BWE BW4 D 36 Q DQP4 DQ31-DQ24 BYTE WRITE REGISTERS CLK D BW3 DQP3 Q DQ23-DQ16 BYTE WRITE REGISTERS CLK D BW2 Q DQP2 DQ15-DQ8 BYTE WRITE REGISTERS CLK D BW1 DQP1 Q DQ8-DQ0 BYTE WRITE REGISTERS CLK FT CE CE2 CE2 4 D Q ENABLE REGISTER 36 INPUT REGISTERS CLK DATA[35.0] OE CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® PIN CONFIGURATION A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP and PQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQP2 DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 DQP1 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 NC DQP3 DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 GNDQ VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 DQP4 PIN DESCRIPTIONS A0-A15 Address Inputs DQ1-DQ32 Data Input/Output CLK Clock DQP1-DQP4 Parity Inputs/Outputs ADSP Processor Address Status ZZ Sleep Mode ADSC Controller Address Status MODE Burst Sequence Mode ADV Burst Address Advance VCC +3.3V Power Supply BW1-BW4 Synchronous Byte Write Enable GND Ground BWE Byte Write Enable VCCQ GW Global Write Enable Isolated Output Buffer Supply: +3.3V CE, CE2, CE2 Synchronous Chip Enable GNDQ Isolated Output Buffer Ground OE Output Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 3 ISSI IS61SF6436 ® TRUTH TABLE ADDRESS USED CE CE2 CE2 Deselected, Power-down None H X X X Deselected, Power-down None L X L Deselected, Power-down None L H Deselected, Power-down None L Deselected, Power-down None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current OPERATION Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADSP ADSC ADV WRITE OE DQ L X X X High-Z L X X X X High-Z X L X X X X High-Z X L H L X X X High-Z L H X H L X X X High-Z L L L L L X X H H X H X X H H X H L L L L L X X X X X X X X X X X X H H H H H X X X X X X X X X X X X L L H H H H H X X H X H H X X H X X X L L L H H H H H H H H H H H H X X X X X L L L L L L H H H H H H X X L H H H H H H L L H H H H L L L H X L H L H L H X X L H L H X X Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. PARTIAL TRUTH TABLE FUNCTION READ READ WRITE Byte 1 WRITE All Bytes WRITE All Bytes 4 GW BWE BW1 BW2 BW3 H H H H L H L L L X X H L L X X H H L X X H H L X BW4 X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs VCC Voltage on Vcc Supply Relatiive to GND Value Unit –10 to +85 °C –55 to +150 °C 1.8 W 100 mA –0.5 to VCCQ + 0.3 V –0.5 to 5.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 5 ISSI IS61SF6436 ® OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C VCC 3.3V +10%, –5% –40°C to +85°C 3.3V +10%, –5% Industrial DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V VIL Input LOW Voltage –0.3 0.8 V ILI Input Leakage Current GND - VIN - VCCQ(2) Com. Ind. –5 –10 5 10 µA ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. Ind. –5 –10 5 10 µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) -8.5 Typ. Max. 9Typ. Max. -10 Typ. Max. Unit 190 220 — — 180 210 — — 170 200 180 210 mA mA Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time • tKC min. 45 — 70 — 45 — 70 — 45 50 70 75 mA mA ZZ = VCCQ, CLK Running All Inputs - GND + 0.2V or • VCC – 0.2V 1 — 10 — 1 — 10 — 1 2 10 20 mA mA Symbol Parameter Test Conditions ICC AC Operating Supply Current Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time • tKC min. ISB Standby Current IZZ Power-Down Mode Current Com. Ind. Com. Ind. Note: 1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to VCCQ. 2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V or • Vcc – 0.2V. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 5 pF Including jig and scope 351 Ω Figure 2 7 ISSI IS61SF6436 ® READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8.5 Min. Max. -9 Min. Max. -10 Min. Max. Symbol Parameter tKC Cycle Time 12 — 13 — 15 — ns tKH Clock High Time 4 — 4.5 — 5 — ns tKL Clock Low Time 4 — 4.5 — 5 — ns Clock Access Time — 8.5 — 9 — 10 ns Clock High to Output Invalid 2.5 — 3 — 3 — ns Clock High to Output Low-Z 0 — 0 — 0 — ns tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 2 5 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns tKQ (1) tKQX tKQLZ (1,2) Unit Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® READ CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS ADSC initiate read tSH ADSC tAVH tAVS Suspend Burst ADV tAS tAH A15-A0 RD1 RD2 tWS tWH tWS tWH RD3 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE tKQX DATAOUT High-Z 1a 2a 2b 2c tKQLZ 2d 3a tKQHZ tKQ DATAIN High-Z Single Read Flow-through Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 Burst Read Unselected 9 ISSI IS61SF6436 ® WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8.5 Min. Max. -9 Min. Max. -10 Min. Max. Symbol Parameter tKC Cycle Time 12 — 13 — 15 — ns tKH Clock High Time 4 — 4.5 — 5 — ns tKL Clock Low Time 4 — 4.5 — 5 — ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns 10 Unit Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC tAVH ADV must be inactive for ADSP Write tAVS ADV tAS A15-A0 tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BW4-BW1 WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b Burst Write Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 2c 2d 3a Write Unselected 11 ISSI IS61SF6436 ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8.5 Min. Max. -9 Min. Max. -10 Min. Max. Symbol Parameter tKC Cycle Time 12 — 13 — 15 — ns tKH Clock High Time 4 — 4.5 — 5 — ns tKL Clock Low Time 4 — 4.5 — 5 — ns Clock Access Time — 8.5 — 9 — 10 ns Clock High to Output Invalid 2.5 — 3 — 3 — ns Clock High to Output Low-Z 0 — 0 — 0 — ns tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 2 6 ns tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — ns Output Disable to Output High-Z 2 5 2 5 2 6 ns tKQ (1) tKQX tKQLZ (1,2) tOEHZ (1,2) Unit tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS A15-A0 tAH RD1 RD2 WR1 tWS tWH tWS tWH RD3 GW BWE tWS tWH WR1 BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQX tOEQX DATAOUT High-Z 2c 2d tKQHZ tKQHZ High-Z 1a tDS Single Read Flow-through tDH Single Write Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 2b tKQX tKQ DATAIN 2a 1a tKQLZ Burst Read Unselected 13 ISSI IS61SF6436 ® SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8.5 Min. Max. -9 Min. Max. -10 Min. Max. Symbol Parameter tKC Cycle Time 12 — 13 — 15 — ns tKH Clock High Time 4 — 4.5 — 5 — ns tKL Clock Low Time 4 — 4.5 — 5 — ns Clock Access Time — 8.5 — 9 — 10 ns Clock High to Output Invalid 2.5 — 3 — 3 — ns Clock High to Output Low-Z 0 — 0 — 0 — ns tKQHZ(3,4) Clock High to Output High-Z 2 5 2 5 2 6 ns tOEQ tKQ (3) tKQX tKQLZ (3,4) Unit Output Enable to Output Valid — 5 — 5 — 5 ns (3) Output Disable to Output Invalid 0 — 0 — 0 — ns (3,4) Output Enable to Output Low-Z 0 — 0 — 0 — ns tOEHZ(3,4) Output Disable to Output High-Z 2 5 2 5 2 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns tOEQX tOELZ (1) tZZS ZZ Standby 2 — 2 — 2 — cyc tZZREC ZZ Recovery(2) 2 — 2 — 2 — cyc Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 ISSI IS61SF6436 ® SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A15-A0 RD2 RD1 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE CE2 CE2 tOEHZ tOEQ OE tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 Snooze with Data Retention Read 15 ISSI IS61SF6436 ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part Number Package 8.5 8.5 IS61SF6436-8.5TQ IS61SF6436-8.5PQ TQFP PQFP 9 9 IS61SF6436-9TQ IS61SF6436-9PQ TQFP PQFP 10 10 IS61SF6436-10TQ IS61SF6436-10PQ TQFP PQFP Industrial Range: –40°C to +85°C Speed (ns) Order Part Number Package 10 10 IS61SF6436-10TQI IS61SF6436-10PQI TQFP PQFP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01