ISSI ® IS61LV6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – -100 MHz; 6 ns-83 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power supply • 2.5V VDDQ (I/O supply) • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VDDQ to alter their power-up state JANUARY 2004 DESCRIPTION The ISSI IS61LV6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/ O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/ O56, BW8 controls I/O57-I/O64, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LV6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VDDQ (or no connect) on MODE pin selects INTERLEAVED Burst. Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 1 ISSI IS61LV6464 ® BLOCK DIAGRAM MODE CLK Q0 CLK A0' A0 BINARY COUNTER ADV ADSC ADSP A15-A0 Q1 CE A1' A1 64K x 64 MEMORY ARRAY CLR 16 D Q 14 16 ADDRESS REGISTER CE CLK 64 GW BWE BW8 D 64 Q DQ57-DQ64 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE CE2 8 CE2 D CE3 ENABLE REGISTER CE3 Q INPUT REGISTERS CLK 64 OUTPUT REGISTERS CLK DATA[64:1] OE CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® PIN CONFIGURATION 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VDDQ CE3 CE2 CE3 CE2 GND VDD CE BW8 BW7 BW6 BW5 OE CLK BWE GW BW4 BW3 GND VDD BW2 BW1 ADSC ADSP ADV GNDQ 128-Pin TQFP/PQFP 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 GNDQ VDDQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GNDQ VDDQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 GNDQ GNDQ NC MODE A15 A14 A13 VDD GND A12 A11 A10 A9 A8 NC A7 A6 A5 A4 A3 VDD GND A2 A1 A0 ZZ VDDQ VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GNDQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ GNDQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ GNDQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 PIN DESCRIPTIONS A0-A15 Address Inputs DQ1-DQ64 Data Input/Output CLK Clock ZZ Sleep Mode ADSP Processor Address Status MODE Burst Sequence Mode ADSC Controller Address Status VDD +3.3V Power Supply ADV Burst Address Advance GND Ground BW1-BW8 Synchronous Byte Write Enable VDDQ BWE Byte Write Enable Isolated Output Buffer Supply: +2.5V GW Global Write Enable NC No Connect CE, CE2, CE2, CE3, CE3 Synchronous Chip Enable GNDQ Isolated Output Buffer Ground OE Output Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 3 ISSI IS61LV6464 ® TRUTH TABLE OPERATION ADDRESS USED CE3 CE2 CE3 CE2 CE ADSP ADSC ADV WRITE OE CLK X X X X H X L X X X L-H High-Z I/O Deselected, Power-down None Deselected, Power-down None L X X X L L X X X X L-H High-Z Deselected, Power-down None X L X X L L X X X X L-H High-Z Deselected, Power-down None X X H X L L X X X X L-H High-Z Deselected, Power-down None X X X H L L X X X X L-H High-Z Deselected, Power-down None L X X X L H L X X X L-H High-Z Deselected, Power-down None X L X X L H L X X X L-H High-Z Deselected, Power-down None X X H X L H L X X X L-H High-Z Deselected, Power-down None X X X H L H L X X X L-H High-Z Read Cycle, Begin Burst External H H L L L L X X X L L-H Dout Read Cycle, Begin Burst External H H L L L L X X X H L-H High-Z Write Cycle, Begin Burst External H H L L L H L X L X L-H Din Read Cycle, Begin Burst External H H L L L H L X H L L-H Dout Read Cycle, Begin Burst External H H L L L H L X H H L-H High-Z Next X X X X X H H L H L L-H Dout Read Cycle, Continue Burst Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z Read Cycle, Continue Burst Next X X X X H X H L H L L-H Dout Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din Read Cycle, Suspend Burst Current X X X X X H H H H L L-H Dout Read Cycle, Suspend Burst Current X X X X X H H H H H L-H High-Z Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout Read Cycle, Suspend Burst Current X X X X H X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® TRUTH TABLE ZZ OE I/O STATUS Pipelined Read Pipelined Read Write Write L L L L L H L H Dout High-Z High-Z Din Deselect L X High-Z Sleep H X High-Z Operation WRITE TRUTH TABLE GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 Read H H X X X X X X X X Read H L H H H H H H H H Write all bytes H L L L L L L L L L Write all bytes L X X X X X X X X X Write Byte 1 H L H H H H H H H L Write Byte 2 H L H H H H H H L H Write Byte 3 H L H H H H H L H H Write Byte 4 H L H H H H L H H H Write Byte 5 H L H H H L H H H H Write Byte 6 H L H H L H H H H H Write Byte 7 H L H L H H H H H H Write Byte 8 H L L H H H H H H H Operation Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 BW1 5 ISSI IS61LV6464 ® INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol PD IOUT VIN, VOUT VIN Parameter Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs VDD Voltage on VDD Supply Relative to GND Value 1.0 100 –0.5 to VDDQ + 0.3 –0.5 to 5.5 Unit W mA V V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C VDD 3.3V +10%, –5% VDDQ 2.375V min., 3.465V max. –40°C to +85°C 3.3V +10%, –5% 2.375V min., 3.465V max. Industrial DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –1.0 mA 2.0 — V VOL Output LOW Voltage IOL = 1 mA — 0.4 V VIH Input HIGH Voltage 1.7 VDDQ + 0.3 V VIL Input LOW Voltage –0.3 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VDDQ(2) Com. Ind. –2 –10 2 10 µA ILO Output Leakage Current GND ≤ VOUT ≤ VDDQ, OE = VIH Com. Ind. –2 –10 2 10 µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) -100 Typ. Max. -6 Typ. Max. Unit Com. Ind. 210 250 — — 190 200 200 220 mA mA Com. Ind. 45 — 70 — 45 50 70 75 mA mA Standby Current CMOS Inputs Device Deselected, Com. VDD = Max., Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V CLK Cycle Time ≥ tKC min. 2 — 5 — 2 5 5 10 mA mA Power-Down Mode Current ZZ = VDDQ, CLK Running All Inputs ≤ GND + 0.2V or ≥ VDD – 0.2V 1 — 5 — 1 2 5 15 mA mA Symbol Parameter Test Conditions ICC AC Operating Supply Current Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time ≥ tKC min. ISB1 Standby Current TTL Inputs Device Deselected, VDD = Max., All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min. ISB2 IZZ Com. Ind. Note: 1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to VDDQ. 2. The MODE pin should be tied to VDD or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ VDD – 0.2V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 7 ISSI IS61LV6464 ® CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 5 pF VOUT = 0V 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level for Input Pins Input Pulse Level for I/O Pins Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 0V to 2.5V 1.5 ns 1.25V See Figures 1 and 2 AC TEST LOADS 317 Ω 2.5V ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 1.25V Figure 1 8 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -100 Min. Max. Symbol Parameter tKC Cycle Time 10 tKH Clock High Time tKL -6 Min. Max. Unit — 12 — ns 4 — 4.5 — ns Clock Low Time 4 — 4.5 — ns Clock Access Time — 5 — 6 ns Clock High to Output Invalid 2.5 — 2.5 — ns tKQLZ Clock High to Output Low-Z 0 — 0 — ns tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 ns tOEQ Output Enable to Output Valid — 5 — 5 ns Output Disable to Output Invalid 0 — 0 — ns tOELZ Output Enable to Output Low-Z 0 — 0 — ns tOEHZ(1,2) Output Disable to Output High-Z 2 5 2 5 ns tAS Address Setup Time 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns tKQ tKQX (1) (1,2) (1) tOEQX (1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 9 ISSI IS61LV6464 ® READ CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS ADSC initiate read tSH ADSC tAVH tAVS Suspend Burst ADV tAS A15-A0 tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BW8-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2, CE3 CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC CE2, CE3 CE2, CE3 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read 10 Burst Read Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -100 Min. Max. -6 Min. Max. Symbol Parameter tKC Cycle Time 10 — 12 — ns tKH Clock High Time 4 — 4.5 — ns tKL Clock Low Time 4 — 4.5 — ns tAS Address Setup Time 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — ns tDS Data In Setup Time 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 Unit 11 ISSI IS61LV6464 ® WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC tAVH ADV must be inactive for ADSP Write tAVS ADV tAS A15-A0 tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE BW8-BW1 WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC Unselected with CE2, CE3 CE2, CE3 CE2, CE3 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 12 tDH 1a BW8-BW1 only are applied to first cycle of WR2 2a 2b Burst Write 2c 2d 3a Write Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -100 Min. Max. Symbol Parameter tKC Cycle Time 10 tKH Clock High Time tKL -6 Min. Max. Unit — 12 — ns 4 — 4.5 — ns Clock Low Time 4 — 4.5 — ns Clock Access Time — 5 — 6 ns Clock High to Output Invalid 2.5 — 2.5 — ns tKQLZ Clock High to Output Low-Z 0 — 0 — ns tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 ns tOEQ Output Enable to Output Valid — 5 — 5 ns Output Disable to Output Invalid 0 — 0 — ns tOELZ Output Enable to Output Low-Z 0 — 0 — ns tOEHZ(1,2) Output Disable to Output High-Z 2 5 2 5 ns tAS Address Setup Time 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tKQ tKQX (1) (1,2) (1) tOEQX (1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 13 ISSI IS61LV6464 ® READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS A15-A0 tAH RD1 RD2 WR1 tWS tWH tWS tWH RD3 GW BWE tWS tWH WR1 BW8-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC CE2, CE3 Unselected with CE2, CE3 CE2, CE3 tOEHZ tOEQ OE DATAOUT High-Z 2a 1a tKQLZ tKQ DATAIN tKQX tOEQX tOELZ 2c 2d tKQHZ tKQX tKQHZ High-Z 1a tDS Single Read 14 2b tDH Single Write Burst Read Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -100 Min. Max. -6 Min. Max. Symbol Parameter tKC Cycle Time 10 — 12 — ns tKH Clock High Time 4 — 4.5 — ns tKL Clock Low Time 4 — 4.5 — ns Clock Access Time — 5 — 6 ns Clock High to Output Invalid 2.5 — 2.5 — ns tKQLZ Clock High to Output Low-Z 0 — 0 — ns tKQHZ(3,4) Clock High to Output High-Z 2 5 2 5 ns tOEQ Output Enable to Output Valid — 5 — 5 ns Output Disable to Output Invalid 0 — 0 — ns tOELZ Output Enable to Output Low-Z 0 — 0 — ns tOEHZ(3,4) Output Disable to Output High-Z 2 5 2 5 ns tAS Address Setup Time 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns 2 — 2 — cyc 2 — 2 — cyc tKQ tKQX (3) (3,4) (3) tOEQX (3,4) (1) tZZS ZZ Standby tZZREC ZZ Recovery(2) Unit Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 15 ISSI IS61LV6464 ® SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A15-A0 RD2 RD1 GW BWE BW8-BW1 tCES tCEH tCES tCEH tCES tCEH CE CE2, CE3 CE2, CE3 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read 16 Snooze with Data Retention Read Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 ISSI IS61LV6464 ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part Number Package 100 IS61LV6464-100TQ TQFP 83 83 IS61LV6464-6TQ IS61LV6464-6PQ TQFP PQFP Industrial Range: –40°C to +85°C Speed (ns) Order Part Number Package 83 IS61LV6464-6TQI TQFP Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 17 ISSI PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. ® ISSI PACKAGING INFORMATION PQFP (Plastic Quad Flat Pack Package) Package Code: PQ D D1 E E1 N 1 L1 L C e SEATING PLANE A2 A b A1 Plastic Quad Flat Pack (PQ) Inches Millimeters Min Max Min Max Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — — — — A1 0.25 — 0.010 — A2 2.57 2.97 0.101 0.117 b 0.25 0.375 0.010 0.015 C 0.17 0.23 0.007 0.009 D 23.00 23.40 0.905 0.921 D1 19.90 20.10 0.783 0.791 E 17.00 17.40 0.669 0.685 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.65 0.95 0.025 0.037 L1 1.60 Nom. 0.063 Nom. Integrated Silicon Solution, Inc. PK13197PQ Rev. D 09/29/97 Inches Min Max 128 — 3.40 0.15 0.35 2.55 3.05 0.17 0.27 0.10 0.23 23.00 23.40 19.90 20.10 17.00 17.40 13.90 14.10 0.50 BSC 0.65 0.95 1.60 Nom. — 0.134 0.008 0.014 0.100 0.120 0.007 0.011 0.004 0.009 0.906 0.921 0.783 0.791 0.669 0.685 0.547 0.555 0.020 BSC 0.026 0.037 0.063 Nom. Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2.. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. ®