LTC1164 Low Power, Low Noise, Quad Universal Filter Building Block U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Power 4 Filters in a 0.3" Wide Package 1/2 the Noise of the LTC1059, 60, 61 Devices Wide Output Swing Clock-to-Center Frequency Ratios of 50:1 and 100:1 Operates from ±2.37V to ±8V Power Supplies Customized Version with Internal Resistors Available Ratio of 50:1 and 100:1 Simultaneously Available U APPLICATIO S ■ ■ ■ ■ ■ Antialiasing Filters Telecom Filters Spectral Analysis Loop Filters For Fixed Lowpass Filter Requirements use the LTC1164-XX Series The LTC®1164 consists of four low power, low noise 2nd order switched capacitor filter building blocks. Each building block typically consumes 850µA supply current. Low power is achieved without sacrificing noise and distortion. Each building block, together with 3 to 5 resistors, can provide 2nd order functions like lowpass, highpass, bandpass, and notch. The center frequency of each 2nd order section can be tuned with an external clock, or a clock and resistor ratio. For Q < 5, the center frequency range is from 0.1Hz to 20kHz. Up to 8th order filters can be realized by cascading all four 2nd order sections. Any classical filter realization (such as Butterworth, Cauer, Bessel, and Chebyshev) can be formed. A customized monolithic version of the LTC1164 including internal thin film resistors can be obtained. Consult LTC Marketing for details. The LTC1164 is manufactured using Linear Technology’s enhanced LTCMOS™ silicon gate process. , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Dual 5th Order Linear Phase Filter with Stopband Notch, fCLK = 500kHz Dual 5th Order Linear Phase Filter with Stopband Notch 549k 10.00 63.4k VIN1 102k 133k 174k 1 24 2 23 3 22 4 21 0.0 –10.00 –20.00 49.9k 36.5k GAIN (dB) 210k 78.7k 8.66k 6 V+ 0.1µF 174k 102k VIN2 210k LTC1164 18 8 17 9 16 133k 10 15 11 14 12 13 C1 = 0.0033µF C2 = 0.0068µF fCLK = 500kHz WIDEBAND NOISE = 50µVRMS TOTAL SUPPLY CURRENT = 3mA ALL RESISTORS ARE 1% METAL FILM –60.00 V– –80.00 0.1µF fCLK –40.00 –70.00 19 7 –90.00 1k 8.66k VOUT2 C2 78.7k VOUT1 –50.00 VOUT1 C1 20 5 VOUT2 –30.00 36.5k 49.9k 63.4k 549k LTC1164 • TA01 10k FREQUENCY (Hz) 100k LTC1164 • TA02 SUPPLY VOLTAGE VIN TOTAL HARMONIC DISTORTION SIGNAL/NOISE ±2.5 ±5.0 ±7.5 1VRMS 2VRMS 4VRMS 0.015% (–76dB) 0.025% (–72dB) 0.04% (–68dB) 86dB 92dB 98dB 1164fa 1 LTC1164 W W W AXI U U ABSOLUTE RATI GS (Note 1) Total Supply Voltage (V + to V –) ............................ 16.5V Power Dissipation .............................................. 500mW Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C Operating Temperature Range LTC1164AM, LTC1164M (OBSOLETE) ..... –55°C to 125°C LTC1164AC, LTC1164C .......................–40°C to 85°C U U W PACKAGE/ORDER I FOR ATIO TOP VIEW INV B 1 24 INV C HPB/NB 2 23 HPC/NC BPB 3 22 BPC LPB 4 21 LPC SB 5 20 SC AGND 6 19 V – V+ 7 18 CLK SA 8 17 50/100 LPA 9 16 LPD ORDER PART NUMBER LTC1164ACN LTC1164CN ORDER PART NUMBER TOP VIEW INV B 1 24 INV C HPB/NB 2 23 HPC/NC BPB 3 22 BPC LPB 4 21 LPC SB 5 20 SC AGND 6 19 V – 18 CLK BPA 10 15 BPD V+ HPA 11 14 HPD SA 8 INV A 12 13 INV D LPA 9 16 LPD N PACKAGE 24-LEAD PDIP TJMAX = 110°C, θJA = 65°C/W J PACKAGE 24-LEAD CERDIP TJMAX = 150°C, θJA = 100°C/W OBSOLETE PACKAGE Consider the N24 Package as an Alternate Source LTC1164AMJ LTC1164MJ LTC1164ACJ LTC1164CJ 7 LTC1164CSW LTC1164ACSW 17 50/100 BPA 10 15 BPD HPA 11 14 HPD INV A 12 13 INV D SW PACKAGE 24-LEAD PLASTIC SO TJMAX = 110°C, θJA = 75°C/W LTC221/222 • POI01 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Internal Op Amps) VS = ±5V, RL = 5kΩ unless otherwise noted. PARAMETER CONDITIONS MIN Supply Voltage Range Voltage Swings TYP ±2.37 VS = ±2.5V VS = ±5.0V VS = ±7.5V ● ±3.8 MAX ±8 ±1.6 ±4.2 ±6.1 UNITS V V V V Output Short Circuit Current (Source/Sink) VS = ±5.0V 1 mA DC Open Loop Gain VS = ±5.0V 80 dB GBW Product VS = ±5.0V 2 MHz Slew Rate VS = ±5.0V 1.6 V/µs 1164fa 2 LTC1164 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Complete Filter) VS = ±5V, TTL Clock Input Level, unless otherwise specified. PARAMETER CONDITIONS MIN Center Frequency Range MAX 0.1 to 20k Input Frequency Range (Note 2) 50:1 100:1 Clock-to-Center Frequency Ratio, fCLK/fO LTC1164A Sides A, B, C: Mode 1, R1 = R3 = 50k, R2 = 5k, Side D: Mode 3, R1 = R3 = 50k, R2 = R4 = 5k fO = 5kHz, Q = 10 50:1, fCLK = 250kHz LTC1164 50:1, fCLK = 250kHz LTC1164A LTC1164 UNITS Hz < fCLK < fCLK/2 Hz Hz ● 50 ±0.5 % ● 50 ±0.9 % 100:1, fCLK = 500kHz ● 100 ±0.5 % 100:1, fCLK = 500kHz ● 100 ±0.9 % LTC1164A Sides A, B, C, Mode 1, fO = 5kHz, Q = 10 Side D Mode 3, fO = 5kHz, Q = 10 50:1, fCLK = 250kHz ● 0.5 % LTC1164 50:1, fCLK = 250kHz ● 1.0 % Sides A, B, C, Mode 1, fO = 5kHz, Q = 10 50:1, fCLK = 250kHz ● ±2 ±5 % 100:1, fCLK = 500kHz ● ±2 ±5 % Side D Mode 3, fO = 5kHz, Q = 10 50:1, fCLK = 250kHz ● ±3 ±6 % 100:1, fCLK = 500kHz ● ±6 ±12 % Clock-to-Center Frequency Ratio, Side to Side Matching Q Accuracy TYP fO Temperature Coefficient fCLK ≤ 500kHz ±1 ppm/°C Q Temperature Coefficient fCLK ≤ 250kHz ±5 ppm/°C Maximum Clock Frequency Mode 1, Q < 2.5 VS ≥ ±7.0V, 50:1 or 100:1 1.5 MHz Mode 3, Q < 5 VS ≥ ±5V, 50:1 or 100:1 1.0 MHz Mode 3, Q < 5 VS = ±2.5V, 50:1 or 100:1 500 kHz fCLK Feedthrough fCLK ≤ 500kHz, VS = ±5V DC Offset Voltages (See Figure 1 and Table 1) VOS1 VOS2 VOS3 Power Supply Current 200 µVRMS ● ● ● 2 3 3 VS = ±5V, Temp ≥ 25°C VS = ±5V ● 3.6 5.6 5 8 mA mA VS = ±7.5V, Temp ≥ 25°C VS = ±7.5V ● 6 9 8 11 mA mA VS = ±2.5V 20 45 45 4 mV mV mV mA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note: 2: Guaranteed by design. Not tested. 1164fa 3 LTC1164 ELECTRICAL CHARACTERISTICS (12, 13, 24) 1 VOS1 + – – + (11, 14, 23) (10, 15, 22) (9, 16, 21) 2 3 4 VOS2 + + Σ – – + – 5 (8, 20) VOS3 – – + + 6 LTC1164 • BD01 Figure 1. Equivalent Input Offsets of 1/4 LTC1164 Filter Building Block Table 1. Output DC Offsets One 2nd Order Section VOSN PIN 2, 11, 14, 23 MODE VOSBP PINS 3, 10, 15, 22 VOSLP PINS 4, 9, 16, 21 1 VOS1[(1/Q) + 1 + ||HOLP||] – V0S3/Q VOS3 VOSN – VOS2 1b VOS1[(1/Q) + 1 + R2/R1] – V0S3/Q VOS3 ~ (VOSN – VOS2) (1 + R5/R6) 2 [VOS1(1 + R2/R1 + R2/R3 + R2/R4) – V0S3(R2/R3)] • [R4/(R2 + R4)] + V0S2[R2/(R2 + R4)] VOS3 VOSN – VOS2 3 V0S2 VOS3 [ VOS1 1 + –VOS3 R4 R1 + R4 R2 + R4 R3 R4 ] – V ( R2 ) OS2 R4 ( R3 ) 1164fa 4 LTC1164 W BLOCK DIAGRA HPA/NA(11) BPA(10) LPA(9) V +(7) INV A(12) AGND(6) – + Σ + +∫ 50/100(17) +∫ – CLK(18) HPB/NB(2) BPB(3) SA(8) LPB(4) V –(19) INV B(1) – + + Σ +∫ – HPC/NC(23) SB(5) INV C(24) – + + Σ BPC(22) +∫ LPC(21) +∫ – HPD(14) INV D(13) +∫ BPD(15) SC(20) LPD(16) – +∫ + +∫ BY TYING PIN 17 TO V + ALL SECTIONS OPERATE WITH (fCLK/fO) = (50:1) BY TYING PIN 17 TO V – ALL SECTIONS OPERATE WITH (fCLK/fO) = (100:1) BY TYING PIN 17 TO AGND SECTIONS A & D OPERATE WITH (fCLK/fO) = (100:1) AND SECTIONS B & C OPERATE AT (50:1) LTC1164 • BD02 1164fa 5 LTC1164 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C Q = 2.5 5 Q = 2.5 0 20 VS = ±2.5V VS = ±7.5V 15 Q=7 Q = 2.5 10 5 0 –5 fO ERROR (%) VS = ±7.5V Q=7 Q = 7 Q = 2.5 Q=7 1.5 1 VS = ±7.5V Q = 2.5 0.5 Q=7 Q=7 1.5 VS = ±2.5V Q = 2.5 1 0.5 VS = ±7.5V Q=7 Q = 2.5 –11 10 5 –9 Q=7 VS = ±7.5V Q = 2.5 0 fO ERROR (%) –5 1 Q = 7 VS = ±7.5V Q = 2.5 0 0 10 15 20 25 5 CENTER FREQUENCY, fO (kHz) 50:1 –8 –7 –6 –5 VS = ±7.5V 5 10 15 20 25 30 35 40 45 50 55 60 CENTER FREQUENCY, fO (kHz) LTC1164 • TPC03 –1 160 ±7.5V ±5.0V ±2.5V 140 120 100 80 60 20 0 0 30 ONE SECOND ORDER SECTION 220 LP OR BP OUTPUT 200 MODE 1, 2, OR 3 100:1 OR 50:1 180 40 1 2 3 4 5 6 7 IDEAL Q 8 9 10 11 0 0 2 4 6 8 10 12 14 16 18 20 22 24 Q LTC1164 • TPC05 Total Harmonic Distortion vs Output Amplitude LTC1164 • TPC06 Power Supply Current vs Voltage 1 VS = ±2.5V 8.000 VS = ±5V VS = ±7.5V 0.010 fIN = 1kHz fCLK = 250kHz 50:1 R1 = R2 = R3 = R4 = 25k 0.001 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 AMPLITUDE (VRMS) LTC1164 • TPC07 POWER SUPPLY CURRENT (mA) THD + N (%) Q = 2.5 0 50:1 fCLK = 200kHz 100:1 fCLK = 400kHz LTC1164 • TPC04 0.1 0.5 Q = 2.5 Q=7 Wideband Noise vs Q – 3 100:1 –2 Q = 2.5 Q=7 0.5 Q=7 240 –4 2 1.5 VS = ±2.5V VS = ±2.5V 1 30 WIDEBAND NOISE (µVRMS) 15 TA = 25°C VS = ±5V –10 Q ERROR (%) Q ERROR (%) 20 2 1.5 Mode 3 Q Error vs Ideal Q TA = 25°C VS = ±2.5V Q=7 Q = 2.5 Q = 2.5 LTC1164 • TPC02 Mode 3, (fCLK/fO) = 100:1 25 VS = ±7.5V 0 25 10 15 20 5 CENTER FREQUENCY, fO (kHz) 0 LTC1164 • TPC01 30 5 Q=7 –5 2 0 0 5 10 15 20 25 30 35 40 45 50 55 60 CENTER FREQUENCY, fO (kHz) V = ±2.5V 20 S Q=7 15 Q = 2.5 10 0 Q = 2.5 –5 VS = ±2.5V 2 TA = 25°C 25 fO ERROR (%) 10 Q ERROR (%) Q=7 15 Mode 3, (fCLK/fO) = 50:1 30 TA = 25°C 25 VS = ±2.5V 20 fO ERROR (%) Q ERROR (%) 25 0 Mode 1, (fCLK/fO) = 100:1 30 Q ERROR (%) Mode 1, (fCLK/fO) = 50:1 30 fCLK ≤ 500kHz 6.400 –55°C 4.800 3.200 25°C 125°C 1.600 0.000 ±2.500 ±3.500 ±4.500 ±5.500 ±6.500 ±7.500 ±VSUPPLY (V) LTC1164 • TPC08 1164fa 6 LTC1164 U U U PI FU CTIO S Power Supplies (Pins 7,19) AGND (PIN 6) They should be bypassed with 0.1µF ceramic disc. Low noise, non-switching, power supplies are recommended. The device operates with a single 5V supply and with dual supplies. The absolute maximum operating power supply voltage is ±8.25V. Supply reversal is not allowed and can cause latch up. When using dual supplies, loads between the positive and negative supply (even light loads) can cause momentary supply reversal during power-up. A clamp diode from each supply to ground will prevent reversal and latch problems. When the LTC1164 operates with dual supplies, Pin 6 should be tied to system ground. When the LTC1164 operates with a single positive supply, the analog ground pin should be tied to 1/2 supply and it should be bypassed with a 4.7µF solid tantalum in parallel with a 0.1µF ceramic disc, Figure 2. The positive input of all the internal op amps, as well as the common reference of all the internal switches, are internally tied to the analog ground pin. Because of this, a very “clean” ground is recommended. 50/100 (Pin 17) Clock (Pin 18) By tying Pin 17 to V+, all filter sections operate with a clockto-center frequency ratio internally set at 50:1. When Pin 17 is at mid-supplies, sections B and C operate with (fCLK/ fO) = 50:1 and sections A and D operate at (100:1). When Pin 17 is shorted to the negative supply pin, all filter sections operate with (fCLK/fO) = 100:1. For ±5V supplies the logic threshold level is 1.8V. For ±8V and 0 to 5V supplies the logic threshold level is 2.8V. The logic threshold levels vary ±100mV over the full military temperature range. The recommended duty cycle of the input clock is 50%, although for clock frequencies below 500kHz the clock “on” time can be as low as 200ns. The maximum clock frequency for single 5V supply and Q values <5 is 500kHz and for ±5V supplies and above is 1MHz. The clock input can be applied before power is turned on as long as there is no chance the clock signal will go below the V – supply. V+ 1 24 2 23 3 22 4 7.5k V+/2 + 0.1µF 4.7µF 6 7 LT1004* 0.1µF ANALOG GROUND PLANE 21 LTC1164 5 20 AGND V+ 8 V– CLK 50/100 19 CLOCK INPUT V + = 15V, TRIP VOLTAGE = 7V V + = 10V, TRIP VOLTAGE = 6.4V V + = 5V, TRIP VOLTAGE = 3V 18 17 9 16 10 15 11 14 12 13 NOTE: PIN 5, 8, 20, IF NOT USED, SHOULD BE CONNECTED TO PIN 6. *LT1004 CAN BE REPLACED WITH A 7.5k RESISTOR FOR V+ >6.5V TO DIGITAL GROUND LTC1164 • PD01 Figure 2. Single Supply Operation 1164fa 7 LTC1164 U W U U APPLICATIO S I FOR ATIO ANALOG CONSIDERATIONS 1. Grounding and Bypassing The LTC1164 should be used with separated analog and digital ground planes and single point grounding techniques. Pin 6 (AGND) should be tied directly to the analog ground plane. Pin 7 (V +) should be bypassed to the ground plane with a 0.1µF ceramic disk with leads as short as possible. Pin 19 (V –) should be bypassed with a 0.1µF ceramic disk. For single supply applications, V – can be tied to the analog ground plane. For good noise performance, V + and V – must be free of noise and ripple. Figure 3 shows an example of an ideal ground plane design for a two sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this as possible. Proto boards are not recommended. 2. Buffering the Filter Output When driving coaxial cables and 1x scope probes, the filter output should be buffered. This is important especially when high Qs are used to design a specific filter. Inadequate buffering may cause errors in noise, distortion, Q, and gain measurements. When 10x probes are used, buffering is usually not required. A buffer is recommended especially when THD tests are performed. As shown in Figure 4, the buffer should be adequately bypassed to minimize clock feedthrough. All analog inputs should be referenced directly to the single point ground. The clock inputs should be shielded from and/or routed away from the analog circuitry and a separate digital ground plane used. 7.5V 0.1µF CERAMIC DISK ANALOG GROUND PLANE 1 • PIN 1 DENT 24 2 23 3 22 4 21 5 20 –7.5V 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VIN FOR BEST HIGH FREQUENCY RESPONSE PLACE RESISTORS PARALLEL TO DOUBLE SIDED COPPER CLAD BOARD AND LAY FLAT (4 RESISTORS SHOWN HERE TYPICAL) 0.1µF CERAMIC DISK CLOCK DIGITAL GROUND PLANE (SINGLE POINT GROUND) NOTE: CONNECT ANALOG AND DIGITAL GROUND PLANES AT A SINGLE POINT AT THE BOARD EDGE LTC1164 • AI01 Figure 3. Example Ground Plane Breadboard Technique for LTC1164 1164fa 8 LTC1164 U W U U APPLICATIO S I FOR ATIO 3. Offset Nulling 4. Noise Lowpass filters may have too much DC offset for some users. A servo circuit may be used to actively null the offsets of the LTC1164 or any LTC switched capacitor filter. The circuit shown in Figure 5 will null offsets to better than 300µV. This circuit takes seconds to settle because of the integrator pole frequency. All the noise performance mentioned excludes the clock feedthrough. Noise measurements will degrade if the already described grounding, bypassing, and buffering techniques are not practiced. The Wideband Noise vs Q curve shown in the Typical Performance Characteristics Section is a very good representation of the noise performance of this device. SEPARATE V + POWER SUPPLY TRACE FOR BUFFER R12 1µF TA R11 FROM FILTER OUTPUT 0.1µF VIN R22 R21 LTC1164 R32 R3 1k – R1 1M 4 TO FILTER FIRST SUMMING NODE V + TRACE FOR FILTER + 19 POSITIVE SUPPLY 7 0.1µF 7 + R3 100k – 0.1µF NEGATIVE SUPPLY 1µF TA C1 0.1µF LT1012 R2 1M C2 0.1µF 0.1µF C1 = C2 = LOW LEAKAGE FILM (I.E. POLYPROPYLENE) R1 = R2 = METAL FILM 1% LTC1164 • AI03 LTC1164 • AI02 Figure 4. Buffering the Output of a 4th Order Bandpass Realization Figure 5. Servo Amplifier U ODES OF OPERATIO W PRIMARY MODES R3 Mode 1 In Mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at 50:1 or 100:1. Figure 6 illustrates Mode 1 providing 2nd order notch, lowpass, and bandpass outputs. Mode 1 can be used to make high order Butterworth Iowpass filters; it can also be used to make low Q notches and for cascading 2nd order bandpass functions tuned at the same center frequency with unity gain. Mode 1 is faster than Mode 3. Note that Mode 1 can only be implemented with 3 of the 4 LTC1164 sections because section D has no externally available summing node. Section D, however, can be internally connected in Mode 1 upon special request. R2 N VIN R1 – S + BP LP – Σ ∫ ∫ + 1/4 LTC1164 AGND fo = fCLK ;f =f ;H = – R2 ; HOBP = – R3 ; HON1 = – R2 Q = R3 100(50) n O OLP R1 R1 R1 R2 LTC1164 • MOO01 Figure 6. Mode 1: 2nd Order Filter Providing Notch, Bandpass, Lowpass 1164fa 9 LTC1164 U ODES OF OPERATIO W Mode 3 SECONDARY MODES Mode 3 is the second of the primary modes. In Mode 3, the ratio of the external clock frequency to the center frequency of each 2nd order section can be adjusted above or below 50:1 or 100:1. Side D of the LTC1164 can only be connected in Mode 3. Figure 7 illustrates Mode 3, the classical state variable configuration, providing highpass, bandpass, and lowpass 2nd order filter functions. Mode 3 is slower than Mode 1. Mode 3 can be used to make high order all-pole bandpass, lowpass, highpass and notch filters. Mode 1b When the internal clock-to-center frequency ratio is set at 50:1, the design equations for Q and bandpass gain are different from the 100:1 case. This was done to provide speed without penalizing the noise performance. CC R4 R3 R2 HP VIN R1 – S + BP LP – Σ ∫ Mode 1b is derived from Mode 1. In Mode 1b, Figure 8, two additional resistors R5 and R6, are added to alternate the amount of voltage feedback from the lowpass output into the input of the SA (or SB or SC) switched capacitor summer. This allows the filter clock-to-center frequency ratio to be adjusted beyond 50:1 or 100:1. Mode 1b maintains the speed advantages of Mode 1. Mode 2 Mode 2 is a combination of Mode 1 and Mode 3, as shown in Figure 9. With Mode 2, the clock-to-center frequency ratio, fCLK/fO, is always less than 50:1 or 100:1. The advantage of Mode 2 is that it provides less sensitivity to resistor tolerances than does Mode 3. As in Mode 1, Mode 2 has a notch output which depends on the clock frequency, and the notch frequency is therefore less than the center frequency, fO. When the internal clock-to-center frequency ratio is set at 50:1, the design equations for Q and bandpass gain are different from the 100:1 case. ∫ + R6 1/4 LTC1164 R3 R2 AGND N VIN MODE 3 (100:1): f fo = CLK 100 R5 R2 ; Q = R3 R4 R2 R1 – R2 ; H = – R2/R1; R4 OHP S + Σ BP LP – ∫ ∫ + HOBP = – R3/R1; HOLP = – R4/R1 MODE 3 (50:1): f fo = CLK 50 R2 ; Q = 1.005 (√R2/R4) (R2/R3) – (R2/16R4); R4 AGND R3/R1 HOLP = – R2/R1; HOBP = – = – R4/R1 ;H 1 – (R3/16R4) OLP NOTE: THE 50:1 EQUATIONS FOR MODE 3 ARE DIFFERENT FROM THE EQUATIONS FOR MODE 3 OPERATION OF THE LTC1059, LTC1060 AND LTC1061. START WITH fo, CALCULATE R2/R4, SET R4; FROM THE Q VALUE, CALCULATE R3: R3 = R2 1.005 Q R2 + R2 R4 16R4 ; THEN CALCULATE R1 TO SET THE DESIRED GAIN Figure 7. Mode 3: 2nd Order Filter Providing Highpass, Bandpass, Lowpass LTC1164 • MOO02 fo = fCLK 100(50) R6 ; f = f ; Q = R3 R5 + R6 n o R2 ( ) R6 ; R5 + R6 f – R2/R1 HON1 (f → 0) = HON2 f → CLK = – R2 ; HOLP = ; 2 R6/(R5 + R6) R1 R3 HOBP = – ; (R5//R6) < 5kΩ LTC1164 • MOO03 R1 Figure 8. Mode 1b: 2nd Order Filter Providing Notch, Bandpass, Lowpass 1164fa 10 LTC1164 U ODES OF OPERATIO W Mode 3A This is an extension of Mode 3 where the highpass and lowpass output are summed through two external resistors RH and RL to create a notch. This is shown in Figure 10. Mode 3A is more versatile than Mode 2 because the notch frequency can be higher or lower than the center frequency of the 2nd order section. The external op amp of Figure 10 is not always required. When cascading the sections of the LTC1164, the highpass and lowpass R4 outputs can be summed directly into the inverting input of the next section. The topology of Mode 3A is useful for elliptic highpass and notch filters with clock to cutoff frequency ratios higher than 100:1. This is often required to extend the allowed input signal frequency range and to avoid premature aliasing. When the internal clock-to-center frequency ratio is set at 50:1, the design equations for Q and bandpass gain are different from the 100:1 case. MODE 2 (100:1): f fo = CLK 100 fCLK ; Q = R3 1 + R2 ; fn = 50 R2 R4 MODE 2 (50:1): fo = fCLK 50 f 1 + R2 ; fn = CLK ; Q = 1.005 (√1 + R2/R4) ; HOLP = – R2/R1 R4 1 + (R2/R4) (R2/R3) – (R2/16R4) 50 R3 R2 N VIN R1 – S + Σ BP LP – ( ) R3/R1 – R2/R1 ; H (f → 0) = 1 – (R3/16R4) ON1 1 + (R2/R4) fCLK HON2 f → 2 = – R2/R1 HOBP = – ∫ ∫ –R2/R1 1 + R2 ; HOLP = 1 + (R2/R4) R4 f – R2/R1 HOBP = – R3/R1; HON1 (f → 0) = f → CLK = – R2/R1 ;H 1 + (R2/R4) ON2 2 ( + 1/4 LTC1164 ) NOTE: THE 50:1 EQUATIONS FOR MODE 2 ARE DIFFERENT FROM THE EQUATIONS FOR MODE 2 OPERATION OF THE LTC1059, LTC1060 AND LTC1061. START WITH fo, CALCULATE R2/R4, SET R4; FROM THE Q VALUE, CALCULATE R3: R3 = 1.005 Q R2 ; THEN CALCULATE R1 TO SET THE DESIRED GAIN 1 + R2 + R2 R4 16R4 LTC1164 • MOO04 Figure 9. Mode 2: 2nd Order Filter Providing Notch, Bandpass, Lowpass f MODE 3A (100:1): fo = CLK 100 CC ( R3 R2 HP VIN – + S BP LP MODE 3A (50:1): – Σ RG 1/4 LTC1164 RH RL – R2 ; f = fCLK R4 n 50 f fo = CLK 50 HOBP = – ∫ ∫ + AGND RH RL ; HOHP = – R2/R1; HOBP = –R3/R1 ( ) f R R HOLP = – R4/R1; HON1(f → 0) = G × R4 ; HON2 f → CLK = G × R2 RL R1 RH R1 2 R R R2 HON (f = fo) = Q G HOLP – G HOHP ; Q = R3 RL RH R2 R4 R4 R1 R2 ; f = fCLK R4 n 100 ) ( ) f RH ;H f → CLK = –R2/R1 RL OHP 2 R3/R1 ; H (f = 0) = – R4/R1; Q = 1.005 (√R2/R4) 1 – (R3/16R4) OLP (R2/R3) – (R2/16R4) NOTE: THE 50:1 EQUATIONS FOR MODE 3A ARE DIFFERENT FROM THE EQUATIONS FOR MODE 3A OPERATION OF THE LTC1059, LTC1060 AND LTC1061. START WITH fo, CALCULATE R2/R4, SET R4; FROM THE Q VALUE, CALCULATE R3: R3 = 1.005 NOTCH Q R2 ; THEN CALCULATE R1 TO SET R2 + R2 THE DESIRED GAIN R4 16R4 + LTC1164 • MOO05 EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1164, SIDE A, B, C, D Figure 10. Mode 3A: 2nd Order Filter Providing Highpass, Bandpass, Lowpass, Notch 1164fa 11 LTC1164 U TYPICAL APPLICATIO S 82.5k VIN 196k 1 24 75k 2 23 154k 3 22 76.8k 75k 4 21 88.7k 5 20 19 6 7 8V 0.1µF 88.7k LTC1164 18 8 17 9 16 -8V 8V 15V 0.1µF fCLK 1k 130k 10 15 154k 76.8k 11 14 76.8k 130k 12 13 154k 0.1µF + VOUT LT1056 – 90.9k 0.1µF 90.9k f f–3dB = CLK 50 -15V fCLK = 500kHz LTC1164 • AC01 Figure 11. 8th Order Lowpass Butterworth, Passband Noise 90µVRMS (Also Refer to the LTC1164-5) LTC1164 8th Order Butterworth, fCLK = 500kHz, f –3dB = 10kHz ±8V, A. 2VRMS, B. 4VRMS LTC1164 8th Order Butterworth, fCLK = 500kHz, f –3dB = 10kHz 0.1 10.00 HARMONIC DISTRIBUTION (%) 0.0 –10.00 GAIN (dB) –20.00 –30.00 –40.00 –50.00 –60.00 –70.00 B 0.010 A –80.00 –90.00 1k 10k FREQUENCY (Hz) 50k 0.001 500 1k 10k FREQUENCY (Hz) LTC1164 • AC02 LTC1164 • AC03 1164fa 12 LTC1164 U TYPICAL APPLICATIO S 78.7k 267k VIN 63.4k 1 24 40.2k 2 23 40.2k 41.2k 3 22 48.7k 60.4k 4 21 69.8k 84.5k 2.5V 20 6 19 2.5V 5V LTC1164 5V 7.5k LT1004 5 7 18 8 17 fCLK 0.1µF 0.1µF 1k 88.7k 9 16 107k 46.4k 10 15 52.3k 40.2k 11 14 102k 12 13 + LT1006 VOUT – 95.3k 215k f f–3dB = CLK 100 LTC1164 • AC04 fCLK = 500kHz Figure 12. 8th Order Lowpass Single Supply Elliptic-Bessel Transitional Filter Total Supply Current = 4mA, Passband Noise 50µVRMS LTC1164 8th Order Lowpass, Elliptic-Bessel Traditional Filter Single 5V Supply Transient Response 10.00 0.0 –10.00 GAIN (dB) –20.00 0.5V/DIV –30.00 –40.00 –50.00 100µs/DIV INPUT 1kHz, 1V SQUAREWAVE –60.00 –70.00 –80.00 –90.00 500 fCLK = 500kHz f-3dB=5kHz 1k 10k FREQUENCY (Hz) 50k LTC1164 • AC05 1164fa 13 LTC1164 U TYPICAL APPLICATIO S RH RH RL ALL RESISTORS MF 1% A B 1 24 R2 2 23 R2 R3 3 22 R3 R4 4 21 R4 A 20 6 19 7 18 8 17 R4 9 16 R4 R3 10 15 R3 R2 11 14 R2 12 13 R1 VIN C B C D 48.7k 46.4k 34.0k 31.6k 43.2k 31.6k 127k 39.2k 31.6k 40.2k 29.4k 30.1k 69.8k RI 309k 158k 210k Rh 63.4k 28.0k 27.4k RL LTC1164 5 V+ 0.1µF R1 R2 R3 R4 V– V+ 0.1µF fCLK 0.1µF V+ 1k + LT1006 VOUT – D 0.1µF V– RL LTC1164 • AC06 RH Figure 13. LTC1164 8th Order Lowpass Elliptic, fCUTOFF = 5kHz, fCLK = 250kHz, –78dB at 10kHz, Passband Noise = 110µVRMS ±5V (Also Refer to the LTC1164-6) 10.00 0.0 –10.00 GAIN (dB) –20.00 –30.00 –40.00 –50.00 –60.00 fCLK = 250kHz VS = ±7.5V fC = 5kHz, 100:1 –78dB AT 2.0 fCUTOFF –70.00 –80.00 –90.00 1k 10k 50k FREQUENCY (Hz) LTC1164 • AC07 Figure 14. LTC1164 8th Order Lowpass Elliptic, fCUTOFF = 5kHz 1164fa 14 LTC1164 U TYPICAL APPLICATIO S RH RH RL 24 2 23 R2 R3 3 22 R3 R4 4 21 R4 A C R1 R2 R3 R4 20 6 19 7 V+ 8 LTC1164 18 17 0.1µF A V+ 9 16 R4 R3 10 15 R3 R2 11 14 R2 12 13 R1 VIN –10.00 –20.00 C 0.1µF –30.00 –40.00 –50.00 –60.00 RG –70.00 –80.00 V+ –90.00 D 10k 1k 0.1µF LTC1164 • AC07 LT1006 VOUT Figure 16. LTC1164 9th Order Lowpass Elliptic, fCUTOFF = 4kHz + RH 20k FREQUENCY (Hz) – RH RL 0.0 D RG = 80.6k C = 0.001µF RL R4 C 82.5k 30.1k 28.7k 30.9k 38.3k 71.5k 301k 124k 57.6k 44.2k 28.7k 31.1k 118k V– fCLK B RL 121k 124k 40.2k 24.3k RH 75k 68.1k 30.9k 30.1k RL 5 fCLK = 400kHz VS = ±7.5V fC = 4kHz 100:1 –74dB AT 1.25 fCUTOFF ALL RESISTORS MF 1% GAIN (dB) R2 B 10.00 1 0.1µF V– LTC1164 • AC08 Figure 15. LTC1164 9th Order Lowpass Elliptic, Fixed fCUTOFF = 4kHz, fCLK = 400kHz, –74dB at 5kHz, Passband Noise = 210µVRMS ±5V U PACKAGE DESCRIPTIO J Package 24-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 1.290 (32.77) MAX 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 .025 .220 – .310 (5.588 – 7.874) (0.635) RAD TYP 1 .005 (0.127) MIN .300 BSC (7.62 BSC) .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .125 (3.175) MIN .045 – .065 (1.143 – 1.651) .014 – .026 (0.360 – 0.660) .100 (2.54) BSC J24 0801 OBSOLETE PACKAGE 1164fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1164 U PACKAGE DESCRIPTIO N Package 24-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 1.265* (32.131) MAX 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .020 (0.508) MIN .008 – .015 (0.203 – 0.381) .120 (3.048) MIN +.035 .325 –.015 ( +0.889 8.255 –0.381 .065 (1.651) TYP ) .018 ± .003 (0.457 ± 0.076) .100 (2.54) BSC NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) N24 1002 SW Package 24-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP N 24 23 22 21 .598 – .614 (15.190 – 15.600) NOTE 4 20 19 18 17 16 15 14 13 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 .093 – .104 (2.362 – 2.642) 7 8 9 10 11 12 .037 – .045 (0.940 – 1.143) 0° – 8° TYP .050 (1.270) BSC NOTE 3 .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .004 – .012 (0.102 – 0.305) .014 – .019 (0.356 – 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S24 (WIDE) 0502 1164fa 16 Linear Technology Corporation LT/TP 1202 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1991