ETC LXT6155LE

Intel® LXT6155
155 Mbps SDH/SONET/ATM Transceiver
Datasheet
The Intel® LXT6155 is a high speed fully integrated transceiver designed for 155 Mbps SDH/
SONET/ATM transmission system applications. The Intel® LXT6155 provides a LVPECL
interface for fiber optics modules, and a CMI interface for coax cable drive. These circuits are
implemented using Intel’s proven low power 3.3V CMOS analog and digital circuits. The
transmitter incorporates a parallel-to-serial converter, a frequency multiplier PLL, CMI line
encoders, and line interfaces for both coax cable and optical fiber. The receiver incorporates an
adaptive equalizer, a clock recovery PLL, Loss of Signal (LOS) detector, CMI and NRZ
decoders, a serial-to-parallel converter, and an SDH/SONET frame byte detector/aligner. At the
system interface, the Intel® LXT6155 offers both parallel 8-bit and serial differential interfaces.
The Intel® LXT6155 also operates in either Hardware stand-alone mode or Software mode.
Software mode is controlled by a serial microprocessor (µP) to program formats and operating/
test modes.
Product Features
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■
■
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Complies with:
— Bellcore SONET GR-253
— ITU-T G.703/813/958 STM1
Two line interface formats:
— Fiber LVPECL NRZ
— Coax CMI
Transmit synthesizer PLL
Receive clock recovery PLL
Adaptive CMI equalizer
Analog circuitry for transformer drive
Programmable LOS function
CMI encoder and decoder
Serial/Parallel and Parallel/Serial
conversion
Byte alignment for SDH/SONET frames
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Two modes of operation:
— Microprocessor controlled; software
mode
— Stand-alone; hardware mode
No external crystal required. A 19.44 MHz
crystal is optional
Low power consumption (less than 760
mW typical)
Operates from a single 3.3 V supply
64 pin LQFP package
Applications
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OC3/STM1 SDH/SONET Cross Connects
OC3/STM1 SDH/SONET Add/Drop Mux
OC3/STM1 Transmission Systems
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OC3/STM1 Short Haul Serial Links
OC3/STM1 ATM/WAN Transmission
Systems
OC3/STM1 ATM/WAN Access Systems
Order Number: 249612-003
August 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT6155 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
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*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0
Pin Assignments and Signal Descriptions ................................................................................. 8
2.0
Functional Description................................................................................................................ 12
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Datasheet
Transmitter.......................................................................................................................... 12
2.1.1 Transmitted Signal ................................................................................................. 13
2.1.1.1 Fiber Based G.957/GR-253 Transmission Systems .............................. 13
2.1.2 Coax Based G.703/GR-253 Transmission Systems.............................................. 13
2.1.2.1 CMI Encoding ........................................................................................ 13
2.1.3 Tx Clock Monitoring ............................................................................................... 13
Receiver.............................................................................................................................. 14
2.2.1 Analog Front End and Timing Recovery ................................................................ 14
2.2.1.1 CMI Mode ..............................................................................................14
2.2.1.2 NRZ Mode..............................................................................................14
2.2.2 Receive Frame Detect and Byte Alignment ........................................................... 15
2.2.2.1 Loss of Signal (LOS).............................................................................. 15
2.2.2.2 Coax Interface........................................................................................ 15
2.2.2.3 Fiber Interface........................................................................................ 15
Clocks ................................................................................................................................. 17
2.3.1 Parallel Mode ......................................................................................................... 17
2.3.1.1 Transmit Parallel Input Clock (TPICLK) ................................................. 17
2.3.1.2 Receive Parallel Output Clock (RPOCLK) ............................................. 17
2.3.2 Serial Mode............................................................................................................ 18
2.3.2.1 Transmit Serial Input Clock (TSICLKP/TSICLKN) ................................. 18
2.3.2.2 Receive Serial Output Clock (RSOCLKP/RSOCLKN) ........................... 18
2.3.3 Crystal Reference Clock (XTALIN/XTALOUT)....................................................... 18
Jitter .................................................................................................................................... 18
2.4.1 Jitter Tolerance ...................................................................................................... 18
2.4.2 Jitter Generation (Intrinsic Jitter)............................................................................ 19
2.4.3 Jitter Transfer......................................................................................................... 19
Operational Modes ............................................................................................................. 19
2.5.1 Hardware Mode ..................................................................................................... 19
2.5.1.1 PLL Clock Reference (CIS pin) .............................................................. 20
2.5.1.2 Loopback Test (RLIS and LLIS pins) ..................................................... 20
2.5.1.3 Line Interface Selection (MODE Pin) ..................................................... 21
2.5.1.4 Parallel/Serial Mode Selection (SP pin) ................................................. 21
2.5.1.5 Tx Amplitude Trim .................................................................................. 21
2.5.2 Software Mode....................................................................................................... 21
2.5.2.1 Serial Input Clock (SCLK) ...................................................................... 22
2.5.2.2 Chip Select Input (CS) ........................................................................... 22
2.5.2.3 Serial Input Word (SDI) .......................................................................... 22
2.5.2.4 Serial Output Word (SDO) ..................................................................... 22
Serial System Interface....................................................................................................... 23
Parallel System Interface .................................................................................................... 23
Loopback Modes ................................................................................................................ 24
2.8.1 Local Loopback...................................................................................................... 24
2.8.2 Remote Loopback.................................................................................................. 25
3
Contents
3.0
Register Definitions..................................................................................................................... 26
4.0
Application Information .............................................................................................................. 33
4.1
4.2
Fiber Optic Module Interface .............................................................................................. 33
Coax Interface .................................................................................................................... 33
5.0
Test Specifications...................................................................................................................... 36
6.0
Mechanical Specifications.......................................................................................................... 46
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
4
Intel® LXT6155 Block Diagram ..................................................................................................... 7
Intel® LXT6155 Pin Assignments.................................................................................................. 8
Intel® LXT6155 System Interface................................................................................................ 13
Framing State ............................................................................................................................. 15
Criteria for LOS Output............................................................................................................... 16
Receive Frame Synchronization and Frame Pulse Position ...................................................... 16
Example of CMI Encoded Binary Signal..................................................................................... 17
Hardware Mode .......................................................................................................................... 19
Software Mode ........................................................................................................................... 22
Serial Data Output Word Structure (Read Cycle: R/W=High) .................................................... 23
Serial Data Input Word Structure (Write Cycle: R/W = Low) ...................................................... 23
Serial Interface ........................................................................................................................... 24
Parallel Interface......................................................................................................................... 24
Local Loopback .......................................................................................................................... 25
Remote Loopback ...................................................................................................................... 25
3.3 V LVPECL to 3.3 V LVPECL Interface ................................................................................. 34
75 W Coax Cable Interface ........................................................................................................ 35
Transmit Parallel Input Data Timing (See Table 29) ................................................................... 38
Transmit Serial Input Data Timing (See Table 29)...................................................................... 38
Receive Serial Output Data Timing (See Table 31) .................................................................... 39
Receive Parallel Output Data Timing (See Table 31) ................................................................. 40
Microprocessor Input Timing Diagram........................................................................................ 41
Microprocessor Output Timing Diagram ..................................................................................... 42
CMI Encoded Zero per G.703 and STS-3 .................................................................................. 42
CMI Encoded One per G.703 and STS-3 ................................................................................... 43
Jitter Tolerance ........................................................................................................................... 44
Generation Measurement Filter Characteristics ......................................................................... 45
Typical Coax Jitter Transfer........................................................................................................ 45
Typical Fiber Jitter Transfer ........................................................................................................ 46
Intel® LXT6155LE Package Specification................................................................................... 46
Datasheet
Contents
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Intel® LXT6155 Pin Descriptions................................................................................................... 8
Standards Compliance ............................................................................................................... 16
Reference Clock Settings1 ......................................................................................................... 20
Loopback Selection .................................................................................................................... 20
MODE Line Interface Settings .................................................................................................... 21
Device Address/Control Byte...................................................................................................... 26
Intel® LXT6155 Register Map (A<3:0>) ...................................................................................... 26
Primary Control Register Settings, Register #0 (Address A<3:0>=0000).................................. 27
Tx Control, Register #1 (Address A<3:0>=0001) ...................................................................... 27
Transmit PLL1, Register #2 (Address A<3:0>=0010).................................................................28
Transmit PLL2, Register #3 (Address A<3:0>=0011).................................................................28
Equalizer Load, Register #4 (Address A<3:0>=0100) ............................................................... 28
Equalizer & AGC, Register #5 (Address A<3:0>=0101) ............................................................ 28
Matching Filter 2, Register #6 (Address A<3:0>=0110) ............................................................ 29
Slicer, Register #7 (Address A<3:0>=0111) ............................................................................... 29
RxPLL 1, Register #8 (Address A<3:0>=1000) .......................................................................... 29
Rx PLL 2, Register #9 (Address A<3:0>=1001) ........................................................................ 30
Test, Register #10 (Address A<3:0>=1010) .............................................................................. 30
Register, Bias and Fuse Controls, Register #11 (Address A<3:0>=1011) ................................ 30
Rx Digital 1, Register #12 (Address A<3:0>=1100)................................................................... 30
Rx Digital 2, Register #13 (Address A<3:0>=11001).................................................................. 31
Status Control, Register #14 (Address A<3:0>=1110) .............................................................. 31
Read-Only Register #15 (Address A<3:0>=1111) ...................................................................... 32
Transformer Specifications ......................................................................................................... 35
Crystal Specifications ................................................................................................................. 36
Absolute Maximum Ratings ........................................................................................................ 36
Recommended Operating Conditions......................................................................................... 36
DC Electrical Characteristics (Vcc = 3.0 V to 3.6 V; TA = -40 °C to 85 °C) ................................ 37
Transmit Timing Characteristics (See Figure 18 and Figure 19) ................................................ 37
Transmit Analog Characteristics................................................................................................. 38
Receive Timing Characteristics (See Figure 20 and Figure 21) ................................................. 39
Receive Analog Characteristics.................................................................................................. 40
Serial Control Timing .................................................................................................................. 41
Jitter Tolerance (in UIpp) ............................................................................................................ 43
Jitter Generation ......................................................................................................................... 44
Jitter Transfer.............................................................................................................................. 44
Intel® LXT6155LE Package Specification (64-Pin Low-Profile Quad Flat Pack [Part
Number Intel® LXT6155LE, Extended Temperature Range: -40 °C to 85 °C])........................... 47
Datasheet
5
Contents
Revision History
6
Date
Revision
Description
August
003
Figure 16, note 1: R3, R4, R7, R8 = 82.5
July 2002
002
Changed “Level One” to “Intel”
January 2001
001
Initial release
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 1. Intel® LXT6155 Block Diagram
µ P Control (CS, SCLK, SDI, SDO),
Hardware (MODE0, SP, CIS, RIFE)
Optional
19.4MHz crystal
RLIS,
LLIS
4
2
HWSEL
XTALOUT
XTALIN
TXISH
2
TTIP1
Control
Logic
TRING1
TTIP0
Control
Registers
CMI
Encode
TRING0
8
RTIP
RRING
Frequency
Doubler
Adaptive
Equalizer
TPID<7:0>
Parallel/
Serial
2
Local
Loopback
TPOS, TNEG
Data
Recovery
Remote
Loopback
Divide
8
RPOCLK
2
Equalizer
Control
RXISH
TPICLK
x 8 Synthesizer
PLL
Clock
Recovery
PLL
CMI/NRZ
Decode
TSICLKP, TSICLKN
Serial/
Parallel
Frame Detect &
Byte Aligner
8
RSOCLKP, RSOCLKN
RPOD<7:0>
2
RPOS, RNEG
ROFP/CMIERR
LOS
Loss of Signal
(LOS)
LOCK
Datasheet
7
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
1.0
Pin Assignments and Signal Descriptions
XTALIN
1
XTALOUT
2
TAGND
3
TXISH
4
12
SCLK/SP
13
TVCC
TTIP1
TRING1
TTIP0
TRING0
TGND
WELL
SUB
HWSEL
ADDR1/LLIS
ADDR0/RLIS
RAGND
RTIP
RRING
RAGND
RXISH
62
61
60
59
58
57
56
55
54
53
52
51
50
49
15
27
28
29
RPOD7
RPOD6
RPOD5
32
26
RPOCLK
RPOD2
25
VCC
31
24
TPICLK
RPOD3
23
TPID0
30
22
TPID1
RPOD4
21
16
TPID2
TPID7
14
20
SDO/RIFE
63
11
CS/MODE
SDI/CIS
Table 1.
10
TPID3
TDGND
(top view)
19
TNEG
9
TPID4
TPOS
LXT6155LE
8
18
TSICLKN
7
TPID5
TSICLKP
6
17
TDVCC
5
TPID6
TAVCC
64
Figure 2. Intel® LXT6155 Pin Assignments
48
VBIAS
47
ATST
46
RAVCC
45
LOS
44
LOCK
43
ROFP/CMIERR
42
RDGND
41
RDVCC
40
RPOS
39
RNEG
38
PVCC
37
RSOCLKN
36
RSOCLKP
35
GND
34
RPOD0
33
RPOD1
Intel® LXT6155 Pin Descriptions
Pin #
Symbol
I/O1
1
XTALIN
AI/O
2
XTALOUT
3
TAGND
S
4
TXISH
AI/O
Type2
Description
Crystal Input/Output. These pins are connected to an external
19.44 MHz crystal. Alternately, a stable external clock signal may
be connected to XTALIN with XTALOUT left open. XTALIN
should be connected to TAGND and XTALOUT should be left
open if the transmit input clock is used as a clock reference
Transmit Analog Ground.
Transmit PLL Loop Filter Pin. Connecting a capacitor to
TAGND from this pin controls the Tx PLL transfer function. This
pin requires a 68 nF cap to TAGND.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog
Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5 V tolerant); LVPECL = Low-Voltage positive ECL.
8
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 1.
Pin #
Intel® LXT6155 Pin Descriptions (Continued)
Symbol
I/O1
Type2
Description
5
TAVCC
S
Transmit Analog Power Supply.
6
TDVCC
S
Transmit Digital Power Supply.
7
TSICLKP
DI
LVPECL
8
TSICLKN
Transmit Serial Input Clock, positive and negative.
Differential Transmit clocks at 155.52 MHz. These pins are
disabled when parallel mode is selected.
9
TPOS
DI
LVPECL
10
TNEG
Transmit Serial Input Data, positive and negative. Differential
input data from an overhead terminator at 155.52 Mbps, clocked
in by TSICLK. These pins are disabled when parallel mode is
selected.
11
TDGND
S
12
CS/MODE
DI
Transmit Digital Ground.
TTL
Chip Select Input, software mode (HWSEL = High). Register
transactions through the µP interface are initiated by the falling
edge of this signal.
Line Interface Mode, hardware mode (HWSEL = Low). Sets
line interface mode to LVPECL (MODE = Low) or CMI (MODE =
High).
13
SCLK/SP
DI
TTL
Serial Clock Input, software mode (HWSEL = High). Serial
Microprocessor uses this pin to clock in/out data. SCLK can be
from 0 to 4.096 MHz.
Serial/Parallel Select, hardware mode (HWSEL = Low). When
SP = Low, serial systems interface is used. When SP = High, 8bit parallel system interface is used.
14
SDI/CIS
DI
TTL
Serial Input Data, software mode (HWSEL = High). The serial
data is applied to this pin when the Intel® LXT6155 operates in
software mode. SDI is sampled on the rising edge of SCLK.
Clock Input Select, hardware mode (HWSEL = Low). CIS sets
the reference clock for centering the Rx PLL. If CIS = Low, then
the Intel® LXT6155 uses the transmit input clock as the
reference. If CIS = High, then the Intel® LXT6155 uses the crystal
clock input (XTALIN) as the reference.
15
SDO/RIFE
DI/O
TTL
Serial Output Data, software mode (HWSEL = High). The serial
data from the on-chip register is output on this pin in software
mode. Data output is valid on the rising edge of SCLK. This pin
goes to a high impedance state when the serial port is being
written to or when CS is High.
Receive Input Frame Enabler, hardware mode (HWSEL =
Low). The frame detection option is available only in parallel
mode. If RIFE = Low, then the Intel® LXT6155 disables the frame
detection, and byte alignment. If RIFE = High, then the Intel®
LXT6155 enables the frame detection, and outputs RPOD bytes
aligned to the SONET/SDH framer. This feature, if used, must be
enabled prior to applying data to Rtip/Rring.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog
Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5 V tolerant); LVPECL = Low-Voltage positive ECL.
Datasheet
9
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 1.
Intel® LXT6155 Pin Descriptions (Continued)
Pin #
Symbol
I/O1
Type2
Description
16
17
18
19
TPID7/TXTRIM3
TPID6/TXTRIM2
TPID5/TXTRIM1
TPID4/TXTRIM0
DI
TTL
Transmit Parallel Input Data. Transmit data from an Overhead
Terminator at parallel speed 19.44 MHz, clocked in by TPICLK.
TPID7 is the most significant bit, and is the first bit to be sent.
These pins should be grounded or not connected when the Intel®
LXT6155 is used in serial mode.
Transmit Trim Controls, in serial, hardware, coax mode only.
These pins trim the amplitude of the line driver output from (nom 21%) to (nom +24%) in 3% steps. This feature is only enabled
when pin #20 (TXTRIMENA) is High.
20
TPID3/TXTRIMENA
DI
TTL
Transmit Parallel Input Data. Transmit data from an Overhead
Terminator at parallel speed 19.44 MHz, clocked in by TPICLK.
TPID7 is the most significant bit, and is the first bit to be sent.
These pins should be grounded or not connected when the Intel®
LXT6155 is used in serial mode.
Transmit Trim Enable, in serial, hardware, coax mode only. This
pin enables the trimming of the line driver output by pins 16-19
when high.
21
22
23
TPID2
TPID1
TPID0
DI
TTL
Transmit Parallel Input Data. Transmit data from an Overhead
Terminator at parallel speed 19.44 MHz, clocked in by TPICLK.
TPID7 is the most significant bit, and is the first bit to be sent.
These pins should be grounded or not connected when the Intel®
LXT6155 is used in serial mode.
24
TPICLK
DI
TTL
Transmit Parallel Input Clock. Parallel transmit clock at
19.44 MHz. This pin is disabled when serial mode is selected and
should be grounded or not connected.
25
VCC
S
26
RPOCLK
DO
TTL
Receive Parallel Output Clock. Parallel receive clock as
recovered from received data. The clock is nominally 19.44 MHz,
synchronized with RPOD<7:0>.
27
28
29
30
31
32
33
34
RPOD7
RPOD6
RPOD5
RPOD4
RPOD3
RPOD2
RPOD1
RPOD0
DO
TTL
Receive Parallel Output Data. RPOD<7:0> output aligned 8-bit
bytes at RPOCLK clock rate. These pins are to be left open when
serial mode is selected. RPOD7 is the most significant bit, and is
the first to arrive.
35
GND
S
36
RSOCLKP
DO
37
RSOCLKN
38
PVCC
S
39
RNEG
DO
40
RPOS
Power Supply.
Ground.
LVPECL
Receive Serial Output Clock. Serial receive clock as recovered
from received data. The clock is nominally 155.52 MHz,
synchronized with output serial data RPOS and RNEG.
PECL Buffers Power Supply.
LVPECL
Receive Serial Output Data, positive and negative. These two
pins provide recovered data synchronized to receive serial output
clocks RSOCLKP and RSOCLKN. These pins are tristated and
should be left open when parallel mode is selected.
41
RDVCC
S
Receive Digital Power Supply.
42
RDGND
S
Receive Digital Ground.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog
Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5 V tolerant); LVPECL = Low-Voltage positive ECL.
10
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 1.
Pin #
43
Intel® LXT6155 Pin Descriptions (Continued)
Symbol
I/O1
Type2
Description
ROFP/
DO
TTL
Receive Output Frame Pulse. In hardware mode (HWSEL =
Low), this pin is asserted (High) on the last A2 byte in the
(A1.....A1, A2.....A2) sequence in the RPOD<7:0> traffic.
A1=1111,0110 and A2=0010,1000 in binary. In software mode
(HWSEL = High), this position is programmable. During coax
operation, when frame detection is disabled (RIFE = 0 in HW/Reg
#12, bit3 = 0), or in serial mode, this pin indicates CMI line code
errors. These pulses are 50 ns wide (active high). One or more
errors in 16 consecutive bits will causes a single pulse.
CMIERR
44
LOCK
DO
TTL
Receive Output PLL Lock. A High indicates receive PLL has
locked to incoming data. A Low indicates receive PLL is not
locked.
45
LOS
DO
TTL
Loss of Signal. An alarm output signal (high) indicating incoming
signal voltage is weak or incoming data does not contain enough
transitions. In software mode (HWSEL = 1) this pin can be
configured to combine LOS and LOCK alarms.
46
RAVCC
S
Receive Analog Power Supply.
47
ATST
-
Analog Test. For factory test purposes only; do not connect.
48
VBIAS
AI
Analog
Bias Input Voltage. This pin requires a 15 K (1%) pull-down
resistor to RAGND.
49
RXISH
A0
Analog
Rx PLL External Cap. Connecting a capacitor to RAGND from
this pin controls the Rx PLL transfer function. This pin requires a
330 nF cap to RAGND.
50
RAGND
S
51
RRING
AI
52
RTIP
53
RAGND
S
54
ADDR0/RLIS
DI
Receive Analog Ground.
Analog
Receive Input Data, positive (RTIP) and negative (RRING).
Accepts incoming signals (LVPECL or CMI) from the line
interface.
Receive Analog Ground.
TTL
Address 0, software mode (HWSEL = High). This pin together
with ADDR1 sets the chip select address. Up to 4 Intel® LXT6155
chips can be addressed by the µP interface.
Remote Loopback Input Select, hardware mode (HWSEL =
Low). Together with LLIS sets the Intel® LXT6155 in a loopback
test mode. See Table 4
55
ADDR1/LLIS
DI
TTL
Address 1, software mode (HWSEL = High). This pin together
with ADDR0 sets the chip select address. Up to 4 Intel® LXT6155
chips can be addressed by the µP interface.
Local Loopback Input Select, hardware mode (HWSEL =
Low). Together with RLIS sets the Intel® LXT6155 in remote
loopback mode. See Table 4
56
HWSEL
DI
TTL
Hardware/Software Mode Select. When HWSEL = High, the
Intel® LXT6155 enters software (host) mode, and is ready to
communicate with a serial microprocessor. When HWSEL = Low,
the Intel® LXT6155 operates in hardware standalone mode
(without a serial µP).
57
SUB
S
Reserved. Must be connected to GND.
58
WELL
S
Reserved. Must be connected to VCC.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog
Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5 V tolerant); LVPECL = Low-Voltage positive ECL.
Datasheet
11
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 1.
Pin #
Intel® LXT6155 Pin Descriptions (Continued)
Symbol
I/O1
Type2
Description
59
TAGND
S
60
TRING0
AO
61
TTIP0
Transmit Output Data, positive (TTIP0) and negative
(TRING0). Differential CMI driver outputs for coax interface.
62
TRING1
DO
63
TTIP1
Transmit Output Data, positive (TTIP1) and negative
(TRING1). Differential LVPECL NRZ driver outputs for a fiber
optic transceiver.
64
TAVCC
S
Transmit Analog Ground.
Transmit Analog Power Supply.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog
Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5 V tolerant); LVPECL = Low-Voltage positive ECL.
2.0
Functional Description
The Intel® LXT6155 is a front-end transceiver designed for 155 Mbps OC3/STM1/ATM
transmission applications. Table 2 lists the standards with which the Intel® LXT6155 is compliant.
The Intel® LXT6155 interfaces to either a fiber transceiver or a coax cable on the line side, and on
the system side, to an SDH/SONET Overhead Terminator or an ATM UNI. The Intel® LXT6155
can function in Hardware stand-alone mode, or in Software mode controlled through an industry
standard Motorola compatible 4-wire serial microprocessor interface.
The Intel® LXT6155 can be set to operate in either CMI mode for the 75 Ω coax interface or NRZ
mode for the optical transceiver interface. The operating mode can be set in either hardware mode
by using the MODE pin, or software mode by using Primary Control Register, bit 0.
2.1
Transmitter
In serial mode, the Intel® LXT6155 accepts both data (TPOS, TNEG) and clock signals (TSICLKP,
TSICLKN). Serial clock signals are required for the Intel® LXT6155 to run internal logic, reshape
the line transmit pulses and generate the low-jitter clocks for Tx data generation.
In parallel mode, the Intel® LXT6155 accepts data TPID<7:0> and clock TPICLK. TPICLK is
internally multiplied by 8 to yield the 155.52 MHz clock for Tx data generation.
Both serial and parallel clocks (TSICLKP/TSICLKN and TPICLK) must conform to the SONET/
SDH standard frequency accuracy requirements.
Depending on whether the selected media interface is coax or fiber, the data is CMI or NRZ
encoded respectively, and passed to the appropriate line drivers. The Intel® LXT6155 line drivers
are high-speed buffers that meet the CMI templates and industry standard LVPECL signal
requirements. The CMI output pins are TTIP0 and TRING0, and the NRZ LVPECL pins, TTIP1
and TRING1.
12
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.1.1
Transmitted Signal
Transmitted signals conform to the standard templates listed in Table 2.
2.1.1.1
Fiber Based G.957/GR-253 Transmission Systems
The Intel® LXT6155 provides 3.3 V LVPECL compatible signals for interfacing to a fiber optic
transceiver. Please refer to Application Information for interface schematics.
2.1.2
Coax Based G.703/GR-253 Transmission Systems
The Intel® LXT6155 encodes and decodes CMI signals that are transmitted onto a 75 Ω coax cable
compliant with STM1/STS-3 CMI templates. Please refer to the CMI templates shown in Figure 24
and Figure 25.
Figure 3. Intel® LXT6155 System Interface
2
Fiber Optic Modules
or Coax Transformers
2
1
Tx
2
Rx
4
µ Processor
(optional)
2.1.2.1
System Interface
LXT6155
Line Interface
SONET/SDH
Overhead
Terminator
ATM UNI
1
Data/Clock (8-bit parallel or serial mode)
2
Data/Clock (8-bit parallel or serial mode)
Receive Output Frame Pulse (ROFP)
Receive Ouput PLL Lock (LOCK)
Loss of Signal (LOS)
CMI Encoding
Coded Mark Inversion (CMI) is an encoding scheme adopted by SONET STS-3 and SDH STM1
standards. CMI encoding guarantees at least one transition per bit, thereby enhancing the clock
recovery process. CMI encodes a “0” with a midpoint positive transition, and a “1” as Low or
High, in opposite polarity to the previous encoded “1”. Refer to Figure 7, Figure 24 and Figure 25
for encoding and pulse template information.
2.1.3
Tx Clock Monitoring
The Intel® LXT6155 provides transmit clock monitoring for both serial and parallel operating
modes. When using the crystal clock as a reference, the Intel® LXT6155 monitors the TSICLKP/
TSICLKN or the TPICLK input(s) for transitions. If no transition is seen within 200 ns, the
tx_clk_alarm flag will be set (reg #15) and the transmitter outputs ttip1/tring1 or ttip0/tring0 will
stop sending data to the line. This condition will remain until the Intel® LXT6155 detects clock
transitions at the transmitter input(s) TSICLKP/TSICLKN or TPICLK. Transmit clock monitoring
can be disabled in software mode only.
Datasheet
13
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
In remote loopback, transmit clock monitoring is disabled in SW and HW mode. In SW mode,
when using transmit clocks as the receive PLL reference, the user must disable transmit clock
monitoring by setting reg #1 bit <0> low.
2.2
Receiver
2.2.1
Analog Front End and Timing Recovery
2.2.1.1
CMI Mode
Received data on RTIP/RRING goes through an adaptive equalizer. An adaptive f equalizer and
adaptive Automatic Gain Control (AGC) compensate the frequency-and-cable length dependent
loss in data signal, and reshapes the signal to the optimal waveform. A Phase Locked Loop (PLL)
then performs clock recovery operation, comparing the reshaped data phase against the receive
output clock phase. The receive PLL requires an external reference (e.g. transmit input clock or
XTAL clock) to start up the clock recovery process. This clock can be derived from XTALIN,
TPICLK or TSICLK (÷8). The recovered clock is used to retime the CMI signals, and to decode
CMI to NRZ. Coding errors are detected and flagged via the CMIERR pin in HW mode with the
frame detect disabled or in serial mode. In software mode (HWSEL = High) CMI coding errors are
indicated via the µP interface interrupt register: Reg #15, mode 05.
2.2.1.2
NRZ Mode
The on chip adaptive equalizer is bypassed. Data goes straight to the clock recovery phase locked
loop. The PLL then performs clock recovery operation, comparing the data phase against the clock
phase. This clock can be derived from XTALIN, TPICLK or TSICLK (÷8). The receive PLL
requires an external reference (e.g. transmit input clock or XTAL clock) to start up the clock
recovery process.
The recovered clock is used to retime the data signals. When the recovered clock is within 488 ppm
of the reference clock, the LOCK signal asserts. This alarm is also accessible on the µP interface as
a status bit (Reg #15, mode 0) and as an interrupt (Reg #15, mode 05). Once the recovered clock
has been obtained and the NRZ data has been recovered, the Intel® LXT6155 performs framedetect-and-byte-alignment, and serial-to-parallel conversion. The Intel® LXT6155 optionally
provides output data RPOD<7:0> aligned to the SDH/SONET byte boundary. The user has the
option to enable/disable the frame-alignment function in both hardware and software mode. The
frame detect/byte alignment function generates the receive output frame pulse (ROFP). In HW
mode (HWSEL = Low) ROFP asserts (high) on the third A2 byte. In SW mode (HWSEL = High)
this position is programmable via register #13, bits <6:3>. When byte alignment is disabled and the
Intel® LXT6155 is in CMI mode, the ROFP pin indicates CMI coding errors including polarity
errors for ones and inversion errors for zeroes.
The clock recovery PLL’s center frequency comes from either the local crystal or a stable transmit
input clock (TSICLKP/TSICLKN or TPICLK). If operated in loop-timed mode or remote loopback
mode, an external reference clock must be used to center the internal PLL clock. In remote
loopback, the receive reference remains either XTALIN or TSICLK or TPICLK, depending on the
control selection. If an independent and stable transmit clock is available, the designer has the
option of applying this clock to pin XTALIN to center the PLL, without the external crystal.
The user can also replace the crystal by connecting the TPICLK (19.44 MHz) signal to the
XTALIN pin. However, a local crystal is recommended for “keep alive” purposes in case the clock
becomes unavailable.
14
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.2.2
Receive Frame Detect and Byte Alignment
Receive Frame Detection only operates in parallel mode, if Frame Detection is enabled. The Intel®
LXT6155 provides aligned bytes RPOD<7:0> following the distinct SONET OC3/STM1 frame
marker word, 3 x A1, followed by 3 x A2, where A1=F6h and A2=28h. The Receive Output Frame
Pulse (ROFP) asserts during the third A2 byte, and de-asserts after one complete RPOCLK clock
period. If this feature is used, it can be enabled in register #12 bit <3> in software mode1, or by
setting the RIFE (pin 15) high in hardware mode prior to applying data to Rtip/Rring. Two
consecutive frames with correct frame words (A1… A1 A2…A2) are required to change from an
out-of-frame state (OOF) to an in-frame state. The OOF alarm is accessible in SW mode (HWSEL
= High) as a status or interrupt signal (Reg #15). To declare an OOF condition, four consecutive
frames with incorrect frame words are required. Byte alignment occurs when entering the in-frame
state. In case of an OOF event, the byte alignment and frame pulse position are frozen. The ROFP
output continues unchanged until re-entering the in-frame state.
Figure 4. Framing State
4 consecutive frames
with errored FAS
In Frame
Out of Frame
2 consecutive frames
with correct FAS
2.2.2.1
Loss of Signal (LOS)
Loss of Signal provides an alarm signal indicating incoming signal voltage is weak or incoming
data does not contain enough transitions. This signal is available in HW mode on pin #45 and in
SW mode as status and interrupt (Reg #15, modes 00 and 05).
2.2.2.2
Coax Interface
Loss of Signal provides an alarm output that indicates weak line input signal. The LOS signal
asserts when the incoming signals fall below a specified loss threshold, and de-asserts when the
line signal rises nominally 2 dB above the assert threshold. The threshold is adjustable in SW mode
(HWSEL = High) via the µProcessor interface.
2.2.2.3
Fiber Interface
If no transition is detected during any 3112 bit times (20 µsec), LOS asserts. LOS is cleared when
two consecutive frame words with no LOS events between then are received. In SW mode
(HWSEL = High) the assertion window is programmable from 128 bits to 4096 bits in four steps.
The deassertion criteria can also be configured to 12.5% transition density. The 12.5% density is
determined by receipt of at least 4 transitions during a 32-bit sliding window.
1. For further details see register #12 description for usage.
Datasheet
15
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 5. Criteria for LOS Output
Nominal Value
LOS
De-assert
HYS = 3 dB
LOS
Assert
Level below nominal
Figure 6. Receive Frame Synchronization and Frame Pulse Position
RPOCLK
A1
RPOD <7:0>
A1
A1
A2
A2
A2
J0
Z0
Z0
Start of SPE
End of Previous Frame
Frame Pulse Position
-7
-6
-5
-4
-3
-2
-1
0
+1
+2
+3
+4
+5
+6
+7
Hex
Fh
Eh
Dh
Ch
Bh
Ah
9h
0h
8h
1h
2h
3h
4h
5h
6h
7h
Contents of
REG 13h
Table 2.
Binary 1111 1110 1101 1100 1011 1010 1001 0000 0001 0010 0011 0100 0101 0110 0111
1000
Standards Compliance
SDH/SONET (Fiber)
SDH/SONET (Coax)
Item
STM1
Line Rate (Mbps)
Line Interface
Line Code
Signal Templates
Jitter
16
OC3
STM1
STS-3
155
155
155
155
50 Ω LVPECL
50 Ω LVPECL
75 Ω coax
75 Ω coax
NRZ
NRZ
CMI
CMI
G.957
STM1 Eye
OC3
OC3 Eye
G.703
CMI Template.
CMI Eye
STSX-3
CMI Template.
CMI Eye
G.958
G.825
GR-253
G.813
G.825
GR-253
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 7. Example of CMI Encoded Binary Signal
Binary
0
0
1
0
1
1
1
CMI
T/2 T/2
T
2.3
Clocks
2.3.1
Parallel Mode
The Intel® LXT6155 accepts TPICLK synchronized with transmit input parallel data TPID<7:0>.
The data is serialized and transmitted at TTIP0/TRING0 or TTIP1/TRING1 depending on which
line encoding mode is selected. The Intel® LXT6155 in turn produces the receive output parallel
clock RPOCLK, that is recovered from incoming line data RTIP/RRING, and is synchronized with
receive output parallel data RPOD<7:0>.
2.3.1.1
Transmit Parallel Input Clock (TPICLK)
TPICLK is the transmit parallel input clock provided by the systems interface. This clock must be
nominally 19.44 MHz, synchronized with parallel input data TPID<7:0>. This clock is then
internally multiplied by 8 to produce a serial clock, used for parallel-to-serial conversion, line
drivers, and pulse reshaping. In HW mode (HWSEL = Low), TPID data is sampled on the falling
edge of TPICLK. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit
#3).
2.3.1.2
Receive Parallel Output Clock (RPOCLK)
RPOCLK is the parallel output clock that is recovered from the line input data RTIP/RRING. This
clock is at 19.44 MHz, synchronized with parallel output data RP0D<7:0>. In HW mode (HWSEL
= Low), the RPOCLK clock rising edge is at the center of eye opening of RPOD<7:0> as shown in
Figure 21. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit #2).
Under LOS (LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RPOCLK is switched to
the reference selected by the CIS control in HW mode, or Reg #0 bit #5 in SW mode. Also, the
parallel output is forced to all zeros. This feature can be disabled in SW mode (HWSEL = High)
via register #10, bit #7.
Datasheet
17
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.3.2
Serial Mode
At the transmit systems interface, the Intel® LXT6155 accepts the transmit input clock TSICLKP/
TSICLKN that is synchronized to incoming serial differential data TPOS/TNEG. At the line
interface, the Intel® LXT6155 accepts RTIP/RRING data and produces the clocks RSOCLKP/
RSOCLKN synchronized to receive output data RPOS/RNEG. RSOCLKP/RSOCLKN clock edges
are at the center of RPOS/RNEG.
2.3.2.1
Transmit Serial Input Clock (TSICLKP/TSICLKN)
TSICLKP/TSICLKN is the serial input clock from the overhead terminator. This 155.52 MHz
clock is rising edge centered with input serial data on TPOS and TNEG. These clock pins should be
left open when the Intel® LXT6155 operates in parallel mode.
2.3.2.2
Receive Serial Output Clock (RSOCLKP/RSOCLKN)
RSOCLKP/RSOCLKN is the serial clock recovered from the line input data on RTIP/RRING. This
155.52 MHz clock is falling edge centered with receive serial output data on RPOS/RNEG. These
clock pins should be left open when the Intel® LXT6155 operates in parallel mode. Under LOS
(LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RSOCLK P/N is switched to the Tx
serial clock. Also the serial output data is forced to all zeros. This feature can be disabled in SW
mode (HWSEL = High) via register #10, bit #7.
2.3.3
Crystal Reference Clock (XTALIN/XTALOUT)
An optional 19.44 MHz crystal can be connected across the XTALIN and XTALOUT pins. This
crystal reference provides an onchip clock that is independent of the external system clock
(TSICLKP/TSICLKN or TPICLK). The main functions of the crystal reference clock are threefold:
(1) to center the receive PLL at 155 MHz, (2) to keep the PLL centered at 155 MHz when LOS
asserts, and (3) In the event incoming data is lost, to provide a reference clock for other devices
which require it. The designer has the option to use this crystal reference clock or the transmit input
clock (TSICLKP/TSICLKN or TPICLK) to center the receive PLL.
2.4
Jitter
The Bellcore GR-253 standard defines jitter as the “short-term variations of a digital signal’s
significant instants from their ideal positions in time”. Significant instants are the optimum data
sampling instants. Jitter parameters can be measured at the line interface, with system interface in
loopback mode, yielding jitter accumulated in both transmitter and receiver. Isolated jitter
measurements for transmitter and receiver can also be performed. Jitter specs are divided into three
categories: jitter tolerance, jitter generation, and jitter transfer. Jitter values, in effect, measure the
performance of the receive PLL and the transmit synthesizer PLL.
2.4.1
Jitter Tolerance
Jitter tolerance is the peak-to-peak amplitude of sinusoidal jitter applied at the line interface input
that causes an equivalent 1 dB SNR loss measured as BER = 10-10. Refer to Figure 26 on page 44
for the Intel® LXT6155 performance.
18
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.4.2
Jitter Generation (Intrinsic Jitter)
Jitter generation is the amount of transmit jitter at the output of the equipment with a jitter-free
transmit input data and clock. For SONET/SDH, jitter generation is less than 0.01 UI rms,
measured with a band-pass filter from 12 kHz to 1.3 MHz. Refer to Figure 27 on page 45 for the
Intel® LXT6155 performance.
2.4.3
Jitter Transfer
Jitter transfer is defined as the ratio of output jitter to input jitter amplitude versus jitter frequency
for a given bit rate. Input jitter amplitude is shown in the Jitter Tolerance curve. Output jitter is
under the Jitter Transfer template. Refer to Figure 27 on page 45 and Figure 28 on page 45 for the
Intel® LXT6155 performance.
2.5
Operational Modes
The Intel® LXT6155 functions in both Hardware standalone and Software modes. The operating
mode is set by the state of the HWSEL pin.
2.5.1
Hardware Mode
By setting HWSEL = Low, the Intel® LXT6155 operates in standalone hardware mode, without a
serial microprocessor interface. A subset of the functions available in the Software Mode can be set
in Hardware Mode. Intel® LXT6155 provides a comprehensive flexibility in configuring system
clock preference settings, as well as providing pins for activating loopback test modes. Table 3,
Table 4 and Table 5 show the settings that enable the functions available in hardware mode.
Figure 8. Hardware Mode
Nevada
RLIS
GND
Line interface encode/
decode
Remote loopback
LLIS
Local loopback
HWSEL
MODE
Datasheet
CIS
Clock reference select
SP
Serial/Parallel
RIFE
Frame Enable
19
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 3.
Reference Clock Settings1
CIS
Clock Reference
Note
Low
TICLK
Default mode. The Intel® LXT6155 uses the transmit
input clock as the reference clock for on chip
operations. No crystal is needed.
High
XTAL
The Intel® LXT6155 uses the clock signal at XTALIN as
the reference clock for Rx operation. This can either be
an applied 19.44 MHz clock or a 19.44 MHz crystal
can be connected across XTALIN & XTALOUT. See
Table 25 for the crystal specifications.
1. For explanation, see clock sections below.
2.5.1.1
PLL Clock Reference (CIS pin)
The reference clock plays two roles: it centers the receive PLL, and it provides the receive output
clocks RSOCLKP/RSOCKLN and RPOCLK in case of Loss of Signal. When the Intel® LXT6155
powers up, it looks for this reference clock to start-up internal blocks, including the receive PLL
circuitry.
2.5.1.1.1
TICLK
This is the transmit input clock(s): either TSICLKP/TSICLKN in serial mode or TPICLK in
parallel mode.
2.5.1.1.2
XTAL
XTAL is an optional clock, created using an external crystal, connected across the XTALIN and
XTALOUT pins. The crystal provides an independent and stable clock source. This clock is also
used as the reference for the Tx clock monitoring circuitry.
2.5.1.2
Loopback Test (RLIS and LLIS pins)
The Intel® LXT6155 allows two types of loopback test: Remote loopback and Local loopback. In
Remote loopback, the received data and clock are looped back to the transmit line interface. The
Intel® LXT6155 still outputs recovered data and clock at the system interface. In Local loopback,
the transmit data is looped back to the receive input at the line interface. The Intel® LXT6155 also
transmit data onto the line interface while looping back. For descriptive diagrams, please refer to
Figure 14 and Figure 15.
Table 4.
20
Loopback Selection
RLIS
LLIS
Description
Low
Low
Normal operation. No loopback testing.
Low
High
Local loopback test activate.
High
Low
Remote loopback test activate.
High
High
Invalid mode. Do not use.
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.5.1.3
Line Interface Selection (MODE Pin)
The MODE pin sets one of the two line interfaces, as described in Table 5.
Table 5.
2.5.1.4
MODE Line Interface Settings
MODE
Description
Low
Sets LVPECL NRZ mode to interface to a fiber
optic module. CMI related blocks (e.g. input/output
buffers, equalizer) are disabled.
High
Sets CMI mode to interface to a transformer and a
75 Ω coax cable. NRZ related input/output buffers
are disabled.
Parallel/Serial Mode Selection (SP pin)
In Hardware Mode, HWSEL = Low, the Intel® LXT6155 can be set to operate in serial or parallel
data mode, depending on how the Serial/Parallel SP pin is set.
Setting the SP pin = High sets the Intel® LXT6155 to an 8-bit parallel mode. Parallel pins
TPID<7:0>, TPICLK, RPOD<7:0>, ROFP, RPOCLK, LOCK and LOS are be used. Serial pins
TPOS, TNEG, TSICLKP, TSICLKN, RPOS, RNEG, RSOCLKP, RSOCLKN are unused and
should be left open.
Setting the SP pin = Low sets the Intel® LXT6155 to serial mode. Pins TPOS, TNEG, TSICLKP,
TSICLKN, RPOS, RNEG, RSOCLKP, RSOCLKN, LOCK and LOS are used. Pins TPID<7:0>,
TPICLK, RPOD<7:0> and RPOCLK are unused and should be left open.
2.5.1.5
Tx Amplitude Trim
In Hardware, serial, coax mode, the line driver output amplitude can be controlled via pins 16 to
20. Setting TXTRIMENA (pin #20) high enables the trim capability. The trim rage is -21% to
+24% in 3% steps controlled by TXTRIM0-TXTRIM3. The minimum amplitude is at 0000 and the
maximum amplitude is at 1111. This is the same control range as in SW mode.
2.5.2
Software Mode
When HWSEL = High, the Intel® LXT6155 operates in Software Mode. Control is through an
external serial µP interface. Figure 9 shows the pins used in Software Mode. The Intel® LXT6155
uses four pins for the industry standard Serial Control Interface (SCP) bus: SCLK, CS, SDI and
SDO. SCLK is the serial input control clock pin. CS is the chip select input. SDI is the serial data
input pin, and SDO is the serial data output pin. Figure 10 and Figure 11 show the serial interface
data structure. A data transaction is initiated by a falling edge on the Chip Select pin CS. A Highto-Low transition on CS is required for each access to the control registers. The first bit is a read/
write bit (R/W), followed by seven address bits (A<6:0>), and eight data bits (D<7:0>). Every data
transaction requires 16 SCLK cycles to complete. If R/W = High (Read), the Intel® LXT6155
outputs a data byte D<7:0> on the SDO pin. If R/W = Low (Write), the Intel® LXT6155 accepts a
data byte D<7:0> on the SDI pin, while tristating SDO pin.
It is recommended in SW mode operation, the registers are first initialized by writing a “0” to
register #11 bit #6 (reset).
Datasheet
21
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.5.2.1
Serial Input Clock (SCLK)
This pin accepts a clock up to 4.096 MHz for data transactions between the Intel® LXT6155 and
the SCP bus. The Intel® LXT6155 clocks SDO data out on the falling edge, and clocks SDI data in
on the rising edge of SCLK (see Figure 10 and Figure 11).
2.5.2.2
Chip Select Input (CS)
On the falling edge of CS, the Intel® LXT6155 starts data transactions. On the rising edge of CS,
the Intel® LXT6155 stops data transaction. The CS pin must be held Low for at least 16 SCLK
cycles to complete a full Read or Write data transaction. If CS is held Low less than 16 SCLK
cycles, then the data transaction is ignored. At the end of each Write/Read transaction, CS must
return High, between the 16th and 17th clock edges.
2.5.2.3
Serial Input Word (SDI)
Figure 11 shows the serial interface input data word structure. When the first input bit R/W = Low,
a Write operation is performed. The SCLK clocks data in on the SDI pin during the second 8 bits
D<7:0> of the Write operation. Data is clocked in on the rising edge of SCLK. During the entire 16
bit operation, SDO remains tristated. Refer to Table 6 through Table 23 for control register
descriptions.
2.5.2.4
Serial Output Word (SDO)
The serial output word structure is shown in Figure 10. When the first input bit R/W = High, a
Read operation is specified. SDO becomes active after A0 has been clocked in. The first bit out of
SDO changes the state of SDO from High-Z to a Low/High. SDO is clocked out on the falling edge
of SCLK.
Figure 9. Software Mode
LXT6155
HWSEL
CS
Chip select in
SDI
Serial data in
SDO
Serial data out
SCLK
Serial clock in
ADDR0, ADDR1
22
VCC
Device address settings
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 10. Serial Data Output Word Structure (Read Cycle: R/W=High)
CS
SCLK
DON'T
CARE
SDI
DON'T
CARE
Don't Care
R/W
=1
A6
SDO
A5
A4
A3
A2
A1
A0
High Impedance
Don't Care
D7
D6
D5
D4
D3
D2
D1
D0
Figure 11. Serial Data Input Word Structure (Write Cycle: R/W = Low)
CS
SCLK
SDI
Don't Care
R/W
=0
A6
A5
A4
A3
SDO
2.6
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Don't Care
High Impedance
Serial System Interface
The serial interface permits the Intel® LXT6155 to communicate with an Overhead Termination
device at 155.52 Mbps. Data and clock lines are differential 3.3 V LVPECL signals. Refer to
Figure 12.
2.7
Parallel System Interface
Parallel interface allows the Intel® LXT6155Intel® LXT6155 to communicate with the system chip
at 19.44 MHz, 8 bits per clock cycle. Data and clock lines are TTL compatible signals. Refer to
Figure 13.
Datasheet
23
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 12. Serial Interface
Overhead
Terminator/ATM UNI
Nevada
4
TPOS, TNEG
TSICLKP,
TSICLKN
DATA_OUT<0:1>
CLK_OUT<0:1>
4
RPOS, RNEG
RSOCLKP,
RSOCLKN
DATA_IN<0:1>
CLK_IN<0:1>
CMIERR, LOS
LOS
µProcessor (optional)
CS
SDI
SDO
SCLK
4
Chip Select
Data I/O
Clock
Figure 13. Parallel Interface
Overhead
Terminator/ATM UNI
Nevada
9
DATA_OUT<0:7>
BYTE_TCLK
RPOD<0:7>
RPOCLK
9
DATA_IN<0:7>
BYTE_RCLK
LOS, ROFP/
CMIERR
2
TPID<0:7>
TPICLK
CS
SDI
SDO
SCLK
2.8
LOS, RIFP
µProcessor (optional)
4
Chip Select
Data I/O
Clock
Loopback Modes
The Intel® LXT6155 provides two loopback modes that can be executed in either hardware or
software mode: local loopback and remote loopback. In remote loopback mode, the crystal
reference clock is used to center the receive PLL to prevent illegal clock looping.
2.8.1
Local Loopback
Local loopback routes the transmit line output signals (TTIP and TRING) back to the receive line
inputs (RTIP and RRING). In this mode, the line transmit output signals are active (see Figure 14).
24
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
2.8.2
Remote Loopback
Remote loopback routes the receive system output signals, both data and clock, to the transmit
system input (see Figure 15). In this mode, system outputs (RPOD<7:0> or RPOS/RNEG) are still
active.
Figure 14. Local Loopback
TTIP0, TRING0,
TTIP1, TTIP1
RTIP, RRING
Line
Buffer
P/S
Equalizer
PLL
TPID <7:0>, TPICLK,
TPOS/TNEG, TSICLKP/N
S/P
RPOD <7:0>, RPOCLK,
RPOS/RNEG, RSOCLKP/N
Figure 15. Remote Loopback
TTIP0, TRING0,
TTIP1, TTIP1
RTIP, RRING
Datasheet
Line
Buffer
Equalizer
TPID <7:0>, TPICLK,
TPOS/TNEG, TSICLKP/N
P/S
PLL
S/P
RPOD <7:0>, RPOCLK,
RPOS/RNEG, RSOCLKP/N
25
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
3.0
Register Definitions
There are a total of sixteen (16) control registers in the Intel® LXT6155 addressed by the lowest
four address bits, A<3:0>. See Table 8 through Table 23 for details.
Table 6.
Device Address/Control Byte
A<6:0>
A<6:5>
A4
A<3:0>
Table 7.
26
Description
®
Intel LXT6155 Device Select. By using pins ADDR1 and ADDR0, up to four Intel® LXT6155
devices can be addressed. For a successful data transaction to occur, A6 and A5 must match the
polarity settings on ADDR1 and ADDR0, respectively. Using these controls, up to four Intel®
LXT6155 devices can be independently controlled.
Not Used. Set to 0 during transactions.
Intel® LXT6155 Register Map (see Table 7).
Intel® LXT6155 Register Map (A<3:0>)
Register #
A<3:0>
Register Name
Type
0
0000
Primary Control
R/W
1
0001
Transmit Control
R/W
2
0010
Transmit PLL1
R/W
3
0011
Transmit PLL2
R/W
4
0100
Equalizer load
R/W
5
0101
Equalizer/AGC
R/W
6
0110
Matching filter2
R/W
7
0111
Slicer
R/W
8
1000
Receive PLL 1
R/W
9
1001
Receive PLL 2
R/W
10
1010
Test
R/W
11
1011
Reset and Bias
R/W
12
1100
Receive Digital 1
R/W
13
1101
Receive Digital 2
R/W
14
1110
Status/Interrupt Control
R/W
15
1111
Status/Interrupt Output
Read-only
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 8.
Primary Control Register Settings, Register #0 (Address A<3:0>=0000)
Bit
Default
Mnemonic
7
0
lpbk_cntl
6
0
5
0
pll_ref
4
0
-
3
1
clk_inv
2
1
1
0
sys_int
0
0
media_sel
Description
Local loopback:
0 = No loopback
1 = Activate local loopback
Remote loopback:
0 = No loopback
1 = Activate remote loopback
PLL/Equalizer reference clock control:
0 = Use TPICLK clock
1 = Use external crystal (XTALIN)
Not used
TPICLK polarity at system interface:
0 = TPID <7:0> sampled on the rising edge of TPICLK
1 = TPID <7:0> sampled on the falling edge of TPICLK
RPOCLK polarity at system interface:
0 = RPOD <7:0> transitions on the rising edge of RPOCLK
1 = RPOD <7:0> transitions on the falling edge of RPOCLK
Systems interface mode selection:
0 = Serial mode
1 = Parallel 8-bit mode
Media and line code selection:
0 = Fiber (NRZ)
1 = Coax (CMI)
.
Table 9.
Datasheet
Tx Control, Register #1 (Address A<3:0>=0001)
Bit
Default
Mnemonic
7
1
tx_ena
6
1
tx_dig_reset
5
0
4:1
0.1.1.1
tx_amp_trim
0
1
tx_clk_sw_ena
Description
Tx output enable:
0 = outputs disabled
1 = outputs active
Tx digital circuitry reset. This can be used to minimize power
comsumption when the device is disabled but not powered down. It
must be enabled when the device is active.
0 = reset
1 = active
Not for customer use.
Transmit amplitude trim:
0000 = -21%
1111 = +24%
Tx clock detection enable. This must be disabled in SW mode when
pll_ref=0 (reg#0<5>=0)
0 = disable
1 = enable
27
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
.
Table 10. Transmit PLL1, Register #2 (Address A<3:0>=0010)
Bit
Default
Mnemonic
Description
7:5
0.1.1
Not for customer use.
4:3
0.0
Not for customer use.
2:1
1.0
Not for customer use.
0
1
Not for customer use.
.
Table 11. Transmit PLL2, Register #3 (Address A<3:0>=0011)
Bit
Default
Mnemonic
Description
7
1
Not for customer use.
6
1
Not for customer use.
5
1
Not for customer use.
4
0
Not for customer use.
3
0
Not for customer use.
2
0
Not for customer use.
1:0
1.0
Not for customer use.
Table 12. Equalizer Load, Register #4 (Address A<3:0>=0100)
Bit
Default
Mnemonic
Description
7
0
Not for customer use.
6:2
0.0.0.0.0
Not for customer use.
1
0
Not for customer use.
0
1
Not for customer use.
Table 13. Equalizer & AGC, Register #5 (Address A<3:0>=0101)
28
Bit
Default
Mnemonic
Description
7
1
eq_adapt_enab
Equalizer adaption enable:
0 = freeze adaption
1 = activate adaption
6:5
0.0
eq_adapt_gain
Equalizer adaption step size:
00 = 1
01 = 2
10 = 4
11 = 8
4
1
agc_adapt_ena
AGC adaption enable:
0 = freeze adaption
1 = activate adaption
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 13. Equalizer & AGC, Register #5 (Address A<3:0>=0101) (Continued)
Bit
Default
Mnemonic
3:2
0.0
agc_adapt_gain
1
1
afe_ena
0
0
Description
AGC adaption step size:
00 = 1
01 = 2
10 = 4
11 = 8
Analog front end enable (also enables matching filter oscillator core):
0 = disabled (no bias)
1 = enabled
Not for customer use.
Table 14. Matching Filter 2, Register #6 (Address A<3:0>=0110)
Bit
Default
Mnemonic
Description
7:5
0.1.0
Not for customer use.
4:3
1.0
Not for customer use.
2:1
0.0
Not for customer use.
0
1
Not for customer use.
1. This register is used in CMI (co-ax) mode only.
Table 15. Slicer, Register #7 (Address A<3:0>=0111)
Bit
Default
Mnemonic
Description
7:4
0.0.0.0
3
1
2
0
Not for customer use.
1
0
Not for customer use.
0
0
Not for customer use.
Not for customer use.
-
Unused
Table 16. RxPLL 1, Register #8 (Address A<3:0>=1000)
Datasheet
Bit
Default
Mnemonic
Description
7:5
0.1.1
Not for customer use.
4:3
0.0
Not for customer use.
2
0
Not for customer use
1
0
Unused
0
1
Not for customer use.
29
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 17. Rx PLL 2, Register #9 (Address A<3:0>=1001)
Bit
Default
Mnemonic
7
1
Not for customer use.
6
1
Not for customer use.
5:3
0.1.1
2
1
Not for customer use.
1
1
Not for customer use.
0
1
Not for customer use.
freq_det_pw
Description
Frequency detector output pulse width ({1 to 8} * 6.43 ns)
Table 18. Test, Register #10 (Address A<3:0>=1010)
Bit
Default
Mnemonic
7
1
los_clk_ena
Description
Enables Rx clock switching under LOS/LOCK condition:
0 = disable
1 = enable
6
0
Not for customer use.
5:2
0.0.0.0
Not for customer use.
1
1
Not for customer use.
0
0
Not for customer use.
Table 19. Register, Bias and Fuse Controls, Register #11 (Address A<3:0>=1011)
Bit
Default
Mnemonic
Description
7
0
bias_pwrdn
6
1
reg_reset
5:2
1.0.0.0
Not for customer use.
1:0
0.0
Not for customer use.
Power down all bias generators. This bit can be used to power down
all the active analog circuitry on the device.
0= active
1=power down
Register array reset, ignores remainder of transaction (active low).
This register is write only.
.
Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100)
30
Bit
Default
Mnemonic
7
0
los_format
6
1
los_amp_trim
5:4
1.1
los_ena
Description
Combine (logical OR) LOS/LOCK function onto LOS pin:
0 = disable
1 = enable
Amplitude LOS threshold trim:
0 = Reduced ALOS dessert threshold (-3db)
1 = Nominal ALOS thresholds
LOS disable controls (amplitude LOS & digital LOS):
0 = disable
1 = enable
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100) (Continued)
Bit
Default
Mnemonic
Description
3
0
frame_ena
Byte align enable: If used, this feature must be enabled during system
configuration prior to applying data to the receiver. If this is not
possible see the Intel® LXT6155 155 Mbps SDH/SONET/ATM
Transceiver Application Note (Intel order number 249280) for further
details.
0 = byte align disabled
1 = byte align enabled
2
0
Not for customer use.
1
0
Not for customer use.
0
1
Not for customer use.
.
Table 21. Rx Digital 2, Register #13 (Address A<3:0>=11001)
Bit
Default
Mnemonic
7
1
rx_dig_reset
6:3
0.0.0.0
cnffp
2:1
1.0
los_tran_assert
Description
Rx digital circuitry reset. This can be used to minimize power
comsumption when the device is disabled but not powered down. It
must be enabled when the device is active
0 = reset
1 = normal operation
Frame pulse position. Refer to Figure 5 for usage.
D-LOS transition density count for assertion:
00 = 128
01 = 512
10 = 3112
11 = 4096
A-LOS assertion integration period:
00 = 2048 bits
01 = 512 bits
10 = 128 bits
11 = 32 bits
0
1
los_tran_deass
ert
D-LOS transition density count for de-assertion:
0 = 4/32
1 = SONET compliant1
A-LOS de-assertion integration period:
0 = 0 bits
1 = 128 bits
1. SONET compliant LOS de-assertion refers to Bellcore GR-253, pages 6-16 (section 6.2.1.1.1),
recommendation R6-54, LOS alarm is de-asserted (cleared) when two valid frame headers have been
received with no LOS events in the interval.
.
Table 22. Status Control, Register #14 (Address A<3:0>=1110)
Datasheet
Bit
Default
Mnemonic
7:4
0.0.0.0
-
3:0
0.0.0.0
stat_cont
Description
Unused
Status register (register #15) mux control (indirect addressing to
increase read space)
31
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 23. Read-Only Register #15 (Address A<3:0>=1111)
Value of:
stat_cont
00
(Status
register)
Status Output
bit 7
bit 6
bit 5
bit 4
Analog
LOS
Digital
LOS
Tx clock
activity
alarm
status
SONET
OOF
signal
01
Not for customer use.
02
Not for customer use.
03
bit 3
bit 2
Unused3
bit 1
bit 0
Rx PLL
frequency
lock alarm
Unused3
Not for customer use.
Not for customer use.
Not for customer use.
(Fuse
contentsupper bits)
04
Not for customer use.
Not for customer use.
(Fuse
contentsupper bits)
051,2
(Interrupt
register)
Analog
LOS
interrupt
Digital
LOS
interrupt
(los_ana_i)
(los_dig_i)
Tx clock
alarm
interrupt
OOF
interrupt
Unused3
(oof_i)
Unused3
Rx PLL
frequency
lock alarm
interrupt
CMI coding
error alarm
interrupts
(cmi_err_i)
(rx_lock_i)
064
MSB
LSB
(Device ID)
1.
2.
3.
4.
32
Bits 7:1 are cleared upon reading the status register (stat_cont = 00).
Bit 0 is cleared upon reading interrupt register (stat_cont = 05).
Ignore these bits during register transactions, unpredictable contents
Contains device revision number in hexadecimal notation.
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
4.0
Application Information
The following provides application examples of interfacing the Intel® LXT6155 to the line side and
the overhead terminator side. Line side encoding schemes can be one of two types: LVPECL NRZ
encoded for a fiber optic module, or CMI encoded for a 75 Ω coax cable. On the systems side,
serial differential or parallel eight-bit modes can be used. All signals are TTL level compatible,
except serial interface signals (TPOS, TNEG, TSICLKP, TSICLKN, RSOCLKP, RSOCLKN,
RPOS, and RNEG) which are 3.3 V LVPECL compatible.
4.1
Fiber Optic Module Interface
The Intel® LXT6155 is designed to directly drive a 3.3 V LVPECL fiber optic transceiver. The
LVPECL drivers require the proper transmission line impedance to correctly drive the fiber
module. Signal traces should be 50 Ω controlled impedance lines and should be biased to the
appropriate level. Please refer to Figure 16 for the proper interface.
To interface the Intel® LXT6155 LVPECL signals to a 5 V PECL fiber optic module, please refer
to the Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver Application Note (Intel order
number 249280).
4.2
Coax Interface
As shown in Figure 17 on page 35, the Intel® LXT6155 directly drives a transformer connected to
a 75 Ω coaxial cable, up to12.7 dB cable loss at 78 MHz. This is approximately 110 m of RG59U.
Please refer to manufacturers specifications for maximum cable lengths. Output CMI waveform
conform to the ITU G.703 specifications. Rise and fall times are less than 2.0 ns.
Datasheet
33
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
49
RXISH
330 nF
48
RAVCC
RAGND
RDGND
GND
TDGND
RAGND
SUB
TAVCC
RDVCC
PVCC
VCC
TDVCC
RAVCC
Well
53
42
35
11
50
57
5
41
38
25
6
46
38
TAVCC
DVCC
Figure 16. 3.3 V LVPECL to 3.3 V LVPECL Interface
VCC
R1
R2
50 Ω
Controlled
impedance
RTIP 52
VBIAS
RD
15k
1%
4
RRING 51
RD*
TXISH
VCC
68 nF
R3
Intel®
LXT6155
Transceiver
R5
NC
47
ATST
3.3V
Fiber Optic
Module
R4
R6
TTIP1 63
TD
TRING1 62
TD*
R7
R8
Notes:
1) R1, R2, R5, R6 = 127Ω, 1%
2) R3, R4, R7, R8 = 82.5Ω, 1%
3) Transmission lines should be 50Ω , controlled impedance strip lines.
Keep length as short as possible.
4) VCC = 3.3V for both resistor network, and Fiber Optic Module.
B0072-01
34
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
49
RAVCC
RAGND
RDGND
GND
TDGND
RAGND
SUB
TAVCC
RDVCC
PVCC
VCC
TDVCC
RAVCC
Well
53
42
35
11
50
57
5
41
38
25
6
46
38
TAVCC
DVCC
Figure 17. 75 Ω Coax Cable Interface
RXISH
330 nF
48
1.0 nF
75Ω coax
1:1
RTIP 52
VBIAS
15k
1%
37.5Ω
strip line
75Ω
1%
4
1.0 nF
75Ω
strip line
RRING 51
TXISH
VCC
68 nF
Intel®
LXT6155
Transceiver
37.5Ω
1%
NC
47
ATST
TTIP0
37.5Ω
1%
1:1
61
75Ω coax
37.5Ω
strip line
TRING0 60
1.0 nF
1.0 nF
B0073-01
.
Table 24. Transformer Specifications
Parameter
Min
Typ
-3 dB Low
Max
Unit
10
MHz
-
MHz
Notes
Transmission, S12
-3 dB High
320
-20 dB Low
5
MHz
-
MHz
In-band Loss
0.5
dB
30 MHz ~ 300 MHz
Common mode rejection
-10
dB
DC~250 MHz
-40
dB
DC~156 MHz
Return Loss, S11
-20 dB High
250
Cross-talk in dual packages
Turns ratio
Datasheet
0.97
1.0
1.03
35
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 25. Crystal Specifications
Parameter
Min
Typ
Center frequency
Max
19.44
Notes
MHz
At 25 °C
Freq tolerance
-20
20
ppm
Temperature drift
-20
20
ppm
-40 ~ 85 °C
Aging
-10
10
ppm
First 10 years
5
pF
Mode
Fundamental
Shunt capacitance
Equivalent resistance
8.4
Temperature Range
5.0
Unit
W
-40
°C
85
Test Specifications
Information in Table 26 through Table 36 and Figure 18 through Figure 28 represent the
performance specifications of the Intel® LXT6155 and are guaranteed by test, except as noted by
design.
Table 26. Absolute Maximum Ratings
Parameter
Sym
DC supply (reference to GND)
Min
Vcc
Max
Unit
4.0
V
Input voltage, TTL pins
Vin (TTL)
GND -0.3
5.5
V
Input voltage, other pins
Vin
GND -0.3
VCC + 0.3
V
Input current, any pin
Iin
-10
25
mA
Storage temperature
Tstg
-65
150
°C
Caution:
Operating at or beyond these limits may result in damage to the device.
Normal operation not guaranteed at these extremes.
Table 27. Recommended Operating Conditions
Parameter
Sym
Min
Typ
Max
Unit
DC supply (referenced to GND)
Vcc
3.0
3.3
3.6
V
Ambient operating temperature
Ta
-40
25
85
°C
Total current consumption
36
serial/fiber
150
serial/coax
210
parallel/fiber
100
parallel/coax
150
mA
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 28. DC Electrical Characteristics (Vcc = 3.0 V to 3.6 V; TA = -40 °C to 85 °C)
Parameter
Typ1
Sym
Min
Max
Unit
High level input voltage (LVPECL)
Vih1
Low level input voltage (LVPECL)
Vil1
Vcc-1.03
Vcc-0.88
V
Vcc-1.81
Vcc-1.62
V
High level output voltage (LVPECL)
Voh1
Vcc-1.03
Vcc-0.95
Vcc-0.88
V
Low level output voltage (LVPECL)
Vol1
Vcc-1.81
Vcc-1.70
Vcc-1.62
V
High level input voltage (TTL)
Vih2
2.0
Low level input voltage (TTL)
Vil2
Voh2
Low level output voltage (TTL)
50 Ω pulled
down to VCC 2.0 V.
V
0.8
High level output voltage (TTL)
Test Conditions
V
2.4
V
IOH = 4 mA
IOL = 4 mA
Vol2
0.4
V
Input leakage current, low (TTL)
Ill
10
µA
Input leakage current, high (TTL)
Ilh
10
µA
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
Table 29. Transmit Timing Characteristics (See Figure 18 and Figure 19)
Parameter
Sym
Min
Transmit serial input clock frequency
Typ1
Max
155.52
Unit
MHz
Transmit serial input clock frequency error
-20
+20
ppm
Transmit serial input clock duty cycle
45
55
%
1.2
ns
Transmit serial input clock and data rise /
fall time2
Transmit parallel input clock frequency
Test Conditions
19.44
Compliant with GR253
20% - 80%
MHz
Transmit parallel input clock frequency
error
-20
+20
ppm
Transmit parallel input clock duty cycle
45
55
%
Transmit parallel input data & clock rise/
fall time2
2
10
ns
TPICLK to TPID<0:7> hold time
Thtpid
3
ns
TPICLK to TPID<0:7> setup time
Tstpid
2
ns
TSICLKP(TSICLKN) to TPOS (TNEG)
setup time
Tstpos
1.25
ns
TSICLKP (TSICLKN) to TPOS (TNEG)
hold time
Thtpos
0.75
ns
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
2. Not production tested, guaranteed by design and other correlation factors.
Datasheet
37
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 18. Transmit Parallel Input Data Timing (See Table 29)
TPICLK*
TPID<0:7>
Tstpid
Thtpid
*HW mode timing shown. In SW mode (HWSEL=1) TPICLK polarity can be inverted. See Table 8 for details.
Figure 19. Transmit Serial Input Data Timing (See Table 29)
TSICLKP
TSICLKN
Tstpos
Thtpos
TPOS
TNEG
Table 30. Transmit Analog Characteristics
Parameters
Transmit jitter generation2
Note
Min
Typ1
12 kHz - 1.3 MHz
Max
Unit
0.1
UIpp
0.01
UIrm
s
(Intrinsic jitter SONET spec)
Transmit jitter generation2
500 Hz - 1.3 MHz
1.5
UIpp
(Intrinsic jitter SDH spec)
65 kHz - 1.3 MHz
0.075
UIpp
0.4
dB
Transmit jitter transfer
function peaking2
DC - 230 kHz
Synthesizer capture range
Fcap
-20
+20
ppm
Synthesizer track range
Ftrack
-20
+20
ppm
Synthesizer lock time
Tlock
100
µs
2.2
ns
1.1
Vpp
Transmit output rise and fall
times - CMI signals
TRING0
Transmit output amplitude CMI signals
TRING0
TTIP0/TRING0
output impedance
TTIP0
TTIP0
Zout
0.9
1.6
2.0
Test Conditions
PRBS(23) pattern.
Transmit input data and
clock have no input jitter.
Receive line input is all
zeros.
PRBS(23) data. Input jitter
as shown in Figure 26.
parallel mode
10% - 90%
0m cable length
kΩ
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
2. Not production tested, guaranteed by design and other correlation factors.
38
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 31. Receive Timing Characteristics (See Figure 20 and Figure 21)
Parameter
Sym
Receive serial output clock
frequency
RSOCLKp
Receive serial output clock
duty cycle
RSOCLKdc
Receive serial output clock
and data rise/fall time2
-
RSOCLKP/RSOCLKN to
RPOS/RNEG propagation
delay
RSOCLKpd
Min
Typ1
Max
155.5
2
RSOCLKn
45
-0.5
Unit
MHz
55
%
1.2
ns
1.5
ns
Receive parallel output clock
frequency
RPOCLK
Receive parallel output clock
duty cycle
RPOCPdc
45
55
%
Receive parallel output data
& clock rise/fall time
RPOCLKt
2
5
ns
RPOCLKpd
0
7
ns
RPOCLK to ROFP
propagation delay
ROFPpd
0
4
ns
Reference Input Clock into
XTALIN pin (TTL)
REFCLK
RPOCLK to RPOD<0:7>
propagation delay
Reference Clock Offset from
Nominal
19.44
20% - 80%.
MHz
19.44
-100
Test Conditions
MHz
100
The REFCLK replaces the
crystal
ppm
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
2. Not production tested, guaranteed by design and other correlation factors.
Figure 20. Receive Serial Output Data Timing (See Table 31)
RSOCLKP
RSOCLKN
RSOCLKPD
RPOS
RNEG
Datasheet
39
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 21. Receive Parallel Output Data Timing (See Table 31)
RPOCLK*
RPOCLKPD
RPOD<0:7>
ROFPPD
ROFP
*This shows timing in HW mode. In SW mode (HWSEL=1) this clock polarity can be inverted. See Table 8 for details.
Table 32. Receive Analog Characteristics
Parameter
End to end loss budget (coax)1
Note
Min
-
15
Typ1
Max
Test Conditions
dB
BER=1E-12. PRBS (23) data.
CMI encoded. Input white
noise = 5 mV RMS max.
Assert
20
µsec
No data transition. Default
LOS setting.
De-assert
187.5
µsec
No LOS events. Default LOS
settings.
LOS - fiber
LOS Thresholds - Coax
Unit
Assert
18
dB
De-assert
17
dB
HYS
1.0
4.0
dB
0.01
UIrms
0.1
UIpp
LOS hysteresis - coax
Receive jitter generation2
12 kHz - 1.3 MHz
(intrinsic jitter SONET spec)
2
500 Hz - 1.3 MHz
1.5
UIpp
(intrinsic jitter SDH spec)
65 kHz - 1.3 MHz
0.075
UIpp
DC - 230 kHz
0.4
dB
Receive jitter generation
Receive jitter transfer peaking2
Receive jitter tolerance
2
PLL nominal center frequency
0.1 Hz - 19.3 Hz
39
UIpp
500 Hz - 6.5 kHz
1.5
UIpp
65 kHz -
0.15
UIpp
Fnom
155.5
2
Attenuation measured at
78 MHz, CMI, 75 Ω load.
12.7 dB cable loss plus
remaining flat loss.
Measured from the level
where LOS is asserted.
PRBS(23) data.
CMI encoded PRBS(23) at
RTIP/RRING with no data
jitter. Transmit input = all
zeros Refer to Figure 27 and
Table 35.
PRBS(23) Data. Input jitter as
the max. tolerance curve
shown in Figure 26.
BER=1E-10. Tolerated jitter
meets Figure 26
MHz
PLL capture range
Fcap
-20
+20
ppm
PLL track range
Ftrack
-20
+20
ppm
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to production
testing.
2. Not production tested, guaranteed by design and other correlation factors.
40
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 32. Receive Analog Characteristics (Continued)
Parameter
Note
PLL lock time
Min
Tlock
Equalizer adaptation time
Line input impedance
RIN
(RTIP and RRING)
Typ1
Max
Unit
Test Conditions
100
µs
PRBS(23) pattern, from data
applied at RTIP/RRING.
Device in fiber optic mode.
500
bits
From data applied
kΩ
Differential resistance
4
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to production
testing.
2. Not production tested, guaranteed by design and other correlation factors.
Table 33. Serial Control Timing
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions1
25
ns
Load 1.6 mA, 50 pF
Rise/Fall time - All TTL outputs
tRF
SDI to SCLK setup time
tDC
5
ns
SCLK to SDI hold time
tCDH
5
ns
SCLK low time
tCL
120
ns
SCLK high time
tCH
120
ns
SCLK rise and fall time
tR, tF
CS to SCLK setup time
tCC
5
ns
SCLK to CS hold time
tCCH
5
ns
CS inactive time
tCWH
5
ns
SCLK to SDO valid
tCDV
0
20
ns
SCLK falling edge to SDO high Z
tCDZ
0
20
ns
tCZ
0
20
ns
CS rising edge to SDO high Z
25
ns
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
Figure 22. Microprocessor Input Timing Diagram
CS
tCC
tCCH
tCH
tCWH
tCL
SCLK
tDC
SDI
tCDH
R/W
CONTROL BYTE
Datasheet
DATA BYTE
41
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 23. Microprocessor Output Timing Diagram
CS
tCZ
SCLK
tCDV
SDO
tCDZ
High Z
High Z
Figure 24. CMI Encoded Zero per G.703 and STS-3
T = 6.43 ns
V
0.60
0.55
0.50
0.45
0.40
(Note 1)
(Note 1)
1 ns
0.1 ns
1.608 ns
1 ns
0.1 ns
0.35 ns
Nominal
zero
level
(Note 2)
0.35 ns
Nominal
pulse
1.608 ns
1 ns
0.1 ns
0.1 ns
0.05
–0.05
1 ns
–0.40
–0.45
–0.50
–0.55
–0.60
1 ns
1 ns
1.608 ns
1.608 ns
(Note 1)
(Note 1)
T1818930-92
Negative transitions
Positive transition at mid-unit interval
42
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 25. CMI Encoded One per G.703 and STS-3
T = 6.43 ns
V
0.60
0.55
0.50
0.45
0.40
(Note 1)
(Note 1)
1 ns
0.1 ns
Nominal
pulse
0.1 ns
1 ns
(Note 4)
0.5 ns 0.5 ns
Nominal 0.05
zero
level
– 0.05
(Note 2)
3.215 ns
3.215 ns
1.2 ns
1.2 ns
1 ns
– 0.40
– 0.45
– 0.50
– 0.55
– 0.60
1 ns
1.608 ns
1.608 ns
(Note 1)
Negative transition
Positive transition
T1818940-92
Note:
The maximum “steady state” amplitude should not exceed the 0.55 V limit. Overshoots and other
transients are permitted to fall into the dotted area.
Note:
With the signal applied, the vertical position of the trace can be adjusted with the objective of
meeting the limits of the masks. Any such adjustment should be the same for both masks and
should not exceed ±0.05 V.
Table 34. Jitter Tolerance (in UIpp)
Frequency
OC3
10 Hz
15
19.3 Hz
39
30 Hz
15
300 Hz
1.5
500 Hz
Datasheet
STM1
1.5
6.5 kHz
1.5
1.5
65 kHz
0.15
0.15
1.3 MHz
0.15
0.15
43
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 26. Jitter Tolerance
100
Input Jitter [UI(pk-pk)]
Measured Data
OC3 Template
10
STM1 Template
1
0.1
10Hz
1Hz
100Hz
1KHz
10KHz
Frequency
100KHz
1MHz
10MHz
Table 35. Jitter Generation
Signal
f1
f2
Measured Jitter
OC3
12 kHz
1.3 MHz
0.01 UI rms
0.1 UIpp
500 Hz
1.3 MHz
1.5 UIpp
65 kHz
1.3 MHz
0.075 UIpp
STM1
Table 36. Jitter Transfer
44
Signal
f1
A1
Unit
OC3
230 kHz
0.4
dB
STM1
230 kHz
0.4
dB
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 27. Generation Measurement Filter Characteristics
Figure 28. Typical Coax Jitter Transfer
10
A1 0
-10
Gain
Coax mode
LXT6155 spec.
-20
ITU G.825 template
-30
-40
1
10
100
1000
10000
Frequency [Hz]
Note:
Datasheet
100000
1000000 1000000
0
f1
Measured with the device in remote loopback. Data reflects total jitter in both Tx and Rx path.
45
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Figure 29. Typical Fiber Jitter Transfer
10
A1 0
Gain
-10
Fiber mode
Intel® LXT6155 ATM Transceiver spec.
ITU G.825 spec.
-20
-30
-40
1
10
1000
100
10000
100000
Frequency (Hz)
1000000
1E+07
f1
B0074-01
Note:
6.0
Measured with the device in remote loopback. Data reflects total jitter in both Tx and Rx path.
Mechanical Specifications
Figure 30. Intel® LXT6155LE Package Specification
D
D1
e/
2
for sides with even
number of pins
e
E1
for sides with odd
number of pins
E
θ3
L1
A2
A
θ
A1
L
46
B
θ3
Datasheet
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Table 37. Intel® LXT6155LE Package Specification (64-Pin Low-Profile Quad Flat Pack [Part
Number Intel® LXT6155LE, Extended Temperature Range: -40 °C to 85 °C])
Inches
Millimeters
Dim
Min
Max
A
Min
Max
.063
1.60
A1
.002
.006
0.05
0.15
A2
.053
.057
1.35
1.45
B
.007
.011
0.17
0.27
1
12.00 BSC
D1
1
0.394 BSC
10.00 BSC1
E
0.472 BSC1
12.00 BSC1
E1
0.394 BSC1
10.00 BSC1
D
0.472 BSC
1
e
L
0.50 BSC1
0.020 BSC
0.018
L1
1
0.030
0.45
0.039 REF
0.75
1.00 REF
θ3
11°
13°
11°
13°
q
0°
7°
0°
7°
1. BSC—Basic Spacing between Centers
Datasheet
47
Intel® LXT6155 155 Mbps SDH/SONET/ATM Transceiver
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Datasheet