LXT384 Octal T1/E1/J1 Line Interface Unit Datasheet The LXT384 is an octal short haul Pulse Code Modulation (PCM) Line Interface Unit for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates eight independent receivers and eight independent transmitters in a single 144 pin LQFP or 160 ball PBGA package. The LXT384 transmits shaped waveforms meeting G.703 and T1.102 specifications. The transmit drivers provide low impedance independent of the transmit pattern and supply voltage variations. The LXT384 exceeds the latest transmit return loss specifications, such as ETSI ETS300166. All transmitters include a power down mode with fast output tristate capability. The LXT384’s differential receiver architecture provides high noise interference margin and is able to work with up to 12 dB of cable attenuation. The optional digital clock recovery PLL and jitter attenuator are referenced to a low frequency 1.544 MHz or 2.048 MHz clock. The LXT384 incorporates an advanced crystal-less jitter attenuator switchable between the receive and transmit path. The jitter attenuation performance meets the latest international specifications such as CTR12/13. The jitter attenuation performance was optimized for Sychronous Optical NETwork/Sychronous Digital Hierarchy (SONET/SDH) applications. The LXT384 can be configured as a 7 channel transceiver with G.772 compliant non intrusive protected monitoring points. The LXT384 includes Hitless Protection Switching (HPS) feature which helps increase quality of service and eliminates relays in redundancy and 1+1 protection applications. Fast tristate-able drivers and a constant delay jitter attenuator are critical to achieving HPS. Product Features ■ ■ ■ ■ Single rail 3.3V supply with 5V tolerant inputs Low power consumption of 130mW per channel (typ.) Superior crystal-less jitter attenuator — Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications — Optimized for SONET/SDH applications, meets ITU G.783 mapping jitter specification — Constant throughput delay jitter attenuator Hitless Protection Switching (HPS) for 1 to 1 protection without relays ■ ■ ■ ■ ■ ■ ■ ■ ■ Transmit return loss exceeds ETSI ETS 300166 HDB3, B8ZS, or AMI line encoder/decoder Provides protected monitoring points per ITU G.772 Analog/digital and remote loopback testing functions LOS per ITU G.775, ETS 300 233 and T1.231 8 bit parallel or 4 wire serial control interface Hardware and Software control modes JTAG Boundary Scan test port per IEEE 1149.1 144 pin LQFP and 160 ball PBGA packages As of January 15, 2001, this document replaces the Level One document known as Octal T1/E1 Transceiver. Order Number: 248994-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT384 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Octal T1/E1/J1 Line Interface Unit — LXT384 Contents 1.0 Pin Assignments and Signal Descriptions.......................................................................... 9 2.0 Functional Description......................................................................................................22 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Initialization..........................................................................................................22 2.1.1 Reset Operation .....................................................................................23 Receiver ..............................................................................................................23 2.2.1 Loss of Signal Detector ..........................................................................23 2.2.1.1 E1 Mode ....................................................................................24 2.2.1.2 T1 Mode ....................................................................................24 2.2.1.3 Data Recovery Mode.................................................................24 2.2.2 Alarm Indication Signal (AIS) Detection .................................................24 2.2.2.1 E1 Mode ....................................................................................24 2.2.2.2 T1 Mode ....................................................................................25 2.2.3 Receive Alarm Indication Signal (RAIS) .................................................25 2.2.4 In Service Code Violation Monitoring .....................................................25 Transmitter ..........................................................................................................25 2.3.1 Transmit Pulse Shaping .........................................................................26 2.3.1.1 Hardware Mode .........................................................................26 2.3.1.2 Host Mode .................................................................................26 2.3.1.3 Output Driver Power Supply ......................................................27 2.3.1.4 Power Sequencing ....................................................................27 Driver Failure Monitor..........................................................................................27 Line Protection ....................................................................................................30 Jitter Attenuation .................................................................................................30 Loopbacks ...........................................................................................................31 2.7.1 Analog Loopback....................................................................................31 2.7.2 Digital Loopback.....................................................................................32 2.7.3 Remote Loopback ..................................................................................32 2.7.4 Transmit All Ones (TAOS)......................................................................32 G.772 Performance Monitoring ...........................................................................33 Hitless Protection Switching (HPS) .....................................................................34 Operation Mode Summary ..................................................................................34 Interfacing with 5V Logic .....................................................................................35 Parallel Host Interface .........................................................................................35 2.12.1 Motorola Interface ..................................................................................36 2.12.2 Intel Interface..........................................................................................36 Interrupt Handling................................................................................................36 2.13.1 Interrupt Sources....................................................................................36 2.13.2 Interrupt Enable......................................................................................37 2.13.3 Interrupt Clear ........................................................................................37 Serial Host Mode.................................................................................................37 3.0 Register Descriptions ....................................................................................................... 38 4.0 JTAG Boundary Scan.......................................................................................................45 4.1 4.2 Datasheet Overview .............................................................................................................45 Architecture .........................................................................................................45 3 LXT384 — Octal T1/E1/J1 Line Interface Unit 4.3 4.4 5.0 Test Specifications ........................................................................................................... 54 5.1 6.0 TAP Controller..................................................................................................... 46 JTAG Register Description.................................................................................. 48 4.4.1 Boundary Scan Register (BSR).............................................................. 49 4.4.2 Analog Port Scan Register (ASR) .......................................................... 52 4.4.3 Device Identification Register (IDR) ....................................................... 53 4.4.4 Bypass Register (BYR) .......................................................................... 53 4.4.5 Instruction Register (IR) ......................................................................... 53 Recommendations and Specifications ................................................................ 76 Mechanical Specifications................................................................................................ 78 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 LXT384 Detailed Block Diagram ........................................................................... 7 LXT384 Detailed Block Diagram ........................................................................... 8 LXT384 Low-Profile Quad Flate Package (LQFP) 144-Pin Assignments and Package Markings9 LXT384 Plastic Ball Grid Array (PBGA) Package Pin Assignments ................... 10 50% AMI Encoding.............................................................................................. 26 External Transmit/Receive Line Circuitry ............................................................ 29 Jitter Attenuator Loop.......................................................................................... 31 Analog Loopback ................................................................................................ 31 Digital Loopback.................................................................................................. 32 Remote Loopback ............................................................................................... 32 TAOS Data Path ................................................................................................. 33 TAOS with Digital Loopback ............................................................................... 33 TAOS with Analog Loopback .............................................................................. 33 Serial Host Mode Timing..................................................................................... 38 JTAG Architecture............................................................................................... 46 JTAG State Diagram ........................................................................................... 48 Analog Test Port Application............................................................................... 53 Transmit Clock Timing Diagram.......................................................................... 61 Receive Clock Timing Diagram........................................................................... 62 JTAG Timing ....................................................................................................... 63 Non-Multiplexed Intel Mode Read Timing ........................................................... 64 Multiplexed Intel Mode Read Timing................................................................... 64 Non-Multiplexed Intel Mode Write Timing ........................................................... 66 Multiplexed Intel Mode Write Timing ................................................................... 66 Non-Multiplexed Motorola Mode Read Timing.................................................... 68 Multiplexed Motorola Mode Read Timing............................................................ 68 Non-Multiplexed Motorola Mode Write Timing .................................................... 69 Multiplexed Motorola Mode Write Timing ............................................................ 70 Serial Input Timing .............................................................................................. 71 Serial Output Timing ........................................................................................... 71 E1, G.703 Mask Templates................................................................................. 72 T1, T1.102 Mask Templates ............................................................................... 73 LXT384 Jitter Tolerance Performance ................................................................ 74 LXT384 Jitter Transfer Performance................................................................... 75 LXT384 Output Jitter for CTR12/13 Applications ................................................ 76 Datasheet Octal T1/E1/J1 Line Interface Unit — LXT384 36 37 Low Quad Flat Packages (LQFP) Dimensions....................................................78 Plastic Ball Grid Array (PBGA) Package Dimensions .........................................79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 LXT384 Pin Description.......................................................................................11 Line Length Equalizer Inputs...............................................................................27 Jitter Attenuation Specifications ..........................................................................30 Operation Mode Summary ..................................................................................34 Microprocessor Interface Selection .....................................................................35 Serial and Parallel Port Register Addresses .......................................................38 Register Bit Names .............................................................................................39 ID Register, ID (00h) ...........................................................................................40 Analog Loopback Register, ALOOP (01h) ..........................................................40 Remote Loopback Register, RLOOP (02h).........................................................40 TAOS Enable Register, TAOS (03h)...................................................................40 LOS Status Monitor Register, LOS (04h) ............................................................41 DFM Status Monitor Register, DFM (05h)...........................................................41 LOS Interrupt Enable Register, LIE (06h) ...........................................................41 DFM Interrupt Enable Register, DIE (07h) ..........................................................41 LOS Interrupt Status Register, LIS (08h) ............................................................41 DFM Interrupt Status Register, DIS (09h) ...........................................................41 Software Reset Register, RES (0Ah) ..................................................................42 Performance Monitoring Register, MON (0Bh) ...................................................42 Digital Loopback Register, DL (0Ch)...................................................................42 LOS/AIS Criteria Register, LCS (0Dh) ................................................................42 Automatic TAOS Select Register, ATS (0Eh) .....................................................42 Global Control Register, GCR (0Fh) ...................................................................43 Pulse Shaping Indirect Address Register, PSIAD (10h)......................................43 Pulse Shaping Data Register, PSDAT (11h).......................................................44 Output Enable Register, OER (12h)....................................................................44 AIS Status Monitor Register, AIS (13h)...............................................................44 AIS Interrupt Enable Register, AISIE (14h) .........................................................44 AIS Interrupt Status Register, AISIS (15h) ..........................................................45 TAP State Description .........................................................................................46 Boundary Scan Register (BSR)...........................................................................49 Analog Port Scan Register (ASR) .......................................................................52 Device Identification Register (IDR) ....................................................................53 Instruction Register (IR) ......................................................................................54 Absolute Maximum Ratings.................................................................................54 Recommended Operating Conditions .................................................................55 DC Characteristics ..............................................................................................55 E1 Transmit Transmission Characteristics..........................................................56 E1 Receive Transmission Characteristics...........................................................57 T1 Transmit Transmission Characteristics ..........................................................58 T1 Receive Transmission Characteristics ...........................................................58 Jitter Attenuator Characteristics ..........................................................................59 Analog Test Port Characteristics.........................................................................60 Transmit Timing Characteristics..........................................................................60 Receive Timing Characteristics...........................................................................61 Tables Datasheet 5 LXT384 — Octal T1/E1/J1 Line Interface Unit 46 47 48 49 50 51 52 53 54 6 JTAG Timing Characteristics .............................................................................. 62 Intel Mode Read Timing Characteristics2 ........................................................... 63 Intel Mode Write Timing Characteristics2 ........................................................... 65 Motorola Bus Read Timing Characteristics2....................................................... 67 Motorola Mode Write Timing Characteristics2 .................................................... 69 Serial I/O Timing Characteristics......................................................................... 70 Transformer Specifications ................................................................................. 71 G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 72 T1.102 1.544 Mbit/s Pulse Mask Specifications.................................................. 72 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Applications ■ ■ ■ SONET/SDH tributary interfaces Digital cross connects Public/private switching trunk line interfaces ■ ■ Microwave transmission systems M13, E1-E3 MUX Figure 1. LXT384 Detailed Block Diagram MODE JTAG SERIAL/ PARALLEL PORT LOOP 0..7 HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) JASEL CLKE MCLK LOS LOS TRING LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK DATA CLOCK CLOCK RECOVERY DIGITAL LOOPBACK TTIP G.772 MONITOR RRING ANALOG LOOPBACK DATA SLICER RTIP RPOS B8ZS / HDB3 DECODER RCLK RNEG TPOS B8ZS / HDB3 ENCODER TCLK TNEG 0 1 2 3 4 5 6 7 Datasheet 7 LXT384 — Octal T1/E1/J1 Transceiver Figure 2. LXT384 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT MODE LOOP 0..7 JASEL CLKE MCLK HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) Transceiver 7 LOS7 LOS RRING7 TTIP7 DATA CLOCK CLOCK RECOVERY LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH TRING7 REMOTE LOOPBACK ANALOG LOOPBACK RTIP7 DIGITAL LOOPBACK DATA SLICER B8ZS / HDB3 DECODER RPOS7 RCLK7 RNEG7 B8ZS / HDB3 ENCODER TPOS7 TCLK7 TNEG7 LOS6 RPOS6/RNEG6/RCLK6 TPOS6/TNEG6/TCLK6 RTIP6/RRING6 Transceiver 6 TTIP6/TRING6 LOS5 RTIP5/RRING5 RTIP4/RRING4 TTIP4/TRING4 RTIP3/RRING3 TTIP3/TRING3 RTIP2/RRING2 G.772 Protected Monitoring Point TTIP5/TRING5 Transceiver 5 RPOS5/RNEG5/RCLK5 TPOS5/TNEG5/TCLK5 LOS4 Transceiver 4 RPOS4/RNEG4/RCLK4 TPOS4/TNEG4/TCLK4 LOS3 Transceiver 3 RPOS3/RNEG3/RCLK3 TPOS3/TNEG3/TCLK3 LOS2 Transceiver 2 RPOS2/RNEG2/RCLK2 TPOS2/TNEG2/TCLK2 TTIP2/TRING2 RTIP1/RRING1 LOS1 Transceiver 1 RPOS1/RNEG1/RCLK1 TPOS1/TNEG1/TCLK1 TTIP1/TRING1 Transceiver 0 LOS0 LOS TRING0 DATA CLOCK CLOCK RECOVERY LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK TTIP0 MUX DIGITAL LOOPBACK RTIP0 RRING0 ANALOG LOOPBACK DATA SLICER B8ZS / HDB3 DECODER RPOS0 RCLK0 RNEG0 B8ZS / HDB3 ENCODER TPOS0 TCLK0 TNEG0 A3 - A0 8 Datasheet Octal T1/E1/J1 Transceiver — LXT384 1.0 Pin Assignments and Signal Descriptions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 TNEG7/UBS7 RCLK7 RPOS7/RDATA7 RNEG7/BPV7 LOS7 RTIP7 RRING7 TVCC7 TTIP7 TRING7 TGND7 RRING6 RTIP6 TGND6 TRING6 TTIP6 TVCC6 RTIP5 RRING5 TVCC5 TTIP5 TRING5 TGND5 RRING4 RTIP4 TGND4 TRING4 TTIP4 TVCC4 CLKE OE LOS4 RNEG4/BPV4 RPOS4/RDATA4 RCLK4 TNEG4/UBS4 Figure 3. LXT384 Low-Profile Quad Flate Package (LQFP) 144-Pin Assignments and Package Markings 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Part # LOT # FPO # LXT384LE XX XXXXXX XXXXXXXX Rev # 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TPOS4/TDATA4 TCLK4 LOS5 RNEG5/BPV5 RPOS5/RDATA5 RCLK5 TNEG5/UBS5 TPOS5/TDATA5 TCLK5 TDI TDO TCK TMS TRST AT1 AT2 VCCIO1 GNDIO1 VCC1 GND1 MOT/INTL/CODEN CS/JASEL ALE/SCLK/AS/LEN2 R/W/RD/LEN1 DS/WR/SDI/LEN0 ACK/RDY/SDO INT TCLK2 TPOS2/TDATA2 TNEG2/UBS2 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 LOS2 TCLK3 TPOS3/TDATA3 TPOS0/TDATA0 TNEG0/UBS0 RCLK0 RPOS0/RDATA0 RNEG0/BPV0 LOS0 MUX TVCC0 TTIP0 TRING0 TGND0 RTIP0 RRING0 TGND1 TRING1 TTIP1 TVCC1 RRING1 RTIP1 TVCC2 TTIP2 TRING2 TGND2 RTIP2 RRING2 TGND3 TRING3 TTIP3 TVCC3 RRING3 RTIP3 LOS3 RNEG3/BPV3 RPOS3/RDATA3 RCLK3 TNEG3/UBS3 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TPOS7/TDATA7 TCLK7 LOS6 RNEG6/BPV6 RPOS6/RDATA6 RCLK6 TNEG6/UBS6 TPOS6/TDATA6 TCLK6 MCLK MODE A4 A3 A2 A1 A0 VCCIO0 GNDIO0 VCC0 GND0 LOOP0/D0 LOOP1/D1 LOOP2/D2 LOOP3/D3 LOOP4/D4 LOOP5/D5 LOOP6/D6 LOOP7/D7 TCLK1 TPOS1/TDATA1 TNEG1/UBS1 RCLK1 RPOS1/RDATA1 RNEG1/BPV1 LOS1 TCLK0 Package Topside Markings Marking Definition Part # Unique identifier for this product family. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Datasheet Identifies the Finish Process Order. 9 LXT384 — Octal T1/E1/J1 Transceiver Figure 4. LXT384 Plastic Ball Grid Array (PBGA) Package Pin Assignments 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A RCLK 4 RPOS 4 RNEG 4 TVCC 4 TRING 4 TGND 4 RTIP 4 RTIP 7 TGND 7 TRING 7 TVCC 7 RNEG 7 RPOS 7 RCLK 7 A B TCLK 4 TPOS 4 TNEG 4 TVCC 4 TTIP 4 TGND 4 RRING 4 RRING 7 TGND 7 TTIP 7 TVCC 7 TNEG 7 TPOS 7 TCLK 7 B C RCLK 5 RPOS 5 RNEG 5 TVCC 5 TRING 5 TGND 5 RTIP 5 RTIP 6 TGND 6 TRING 6 TVCC 6 RNEG 6 RPOS 6 RCLK 6 C D TCLK 5 TPOS 5 TNEG 5 TVCC 5 TTIP 5 TGND 5 RRING RRING 5 6 TGND 6 TTIP 6 TVCC 6 TNEG 6 TPOS 6 TCLK 6 D E OE CLKE LOS 5 LOS 4 LOS 7 LOS 6 MODE MCLK E F TCK TDO TDI TMS A 4 A 3 A 2 A 1 F G VCCIO 1 AT 2 TRST GNDIO 1 GNDIO A 0 LOOP 0 VCCIO 0 0 G H VCC 1 AT 1 MOT GND 1 GND 0 LOOP 1 LOOP 2 VCC 0 H J DS R/W ALE CS LOOP 3 LOOP 4 LOOP 5 LOOP 6 J K ACK INT LOS 2 LOS 3 LOS 0 LOS 1 MUX LOOP 7 K L TCLK 2 TPOS 2 TNEG 2 TVCC 2 TTIP 2 TGND 2 RRING RRING 2 1 TGND 1 TTIP 1 TVCC 1 TNEG 1 TPOS 1 TCLK 1 L M RCLK 2 RPOS 2 RNEG 2 TVCC 2 TRING 2 TGND 2 RTIP 2 RTIP 1 TGND 1 TRING 1 TVCC 1 RNEG 1 RPOS 1 RCLK 1 M N TCLK 3 TPOS 3 TNEG 3 TVCC 3 TTIP 3 TGND 3 RRING RRING 3 0 TGND 0 TTIP 0 TVCC 0 TNEG 0 TPOS 0 TCLK 0 N P RCLK 3 RPOS 3 RNEG 3 TVCC 3 TRING 3 TGND 3 RTIP 3 RTIP 0 TGND 0 TRING 0 TVCC 0 RNEG 0 RPOS 0 RCLK 0 P 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10 LXT384BE (BOTTOM VIEW) Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 1 of 12) Pin # QFP Ball # PBGA 1 1 Symbol I/O1 B2 TPOS7 DI Transmit Positive Data Input. B2 TDATA7 DI Transmit Data Input. Description Transmit Clock Input. During normal operation TCLK is active, and TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is Low, the output drivers enter a low power high-Z mode. If TCLK is High for more than 16 clock cycles, the pulse shaping circuit is disabled and the transmit output pulse widths are determined by the TPOS and TNEG duty cycles. TCLK Clocked 2 B1 TCLK7 DI Operating Mode Normal operation H TAOS (if MCLK supplied) H Disable transmit pulse shaping (when MCLK is not available) L Driver outputs enter tri-state When pulse shaping is disabled, it is possible to overheat and damage the LXT384 device by leaving transmit inputs high continuously. For example a programmable ASIC might leave all outputs high until it is programmed. To prevent this, clock one of these signals: TPOS, TNEG, TCLK or MCLK. Another solution is to set one of these signals low: TPOS, TNEG, TCLK, or OE. Note: The TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. 3 E3 LOS6 DO Loss of Signal Output. LOS output is High, indicating a loss of signal, when the incoming signal has no transitions for a specified time interval. The LOS condition is cleared and the output pin returns to Low when the incoming signal has sufficient number of transitions in a specified time interval (details in LOS functional description). 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 11 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 2 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Receive Negative Data Output. Bipolar Violation Detect Output. Receive Positive Data Output. Receive Data Output Bipolar Mode: 4 C3 RNEG6 DO 4 C3 BPV6 DO 5 C2 RPOS6 DO 5 C2 RDATA6 DO In clock recovery mode, these pins act as active High bipolar non return to zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING. A High signal on RNEG corresponds to receipt of a negative pulse on RTIP/ RRING. These signals are valid on the falling or rising edges of RCLK depending on the CLKE input. In Data recovery mode, these pins act as RZ data receiver outputs. The output polarity is selectable with CLKE (Active High output polarity when CLKE is High and Active Low Polarity when CLKE is Low). RPOS and RNEG will go to the high impedance state when the MCLK pin is Low. Unipolar Mode: In uni-polar mode, the LXT384 asserts BPV High if any in-service Line Code Violation is detected. RDATA acts as the receive data output. Hardware Mode: During a LOS condition, RPOS and RNEG will remain active. Host Mode: RPOS and RNEG will either remain active or insert AIS into the receive path. Selection is determined by the RAISEN bit in the GCR register. Receive Clock Output. Normal Mode: 6 C1 RCLK6 DO This pin provides the recovered clock from the signal received at RTIP and RRING. Under LOS conditions there is a transition from RCLK signal (derived from the recovered data) to MCLK signal at the RCLK output. Data Recovery Mode: If MCLK is High, the clock recovery circuit is disabled and RPOS and RNEG are internally connected to an EXOR that is fed to the RCLK output for external clock recovery applications. RCLK will be in high impedance state if the MCLK pin is Low. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 12 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 3 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Transmit Negative Data Input. Unipolar/Bipolar Select Input. Transmit Positive Data Input. Transmit Data Input. Bipolar Mode: TPOS/TNEG are active High NRZ inputs. TPOS indicates the transmission of a positive pulse whereas TNEG indicates the transmission of a negative pulse. 7 D3 TNEG6 DI 7 D3 UBS6 DI 8 D2 TPOS6 DI 8 D2 TDATA6 DI TPOS TNEG Selection 0 0 Space 1 0 Positive Mark 0 1 Negative Mark 1 1 Space Unipolar Mode: When TNEG/UBS is pulled High for more than 16 consecutive TCLK clock cycles, unipolar I/O is selected. In unipolar mode, B8ZS/HDB3 or AMI encoding/decoding is determined by the CODEN pin (hardware mode) or by the CODEN bit in the GCR register (software mode). TDATA is the data input in unipolar I/O mode. 9 D1 TCLK6 DI Transmit Clock Input. Master Clock Input. MCLK is an independent, free-running reference clock. It’s frequency should be 1.544 MHz for T1 operation and 2.048 MHz for E1 operation. This reference clock is used to generate several internal reference signals: • Timing reference for the integrated clock recovery unit • Timing reference for the integrated digital jitter attenuator • Generation of RCLK signal during a loss of signal condition • Reference clock during a blue alarm transmit all ones condition 10 E1 MCLK DI • Reference timing for the parallel processor wait state generation logic If MCLK is High, the PLL clock recovery circuit is disabled. In this mode, the LXT384 operates as simple data receiver. If MCLK is Low, the complete receive path is powered down and the output pins RCLK, RPOS and RNEG are switched to tri-state mode. MCLK is not required if LXT384 is used as a simple analog front-end without clock recovery and jitter attenuation. Note: Wait state generation via RDY/ACK is not available if MCLK is not provided. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 13 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 4 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Mode Select Input. This pin is used to select the operating mode of the LXT384. In Hardware Mode, the parallel processor interface is disabled and hardwired pins are used to control configuration and report status. In Parallel Host Mode, the parallel port interface pins are used to control configuration and report status. In Serial Host mode, the serial interface pins: SDI, SDO, SCLK and CS are used. 11 E2 MODE DI MODE Operating Mode Low Hardware Mode High Parallel Host Mode Vcc/2 Serial Host Mode For Serial Host Mode, the pin should connected to a resistive divider consisting of two 10 kΩ resistors across VCC and Ground. 12 F4 A4 DI Address Select Input. In non-multiplexed host mode, this pin is Address 4 input pin. In hardware mode, this pin must be connected to Ground. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 14 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 5 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Protected Monitoring/Address Select Inputs. Hardware Mode In hardware mode, these pins are used to select a specific port for non intrusive monitoring. During protection monitoring receiver 0 inputs are internally connected to a specific transmit or receive port. Receiver 0 routes the data from the selected port to its data and clock recovery circuits. The data on the monitor port can be routed to TTIP0/TRING0 by activating the remote loopback for channel 0 (TCLK0 must be active in order for this operation to take place). In addition, the recovered clock and data can be observed at the RCLK0/RPOS0/RNEG0 outputs. If A0, A1, and A2 are Low, the LXT384 is configured as octal line transceiver without monitoring capability. A3 A2 A1 A0 Selection 0 0 0 0 No Protection Monitoring 0 0 0 1 Receiver 1 0 0 1 0 Receiver 2 0 0 1 1 Receiver 3 0 1 0 0 Receiver 4 13 F3 A3 DI 14 F2 A2 DI 15 F1 A1 DI 0 1 0 1 Receiver 5 16 G3 A0 DI 0 1 1 0 Receiver 6 0 1 1 1 Receiver 7 1 0 0 0 No Protection Monitoring 1 0 0 1 Transmitter 1 1 0 1 0 Transmitter 2 1 0 1 1 Transmitter 3 1 1 0 0 Transmitter 4 1 1 0 1 Transmitter 5 1 1 1 0 Transmitter 6 1 1 1 1 Transmitter 7 Transmitter monitoring is not supported when the respective channel is set to analog loopback mode. Host Mode In non-multiplexed host mode, these pins function as non-multiplexed address pins. 17 G1 VCCIO0 S Power (I/O). 18 G4 GNDIO0 S Ground (I/O). 19 H1 VCC0 S Power (Core). 20 H4 GND0 S Ground (Core). 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 15 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 6 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Loopback Mode Select/Parallel Data bus Input &Output. Host Mode When a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data port. When a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs A0 -A7. 21 G2 LOOP0/D0 DI/O 22 H3 LOOP1/D1 DI/O 23 H2 LOOP2/D2 DI/O 24 J4 LOOP3/D3 DI/O 25 J3 LOOP4/D4 DI/O 26 J2 LOOP5/D5 DI/O 27 J1 LOOP6/D6 DI/O 28 K1 LOOP7/D7 DI/O In serial Mode, D0-7 should be grounded. Hardware Mode In hardware mode, the LXT384 works in normal operation if this pin is left open (unconnected). The LXT384 enters remote loopback mode, if this pin is Low. In this mode, data on TPOS and TNEG is ignored and data received on RTIP and RRING is looped around and retransmitted on TTIP and TRING. Note: in data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. The LXT384 enters analog local loopback mode, if this pin is High. In this mode, data received on RTIP and RRING is ignored and data transmitted on TTIP and TRING is internally looped around and routed back to the receive inputs. Note: When these inputs are left open, they stay in a high impedance state. Therefore, the layout design should not route signals with fast transitions near the LOOP pins. This practice will minimize capacitive coupling. 29 L1 TCLK1 DI Transmit Clock Input. 30 L2 TPOS1 DI Transmit Positive Data Input. 30 L2 TDATA1 DI Transmit Data Input. 31 L3 TNEG1 DI Transmit Negative Data Input. 31 L3 UBS1 DI Unipolar/Bipolar Select Input. 32 M1 RCLK1 DO Receive Clock Output. 33 M2 RPOS1 DO Receive Positive Data Output. 33 M2 RDATA1 DO Receive Data Output. 34 M3 RNEG1 DO Receive Negative Data Output. 34 M3 BPV1 DO Bipolar Violation Detect Output. 35 K3 LOS1 DO Loss of Signal Output. 36 N1 TCLK0 DI Transmit Clock Input. 37 N2 TPOS0 DI Transmit Positive Data Input. 37 N2 TDATA0 DI Transmit Data Input. 38 N3 TNEG0 DI Transmit Negative Data Input. 38 N3 UBS0 DI Unipolar/Bipolar Select Input. 39 P1 RCLK0 DO Receive Clock Output. 40 P2 RPOS0 DO Receive Positive Data. 40 P2 RDATA0 DO Receive Data Output. 41 P3 RNEG0 DO Receive Negative Data. 41 P3 BPV0 DO Bipolar Violation Detect. 42 K4 LOS0 DO Loss of Signal Output. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 16 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 7 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Multiplexed/Non-Multiplexed Select Input. 43 K2 MUX DI 44 N4, P4 TVCC0 S When Low the parallel host interface operates in non-multiplexed mode. When High the parallel host interface operates in multiplexed mode. In hardware mode, tie this unused input low. Transmit Driver Power Supply. Power supply pin for the output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Please refer to the Transmitter description. Transmit Tip Output. Transmit Ring Output. These pins are differential line driver outputs. TTIP and TRING will be in high impedance state if the TCLK pin is Low or the OE pin is Low. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable Register (OER). 45 N5 TTIP0 AO 46 P5 TRING0 AO 47 N6, P6 TGND0 S 48 P7 RTIP0 AI Receive Ring Input. 49 N7 RRING0 AI These pins are the inputs to the differential line receiver. Data and clock are recovered and output on the RPOS/RNEG and RCLK pins. 50 L6, M6 TGND1 S Transmit Driver Ground. 51 M5 TRING1 AO Transmit Ring Output. 52 L5 TTIP1 AO Transmit Tip Output. 53 L4, M4 TVCC1 S Transmit Driver Power Supply. 54 L7 RRING1 AI Receive Ring Input. 55 M7 RTIP1 AI Receive Tip Input. 56 L11, M11 TVCC2 S Transmit Driver Power Supply. Transmit Driver Ground. Ground pin for the output driver. Receive TIP Input. 57 L10 TTIP2 AO Transmit Tip Output. 58 M10 TRING2 AO Transmit Ring Output. 59 L9, M9 TGND2 S Transmit Driver Ground. 60 M8 RTIP2 AI Receive TIP Input. 61 L8 RRING2 AI Receive Ring Input. 62 N9, P9 TGND3 S Transmit Driver Ground. 63 P10 TRING3 AO Transmit Ring. 64 N10 TTIP3 AO Transmit Tip Output. 65 N11, P11 TVCC3 S Transmit Driver Power Supply. 66 N8 RRING3 AI Receive Ring Input. 67 P8 RTIP3 AI Receive Tip Input. 68 K11 LOS3 DO Loss of Signal Output. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 17 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 8 of 12) Pin # QFP Ball # PBGA Symbol I/O1 69 P12 RNEG3 DO Receive Negative Data Output. 69 P12 BPV3 DO Bipolar Violation Detect Output. 70 P13 RPOS3 DO Receive Positive Data Output. 70 P13 RDATA3 DO Receive Data Output. Description 71 P14 RCLK3 DO Receive Clock Output. 72 N12 TNEG3 DI Transmit Negative Data Input. 72 N12 UBS3 DI Unipolar/Bipolar Select Input. 73 N13 TPOS3 DI Transmit Positive Data Input. 73 N13 TDATA3 DI Transmit Data Input. 74 N14 TCLK3 DI Transmit Clock Input. 75 K12 LOS2 DO Loss of Signal Output. 76 M12 RNEG2 DO Receive Negative Data Output. 76 M12 BPV2 DO Bipolar Violation Detect Output. 77 M13 RPOS2 DO Receive Positive Data Output. 77 M13 RDATA2 DO Receive Data Output. 78 M14 RCLK2 DO Receive Clock Output. 79 L12 TNEG2 DI Transmit Negative Data Input. 79 L12 UBS2 DI Unipolar/Bipolar Select Input. 80 L13 TPOS2 DI Transmit Positive Data Input. 80 L13 TDATA2 DI Transmit Data Input. 81 L14 TCLK2 DI Transmit Clock Input. OD Interrupt. This active Low, maskable, open drain output requires an external 10k pull up resistor. If the corresponding interrupt enable bit is enabled, INT goes Low to flag the host when the LXT384 changes state (see details in the interrupt handling section). The microprocessor INT input should be set to level triggering. 82 K13 INT Data Transfer Acknowledge Output (Motorola Mode). Ready Output (Intel mode). Serial Data Output (Serial Mode). Motorola Mode 83 K14 ACK DO 83 K14 RDY DO 83 K14 SDO DO A Low signal during a data bus read operation indicates that the information is valid. A Low signal during a write operation acknowledges that a data transfer into the addressed register has been accepted (acknowledge signal).Wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. read modify write). Intel Mode A High signal acknowledges that a register access operation has been completed. (Ready Signal) A Low signal on this pin signals that a data transfer operation is in progress. The pin goes tristate after completion of a bus cycle. Serial Mode If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low, SDO is valid on the falling edge of SCLK. This pin goes into High Z state during a serial port write access. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 18 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 9 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Data Strobe Input (Motorola Mode). Write Enable Input (Intel mode). Serial Data Input (Serial Mode). 84 J14 DS DI Line Length Equalizer Input (Hardware Mode). 84 J14 WR DI Host Mode 84 J14 SDI DI 84 J14 LEN0 DI This pin acts as data strobe in Motorola mode and as Write Enable in Intel mode. In serial mode, this pin is used as Serial Data Input. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Please refer to Table 2. Read/Write Input (Motorola Mode). Read Enable Input (Intel Mode). Line Length Equalizer Input (Hardware Mode). 85 J13 R/W DI Host Mode 85 J13 RD DI 85 J13 LEN1 DI This pin functions as the read/write signal in Motorola mode and as the Read Enable in Intel mode. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Please refer to Table 2. Address Latch Enable Input. Shift Clock Input (Serial Mode). Address Strobe (Motorola Mode). Line Length Equalizer Input (Hardware Mode). 86 J12 ALE DI Host Mode 86 J12 SCLK DI 86 J12 AS DI The address on the multiplexed address/data bus is clocked into the device with the falling edge of ALE. 86 J12 LEN2 DI In serial Host mode, this pin acts as serial shift clock. In Motorola mode, this pin acts a active Low address strobe. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Please refer to Table 2. Chip Select/Jitter Attenuator Select Input. Host Mode This active Low input is used to access the serial/parallel interface. For each read or write operation, CS must transition from High to Low, and remain Low. 87 J11 CS 87 J11 JASEL Hardware Mode DI This input determines the Jitter Attenuator position: JASEL JA Position L Transmit Path H Receive Path Z Disabled 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 19 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 10 of 12) Pin # QFP Ball # PBGA Symbol I/O1 Description Motorola/Intel/Codec Enable Select Input. Host Mode: 88 H12 MOT/INTL/ CODEN DI When Low, the host interface is configured for Motorola microcontrollers. When High, the host interface is configured for Intel microcontrollers. Hardware Mode: Determines the line encode/decode selection when in unipolar mode. When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively. When High, enables AMI encoder/decoder (transparent mode). 89 H11 GND1 S Ground (Core). 90 91 H14 VCC1 S Power (Core). G11 GNDIO1 S Ground (I/O). 92 G14 VCCIO1 S Power (I/O). 93 G13 AT2 AO JTAG Analog Output Test Port 2. 94 H13 AT1 AI JTAG Analog Input Test Port 1. 95 G12 TRST 96 F11 TMS DI JTAG Test Mode Select Input. Used to control the test logic state machine. Sampled on rising edge of TCK. TMS is pulled up internally and may be left disconnected. 97 F14 TCK DI JTAG Clock Input. Clock input for JTAG. Connect to GND when not used. 98 F13 TDO DO JTAG Data Output. Test Data Output for JTAG. Used for reading all serial configuration and test data from internal test logic. Updated on falling edge of TCK. 99 F12 TDI DI JTAG Data Input. Test Data input for JTAG. Used for loading serial instructions and data into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may be left disconnected. 100 D14 TCLK5 DI Transmit Clock Input. 101 D13 TPOS5 DI Transmit Positive Data Input. 101 D13 TDATA5 DI Transmit Data Input. 102 D12 TNEG5 DI Transmit Negative Data Input. 102 D12 UBS5 DI Unipolar/Bipolar Select Input. JTAG Controller Reset Input. Input is used to reset the JTAG controller. TRST is pulled up internally and may be left disconnected. 103 C14 RCLK5 DO Receive Clock Output. 104 C13 RPOS5 DO Receive Positive Data Output. 104 C13 RDATA5 DO Receive Data Output. 105 C12 RNEG5 DO Receive Negative Data Output. 105 C12 BPV5 DO Bipolar Violation Detect Output. 106 E12 LOS5 DO Loss of Signal Output. 107 B14 TCLK4 DI Transmit Clock Input. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 20 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 1. LXT384 Pin Description (Sheet 11 of 12) Pin # QFP Ball # PBGA 108 108 Symbol I/O1 B13 TPOS4 DI Transmit Positive Data Input. B13 TDATA4 DI Transmit Data Input. 109 B12 TNEG4 DI Transmit Negative Data Input. 109 B12 UBS4 DI Unipolar/Bipolar Select Input. 110 A14 RCLK4 DO Receive Clock Output. 111 A13 RPOS4 DO Receive Positive Data Output. 111 A13 RDATA4 DO Receive Data Output. 112 A12 RNEG4 DO Receive Negative Data Output. 112 A12 BPV4 DO Bipolar Violation Detect Output. 113 E11 LOS4 DO Loss of Signal Output. DI Output Driver Enable Input. If this pin is asserted Low all analog driver outputs immediately enter a high impedance mode to support redundancy applications without external mechanical relays. All other internal circuitry stays active. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable Register (OER). 114 115 E14 E13 OE CLKE DI Description Clock Edge Select Input. In clock recovery mode, setting CLKE High causes RDATA or RPOS and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK. Setting CLKE Low makes RDATA or RPOS and RNEG to be valid on the rising edge of RCLK and SDO to be valid on the falling edge of SCLK. In Data recovery Mode, RDATA or RPOS/RNEG are active High output polarity when CLKE is High and active Low polarity when CLKE is Low. CLKE 116 A11, B11 117 118 RPOS/RNEG SDO L RCLK SCLK H RCLK SCLK TVCC4 S Transmit Driver Power Supply. B10 TTIP4 AO Transmit Tip Output. A10 TRING4 AO Transmit Ring Output. 119 A9, B9 TGND4 S Transmit Driver Ground. 120 A8 RTIP4 AI Receive Tip Input. 121 B8 RRING4 AI Receive Ring Input. 122 C9, D9 TGND5 S Transmit Driver Ground. 123 C10 TRING5 AO Transmit Ring Output. 124 D10 TTIP5 AO Transmit Tip Output. 125 C11, D11 TVCC5 S Transmit Driver Power Supply. 126 D8 RRING5 AI Receive Ring Input. 127 C8 RTIP5 AI Receive Tip Input. 128 C4, D4 TVCC6 S Transmit Driver Power Supply. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. Datasheet 21 LXT384 — Octal T1/E1/J1 Transceiver Table 1. LXT384 Pin Description (Sheet 12 of 12) Pin # QFP Ball # PBGA 129 130 Symbol I/O1 D5 TTIP6 AO Transmit Tip Output. C5 TRING6 AO Transmit Ring Output. 131 C6, D6 TGND6 S Transmit Driver Ground. 132 C7 RTIP6 AI Receive Tip Input. 133 D7 RRING6 AI Receive Ring Input. 134 A6, B6 TGND7 S Transmit Driver Ground. 135 A5 TRING7 AO Transmit Ring Output. 136 B5 TTIP7 AO Transmit Tip Output. 137 A4, B4 TVCC7 S Transmit Driver Power Supply. 138 B7 RRING7 AI Receive Ring Input. 139 A7 RTIP7 AI Receive Tip Input. 140 E4 LOS7 DO Loss of Signal Output. 141 A3 RNEG7 DO Receive Negative Data Output. 141 A3 BPV7 DO Bipolar Violation Detect Output. 142 A2 RPOS7 DO Receive Positive Data Output. 142 A2 RDATA7 DO Receive Data Output. Description 143 A1 RCLK7 DO Receive Clock Output. 144 B3 TNEG7 DI Transmit Negative Data Input. 144 B3 UBS7 DI Unipolar/Bipolar Select Input. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2.0 Functional Description Figure 1 is a block diagram of the LXT384. The LXT384 is a fully integrated octal line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. These two lines comprise a digital data loop for full duplex transmission. The LXT384 can be controlled through hard-wired pins or by a microprocessor through a serial or parallel interface (Host mode). The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT384 is designed to operate without any reference clock when used as an analog front-end (line driver and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All eight clock recovery circuits share the same reference clock defined by the MCLK input signal. 2.1 Initialization During power up, the transceiver remains static until the power supply reaches approximately 60% of VCC. During power-up, an internal reset sets all registers to their default values and resets the status and state machines for the LOS. 22 Datasheet Octal T1/E1/J1 Transceiver — LXT384 2.1.1 Reset Operation Writing to the reset register (RES) initiates a 1 microsecond reset cycle, except in Intel nonmultiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please refer to Host mode section for more information. This operation sets all LXT384 registers to their default values. 2.2 Receiver The eight receivers in the LXT384 are identical. The following paragraphs describe the operation of one. The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG validation relative to RCLK is pin selectable (CLKE). The receive signal is processed through the peak detector and data slicers. The peak detector samples the received signal and determines its maximum value. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1 applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the peak value. This threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the threshold is 50% (typical). The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from impulsive noise. After processing through the data slicers, the received signal goes to the data and timing recovery section. The data and timing recovery circuits provide an input jitter tolerance better than required by Pub 62411 and ITU G.823, as shown in Test Specifications, Figure 33. Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. 2.2.1 Loss of Signal Detector The loss of signal detector in the LXT384 uses a dedicated analog and digital loss of signal detection circuit. It is independent of its internal data slicer comparators and complies to the latest ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be configured to comply to the ETSI ETS 300 233 specification (LACS Register). In hardware mode, the LXT384 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation. The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is Datasheet 23 LXT384 — Octal T1/E1/J1 Transceiver required for receive operation. When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the data content at the receiver input during the entire LOS detection period for that channel. 2.2.1.1 E1 Mode In G.775 mode, a loss of signal is detected if the signal is below 200mV typ. for 32 consecutive pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit period) with no more than 15 consecutive zeros and the signal level exceeds 250mV typ., the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048 consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when the incoming signal has transitions when the signal level is equal or greater than 250mV for more than 32 consecutive pulse intervals. 2.2.1.2 T1 Mode The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for 175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a pulse. The incoming signal is considered to have transitions when the signal level is equal or greater than 250mV. 2.2.1.3 Data Recovery Mode In data recovery mode, the LOS digital timing is derived from a internal self timed circuit. RPOS/ RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775 recommendation. The LXT384 monitors the incoming signal amplitude. Any signal below 200mV for more than 30µs (typical) will assert the corresponding LOS pin. The LOS condition is cleared when the signal amplitude rises above 250mV. The LXT384 requires more than 10 and less than 255 bit periods to declare a LOS condition in accordance to ITU G.775. 2.2.2 Alarm Indication Signal (AIS) Detection The AIS detection is performed by the receiver independent of any loopback mode. This feature is available in host mode only with clock recovery. Because there is no clock in data recovery mode, AIS detection will not work in that mode. AIS requires MCLK to have clock applied, since this function depends on the clock to count the number of ones in an interval. 2.2.2.1 E1 Mode Two different detection modes are available depending on the LACS register setting: • ETSI ETS300233 Mode The AIS condition is declared when the received data stream contains less than 3 zeros within a period of 512 bits. The AIS condition is cleared when 3 or more zeros within 512 bits are detected. • ITU G.775 Mode The AIS condition is declared when, within two consecutive 512 bit periods, less than 3 zeros are detected for each 512 bit period. 24 Datasheet Octal T1/E1/J1 Transceiver — LXT384 The AIS condition is cleared when, within two consecutive 512 bit periods, 3 or more zeros are detected for each 512 bit period. 2.2.2.2 T1 Mode ANSI T1.231 detection is employed. The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This corresponds to a 99.9% ones density over a period of 5.3ms. The AIS condition is cleared when the received signal contains 9 or more zeros in any string of 8192 bits. 2.2.3 Receive Alarm Indication Signal (RAIS) The receiver will generate all ones to RPOS and RNEG outputs upon LOS, when bit 6, RAISEN, for Receive Alarm Indication Signal Enable, is set in the Global Control Register, GCR. This can affect the AIS status by setting to one if the signal at RTIP and RRING is all zeroes, or be clearing to zero if the signal at RTIP and RRING is all ones. Because of this, mask the AIS interrupt enable bits before setting or resetting RAISEN. This will prevent inadvertent interrupts during programming. 2.2.4 In Service Code Violation Monitoring In unipolar I/O mode with HDB3/B8ZS decoding, the LXT384 reports bipolar violations on RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same polarity) are reported at the BPV output. 2.3 Transmitter The eight low power transmitters of the LXT384 are identical. Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O and HDB3/B8ZS/AMI encoding/decoding is selected by pulling TNEG High for more than 16 consecutive TCLK clock cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer to the Test Specifications Section for MCLK and TCLK timing characteristics. If TCLK is not supplied, the transmitter remains powered down and the TTIP/TRING outputs are held in a High Z state. In addition, fast output tristatability is also available through the OE pin (all ports) and/or the port’s OEx bit in the Output Enable Register (OER). Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS, used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings). The LXT384 also supports AMI line coding/decoding as shown in Figure 5. In Hardware mode, AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is selected by bit 4 in the GCR (Global Control Register). Datasheet 25 LXT384 — Octal T1/E1/J1 Transceiver Figure 5. 50% AMI Encoding TTIP Bit Cell 1 0 1 TRING Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse shaper is bypassed if no MCLK is supplied while TCLK is pulled High. In this case TPOS and TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied and TCLK pulled High, the driver enters TAOS (Transmit All Ones pattern). Note: the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. TAOS is inhibited during Remote Loopback. 2.3.1 Transmit Pulse Shaping The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks, spaces or if it is in transition. This well controlled dynamic impedance provides excellent return loss when used with external precision resistors (± 1% accuracy) in series with the transformer. 2.3.1.1 Hardware Mode In hardware mode, pins LEN0-2 determine the pulse shaping as described in Table 2. The LEN settings also determine whether the operating mode is T1 or E1. Note: In hardware mode, all eight ports will share the same pulse shaping setting. Independent pulse shaping for each channel is available in host mode. 2.3.1.2 Host Mode In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of pulse output at TTIP/TRING. Please refer to Table 24 and Table 25. 26 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 2. Line Length Equalizer Inputs LEN2 LEN1 LEN0 Line Length1 Cable Loss2 0 1 1 0 - 133 ft. ABAM 0.6 dB 1 0 0 133 - 266 ft. ABAM 1.2 dB 1 0 1 266 - 399 ft. ABAM 1.8 dB 399 - 533 ft. ABAM 2.4 dB 533 - 655 ft. ABAM 3.0 dB 1 1 0 1 1 1 0 0 0 E1 G.703, 75Ω coaxial cable and 120 Ω twisted pair cable. Operation Mode T1 E1 1. Line length from LXT384 to DSX-1 cross-connect point. 2. Maximum cable loss at 772KHz. 2.3.1.3 Output Driver Power Supply The output driver power supply (TVCC pins) can be either 3.3V or 5V nominal. When TVCC=5V, LXT384 drives both E1 (75Ω/120Ω) and T1 100Ω lines through a 1:2 transformer and 11Ω/9.1Ω series resistors. When TVCC=3.3V, the LXT384 drives E1 (75Ω/120Ω) lines through a 1:2 transformer and 11Ω series resistor. A configuration with a 1:2 transformer and without series resistors should be used to drive T1 100Ω lines. The Channel 4 (TVCC4) power supply pin is used to determine 3.3V or 5.0V transmit operation. Removing the series resistors for T1 applications with TVCC=3.3V, improves the power consumption of the device. See Table 36. On the other hand, series resistors in the transmit configuration improve the transmit return loss performance. Good transmit return loss performance minimizes reflections in harsh cable environments. In addition, series resistors provide protection against surges coupled to the device. The resistors should be used in systems requiring protection switching without external relays. Please refer to Figure 6 for the recommended external line circuitry. 2.3.1.4 Power Sequencing For the LXT384, we recommend sequencing TVCC first then VCC second or at the same time as TVCC to prevent excessive current draw. 2.4 Driver Failure Monitor The LXT384 transceiver incorporates an internal power Driver Failure Monitor (DFM) in parallel with TTIP and TRING that is capable of detecting secondary shorts without cable. DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V). This feature is available in the serial and parallel host modes but not available in the hardware mode of operation. A capacitor, charged via a measure of the driver output current and discharged by a measure of the maximum allowable current, is used to detect a secondary short failure. Secondary shorted lines draw excess current, overcharging the cap. When the capacitor charge deviates outside the nominal Datasheet 27 LXT384 — Octal T1/E1/J1 Transceiver charge window, a driver short circuit fail (DFM) is reported in the respective register by setting an interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. Note: unterminated lines of adequate length (λ/4) may effectively behave as short-circuits as seen by the driver and therefore trigger the DFM. Under these circumstances, the alarm should be disabled. In addition, LXT384 features output driver short-circuit protection. When the output current exceeds 100 mA, LXT384 limits the driver’s output voltage to avoid damage. 28 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 6. External Transmit/Receive Line Circuitry TVCC TVCC TVS1 68µF 1 0.1µF TVCC TGND TVCC 4 D4 RT 1:2 TTIP D3 0.47µF 3.3V TVCC 0.1µF Tx LINE 2 560pF VCC D2 GND TRING RT 3 D1 LXT384 (ONE CHANNEL) 1kΩ 1:2 RTIP RR Rx LINE 0.22µF RR RRING 1kΩ 1 Common decoupling capacitor for all TVCC and TGND pins. 2 Typical value. Adjust for actual board parasitics to obtain optimum return loss. 3 Refer to Transformer Specifications Table for transformer specifications. 4 DC blocking capacitor needed when pulse shaping is disabled. See pin description for TCLK7, pin 2 of QFP package in Table 1. Component 75Ω Coax 120Ω Twisted Pair 100Ω Twisted Pair TVCC = 5V 100Ω Twisted Pair TVCC = 3.3V RT 11Ω ± 1% 11Ω ± 1% 9.1Ω ± 1% 0Ω 9.31Ω ± 1% 15.0Ω ± 1% 12.4Ω ± 1% 12.4Ω ± 1% RR D1 - D4 TVS1 Datasheet International Rectifier.............11DQ04 or 10BQ060 Motorola.......................................MBR0540T1 SGS-Thomson..............SMLVT 3V3 3.3V Transient Voltage Suppressor (TVCC=3.3V) Semtech.......................SMCJ5.0AC 5.0V Transient Voltage Suppressor (TVCC=5.0V) 29 LXT384 — Octal T1/E1/J1 Transceiver 2.5 Line Protection Figure 6 on page 29 shows recommended line interface circuitry. In the receive side, the 1 kΩ series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (70 kΩ typ.) the resistors do not affect the receiver sensitivity. In the transmit side, the Schottky diodes D1-D4 protect the output driver.While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness. 2.6 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the receive or transmit path. In Hardware Mode, the JAL position is determined by the JASEL pin. The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the FIFO with the dejittered JAL clock (Figure 7). When the FIFO is within two bits of overflowing or underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator produces a constant delay of 16 or 32 bits in the associated path (refer to test specifications). This feature can be used for hitless switching applications. This advanced digital jitter attenuator meets latest jitter attenuation specifications. See Table 3. Under software control, the low limit jitter attenuator corner frequency depends on FIFO length and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode. Table 3. Jitter Attenuation Specifications T1 E1 AT&T Pub 62411 1 GR-253-CORE ITU-T G.736 ITU-T G.7423 ITU-T G.7834 TR-TSY-000009 2 ETSI CTR12/13 BAPT 220 1. 2. 3. 4. 30 Category I, R5-203. Section 4.6.3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper. Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 7. Jitter Attenuator Loop FIFO64 TPOS RPOSi TPOSo RPOS TNEG RNEGi TNEGo FIFO IN CK TCLK DPLL IN RCLKi TCLK RCLK OUT JASEL0-1 JASEL0-1 x 32 MCLK RNEG OUT CK JACF GCR control bits 2.7 Loopbacks The LXT384 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP registers are employed. 2.7.1 Analog Loopback When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver inputs (RTIP & RRING) as shown in Figure 8. Data and clock are output at RCLK, RPOS & RNEG pins for the corresponding transceiver. Note: signals on the RTIP & RRING pins are ignored during analog loopback. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder * Figure 8. Analog Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled Datasheet 31 LXT384 — Octal T1/E1/J1 Transceiver 2.7.2 Digital Loopback The digital loopback function is available in software mode only. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS & RNEG pins (see Figure 9). The data presented on TCLK, TPOS & TNEG is also output on the TTIP & TRING pins. Note: signals on the RTIP & RRING pins are ignored during digital loopback. RCLK RPOS RNEG HDB3/B8ZS Encoder* TCLK TPOS TNEG Timing & Control TTIP JA* HDB3/B8ZS Decoder* Figure 9. Digital Loopback JA* Timing Recovery RTIP TRING RRING * If Enabled 2.7.3 Remote Loopback During remote loopback (see Figure 10), the RCLK, RPOS & RNEG outputs routed to the transmit circuits and output on the TTIP & TRING pins. Note: input signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* Figure 10. Remote Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled Note: 2.7.4 In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. Transmit All Ones (TAOS) In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles. In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register. Note: the TAOS generator uses MCLK as a timing reference, therefore TAOS doesn’t work in data recovery mode. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. DLOOP does not function when TAOS is active. 32 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 11. TAOS Data Path MCLK TCLK TPOS TNEG HDB3/B8ZS Encoder* RCLK RPOS RNEG HDB3/B8ZS Decoder* TAOS mode Timing & Control TTIP TRING (ALL 1’s) Timing Recovery JA* RTIP RRING * If Enabled Figure 12. TAOS with Digital Loopback MCLK HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* TAOS Mode TCLK TPOS TNEG JA* Timing & Control TTIP TRING (ALL 1’s) Timing Recovery RTIP RRING * If Enabled Figure 13. TAOS with Analog Loopback MCLK TAOS Mode RCLK RPOS RNEG Timing & Control HDB3/B8ZS Encoder* HDB3/B8ZS Decoder* TCLK TPOS TNEG TTIP TRING (ALL 1’s) JA* Timing Recovery RTIP RRING * If Enabled 2.8 G.772 Performance Monitoring The LXT384 can be configured as an octal line interface unit with all channels working as regular transceivers. In applications using only seven channels, the eighth channel can be configured to monitor any of the remaining channels inputs or outputs. The monitoring is non-intrusive per ITUT G.772. Figure 1 on page 7 illustrates this concept. Datasheet 33 LXT384 — Octal T1/E1/J1 Transceiver The monitored line signal (input or output) goes through channel 0 clock and data recovery. The signal can be observed digitally at the RCLK/RPOS/RNEG outputs. This feature can also be used to create timing interfaces derived from a E1 signal. Channel 0 also displays the appropriate LOS state for the monitored channel, both in transmit and receive directions. In addition, channel 0 can be configured to a Remote Loopback while in monitoring mode (TCLK0 must be active in order for this operation to take place). This will output the same data as in the signal being monitored at the channel 0 output (TTIP/TRING). The output signal can then be connected to a standard test equipment with an E1 electrical interface for monitoring purposes (non -intrusive monitoring). 2.9 Hitless Protection Switching (HPS) The LXT384 transceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Please refer to Application Note 119 for guidelines for implementing redundancy systems for both T1 and E1 operation using the LXT380/1/4/6/8. 2.10 Operation Mode Summary Table 4 lists summarizes all the LXT384 hardware settings and corresponding operating modes. Table 4. Operation Mode Summary MCLK TCLK LOOP1 Receive Mode Transmit Mode Clocked Clocked Open Data/Clock recovery Pulse Shaping ON No Loopback Clocked Clocked L Data/Clock recovery Pulse Shaping ON Remote Loopback Clocked Clocked H Data/Clock recovery Pulse Shaping ON Analog Loopback Clocked L Open Data/Clock recovery Power down No Loopback Loopback Clocked L L Data/Clock Recovery Power down No effect on op. Clocked L H Data/Clock Recovery Power down No Analog Loopback Clocked H Open Data/Clock Recovery Transmit All Ones No Loopback Clocked H L Data/Clock Recovery Pulse Shaping ON Remote Loopback Clocked H H Data/Clock Recovery Transmit All Ones No effect on op. L Clocked Open Power Down Pulse Shaping ON No Loopback L Clocked L Power Down Pulse Shaping ON No Remote Loopback L Clocked H Power Down Pulse Shaping ON No effect on op. L H Open Power Down Pulse Shaping OFF No Loopback L H L Power Down Pulse Shaping OFF No Remote Loop L H H Power Down Pulse Shaping OFF No effect on op. L L X Power Down Power down No Loopback H Clocked Open Data Recovery Pulse Shaping ON No Loopback H Clocked L Data Recovery Pulse Shaping OFF Remote Loopback 1. Hardware mode only. 34 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 4. Operation Mode Summary (Continued) MCLK TCLK H Clocked H L H L H H H H LOOP1 Receive Mode Transmit Mode Loopback H Data Recovery Pulse Shaping ON Analog Loopback Open Data Recovery Power down No Loopback L Data Recovery Pulse Shaping OFF Remote Loopback Open Data Recovery Pulse Shaping OFF No Loopback H L Data Recovery Pulse Shaping OFF Remote Loopback H H Data Recovery Pulse Shaping OFF Analog Loopback 1. Hardware mode only. 2.11 Interfacing with 5V Logic The LXT384 can interface directly with 5V TTL family devices. The internal input pads are tolerant to 5V outputs from TTL and CMOS family devices. 2.12 Parallel Host Interface The LXT384 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is generic and is designed to support both non-multiplexed and multiplexed address/data bus systems for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different operating modes as shown in Table 5. Table 5. Microprocessor Interface Selection Pin Operating Mode MUX MOT/INTL Low Low Motorola, Non-Multiplexed Low High Intel, Non-Multiplexed High Low Motorola, Multiplexed High High Intel, Multiplexed The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS, INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In Motorola mode, ACK Low signals valid information is on the data bus. During a write cycle a Low signal acknowledges the acceptance of the write data. In Intel mode, RDY High signals to the controlling processor that the bus cycle can be completed. While Low the microprocessor must insert wait states. This allows the LXT384 to interface with wait-state capable microcontrollers, independent of the processor bus speed. To activate this function a reference clock is required on the MCLK pin. There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the reset register. Because of timing issues, the RDY line remains high after the first part of the cycle is done, not signalling write cycle completion with another transition low. Add 2 microseconds of Datasheet 35 LXT384 — Octal T1/E1/J1 Transceiver delay to allow the reset cycle to completely initialize the device before proceeding. The overall duration of the Reset cycle from CS low to Reset cycle completion is 3 microseconds when using Intel non-multiplexed host mode. An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to the microprocessor. The LXT384 has a 5-bit address bus and provides 22 user accessible 8-bit registers for configuration, alarm monitoring and control of the chip. 2.12.1 Motorola Interface The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode, the falling edge of DS is used to latch the address information on the address bus. In multiplexed operation the address on the multiplexed address data bus is latched into the device with the falling edge of AS. In non-multiplexed mode, AS should be pulled High. The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/ W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising edge on DS. Both cycles require the CS signal to be Low and the Address pins to be actively driven by the microprocessor. Note: CS and DS can be connected together in Motorola mode. In a write cycle, the data bus is driven by the microprocessor. In a read cycle, the bus is driven by the LXT384. 2.12.2 Intel Interface The Intel interface is selected by asserting the MOT/INTL pin High. The LXT384 supports nonmultiplexed interfaces with separate address and data pins when MUX is asserted Low, and multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS is used as the WR signal. A read cycle is indicated to the LXT384 when the processor asserts RD Low while the WR signal is held High. A write operation is indicated to the LXT384 by asserting WR Low while the RD signal is held High. Both cycles require the CS signal to be Low. 2.13 Interrupt Handling 2.13.1 Interrupt Sources There are three interrupt sources: • Status change in the LOS (Loss of Signal) status register (04H). The LXT384 analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific LOS status bit to indicate presence or absence of a LOS condition. • Status change in the DFM (Driver Failure Monitoring) status register (05H). The LXT384 smart power driver circuit continuously monitors the output drivers signal and updates the specific DFM status bit to indicate presence or absence of a secondary driver short circuit condition. • Status change in the AIS (Alarm Indication Signal) status register (13H). The LXT384 receiver monitors the incoming data stream and updates the specific AIS status bit to indicate presence or absence of a AIS condition. 36 Datasheet Octal T1/E1/J1 Transceiver — LXT384 2.13.2 Interrupt Enable The LXT384 provides a latched interrupt output (INT). An interrupt occurs any time there is a transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM and AIS interrupt enable registers (respectively). Writing a logic “1” into the mask register will enable the respective bit in the respective Interrupt status register to generate an interrupt. The power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers. Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers. When there is a transition on any enabled bit in a status register, the associated bit of the interrupt status register is set and an interrupt is generated (if one is not already pending). When an interrupt occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR operation. 2.13.3 Interrupt Clear When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register clears the "sticky" bit set by the interrupt. Automatically clearing the register prepares it for the next interrupt. The ISR should then read the corresponding status monitor register to obtain the current status of the device. Note: there are three status monitor registers: the LOS (04H), the DFM (05H) and the AIS (013H). Reading either status monitors register will clear its corresponding interrupts on the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes High. 2.14 Serial Host Mode The LXT384 operates in Serial Host Mode when the MODE pin is tied to VCCIO÷2. Figure 14 shows the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/ Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte address specific registers (the address decoder ignores bits A7-6). The data byte depends on both the value of bit R/W and the address of the register as set in the Command/Address byte. Datasheet 37 LXT384 — Octal T1/E1/J1 Transceiver Figure 14. Serial Host Mode Timing CS SCLK INPUT DATA BYTE ADDRESS/COMMAND BYTE SDI R/W A1 A2 A3 A4 A5 A6 X A7 X SDO - REMAINS HIGH Z D0 D1 D2 D3 D4 D5 D6 D7 SDO IS DRIVEN WHEN R/W = 1 R/W = 1: Read from LXT384 R/W = 0: Write to LXT384 X = Don’t care 3.0 Table 6. Register Descriptions Serial and Parallel Port Register Addresses (Sheet 1 of 2) Address 38 Name Symbol ID Register Mode Serial Port A7-A1 Parallel Port A7-A0 ID xx00000 xxx00000 R Analog Loopback ALOOP xx00001 xxx00001 R/W Remote Loopback RLOOP xx00010 xxx00010 R/W TAOS Enable TAOS xx00011 xxx00011 R/W LOS Status Monitor LOS xx00100 xxx00100 R DFM Status Monitor DFM xx00101 xxx00101 R LOS Interrupt Enable LIE xx00110 xxx00110 R/W DFM Interrupt Enable DIE xx00111 xxx00111 R/W LOS Interrupt Status LIS xx01000 xxx01000 R DFM Interrupt Status DIS xx01001 xxx01001 R Software Reset Register RES xx01010 xxx01010 R/W Performance Monitoring MON xx01011 xxx01011 R/W Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 6. Serial and Parallel Port Register Addresses (Sheet 2 of 2) Address Name Table 7. Symbol Serial Port A7-A1 Parallel Port A7-A0 Digital Loopback DL xx01100 xxx01100 R/W LOS/AIS Criteria Selection LOSC xx01101 xxx01101 R/W Automatic TAOS Select ATS xx01110 xxx01110 R/W Global Control Register GCR xx01111 xxx01111 R/W Pulse Shaping Indirect Address Register PSIAD xx10000 xxx10000 R/W Pulse Shaping Data Register PSDAT xx10001 xxx10001 R/W Output Enable Register OER xx10010 xxx10010 R/W AIS Status Register AIS xx10011 xxx10011 R AIS Interrupt Enable AISIE xx10100 xxx10100 R/W AIS Interrupt Status AISIS xx10101 xxx10101 R Register Bit Names (Sheet 1 of 2) Register Name ID Register Bit Sym RW ID R 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ALOOP R/W AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 Remote Loopback RLOOP R/W RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0 TAOS2 TAOS1 TAOS0 Analog Loopback TAOS Enable TAOS R/W TAOS7 TAOS6 TAOS5 TAOS4 TAOS3 LOS Status Monitor LOS R LOS7 LOS6 LOS5 LOS4 LOS3 LOS2 LOS1 LOS0 DFM Status Monitor DFM R DFM7 DFM6 DFM5 DFM4 DFM3 DFM2 DFM1 DFM0 LOS Interrupt Enable LIE R/W LIE7 LIE6 LIE5 LIE4 LIE3 LIE2 LIE1 LIE0 DFM Interrupt Enable DIE R/W DIE7 DIE6 DIE5 DIE4 DIE3 DIE2 DIE1 DIE0 LOS Interrupt Status LIS R LIS7 LIS6 LIS5 LIS4 LIS3 LIS2 LIS1 LIS0 DFM Interrupt Status DIS R DIS7 DIS6 DIS5 DIS4 DIS3 DIS2 DIS1 DIS0 Software Reset Register RES R/W RES7 RES6 RES5 RES4 RES3 RES2 RES1 RES0 Performance Monitoring MON R/W Reserved Reserved A3 A2 A1 A0 DL R/W DL7 DL6 DL3 DL2 DL1 DL0 LACS2 LACS1 LACS0 ATS2 ATS1 ATS0 Digital Loopback LOS/AIS Criteria Select Automatic TAOS Select Datasheet Mode LACS R/W LACS7 ATS R/W ATS7 Reserved Reserved DL5 DL4 LACS6 LACS5 LACS4 LACS3 ATS6 ATS5 ATS4 ATS3 39 LXT384 — Octal T1/E1/J1 Transceiver Table 7. Register Bit Names (Sheet 2 of 2) Register Name Sym RW 7 GCR R/W Reserved Pulse Shaping Indirect Address Register PSIAD R/W Reserved Reserved Reserved Reserved Reserved Pulse Shaping Data Register PSDAT R/W Reserved Reserved Reserved Reserved Reserved LEN2 LEN1 LEN0 Global Control Register Table 8. Bit 6 5 4 3 RAISEN CDIS CODEN FIFO64 2 JACF 1 0 JASEL1 JASEL0 LENAD2 LENAD1 LENAD0 Output Enable Register OER R/W OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 AIS Status Register AIS R AIS7 AIS6 AIS5 AIS4 AIS3 AIS2 AIS1 AIS0 AIS Interrupt Enable AISIE R/W AISIE7 AISIE6 AISIE5 AISIE4 AISIE3 AISIE2 AISIE1 AISIE0 AIS Interrupt Status AISIS R AISIS7 AISIS6 AISIS5 AISIS4 AISIS3 AISIS2 AISIS1 AISIS0 ID Register, ID (00h) Bit Name 7-0 ID7-ID0 Function This register contains a unique revision code and is mask programmed. For Rev. A4, 00h For Rev. A5, 15h Table 9. Analog Loopback Register, ALOOP (01h) Bit Name 7-0 AL7-AL0 Function Setting a bit to “1” enables analog local loopback for transceivers 7- 0 respectively. Table 10. Remote Loopback Register, RLOOP (02h) Bit Name 7-0 RL7-RL0 Function Setting a bit to “1” enables remote loopback for transceivers 7-0 respectively. Table 11. TAOS Enable Register, TAOS (03h) Bit1 Name Function2 7-0 TAOS7-TAOS0 Setting a bit to “1” causes a continuous stream of marks to be sent out at the TTIP and TRING pins of the respective transceiver 7-0. 1. On power up all register bits are set to “0”. 2. MCLK is used as timing reference. If MCLK is not available then the channel TCLK is used as the reference.This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High). 40 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 12. LOS Status Monitor Register, LOS (04h) Bit1 Name 7-0 LOS7-LOS0 Function Respective bit(s) are set to “1” every time the LOS processor detects a valid loss of signal condition in transceivers 7-0. 1. On power up all register bits are set to “0”. Any change in the state causes an interrupt. All LOS interrupts are cleared by a single read operation. Table 13. DFM Status Monitor Register, DFM (05h) Bit Name 7-0 DFM7-DFM0 Function1 Respective bit(s) are set to “1” every time the short circuit monitor detects a valid secondary output driver short circuit condition in transceivers 7-0. Note: DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V). 1. On power-up all the register bits are set to “0”. All DFM interrupts are cleared by a single read operation. Table 14. LOS Interrupt Enable Register, LIE (06h) Bit Name 7-0 LIE7-LIE0 Function1 Transceiver 7-0 LOS interrupts are enabled by writing a “1” to the respective bit. 1. On power-up all the register bits are set to “0” and all interrupts are disabled. Table 15. DFM Interrupt Enable Register, DIE (07h) Bit Name 7-0 DIE7-DIE0 Function1 Transceiver 7-0 DFM interrupts are enabled by writing a “1” to the respective bit. 1. On power-up all the register bits are set to “0” and all interrupts are disabled. Table 16. LOS Interrupt Status Register, LIS (08h) Bit Name 7-0 LIS7-LIS0 Function1 These bits are set to “1” every time a LOS status change has occurred since the last cleared interrupt in transceivers 7-0 respectively. 1. On power up all register bits are set to “0”. Table 17. DFM Interrupt Status Register, DIS (09h) Bit Name Function1 7-0 DIS7-DIS0 These bits are set to “1” every time a DFM status change has occurred since the last cleared interrupt in transceivers 7-0 respectively. 1. On power up all register bits are set to “0”. Datasheet 41 LXT384 — Octal T1/E1/J1 Transceiver Table 18. Software Reset Register, RES (0Ah) Bit Name 7-0 RES7-RES0 Function Writing to this register initiates a 1 microsecond reset cycle, except in Intel nonmultiplexed mode. This operation sets all LXT384 registers to their default values. When using Intel non-multiplexed host mode, extend cycle time to 2 microseconds. Please refer to Host Mode section for details. Table 19. Performance Monitoring Register, MON (0Bh) Bit Name 3-0 A3:A0 4-7 reserved Function Protected Monitoring selection. See Table 1, page 15. Reserved. Table 20. Digital Loopback Register, DL (0Ch) Bit1 Name 7-0 DL7-DL0 Function2 Setting a bit to “1” enables digital loopback for the respective transceiver. 1. On power up all register bits are set to “0”. 2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on TPOS/TNEG/CKLK is looped back to RPOS/RNEG/RCLK. Table 21. LOS/AIS Criteria Register, LCS (0Dh) Bit1 Function2 Name T1 Mode Don’t care. T1.231 compliant LOS/AIS detection is used. 7-0 LCS7-LCS0 E1 Mode Setting a bit to “1” selects the ETSI 300233 LOS. Setting a bit to “0” selects G.775 LOS mode. AIS works correctly for both ETSI and ITU when the bit is cleared to “0”. See errata 10.3 or higher for a way to implement ETSI LOS and AIS. 1. On power-on reset the register is set to “0”. 2. T1 or E1 operation mode is determined by the PSDAT settings. Table 22. Automatic TAOS Select Register, ATS (0Eh) Bit1 Name 7-0 ATS7-ATS0 Function Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is detected in the respective transceiver. 1. On power-on reset the register is set to “0”. 2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High). 42 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 23. Global Control Register, GCR (0Fh) Bit1 Name 0 JASEL0 1 Function These bits determine the jitter attenuator position: JASEL0 JASEL1 JA Position 1 0 Transmit Path 1 1 Receive Path 0 x Disabled JASEL1 2 JACF 3 FIFO64 4 CODEN 5 CDIS This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter Attenuator specifications for details. See Table 42 on page 59. This bit determines the jitter attenuator FIFO depth: 0 = 32 bit 1 = 64 bit This bit selects the zero suppression code for unipolar operation mode: 0 = B8ZS/HDB3 (T1/E1 respectively) 1 = AMI This bit controls enables/disables the short circuit protection feature: 0 = enabled 1 = disabled This bit controls automatic AIS insertion in the receive path when LOS occurs: 6 RAISEN 0 = Receive AIS insertion disabled on LOS 1 = RPOS/RNEG = AIS on LOS Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS interrupts when changing this bit value to prevent inadvertent interrupts. 7 - Reserved. 1. On power-on reset the register is set to “0”. Table 24. Pulse Shaping Indirect Address Register, PSIAD (10h) Bit1 Name Function The three bit value written to these bits determine the channel to be addressed. Data can be read from (written to) the Pulse Shaping Data Register (PSDAT). LENAD 0-2 0-2 37 LENAD 0-2 - Channel LENAD 0-2 Channel 0h 0 4h 4 1h 1 5h 5 2h 2 6h 6 3h 3 7h 7 Reserved. 1. On power-on reset the register is set to “0”. Datasheet 43 LXT384 — Octal T1/E1/J1 Transceiver Table 25. Pulse Shaping Data Register, PSDAT (11h) Bit Name Function LEN0-2 determine the LXT384 operation mode: T1 or E1. In addition, for T1 operation, LEN2-0 set the pulse shaping to meet the T1.102 pulse template at the DSX-1 crossconnect point for various cable lengths: 0-2 37 LEN 0-21, 3 - Line Length Cable Loss2 LEN2 LEN1 LEN0 0 1 1 0 - 133 ft. ABAM 0.6 dB 1 0 0 133 - 266 ft. ABAM 1.2 dB 1 0 1 266 - 399 ft. ABAM 1.8 dB 1 1 0 399 - 533 ft. ABAM 2.4 dB 1 1 1 533 - 655 ft. ABAM 3.0 dB 0 0 0 E1 G.703, 75Ω coaxial cable and 120Ω twisted pair cable. Operation Mode T1 E1 Reserved. 1. On power-on reset the register is set to “0”. 2. Maximum cable loss at 772 KHz. 3. When reading LEN, bit values appear inverted. “B2” revision silicon will fix this so the bits read back correctly. Table 26. Output Enable Register, OER (12h) Bit1 Name 7-0 OE7 - OE0 Function Setting a bit to “1” tristates the output driver of the corresponding transceiver. 1. On power-up all the register bits are set to “0”. Table 27. AIS Status Monitor Register, AIS (13h) Bit1 Name 7-0 AIS7-AIS0 Function Respective bit(s) are set to “1” every time the receiver detects a AIS condition in transceivers 7-0. 1. On power-up all the register bits are set to “0”. All AIS interrupts are cleared by a single read operation. Table 28. AIS Interrupt Enable Register, AISIE (14h) Bit1 Name 7-0 AISIE7-AISIE0 Function Transceiver 7-0 AIS interrupts are enabled by writing a “1” to the respective bit. 1. On power-up all the register bits are set to “0”. 44 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 29. AIS Interrupt Status Register, AISIS (15h) Bit1 Name 7-0 AISIS7-AISIS0 Function These bits are set to “1” every time a AIS status change has occurred since the last clear interrupt in transceivers 7-0 respectively. 1. On power-up all the register bits are set to “0”. 4.0 JTAG Boundary Scan 4.1 Overview The LXT384 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT384 also includes analog test port capabilities. This feature provides access to the TIP and RING signals in each channel (transmit and receive). This way, the signal path integrity across the primary winding of each coupling transformer can be tested. 4.2 Architecture The basic JTAG architecture of the LXT384 is illustrated in Figure 15. The LXT384 JTAG architecture includes a TAP Test Access Port Controller, data registers and an instruction register. The following paragraphs describe these blocks in detail. Datasheet 45 LXT384 — Octal T1/E1/J1 Transceiver Figure 15. JTAG Architecture Boundry Scan Data Register BSR Analog Port Scan Register ASR Device Identification Register IDR TDI MUX TDO Bypass Register BYR Instruction Register IR TCK TAP Controller TMS TRST 4.3 TAP Controller The TAP controller is a 16 state synchronous state machine controlled by the TMS input and clocked by TCK (see Figure 16).The TAP controls whether the LXT384 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 30 describes in detail each of the states represented in Figure 16. Table 30. TAP State Description (Sheet 1 of 2) 46 State Description Test Logic Reset In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the instruction register is set to the ICODE instruction. Run -Test / Idle The TAP controller stays in this state as long as TMS is Low. Used to perform tests. Capture - DR The Boundary Scan Data Register (BSR) is loaded with input pin data. Shift - DR Shifts the selected test data registers by one stage tword its serial output. Update - DR Data is latched into the parallel output of the BSR when selected. Capture - IR Used to load the instruction register with a fixed instruction. Shift - IR Shifts the instruction register by one stage. Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 30. TAP State Description (Sheet 2 of 2) Datasheet State Description Update - IR Loads a new instruction into the instruction register. Pause - IR Pause - DR Momentarily pauses shifting of data through the data/instruction registers. Exit1 - IR Exit1 - DR Exit2 - IR Exit2 - DR Temporary states that can be used to terminate the scanning process. 47 LXT384 — Octal T1/E1/J1 Transceiver Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET 0 0 RUN TEST/IDLE 1 SELECT-DR 1 SELECT-IR 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 0 PAUSE-IR 1 1 EXIT2-DR 0 EXIT2-IR 1 0 UPDATE-DR 1 4.4 1 0 PAUSE-DR 0 1 0 UPDATE-IR 1 0 JTAG Register Description The following paragraphs describe each of the registers represented in Figure 15. 48 Datasheet Octal T1/E1/J1 Transceiver — LXT384 4.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register. Bidirectional pins or tristatable pins require more than one position in the register. Table 31 shows the BSR scan cells and their functions. Data into the BSR is shifted in LSB first. The Analog Test Port can be used to verify continuity across the coupling transformer’s primary winding as shown in Figure 17. By applying a stimulus to the AT1 input, a known voltage will appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface. Table 31. Boundary Scan Register (BSR) (Sheet 1 of 4) Bit # Pin Signal I/O Type Bit Symbol 0 LOOP0 I/O PADD0 1 LOOP0 I/O PDO0 2 LOOP1 I/O PADD1 3 LOOP1 I/O PDO1 4 LOOP2 I/O PADD2 5 LOOP2 I/O PDO2 6 LOOP3 I/O PADD3 7 LOOP3 I/O PDO3 8 LOOP4 I/O PADD4 9 LOOP4 I/O PDO4 10 LOOP5 I/O PADD5 11 LOOP5 I/O PDO5 12 LOOP6 I/O PADD6 13 LOOP6 I/O PDO6 14 LOOP7 I/O PADD7 Comments PDOENB controls the LOOP0 through LOOP7 pins. 15 N/A - PDOENB Setting PDOENB to “0” configures the pins as outputs. The output value to the pin is set in PDO[0..7]. Setting PDOENB to “1” tristates all the pins. The input value to the pins can be read in PADD[0..7]. 16 Datasheet LOOP7 I/O PDO7 17 TCLK1 I TCLK1 18 TPOS1 I TPOS1 19 TNEG1 I TNEG1 20 RCLK1 O RCLK1 21 RPOS1 O RPOS1 22 N/A - HIZ1 23 RNEG1 O RNEG1 24 LOS1 O LOS1 HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to “0” enables output on the pins. Setting HIZ1 to “1” tristates the pins. 49 LXT384 — Octal T1/E1/J1 Transceiver Table 31. Boundary Scan Register (BSR) (Sheet 2 of 4) 50 Bit # Pin Signal I/O Type Bit Symbol 25 TCLK0 I TCLK0 26 TPOS0 I TPOS0 27 TNEG0 I TNEG0 28 RCLK0 O RCLK0 29 RPOS0 O RPOS0 30 N/A - HIZ0 31 RNEG0 O RNEG0 32 LOS0 O LOS0 33 MUX I MUX 34 LOS3 O LOS3 35 RNEG3 O RNEG3 36 N/A - HIZ3 37 RPOS3 O RPOS3 38 RCLK3 O RCLK3 39 TNEG3 I TNEG3 40 TPOS3 I TPOS3 41 TCLK3 I TCLK3 42 LOS2 O LOS2 43 RNEG2 O RNEG2 44 N/A - HIZ2 45 RPOS2 O RPOS2 46 RCLK2 O RCLK2 47 TNEG2 I TNEG2 48 TPOS2 I TPOS2 49 TCLK2 I TCLK2 50 INT O INT 51 N/A - SDOACKENB 52 ACK O ACK 53 DS I WRB 54 R/W I RDB 55 ALE I ALE 56 CS I CSB Comments HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZ0 to “0” enables output on the pins. Setting HIZ0 to “1” tristates the pins. HIZ3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting HIZ3 to “0” enables output on the pins. Setting HIZ3 to “1” tristates the pins. HIZ2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting HIZ2 to “0” enables output on the pins. Setting HIZ2 to “1” tristates the pins. SDOACKENB controls the ACK pin. Setting SDOACKEN to “0” enables output on ACK pin. Setting SDOACKEN to “1” tristates the pin. Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 31. Boundary Scan Register (BSR) (Sheet 3 of 4) Datasheet Bit # Pin Signal I/O Type Bit Symbol 57 MOT/INTL I MOTO 58 TCLK5 I TCLK5 59 TPOS5 I TPOS5 60 TNEG5 I TNEG5 61 RCLK5 O RCLK5 62 RPOS5 O RPOS5 63 N/A - HIZ5 64 RNEG5 O RNEG5 65 LOS5 O LOS5 66 TCLK4 I TCLK4 67 TPOS4 I TPOS4 68 TNEG4 I TNEG4 69 RCLK4 O RCLK4 70 RPOS4 O RPOS4 71 N/A - HIZ4 72 RNEG4 O RNEG4 73 LOS4 O LOS4 74 OE I OE 75 CLKE I CLKE 76 LOS7 O LOS7 77 RNEG7 O RNEG7 78 N/A - HIZ7 79 RPOS7 O RPOS7 80 RCLK7 O RCLK7 81 TNEG7 I TNEG7 82 TPOS7 I TPOS7 83 TCLK7 I TCLK7 84 LOS6 O LOS6 85 RNEG6 O RNEG6 86 N/A - HIZ6 87 RPOS6 O RPOS6 88 RCLK6 O RCLK6 Comments HIZ5 controls the RPOS5, RNEG5 and RCLK5 pins. Setting HIZ5 to “0” enables output on the pins. Setting HIZ5 to “1” tristates the pins. HIZ4 controls the RPOS4, RNEG4 and RCLK4 pins. Setting HIZ4 to “0” enables output on the pins. Setting HIZ4 to “1” tristates the pins. HIZ7 controls the RPOS7, RNEG7 and RCLK7 pins. Setting HIZ7 to “0” enables output on the pins. Setting HIZ7 to “1” tristates the pins. HIZ6 controls the RPOS6, RNEG6 and RCLK6 pins. Setting HIZ6 to “0” enables output on the pins. Setting HIZ6 to “1” tristates the pins. 51 LXT384 — Octal T1/E1/J1 Transceiver Table 31. Boundary Scan Register (BSR) (Sheet 4 of 4) 4.4.2 Bit # Pin Signal I/O Type Bit Symbol 89 TNEG6 I TNEG6 90 TPOS6 I TPOS6 91 TCLK6 I TCLK6 92 MCLK I MCLK 93 MODE I MODE 94 A4 I A4 95 A3 I A3 96 A2 I A2 97 A1 I A1 98 A0 I A0 Comments Analog Port Scan Register (ASR) The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into the ASR is shifted in LSB first. Table 32 shows the 16 possible control codes and the corresponding operation on the analog port. Table 32. Analog Port Scan Register (ASR) 52 ASR Control Code AT1 Forces Voltage To: AT2 Senses Voltage From: 11111 TTIP0 TRING0 11110 TTIP1 TRING1 11101 TTIP2 TRING2 11100 TTIP3 TRING3 11011 TTIP4 TRING4 11010 TTIP5 TRING5 11001 TTIP6 TRING6 11000 TTIP7 TRING7 10111 RTIP0 RRING0 10110 RTIP1 RRING1 10101 RTIP2 RRING2 10100 RTIP3 RRING3 10011 RTIP4 RRING4 10010 RTIP5 RRING5 10001 RTIP6 RRING6 10000 RTIP7 RRING7 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 17. Analog Test Port Application JTAG Port ASR Register RTIP7 Transceiver 7 RRING7 TTIP7 TRING7 RTIP6 Analog Mux RRING6 TTIP6 TRING6 1K Transceiver 6 RTIP0 Transceiver 0 RRING0 1K AT2 AT1 4.4.3 Device Identification Register (IDR) The IDR register provides access to the manufacturer number, part number and the LXT384 revision. The register is arranged per IEEE 1149.1 and is represented in Table 33. Data into the IDR is shifted in LSB first. Table 33. Device Identification Register (IDR) Bit # 31 - 28 Revision number 27 - 12 Part number 11 - 1 0 4.4.4 Comments Manufacturer number Set to “1” Bypass Register (BYR) The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the TDO output. 4.4.5 Instruction Register (IR) The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 34 shows the valid instruction codes and the corresponding instruction description. Datasheet 53 LXT384 — Octal T1/E1/J1 Transceiver Table 34. Instruction Register (IR) 5.0 Instruction Code # Comments EXTEST 000 Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR. Output pins values are loaded from the BSR. INTEST_ANALOG 010 Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and AT2. Refer to Table 32. SAMPLE / PRELOAD 100 Connects the BSR to TDI and TDO. The normal path between the LXT384 logic and the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins. IDCODE 110 Connects the IDR to the TDO pin. BYPASS 111 Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass Register. Test Specifications Note: Table 35 through Table 54 and Figure 18 through Figure 35 represent the performance specifications of the LXT384 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 37 through Table 54 are guaranteed over the recommended operating conditions specified in Table 36. Table 35. Absolute Maximum Ratings Parameter Symbol Min. Max Unit DC supply voltage Vcc0, Vcc1, Vccio0, Vccio1 -0.5 4.0 V DC supply voltage Tvcc 0-7 -0.5 7.0 V Input voltage on any digital pin Vin GND-0.5 5.5 V Input voltage on RTIP, RRING1 Vin GND-0.5 VCC0 + 0.5 VCC1 + 0.5 V ESD voltage on any Pin 2 Vin 2000 – V Transient latch-up current on any pin Iin 100 mA Input current on any digital pin 3 Iin -10 10 mA DC input current on TTIP, TRING 3 Iin – ±100 mA 3 Iin – ±100 mA Tstor -65 DC input current on RTIP, RRING +150 °C PP 1.6 W Case Temperature, 144 pin LQFP package Tcase 120 °C Case Temperature, 160 pin PBGA package Tcase 120 °C Storage temperature Maximum power dissipation in package Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Referenced to ground. 2. Human body model. 3. Constant input current. 54 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 36. Recommended Operating Conditions Parameter LEN Sym Min. Typ Max Unit Test Condition Digital supply voltage (VCC and VCCIO) - VCC 3.135 3.3 3.465 V 3.3V ± 5% Transmitter supply voltage, TVCC=5V nominal - TVCC 4.75 5.0 5.25 V 5V ± 5% Transmitter supply voltage, TVCC=3.3V nominal - TVCC 3.135 3.3 3.465 V 3.3V ± 5% Ambient operating temperature - Ta -40 25 +85 °C ITVCC - 440 490 mA 100% 1’s density 230 - mA 50% 1’s density IVCC - 90 120 mA Rl 25 – – Ω Typ Max1 Unit Test Conditions Average transmitter power supply current, T1 Mode 1, 2 Average digital power supply current 1, 3 Output load at TTIP and TRING Device Power Consumption Mode E1 T12 E1 T12 TVCC Load LEN 75 Ω 000 120 Ω 000 - - 760 - mW 50% 1’s - - 1270 1420 mW 100% 1’s - - 640 - mW 50% 1’s - - 1110 1280 mW 100% 1’s - - 1020 - mW 50% 1’s - - 1820 2100 mW 100% 1’s - - 1000 - mW 50% 1’s - - 1730 1940 mW 100% 1’s - - 820 - mW 50% 1’s - - 1500 1730 mW 100% 1’s - - 1400 - mW 50% 1’s - - 2670 2960 mW 100% 1’s 3.3V 3.3V 100 Ω 101-111 75 Ω 000 5.0V 5.0V 120 Ω 000 100 Ω 101-111 1. Current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 3. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load. Table 37. DC Characteristics (Sheet 1 of 2) Parameter Sym Min. Typ Max Unit VIH 2 – – V VIL – – 0.8 V High level output voltage VOH 2.4 – VCCIO V IOUT= 400µA 1 VOL – – 0.4 V IOUT= 1.6mA High level input voltage Low level input voltage 1 Low level output voltage Test Condition 1. Output drivers will output CMOS logic levels into CMOS loads. Datasheet 55 LXT384 — Octal T1/E1/J1 Transceiver Table 37. DC Characteristics (Sheet 2 of 2) Parameter Sym Min. Typ Max Unit Vinl – – 1/3VCC-0.2 V Midrange level input voltage Vinm 1/3VCC+0.2 1/2VCC 2/3VCC-0.2 V High level input voltage Vinh 2/3VCC+0.2 – – V Low level input current Iinl – – 50 µA High level input current Iinh – – 50 µA Low level input voltage MODE, LOOP0-7 and JASEL Input leakage current Iil -10 +10 µA Tri state leakage current Ihz -10 +10 µA Tri state output current Ihz – – 1 µA – – – 50 TMS TDI TRST – – 50 Line short circuit current Input leakage mA RMS Test Condition The VCC supply refers to VCC0 or VCC1 only. TTIP, TRING 2 x 11 Ω series resistors and 1:2 transformer µA 1. Output drivers will output CMOS logic levels into CMOS loads. Table 38. E1 Transmit Transmission Characteristics (Sheet 1 of 2) Parameter Output pulse amplitude Peak voltage of a space 75Ω 120Ω 75Ω 120Ω Sym – – Transmit amplitude variation with supply – Difference between pulse sequences – Pulse width ratio of the positive and negative pulses – Transmit transformer turns ratio for 75/120Ω characteristic impedance Transmit return loss 75 Ω coaxial cable1 51kHz to 102 kHz Transmit return loss 120 Ω twisted pair cable1 51kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Typ Max Unit 2.14 2.37 2.60 V 2.7 3.0 3.3 V -0.237 0.237 V -0.3 0.3 V -1 +1 % 200 mV 0.95 – – 2.048 MHz to 3.072 MHz 102 kHz to 2.048 MHz Min. – 17 17 15 17 15 20 15 20 15 20 For 17 consecutive pulses Rt = 11 Ω ± 1% 1:2 15 Tested at the line side At the nominal half amplitude 1.05 15 Test Condition dB – dB dB dB – dB dB Using components in the LXD384 evaluation board. Using components in the LXD384 evaluation board 1. Guaranteed by design and other correlation methods. 56 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 38. E1 Transmit Transmission Characteristics (Sheet 2 of 2) Parameter Sym Min. Typ Max Unit – – 0.030 0.050 U.I. Transmit intrinsic jitter; 20Hz to 100kHz Transmit path delay Bipolar mode 2 U.I. Unipolar mode 7 U.I. Test Condition Tx path TCLK is jitter free JA Disabled 1. Guaranteed by design and other correlation methods. Table 39. E1 Receive Transmission Characteristics Parameter Permissible cable attenuation Sym Min. Typ Max Unit Test Condition – – – 12 dB Receiver dynamic range DR 0.5 – – Vp Signal to noise interference margin S/I -15 – – dB Per G.703, O.151 @ 6 dB cable Attenuation SRE 43 50 57 % Rel. to peak input voltage Data slicer threshold – – 150 – mV Loss of signal threshold – – 200 – mV LOS hysteresis – – 50 – mV Data decision threshold Consecutive zeros before loss of signal – – LOS reset – 12.5% Low limit 1Hz to 20Hz input jitter 20Hz to 2.4kHz tolerance 1 18kHz to 100kHz 32 2048 – – – – – 36 – 1.5 – – 0.2 Note 1 U.I. Cable Attenuation is 6 dB @1.024 MHz – 70 – kΩ – – – ±1 % Common mode input impedance to ground – – 20 – kΩ 102 - 2048 kHz – 2048kHz - 3072 kHz dB 20 – 20 1’s density U.I. – 20 ETSI 300 233 specification U.I. Input termination resistor tolerance 51 kHz - 102 kHz G.775 recommendation G735 recommendation Differential receiver input impedance Input return loss1 @1024 kHz dB dB Measured against nominal impedance using components in the LXD384 evaluation board. LOS delay time – – 30 – µs Data recovery mode LOS reset – 10 – 255 marks Data recovery mode Receive intrinsic jitter, RCLK output – – 0.040 0.0625 U.I. Receive path delay Bipolar mode 1 U.I. Unipolar mode 6 U.I. Wide band jitter JA Disabled 1. Guaranteed by design and other correlation methods. Datasheet 57 LXT384 — Octal T1/E1/J1 Transceiver Table 40. T1 Transmit Transmission Characteristics Parameter Sym Min. Typ Max Unit Test Condition Output pulse amplitude – 2.4 3.0 3.6 V Peak voltage of a space – -0.15 – +0.15 V Driver output impedance1 – – 1 – Ω Transmit amplitude variation with power supply – -1 – +1 % Ratio of positive to negative pulse amplitude – 0.95 – 1.05 – T1.102, isolated pulse Difference between pulse sequences – – – 200 mV Pulse width variation at half amplitude – – – 20 ns For 17 consecutive pulses, GR-499-CORE 8KHz - 40KHz – 10Hz - 40KHz – – @ 772 KHz – @ 1544 KHz 12.6 -29 UIpk-pk – 17.9 dBm dBm 21 15 21 15 21 dB Bipolar mode 2 U.I. Unipolar mode 7 U.I. 102 kHz to 2.048 MHz – 2.048 MHz to 3.072 MHz Transmit path delay 0.025 15 51kHz to 102 kHz Transmit Return Loss 1 0.025 AT&T Pub 62411 TCLK is jitter free 0.050 Wide Band Output power levels2 @ 772 KHz 0.020 10Hz - 8KHz Jitter added by Transmitter1 Measured at the DSX dB – dB T1.102 - 1993 Referenced to power at 772 KHz With transmit series resistors (TVCC=5V). Using components in the LXD384 evaluation board. JA Disabled 1. Guaranteed by design and other correlation methods. 2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern. Table 41. T1 Receive Transmission Characteristics (Sheet 1 of 2) Parameter Permissible cable attenuation Sym Min. Typ Max Unit Test Condition – – – 12 dB Receiver dynamic range DR 0.5 – – Vp Signal to noise interference margin S/I -16.5 – – dB @ 655 ft. of 22 ABAM cable SRE 63 70 77 % Rel. to peak input voltage Data slicer threshold – – 150 – mV Loss of signal threshold – – 200 – mV Data decision threshold @ 772 KHz LOS hysteresis – – 50 – mV Consecutive zeros before loss of signal – 100 175 250 – T1.231 - 1993 LOS reset – 12.5% – – – 1’s density 1. Guaranteed by design and other correlation methods. 58 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 41. T1 Receive Transmission Characteristics (Sheet 2 of 2) Parameter Sym Low limit 0.1Hz to 1Hz input jitter 4.9Hz to 300Hz tolerance 1 10KHz to 100KHz Min. - - 0.4 - Input termination resistor tolerance - - Common mode input impedance to ground - - 51 KHz - 102 KHz - 70 20 - kΩ ±1 % - kΩ - - 20 LOS delay time LOS reset 1 Receive intrinsic jitter, RCLK output U.I. dB 20 2048 KHz - 3072 KHz Test Condition AT&T Pub. 62411 U.I. 20 102 - 2048 KHz Unit U.I. 28 - Receive path delay Max 138 - Differential receiver input impedance Input return loss1 Typ dB dB @772 kHz Measured against nominal impedance. Using components in the LXD384 evaluation board. - - 30 - µs Data recovery mode - 10 - 255 - Data recovery mode - - 0.035 0.0625 U.I. Bipolar mode 1 U.I. Unipolar mode 6 U.I. Wide band jitter JA Disabled 1. Guaranteed by design and other correlation methods. Table 42. Jitter Attenuator Characteristics (Sheet 1 of 2) Parameter Min. Typ Max Unit 32bit FIFO - 2.5 - Hz 64bit FIFO - 3.5 - Hz 32bit FIFO - 2.5 - Hz 64bit FIFO - 3.5 - Hz 32bit FIFO - 3 - Hz 64bit FIFO - 3 - Hz 32bit FIFO - 6 - Hz 64bit FIFO - 6 - Hz E1 - 3.5 - Hz T1 - 6 - Hz 32bit FIFO - 16 - UI 64bit FIFO - 32 - UI Test Condition JACF=0 E1 jitter attenuator 3dB corner frequency, host mode1 JACF=1 Sinusoidal jitter modulation JACF=0 T1 jitter attenuator 3dB corner frequency, host mode1 JACF=1 Jitter attenuator 3dB corner frequency, hardware mode1 Data latency delay Delay through the Jitter attenuator only. Add receive and transmit path delay for total throughput delay. 1. Guaranteed by design and other correlation methods. Datasheet 59 LXT384 — Octal T1/E1/J1 Transceiver Table 42. Jitter Attenuator Characteristics (Sheet 2 of 2) Parameter Input jitter tolerance before FIFO overflow or underflow Min. Typ Max Unit 32bit FIFO - 24 - UI 64bit FIFO - 56 - UI Test Condition E1 jitter attenuation @ 3 Hz @ 40 Hz @ 400 Hz @ 100 KHz -0.5 -0.5 +19.5 +19.5 – – dB ITU-T G.736, See Figure 34 on page 75 T1 jitter attenuation @ 1 Hz @ 20 Hz @ 1 KHz @ 1.4 KHz @ 70 KHz 0 0 33.3 40 40 – – dB AT&T Pub. 62411, See Figure 34 on page 75 0.060 0.11 UI ETSI CTR12/13 Output jitter Output Jitter in remote loopback1 1. Guaranteed by design and other correlation methods. Table 43. Analog Test Port Characteristics Parameter 3 dB bandwidth Sym Min. Typ Max Unit At13db - 5 - MHz V V Input voltage range At1iv 0 - VCC0 VCC1 Output voltage range At2ov 0 - VCC0 VCC1 Test Condition Table 44. Transmit Timing Characteristics (Sheet 1 of 2) Parameter Sym Min. Typ Max Unit E1 MCLK – 2.048 – MHz T1 MCLK – 1.544 – MHz Master clock tolerance – -100 – 100 ppm Master clock duty cycle – 40 – 60 % Test Condition Master clock frequency E1 Tw 219 244 269 ns T1 Tw 291 324 356 ns E1 Tclke1 - 2.048 - MHz T1 Tclkt1 - 1.544 - MHz Output pulse width Transmit clock frequency Transmit clock tolerance Tclkt -50 – +50 ppm Transmit clock burst rate Tclkb - – 20 MHz Transmit clock duty cycle Tdc 10 – 90 % NRZ mode Tmpwe1 236 – 252 ns RZ mode (TCLK = H for >16 clock cycles) Tsut 20 - - ns E1 TPOS/TNEG pulse width (RZ mode) TPOS/TNEG to TCLK setup time 60 Gapped transmit clock Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 44. Transmit Timing Characteristics (Sheet 2 of 2) Parameter Sym Min. Typ TCLK to TPOS/TNEG hold time Delay time OE Low to driver High Z Max Unit Tht 20 - - ns Toez - - 1 µs Ttz 50 60 75 µs Delay time TCLK Low to driver High Z Test Condition Figure 18. Transmit Clock Timing Diagram TCLK tSUT TPOS tHT TNEG Table 45. Receive Timing Characteristics (Sheet 1 of 2) Parameter Sym Min. Typ Max Unit E1 – – ±80 – ppm Relative to nominal frequency T1 – – ±180 – ppm MCLK = ±100 ppm Rckd 40 50 60 % E1 Tpw 447 488 529 ns T1 Tpw 583 648 713 ns E1 Tpwl 203 244 285 ns T1 Tpwl 259 324 389 ns E1 Tpwh 203 244 285 ns T1 Tpwh 259 324 389 ns Tr 20 – – ns E1 Tpwdl 200 244 300 ns T1 Tpwdl 250 324 400 ns 200 244 – ns 200 324 – ns Clock recovery capture range Receive clock duty cycle 1 Receive clock pulse width 1 Test Condition Receive clock pulse width Low time Receive clock pulse width High time Rise/fall time 4 RPOS/RNEG pulse width (MCLK=H) 2 E1 RPOS/RNEG to RCLK rising setup time @ CL=15 pF Tsur T1 1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 2. Clock recovery is disabled in this mode. 3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit. 4. For all digital outputs. Datasheet 61 LXT384 — Octal T1/E1/J1 Transceiver Table 45. Receive Timing Characteristics (Sheet 2 of 2) Parameter Sym E1 RCLK Rising to RPOS/RNEG hold time Min. Typ Max Unit 200 244 – ns 200 324 – ns – – 5 ns Test Condition Thr T1 Delay time between RPOS/RNEG and RCLK – MCLK = H 3 1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 2. Clock recovery is disabled in this mode. 3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit. 4. For all digital outputs. Figure 19. Receive Clock Timing Diagram tPW RCLK tPWH tPWL tSUR tHR RPOS RNEG CLKE = 1 tSUR tHR RPOS RNEG CLKE = 0 Table 46. JTAG Timing Characteristics Parameter Sym Min. Typ Max Unit Cycle time Tcyc 200 - - ns J-TMS/J-TDI to J-TCK rising edge time Tsut 50 - - ns Tht 50 - - ns Tdod - - 50 ns J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to J-TDO valid 62 Test Conditions Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 20. JTAG Timing tCYC TCK tSUR tHT TMS TDI tDOD TDO Table 47. Intel Mode Read Timing Characteristics2 Sym Min. Typ1 Max Unit Tsalr 10 – – ns Valid address latch pulse width Tvl 30 – – ns Latch active to active read setup time Tslr 10 – – ns Chip select setup time to active read Tscsr 0 – – ns Chip select hold time from inactive read Thcsr 0 – – ns Address hold time from inactive ALE Thalr 5 Active read to data valid delay time Tprd 10 – 50 ns Parameter Address setup time to latch ns Address setup time to RD inactive Thar 1 – – ns Address hold time from RD inactive Tsar 5 – – ns Inactive read to data tri-state delay time Tzrd 3 – 35 ns Valid read signal pulse width Tvrd 60 – – ns Inactive read to inactive INT delay time Test Conditions Tint – – 10 ns Active chip select to RDY delay time Tdrdy 0 – 12 ns Active ready Low time Tvrdy – – 40 ns Inactive ready to tri-state delay time Trdyz – – 3 ns 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Datasheet 63 LXT384 — Octal T1/E1/J1 Transceiver Figure 21. Non-Multiplexed Intel Mode Read Timing tSAR ADDRESS A4 - A0 tHAR ALE (pulled High) tHCSR tSCSR CS tVRD RD tPRD tZRD D7 - D0 DATA OUT tINT INT tDRDY tDRDY tRDYZ tVRDY Tristate Tristate RDY Figure 22. Multiplexed Intel Mode Read Timing tVL tSLR ALE tSCSR tHSCR CS tVRD tPRD RD tSALR tZRD tHALR ADDRESS AD7-AD0 DATA OUT tINT INT tDRDY tDRDY Tristate RDY 64 tVRDY tRDYZ Tristate Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 48. Intel Mode Write Timing Characteristics2 Parameter Sym Address setup time to latch Min. Typ1 Max Unit Tsalw 10 – – ns Valid address latch pulse width Tvl 30 – – ns Latch active to active write setup time Tslw 10 – – ns Chip select setup time to active write Tscsw 0 – – ns Chip select hold time from inactive write Thcsw 0 – – Address hold time from inactive ALE Thalw 5 Data valid to write active setup time Tsdw 40 – – ns Data hold time to active write Thdw 30 – – ns ns ns Address setup time to WR inactive Thaw 2 – – ns Address hold time from WR inactive Tsaw 6 – – ns Valid write signal pulse width Tvwr 60 – – ns Tint – – 10 ns Chip select to RDY delay time Tdrdy 0 – 12 ns Active ready Low time Tvrdy – – 40 ns Inactive ready to tri-state delay time3 Trdyz – – 3 ns Inactive write to inactive INT delay time 3 Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. 3. These times don't apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset Operation and Host Mode sections for more information. Datasheet 65 LXT384 — Octal T1/E1/J1 Transceiver Figure 23. Non-Multiplexed Intel Mode Write Timing tSAW A4-A0 ALE ADDRESS (pulled High) tHAW tSCSW tHCSW CS tVWR WR tHDW tSDW D7-D0 WRITE DATA tINT INT tDRDY tDRDY tVRDY tRDYZ Tristate Tristate RDY Figure 24. Multiplexed Intel Mode Write Timing tSLW ALE tVL tSCSW tHCSW CS tVWR WR tHALW tHDW tSALW tSDW ADDRESS AD7-AD0 WRITE DATA tINT INT tDRDY tDRDY Tristate tVRDY tDRDYZ Tristate RDY 66 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 49. Motorola Bus Read Timing Characteristics2 Parameter Sym Min. Typ1 Max Unit Address setup time to address or data strobe Tsar 10 – – ns Address hold time from address or data strobe Thar 5 – – ns Valid address strobe pulse width Tvas 95 – – ns R/W setup time to active data strobe Tsrw 10 – – ns R/W hold time from inactive data strobe Thrw 0 – – ns Chip select setup time to active data strobe Tscs 0 – – ns Chip select hold time from inactive data strobe Thcs 0 – – ns Address strobe active to data strobe active delay Tasds 20 – – ns Delay time from active data strobe to valid data Tpds 3 – 30 ns Delay time from inactive data strobe to data High Z Tdz 3 – 30 ns Valid data strobe pulse width Tvds 60 – – ns Inactive data strobe to inactive INT delay time Tint – – 10 ns Data strobe inactive to address strobe inactive delay Tdsas 15 – – ns DS asserted to ACK asserted delay Tdackp – – 40 ns DS deasserted to ACK deasserted delay Tdack – – 10 ns Active ACK to valid data delay Tpack – – 0 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Datasheet 67 LXT384 — Octal T1/E1/J1 Transceiver Figure 25. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS tHAR (pulled High) tSRW tHRW R/W tSCS tHCS CS tVDS DS tPDS tDZ D7-D0 DATA OUT tINT INT tDACKP tPACK tDACK ACK Figure 26. Multiplexed Motorola Mode Read Timing tVAS tDSAS AS tSRW tHRW R/W tSCS tHCS CS tASDS tVDS DS tSAR D7-D0 tPDS tHAR tDZ DATA OUT ADDRESS tINT INT tDACKP tPACK tDACK ACK 68 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Table 50. Motorola Mode Write Timing Characteristics2 Parameter Sym Min. Typ1 Max Unit Address setup time to address strobe Tsas 10 – – ns Address hold time to address strobe Thas 5 – – ns Valid address strobe pulse width Tvas 95 – – ns R/W setup time to active data strobe Tsrw 10 – – ns R/W hold time from inactive data strobe Thrw 0 – – ns Chip select setup time to active data strobe Tscs 0 – – ns Chip select hold time from inactive data strobe Thcs 0 – – ns Address strobe active to data strobe active delay Tasds 20 – – ns Data setup time to DS deassertion Tsdw 40 – – ns Data hold time from DS deassertion Thdw 30 – – ns Valid data strobe pulse width Tvds 60 – – ns Inactive data strobe to inactive INT delay time Tint – – 10 ns Data strobe inactive to address strobe inactive delay Tdsas 15 – – ns Active data strobe to ACK output enable time Tdack 0 – 12 ns DS asserted to ACK asserted delay Tdackp – 40 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Figure 27. Non-Multiplexed Motorola Mode Write Timing A4-A0 ADDRESS tSAS tHAS AS (pulled High) tSRW tHRW R/W tSCS tHCS CS tVDS DS tSDW tHDW WRITE DATA D7-D0 tINT INT tDACKP tDACK ACK Datasheet 69 LXT384 — Octal T1/E1/J1 Transceiver Figure 28. Multiplexed Motorola Mode Write Timing tVAS tDSAS AS tHRW tSRW R/W tHCS tSCS CS tASDS tVDS DS tSAS D7-D0 tHDW tHAS tSDW ADDRESS WRITE DATA tINT INT tDACKP tDACK ACK Table 51. Serial I/O Timing Characteristics Sym Min. Typ1 Max Unit Test Condition Rise/fall time any pin Trf - - 100 ns Load 1.6mA, 50 pF SDI to SCLK setup time Tdc 5 - - ns SCLK to SDI hold time Tcdh 5 - - ns Parameter SCLK Low time Tcl 25 - - ns SCLK High time Tch 25 - - ns Tr, Tf - - 50 ns Tcc 10 - - ns SCLK rise and fall time CS falling edge to SCLK rising edge Last SCLK edge to CS rising edge Tcch 10 - - ns CS inactive time Tcwh 50 - - ns SCLK to SDO valid delay time Tcdv - - 5 ns SCLK falling edge or CS rising edge to SDO High Z Tcdz - 10 - ns 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 70 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 29. Serial Input Timing CS tCWH tCC tCH tCCH tCL SCLK tCDH tDC tCDH LSB LSB SDI MSB CONTROL BYTE DATA BYTE Figure 30. Serial Output Timing CLKE = 0 1 2 3 4 5 6 7 8 9 10 11 1 2 12 13 14 15 5 6 16 SCLK CS tCCH tCDZ SDO 0 4 3 7 CLKE = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK CS 0 SDO 1 2 3 4 5 tCDZ 6 tCCH 7 Table 52. Transformer Specifications Tx/Rx Turns Ratio2 Primary Inductance mH (min.) Leakage Inductance µH (max.) Interwinding Capacitance pF (max.) TX 1:2 1.2 0.60 60 RX 1:2 1.2 0.60 60 DCR Ω (max.) 0.70 pri 1.20 sec 1.10 pri 1.10 sec Dielectric Breakdown Voltage V1 (min.) 1500 Vrms 1500 Vrms 1. This parameter is application dependent. 2. LIU side: Line side. Transformer turns ratio accuracy is ± 2%. Datasheet 71 LXT384 — Octal T1/E1/J1 Transceiver Table 53. G.703 2.048 Mbit/s Pulse Mask Specifications Cable Parameter Unit TWP Coax Test load impedance 120 75 Ω Nominal peak mark voltage 3.0 2.37 V Nominal peak space voltage 0 ±0.30 0 ±0.237 V 244 244 ns Ratio of positive and negative pulse amplitudes at center of pulse 95-105 95-105 % Ratio of positive and negative pulse amplitudes at nominal half amplitude 95-105 95-105 % Nominal pulse width Figure 31. E1, G.703 Mask Templates 20% 194 ns (244- 50) 20% V = 100% 10% 10% 269 ns (244+25) NOMINAL PULSE 50% 244 ns 20% 10% 10% 0% 10% 10% 219 ns (244-25) 488 ns (244+244) Table 54. T1.102 1.544 Mbit/s Pulse Mask Specifications Cable Parameter Unit TWP Test load impedance 100 Ω Nominal peak mark voltage 3.0 V Nominal peak space voltage 0 ±0.15 V 324 ns 95-105 % Nominal pulse width Ratio of positive and negative pulse amplitudes 72 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 32. T1, T1.102 Mask Templates 1.20 1.00 0.80 Normalized Amplitude 0.60 0.40 0.20 -0.80 -0.60 -0.40 -0.20 0.00 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -0.20 -0.40 -0.60 Tim e [UI] Datasheet 73 LXT384 — Octal T1/E1/J1 Transceiver Figure 33. LXT384 Jitter Tolerance Performance 1000 UI Jitter 100 UI 28 UI @ 4.9 Hz AT&T 62411, Dec 1990 (T1) 18 UI @ 1.8 Hz LXT384 typ. 28 UI @ 300 Hz 10 UI GR-499-CORE, Dec 1995 (T1) 5 UI @ 500 Hz 1 UI 1.5 UI @ 2.4 kHz 1.5 UI @ 20 Hz .1 UI 1 Hz 0.4 UI @ 10 kHz ITU G.823, Mar 1993 (E1) 0.2 UI @ 18 kHz 0.1 UI @ 8 kHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency 74 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 34. LXT384 Jitter Transfer Performance E1 10 dB ITU G.736 Template 0.5 dB @ 3Hz 0.5 dB @ 40Hz 0 dB -10 dB Gain f 3dB=2.5 Hz -19.5 dB @ 20 kHz -20 dB f 3dB=3.5 Hz -19.5 dB @ 400 Hz -30 dB -40 dB LXT384 typ. -60 dB -80 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency T1 10 dB 0 dB @ 1 Hz 0 dB @ 20 Hz 0.1 dB @ 40 Hz 0 dB 0.5 dB @ 350 Hz AT&T Pub 62411 GR-253-CORE TR-TSY-000009 Gain -10 dB -6 dB @ 2 Hz -20 dB -33.3 dB @ 1 kHz f -30 dB 3dB= f -33.7 dB @ 2.5kHz 3 Hz 3dB= -40 dB @ 1.4 kHz 6 Hz -40 dB -40 dB @ 70 kHz -49.2 dB @ 15kHz LXT384 typ. -60 dB -60 dB @ 57 Hz -80 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency Datasheet 75 LXT384 — Octal T1/E1/J1 Transceiver Figure 35. LXT384 Output Jitter for CTR12/13 Applications Jitter Amplitude (Ulpp) 0.2 0.15 0.1 LXT384 typ, f 3dB = 2.5Hz & 3.5 Hz 0.05 0 10 Hz 5.1 20 Hz 100 Hz 1 kHz Frequency 10 kHz 100 kHz Recommendations and Specifications • AT&T Pub 62411 • ANSI T1.102 - 199X Digital Hierarchy Electrical Interface • ANSI T1.231 -1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring 76 • • • • • • • • Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives • • • • G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria Bellcore GR-499-CORE Transport Systems Generic Requirements ETS 300166 Physical and Electrical Characteristics ETS 300386-1 Electromagnetic Compatibility Requirement G.703 Physical/electrical characteristics of hierarchical digital interfaces G. 704 Functional characteristics of interfaces associated with network nodes G.735 Characteristics of Primary PCM multiplex equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s G.772 Protected Monitoring Points provided on Digital Transmission Systems G.775 Loss Of Signal (LOS) and alarm indication (AIS) defect detection and clearance criteria G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks Datasheet Octal T1/E1/J1 Transceiver — LXT384 • G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy • O.151 Specification of instruments to measure error performance in digital systems • OFTEL OTR-001 Short Circuit Current Requirements Datasheet 77 LXT384 — Octal T1/E1/J1 Transceiver 6.0 Mechanical Specifications Figure 36. Low Quad Flat Packages (LQFP) Dimensions 144 Pin LQFP • Part Number LXT384LE • Extended Temperature Range (-40°C to 85° C) D NOTE: All dimensions in millimeters. D/2 b e E/2 E1/2 e/2 E1 E M 0 DEG. MIN. A2 0.08 / 0.20 R. D1/2 A1 D1 0.08 R. MIN. 0.25 A L 1.00 REF. 0 - 7 DEG. Millimeters Dimension1 Minimum Nominal Maximum A - - 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 D 22.00 B.S.C. D1 20.00 B.S.C. E 22.00 B.S.C. E1 20.00 B.S.C. e 0.50 B.S.C. L 0.45 0.60 0.75 M 0.14 - - 1. See JEDEC Publication for additional specifications. 78 Datasheet Octal T1/E1/J1 Transceiver — LXT384 Figure 37. Plastic Ball Grid Array (PBGA) Package Dimensions 160 Pin PBGA • Part Number LXT384BE • Extended Temperature Range (-40°C to 85° C) 15.00 13.00 ±0.20 1.00 REF 13.00 4.72 ±0.10 PIN #A1 CORNER 1.00 A 0.50 B ±0.10 C PIN #A1 ID D 4.72 ±0.10 1.00 E F 13.00 15.00 ±0.20 G 13.0 H J K L M N P Ø1.00 (3 plcs) 14 13 12 11 10 9 TOP VIEW 8 7 6 5 4 3 2 1 1.00 R BOTTOM VIEW 0.85 1.81 ± 0.19 NOTE: 1. ALL DIMENSIONS IN MILLIMETERS. SEATING PLANE SIDE VIEW Datasheet 0.56 ±0.04 0.40 ± 0.10 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994. 3. TOLERANCE = ± 0.05 UNLESS SPECIFIED OTHERWISE. 79