PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74LPT646 PI74LPT652 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS 3.3V 8-Bit Registered Transceiver Product Features Product Description • Compatible with LCX™ and LVT™ families of products • Supports 5V tolerant mixed signal mode operation – Input can be 3V or 5V – Output can be 3V or connected to 5V bus • Advanced low power CMOS operation • Excellent output drive capability: Balanced drives (24 mA sink and source) • Low ground bounce outputs • Hysteresis on all inputs • Industrial operating temperature range: –40°C to +85°C • Packages available: – 24-pin 173-mil wide plastic TSSOP (L) – 24-pin 150-mil wide plastic QSOP (Q) – 24-pin 150-mil wide plastic TQSOP (R) – 24-pin 300-mil wide plastic SOIC (S) Pericom Semiconductor’s PI74LPT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74LPT646 and PI74LPT652 are designed with a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The PI74LPT652 utilizes GAB and GBA signals to control the transceiver functions. The PI74LPT646 utilizes the enable control (G) and direction pins (DIR) to control the transceiver functions. SAB and SBA control pins are used to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. A low input level selects real-time data and a high selects stored data. The PI74LPT646 and PI74LPT652 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system. Logic Block Diagram PI74LPT652 ONLY GBA GAB PI74LPT646 ONLY G DIR CPBA SBA CPAB SAB B REG 1 OR 8 CHANNELS 0D C0 B0 A REG A0 0D C0 TO 7 OTHER CHANNELS 1 PS2064A 01/15/97 PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74LPT646 Product Pin Configuration CPAB SAB DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 24 2 23 3 22 4 24-PIN 21 L24 5 20 Q24 6 19 R24 7 18 S24 8 17 9 16 10 15 11 14 12 13 VCC PI74LPT652 Product Pin Configuration CPAB CPBA SAB SBA GAB G A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 GND 1 24 2 23 3 22 4 24-PIN 21 L24 5 20 Q24 6 19 R24 7 18 S24 8 17 9 16 10 15 11 14 12 13 Product Pin Description Pin Name A0-A7 VCC CPBA SBA B0-B7 GBA B0 CPAB, CPBA SAB, SBA DIR, G GAB, GBA GND VCC B1 B2 B3 B4 B5 B6 B7 Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs (LPT646) Output Enable Inputs (LPT652) Ground Power PI74LPT646 Truth Table DATA I/O(2) Inputs Function/Operation Isolation Store A and B Data Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus G H H L L L L DIR X X L L H H CPAB H or L ↑ X X X H or L CPBA H or L ↑ X H or L X X SAB X X X X L H SBA X X L H X X A0-A7 Input B0-B7 Input Output Input Input Output PI74LPT652 Truth Table DATA I/O(2) Inputs Function/Operation Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus GAB L L X H L L L L H H H GBA H H H H X L L L H H L CPAB H or L ↑ ↑ ↑ H or L ↑ X X X H or L H or L CPBA H or L ↑ H or L ↑ ↑ ↑ X H or L X X H or L SAB X X X X(2) X X X X L H H SBA X X X X X X(2) L H X X H A0-A7 Input B0-B7 Input Input Unspecified(1) Input Output (1) Unspecified Input Output Input Output Input Input Output Output Output Notes: 1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 2. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. H = High Voltage Level; L = Low Voltage Level; X = Don't Care; ↑ = LOW-to-HIGH transition 2 PS2064A 01/15/97 PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 REAL-TIME TRANSFER BUS A TO B REAL-TIME TRANSFER BUS B TO A BUS BUS BUS BUS A B A B LPT646 DIR L G L CPAB CPBA X X SAB X SBA L LPT646 DIR H CPAB CPBA X X SAB L SBA X LPT652 GAB GBA CPAB CPBA L L X X SAB X SBA L LPT652 GAB GBA CPAB CPBA H H X X SAB L SBA X CPAB CPBA X H or L H or L X SAB X H SBA H X GAB GBA CPAB CPBA H L H or L H or L SAB H SBA H STORAGE FROM A AND/OR B G L TRANSFER STORES DATA TO A AND/OR B BUS BUS BUS BUS A B A B LPT646 DIR H L X G L L H CPAB CPBA ↑ X X ↑ ↑ ↑ SAB X X X SBA X X X LPT652 GAB GBA CPAB CPBA X H ↑ X L X X ↑ L H ↑ ↑ SAB X X X SBA X X X LPT646(1) DIR L H LPT652 G L L 1. Note: The LPT646 cannot transfer data to A bus and B bus simultaneously. 3 PS2064A 01/15/97 PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ –65°C to +150°C Ambient Temperature with Power Applied ........................... –40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) .... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) –0.5V to +7.0V DC Input Voltage .................................................................. –0.5V to +7.0V DC Output Current ............................................................................ 120 mA Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Dissipation ................................................................................... 1.0W DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V) Parameters VIH IOZH IOZL VIK IODH IODL VOH Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW Voltage (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VOL Output LOW Voltage IOS IOFF VH Short Circuit Current(4) Power Down Disable Input Hysteresis VIL IIH IIL Test Conditions(1) Description Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Min. Typ(2) Max. Units 2.2 2.0 –0.5 — — — 5.5 5.5 0.8 V V V — — — — — — –0.7 –60 90 — 3.0 3.0 — — 0.2 0.3 –85 — 150 ±1 ±1 ±1 ±1 ±1 ±1 –1.2 –110 200 — — — — 0.2 0.4 0.5 –240 ±100 — µA µA µA µA µA µA V mA mA V V V VCC = Max. VIN = 5.5V — VCC = Max. VIN = VCC — VCC = Max. VIN = GND — VCC = Max. VIN = GND — VCC = Max. VOUT = 5.5V — VCC = Max. VOUT = GND — VCC = Min., IIN = –18 mA — VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 VCC = Min. IOH = –0.1 mA Vcc-0.2 VIN = VIH or VIL IOH = –3 mA 2.4 VCC = 3.0V, IOH = –8 mA 2.4(5) VIN = VIH or VIL IOH = –24 mA 2.0 VCC = Min. IOL = 0.1 mA — VIN = VIH or VIL IOL = 16 mA — IOL = 24 mA — VCC = Max.(3), VOUT = GND –60 VCC = 0V, VIN or VOUT ≤ 4.5V — — V V V mA µA mV Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC – 0.6V at rated current. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) CIN COUT Description Test Conditions Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Typ. Max. Units 4.5 5.5 6 8 pF pF Note: 1. This parameter is determined by device characterization but is not production tested. 4 PS2064A 01/15/97 PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Parameters Description ICC Quiescent Power Supply Current Test Conditions(1) Min. Typ(2) Max. Units VCC = Max. VIN = GND or VCC 0.1 10 µA (3) ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC – 0.6V 2.0 30 µA ICCD Dynamic Power Supply(4) VCC = Max., Outputs Open G = DIR = GND One Bit Toggling 50% Duty Cycle VIN = VCC VIN = GND 50 75 µA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fI = 10 MHZ 50% Duty Cycle G = DIR = GND One Bit Toggling VIN = VCC – 0.6V VIN = GND 0.6 2.3 mA VCC = Max., Outputs Open fI = 2.5 MHZ 50% Duty Cycle G = DIR = GND 8 Bits Toggling VIN = VCC – 0.6V VIN = GND 2.1 4.7(5) Notes: 1. ForMax. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 5 PS2064A 01/15/97 PI74LPT646 PI74LPT652 3.3V 8-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74LPT646 Switching Characteristics over Operating Range(1) Parameters Description Conditions(2) tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU Propagation Delay Bus to Bus Output Enable Time G, DIR to Bus Output Disable Time(3) G, DIR to Bus Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Setup Time HIGH or LOW, BUS to Clock Hold Time HIGH or LOW, Bus to Clock Clock Pulse Width(3) HIGH or LOW CL = 50pF RL = 500Ω tH tW LPT646 Com. Min.(3) Max. LPT646A Com. Min.(3) Max. LPT646C Com. Min.(3) Max. Units 2.0 7.5 2.0 6.3 1.5 5.4 ns 2.0 14.0 2.0 9.8 1.5 7.8 ns 2.0 9.0 2.0 6.3 1.5 6.3 ns 2.0 9.0 2.0 6.3 1.5 5.7 ns 2.0 9.5 2.0 7.7 1.5 6.2 ns 4.0 — 2.0 — 2.0 — ns 2.0 — 1.5 — 1.5 — ns 6.0 — 5.0 — 5.0 — ns PI74LPT652 Switching Characteristics over Operating Range(1) Parameters Description Conditions(2) tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU Propagation Delay Bus to Bus Output Enable Time GBA, GAB to Bus Output Disable Time(3) GBA, GAB to Bus Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Setup Time HIGH or LOW, BUS to Clock Hold Time HIGH or LOW, Bus to Clock Clock Pulse Width(3) HIGH or LOW CL = 50pF RL = 500Ω tH tW LPT652 Com. (3) Min. Max. LPT652A Com. (3) Min. Max. LPT652C Com. (3) Min. Max. Units 2.0 7.5 2.0 6.3 1.5 5.4 ns 2.0 14.0 2.0 9.8 1.5 7.8 ns 2.0 9.0 2.0 6.3 1.5 6.3 ns 2.0 9.0 2.0 6.3 1.5 5.7 ns 2.0 9.5 2.0 7.7 1.5 6.2 ns 4.0 — 2.0 — 2.0 — ns 2.0 — 1.5 — 1.5 — ns 6.0 — 5.0 — 5.0 — ns Notes: 1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not production tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 6 PS2064A 01/15/97