Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features Introduction • Supports AT&T TR62411 Stratum 4 and PT7A4408/4408L employs a digital phase-locked Stratum 4 Enhanced for DS1 interfaces and for loop (DPLL) to provide timing and synchronizing ETSI ETS 300 011, TBR 4, TBR 12, and TBR signals for multitrunk T1 and E1 primary rate 13 for E1 interfaces transmission links, and for STS-3/OC3 links. The ST- • Supports ITU-T G.812 Type IV clocks for • BUS clock and framing signals are phase-locked to 1.544kbit/s interfaces and 2.048kbit/s interface input reference signals of either 2.048 MHz, Provides C1.5, C3, C2, C4, C8, C6, C16 and C19 1.544MHz or 8 kHz. output clock signals Provides five kinds of 8kHz ST-BUS framing The PT7A4408/4408L meets the requirements for signals AT&T TR62411 Stratum 4 and Stratum 4 Enhanced, Input reference frequency 1.544MHz, 2.048MHz and ETSI ETS 300 011 in jitter tolerance, jitter trans- or 8kHz selectable fer, intrinsic jitter, frequency accuracy, capture range, • Normal or Free-Run operating modes available phase slope, etc. • Power supply: 5V (4408) and 3.3V(4408L) • • The PT7A4408/4408L operates in Normal or Free- Applications run Mode. • Synchronization and timing control for multitrunk Ordering Information T1 and E1 systems, STS-3/OC3 systems • ST-BUS clock and frame pulse sources • Primary Trunk Rate Converters PT0106(09/02) 1 Pa r t Nu m b er Pa ck a ge PT7A4408J 44-Pin PLCC PT7A4408LJ 44-Pin PLCC Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Contents Features ....................................................................................................................................................... 1 Applications ................................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Ordering Information .................................................................................................................................. 1 Block Diagram ............................................................................................................................................ 3 Pin Information ........................................................................................................................................... 4 Pin Assignment ..................................................................................................................................... 4 Pin Configuration ................................................................................................................................. 4 Pin Description ..................................................................................................................................... 5 Functional Description ................................................................................................................................ 7 Overall Operation ................................................................................................................................. 7 Modes of Operation .............................................................................................................................. 9 Applications Information ...................................................................................................................... 9 Detailed Specifications .............................................................................................................................. 10 Definitions of Critical Performance Specifictions ............................................................................... 10 Absolute Maximum Ratings ............................................................................................................... 11 Recommended Operating Conditions ................................................................................................. 11 DC Electrical and Power Supply Characteristics ................................................................................ 12 AC Electrical Characteristics .............................................................................................................. 13 Mechanical Specifications ......................................................................................................................... 26 Note .......................................................................................................................................................... 27 PT0106(09/02) 2 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Block Diagram Figure 1. Block Diagram VCC RST OSCi OSCo TCK TDI TMS TRST TDO REF APLL Loop Filter Master Clock DPLL Output Interface Circuit IEEE 1149.1a Phase Detector ACKi ACKo C1.5 C2 C3 C4 C6 C8 C16 C19 F0 F8 F16 RSP TSP Feedback Frequency Select MUX Mode Control MS PT0106(09/02) GND FS1 3 FS2 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Information Pin Assignment Table 1. Pin Assignment G r ou p Symb ol F u n ct ion Chip Clock OSCi, OSCo, ACKi, ACKo Clock Power & Ground VCC, AVDD, GND, AGND Power Clock and Framing Outputs C1.5, C3, C2, C4, C6, C8, C16, C19, F0, F8, F16, RSP, TSP Clock and Framing Signals Control Signals MS, FS1, FS2, RST Control Reference Inputs REF Reference Clock IEEE 1149.1a TCK, TDI, TMS, TRST, TDO IEEE 1149.1a Interface Pin Configuration 40 41 42 43 1 44 2 3 4 6 7 39 8 38 9 37 10 36 11 35 44-Pin PLCC 12 34 13 33 14 32 15 31 28 27 26 25 24 23 22 21 TEST NC NC MS TDO NC NC NC GND GND NC C3 C2 C4 C19 ACKi GND ACKo C8 C16 C6 VCC 20 30 29 19 16 17 18 VCC OSCo OSCi AGND F16 RSP F0 TSP F8 C1.5 AVDD 5 REF NC TRST NC TCK GND TMS RST TDI FS1 FS2 Figure 2. Pin Configuration Top View PT0106(09/02) 4 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Description Table 2. Pin Description P in Na m e 1, 23, 30, 31 GND 2 TCK I Test C lock (T T L I n p u t ): Provides the clock to the JTAG test logic. This pin is internally pulled up to VCC. 3, 5, 29, 3234, 37, 38 NC - No con n ect ion 4 TRST I Test R eset (T T L I n p u t ): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally pulled down to GND. 6 REF I R efer en ce (T T L ): The reference signal, internally pulled down to GND. 7, 28 VCC Power 8 OSCo O O scilla t or m a st er clock ou t p u t (C MO S): Output of 20MHz master clock 9 OSCi I O scilla t or m a st er clock in p u t (C MO S): Input of 20MHz master clock (can be connected directly to a clock source) 10 AGND 11 F16 O F r a m e p u lse ST-BUS 16.384Mb /s (C MO S): 8kHz frame signal with 61ns low level pulse that marks the beginning of a ST-BUS frame, typically used for ST-BUS opetation at 8.192Mb/s. See figure 10. 12 RSP O R eceive Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the end of an ST-BUS frame. See Figure 11. 13 F0 O F r a m e p u lse ST-BUS 2.048 Mb /s (C MO S): 8kHz frame signal with 244ns low level pulse that marks the beginning of a ST-BUS frame e, typically used for ST-BUS opetation at 2.048Mb/s. See figure 10. 14 TSP O Tr a n sm it Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the beginning of an ST-BUS frame. See Figure 11. 15 F8 O F r a m e p u lse ST-BUS 8.192 Mb /s (C MO S): 8kHz frame signal with 122ns high level pulse that marks the beginning of a ST-BUS frame 16 C1.5 O 1.544 MH z clock (C MO S): This output is used in T1 applications. 17 AVDD Power 18 C3 O 3.088 MH z clock (C MO S): This output is used in T1 applications. 19 C2 O 2.048 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s. 20 C4 O 4.096 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. 21 C19 O C lock 19.44MH z (C MO S O u t p u t ). This output is used in OC3/STS-3 applications. 22 ACKi I An a log P L L C lock I n p u t (C MO S I n p u t ). This input clock is a reference for an internal analog PLL. This pin is internally pulled down to GND. 24 ACKo O An a log P L L C lock O u t p u t (C MO S O u t p u t ). This output clock is generated by the internal analog PLL. PT0106(09/02) Typ e Descr ip t ion Ground Digit a l G r ou n d Power su p p ly 5V for PT7A4408J. 3.3V for PT7A4408LJ Ground An a log G r ou n d An a log Power Su p p ly: 5V for PT7A4408J and 3.3V for PT7A4408LJ 5 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Table 2. Pin Description (continued) P in Na me Typ e Descr ip t ion 25 C8 O 8.192 MH z clock (C MO S): This output is used for ST-BUS operation at 8.192Mb/s. 26 C16 O 1 6 . 3 8 4 M H z c l o c k ( C M O S ) : T h i s o u t p u t i s u s e d f o r S T- BUS o p e r a t i o n wi t h a 16.384MHz clock. 27 C6 O C lock 6.312 MH z (C MO S O u t p u t ). This output is used for DS2 applications. 35 TDO O Test Ser ia l Da t a O u t (T T L O u t p u t ). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. 36 MS I Mod e/C on t r ol Select (T T L ): determines the operating states, Normal or Free-Run. 39 TEST I Test (T T L I n p u t ). This input is normally tied low. When pulled high, it enables internal test modes. This pin is internally pulled down to GND. 40 FS2 I F r eq u en cy Select 2 (T T L ):Together with FS1, selects one of the three DPLL feedback frequencies to match the desired Input Reference Frequency (8 kHz, 1.544 MHz or 2.048 MHz). 41 FS1 I F r eq u en cy Select 1 (T T L ): Refer to the pin description of FS2. 42 TDI I Test Ser ia l Da t a I n (T T L I n p u t ). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VCC.. 43 RST I R eset (Sch mit t ): Resets the device when at low logic level. Reset is needed whenever the operating mode is changed, or the reference signal frequency is switched or when powerup; so as to ensure proper operation of the device. Following Reset, the output clocks and frame signals are phase-aligned with the input reference source. 44 TMS I Test Mod e Select (T T L I n p u t ). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VCC.. PT0106(09/02) 6 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Table 3. Feedback Frequency Selection Functional Description F S2 F S1 I n p u t F r eq u en cy 0 0 Reserved 0 1 8kHz 1 0 1.544MHz 1 1 2.048MHz Overall Operation The PT7A4408/4408L is a multitrunk synchronizer that provides the clock and frame signals for T1 and E1 primary rate digital transmission links, and STS-3/OC3 links. It basically consists of the Clock Generator, Mode Control, Digital Phase- Locked Loop (DPLL), Analog Phase- Locked Loop (APLL) and Output Interface Circuit. Digital Phase-Locked Loop (DPLL) The DPLL circuit provides synchronization of the output signals with any given input reference signal. The DPLL consists of the Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator (DCO) and Control Circuit. See Figure 3 for the block diagram of DPLL. Master Clock The Reference is sent to Phase Detector for comparison with the Feedback Signal from the Feedback Frequency Select MUX. An error signal corresponding to their instantaneous phase difference is produced and sent to the Limiter. The PT7A4408/4408L uses either an external clock source or an external crystal and a few discrete components with its internal oscillator as the master clock. The Limiter amplifies this error signal to ensure the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125µs. This performance easily meets the maximum phase slope of 7.6ns per 125µs or 81ns per 1.326ms specified by AT&T TR62411. Feedback Frequency Select MUX The feedback frequency is selected by FS1 and FS2 (as shown in Table 3) to match the particular incoming reference frequency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must be performed after every frequency select input change. The Loop Filter is a 1.9Hz low pass filter for all three reference frequency selections: 8kHz, 1.544MHz and 2.048MHz. The filter ensures that the jitter transfer requirements in ETS 300011 and AT&T TR62411 are met. Figure 3. Block Diagram of DPLL Reference Phase Detector Loop Filter Limiter DCO DPLL Reference to Output Interface Circuit Control Circuit Feedback Signal From Frequency Select MUX PT0106(09/02) 7 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| The T1 Divider uses the 12.352MHz signal to generate two clock signals, C1.5 and C3. They have a nominal 50% duty cycle. The Control Circuit decides Normal or Freerun state. The Error Signal, after limited and filtered, is sent to Digitally Controlled Oscillator. Based on the processed error value, the DCO will generate the corresponding digital output signals for the Tapped Delay Line in the Output Interface Circuit to produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz signals. The DCO synchronization method depends upon the PT7A4408/4408L operating state, as follows: The DS2 Divider uses 12.624MHz signal to generate clock signal C6. Clock signal C19 is generated from 19.44MHz by tapped Delay Line. In Normal state, the DCO generates four output signals which are frequency and phase locked to the selected input reference signal. The E1 Divider uses the 16.384MHz signal to generate four clock signals and three frame signals, i.e., C2, C4, C8, C16, F0, F8 and F16. The frame signals are generated directly from the C16 signal. In Free-Run state, the DCO is free running with an accuracy equal to that of the OSCi 20MHz source. The C2, C4, C8 and C16 signals have nominal 50% duty cycle. Output Interface Circuit All the frame and clock outputs are locked to each other for all operating states. They have limited driving capability and should be buffered when driving high capacitance (e.g., 30pF) loads. The Output Interface Circuit consists of the Tapped Delay Line and E1/T1 Dividers as shown in Figure 4. Signals from the DCO are sent to Tapped Delay Line to generate four clock signals, 16.384MHz, 12.624MHz, 19.44MHz and 12.352MHz, which are divided in the T1 and E1 Dividers respectively to provide needed clock and frame signals. Figure 4. Block Diagram of Output Interface Circuit 12.352MHz Signal From DCO T1 Divider 16.384MHz E1 Divider 12.624MHz DS2 Divider Tapped Delay Line OSCi C1.5 C3 C2 C4 C8 C16 F0 F8 F16 RSP TSP C6 19.44MHz C19 ACKi PT0106(09/02) APLL 8 ACKo Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mode Controller Applications Information The Mode Controller determines whether the PT7A4408/ 4408L operates in Normal or Free-Run state. Master Clock The PT7A4408/4408L uses either an external clock source or an external crystal as the master timing source. All state changes are synchronous with the rising edge of F8. See the Modes of Operation section for complete details. In Free-Run State, the frequency tolerance of the PT7A4408/ 4408L output clocks are equal to the frequency tolerance of the timing source. In an application, if an accurate Free-Run State is not required, the tolerance of the master timing source may be 100ppm. If required, the tolerance must be no greater than 32ppm. APLL The analog PLL is intended to be used to achieve a 50% Duty cycle output clock. Connecting C19 to ACKi will generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle and a maximum peak-to-peak unfiltered jitter of 0.174 U.I. . The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low jitter level separate pins are provided to power (AVDD, AGND) the APLL. The capture range of PT7A4408/4408L will also be considered when deciding the accuracy of the master timing source. The sum of the accuracy of the master timing source and the capture range of the PT7A4408/4408L will always equal 230ppm. For example, if the master timing source is 100ppm, the capture range will be 130ppm. Modes of Operation The PT7A4408/4408L operates in Normal or Free-Run controlled by pin MS. MS = 0: Normal MS = 1: Freerun • Clock Oscillator If using an external clock source, its output pin should be connected directly (not AC coupled) to the OSCi pin of the PT7A4408/4408L and the OSCo pin of PT7A4408/4408L can be left open as shown in Figure 5 or connected as an output pin. Normal State In Normal State, the PT7A4408/4408L output signals are synchronized with input reference. Figure 5. Clock Oscillator Connection In this state, the input reference signal is used as reference for the DPLL phase detector. PT7A4408/4408L +5V OSCi Free-Run State +5V 20MHz OUT GND Typically the Free-Run State is used when a master clock is required or immediately following system power-up before network synchronization is achieved. In Free-Run State, the outputs of the PT7A4408/4408L are uncorrelated with the input reference signal and the stored information of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). PT0106(09/02) 0.1µF OSCo No Connection When selecting the clock oscillator, following specifications should be considered. They are - absolute frequency - frequency change over temperature - output rise and fall time - output level - duty cycle Refer to AC Electrical Characteristics. 9 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| • Crystal Oscillator Detailed Specifications If a crystal oscillator is selected as the master timing source, it should be connected to the PT7A4408/4408L as shown in Figure 6. Definitions of Critical Performance Specifictions Intrinsic Jitter: Intrinsic jitter is the jitter produced by the synchronizing circuit. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode - such as free running or holdover - by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. Figure 6. Crystal Oscillator Connection PT7A4408/4408L 20MHz OSCi 56pF 1MΩ OSCo 39pF 3-50pF 100Ω The crystal specification is as follows: - Frequency: - Tolerance: - Oscillation Mode: - Resonance Mode: - Load Capacitance: - Maximum Series Resistance: - Αpproximate Drive Level: 20MHz as required Fundamental Parallel 32pF 35Ω 1mW Reset Circuit A simple power up reset circuit with about a 50µs reset active (low) time is shown in Figure 7. Resistor RP is for protection only. The reset low time is not critical but should be greater than 300ns. Figure 7. Power-up Reset Circuit +5V Its 3 possible input frequencies and 9 outputs give the PT7A4408/4408L 27 possible jitter transfer combinations. However, only three cases of the jitter transfer specifications are given in the AC Electrical Characteristics; as the remaining combinations can be derived from them. For the PT7A4408/4408L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125µs. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125µs. Example : When the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB, The T1 and E1 output jitter can be calculated as follows: R 10kΩ RST PT0106(09/02) Jitter Transfer: Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device with respect to a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. It should be noted that 1UI at 1.544MHz (644ns) is not equal to 1UI at 2.048MHz (488ns). A transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. PT7A4408/4408L RP 1kΩ Jitter Tolerance: Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is present on its reference. The applicable standard specifies how much jitter to apply to the reference when testing for jitter tolerance. C 10nF 10 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| JT1o = JT1i x 10 ( -A 20 ) = 20 x 10 ( -18 ) 20 = 2.5UI JE1o = JT1o x ( 1UIT1) = JT1o x ( 644ns ) = 3.3UI 488ns 1UIE1 Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 6.312MHz, 19.44MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy: Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the PT7A4408/4408L, the Free-Run accuracy is equal to the Master Clock (OSCi) accuracy. Lock Range: If the PT7A4408/4408L DPLL is already in a state of synchronization (“lock”) with the incoming reference signal, it is able to track this signal to maintain lock as its frequency varies over a certain range, called the Lock Range. The size of Lock Range is related to the range of the Digitally Controlled Oscillators and is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a Lock Range of 198ppm. Capture Range: The PT7A4408/4408L DPLL is not at present in a state of synchronization (lock) with the incoming reference signal, it is able to initiate (acquire) lock only if the signal’s frequency is within a certain range, called the Capture Range. For any PLL, no portion of the Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4408/4408L’s Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal of constant frequency. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Absolute Maximum Ratings Storage Temperature ...................................................... -65oC to +150oC Ambient Temperature with Power Applied ...................... -40oC to +85oC Supply Voltage to Ground Potential (Inputs & VCC Only) ...... -0.3 to 7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V DC Input Voltage .................................................................. -0.3 to 7.0V DC Output Current ...................................................................... 120mA Power Dissipation ....................................................................... 900mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Table 4. Recommended Operating Conditions Sym Descr ip t ion Test C on d it ion s Supply Voltage for 4408 VCC Supply Voltage for 4408L TA PT0106(09/02) Over Recommended Operating Conditions Operating Temperature 11 Min Typ Ma x Un it s 4.5 5.0 5.5 V 3.0 3.3 3.6 V -40 25 85 o C Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical and Power Supply Characteristics Table 5. DC Electrical and Power Supply Characteristics Sym Descr ip t ion ICCQ Quiescent Power Supply Current Device Test C on d it ion s Min 4408 Typ Ma x Un it s 20 mA 10 mA 60 mA 35 mA 70 mA 40 mA OSCi = 0V, Note 2 4408L 4408 OSCi = Clock, Note 2 4408L ICC Supply Current 4408 OSCi = Crystal, Note 2 4408L VIH TTL HIGH Input Voltage-All pins except OSCi, RST VIL TTL LOW Input Voltage-All pins except OSCi, RST VCIH CMOS HIGH Input VoltageOSCi pin VCIL CMOS LOW Input VoltageOSCi pin VSIH Schmitt HIGH Input VoltageRST pins VSIL Schmitt LOW Input VoltageRST pins VHYS Schmitt Hysteresis VoltageRST pins Input Leakage Current - Pins: TCK, REF, TDI, TMS IIL Input Leakage Current - Pins: TRST, ACKi, MS, TEST 2.0 0.8 0.7VCC VOL LOW Output Voltage V 4408 3.6 V 4408L 2.6 V 4408 1.8 V 4408L 1.1 V 0.4 V 4408 -140 µA 4408L -100 µA 4408 VI = VCC or 0V 4408L -10 4408 HIGH Output Voltage V V 0.3VCC Input Leakage Current - other pins VOH V IOH = -4mA 4408L 140 µA 100 µA 10 µA 2.4 V 2.0 V IOL = 4mA 0.8 V Note: 1. Supply voltages and operating temperature are as per Recommended Operating Conditions. 2. MS = VCC, FS1 = VCC , FS2= GND, other inputs connected to GND. 3. All outputs are unloaded except for VOH and VOL measurement. PT0106(09/02) 12 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics Performance Table 6. Performance Sym Descr ip t ion Test C on d it ion s* Ma x Un it s 0 0 ppm -32 +32 ppm 100ppm -100 +100 ppm 0ppm -190 +230 ppm -158 +198 ppm -90 +130 ppm 10 30 MHz 0ppm Free-Run State Accuracy with OSCi at: 32ppm DPLL Capture Range With OSCi at: 32ppm 5-8 3, 6-8 100ppm Min Typ APLL Capture Range 43 Phase Lock Time 3, 6-14 23 s Output Phase Slope 3-14, 27 45 µs/s 8kHz 3, 6, 9-11 <-30k or >+30k ppm Reference Input for Auto-Holdover with:1.544MHz 3, 7, 9-11 <-30k or >+30k ppm 3, 8-11 <-30k or >+30k ppm 2.048MHz * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 13 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Voltage Levels for Timing Parameter Measurement Table 7. Voltage Levels for Timing Parameter Measurement Sym Descr ip t ion Sch mit t TTL CMOS Un it s VT Threshold Voltage 0.5VCC 1.5 0.5VCC V VHM Rising and Falling Threshold Voltage High 0.7VCC 2.0 0.7VCC V VLM Rising and Falling Threshold Voltage Low 0.3VCC 0.8 0.3VCC V Figure 8. Voltage Levels for Timing Parameter Measurement Timing Reference Points Signal VHM VT VLM tIF.tOF PT0106(09/02) tIR.tOR 14 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Input and Output Timing Table 8. Input and Output Timing of 4408 Sym tRW Descr ip t ion Test C on d it ion s* Reference Input pulse Width High or Low Min Typ Ma x 100 Un it s ns 3, 6-11, 39 tIRF Reference Input Rising or Falling Time tR8D 8kHz Reference Input to F8 Delay tR15D 1.544kHz Reference Input to F8 Delay tR2D 2.048kHz Reference Input to F8 Delay tF0D F8 to F0 Delay tF16D F8 to F16 Delay tC15D 10 ns -28 -1 ns 337 363 ns 217 238 ns 3-14, 21, 39 110 134 ns 3-14, 21 19 44 ns F8 to C1.5 Delay -45 -31 ns tC6D F8 to C6 Delay -8 9 ns tC3D F8 to C3 Delay -46 -31 ns tC2D F8 to C2 Delay -10 5 ns tC4D F8 to C4 Delay -10 5 ns tC8D F8 to C8 Delay -10 5 ns tC16D F8 to C16 Delay -10 5 ns tTSPD F8 to TSP Delay -10 10 ns 3, 6-14, 21, 23, 38 3-14, 21, 39 tRSPD F8 to RSP Delay -10 10 ns tC19D F8 to C19 Delay 0 52 ns tC15W C1.5 Pulse Width High or Low 309 339 ns tC3W C3 Pulse Width High or Low 149 175 ns tC6W C6 Pulse Width High or Low 72 86 ns tC2W C2 Pulse Width High or Low 230 258 ns tC4W C4 Pulse Width High or Low 111 133 ns tC8W C8 Pulse Width High or Low 52 70 ns * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 15 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Table 9. Input and Output Timing of 4408L Sym tRW Descr ip t ion Test C on d it ion s* Reference Input pulse Width High or Low Min Typ Ma x 100 Un it s ns 3, 6-11, 39 tIRF Reference Input Rising or Falling Time tR8D 8kHz Reference Input to F8 Delay tR15D 1.544kHz Reference Input to F8 Delay tR2D 2.048kHz Reference Input to F8 Delay tF0D F8 to F0 Delay tF16D F8 to F16 Delay tC15D 10 ns -21 6 ns 345 371 ns 232 248 ns 3-14, 21, 39 112 138 ns 3-14, 21 19 44 ns F8 to C1.5 Delay -47 -31 ns tC6D1) F8 to C6 Delay -9 9 ns tC3D F8 to C3 Delay -49 -32 ns tC2D F8 to C2 Delay -11 4 ns tC4D F8 to C4 Delay -11 4 ns tC8D F8 to C8 Delay -11 4 ns tC16D F8 to C16 Delay -11 4 ns tTSPD1) F8 to TSP Delay -10 10 ns 3, 6-14, 21, 23, 38 3-14, 21, 39 tRSPD1) F8 to RSP Delay -10 10 ns tC19D1) F8 to C19 Delay 0 52 ns tC15W C1.5 Pulse Width High or Low 309 339 ns tC3W C3 Pulse Width High or Low 149 175 ns tC6W1) C6 Pulse Width High or Low 72 86 ns tC2W C2 Pulse Width High or Low 230 258 ns tC4W C4 Pulse Width High or Low 111 133 ns tC8W C8 Pulse Width High or Low 52 70 ns * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 16 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Table 10. Input and Output Timing (Continued) Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s 26 37 ns 478 494 ns tC16WL C16 Pulse Width Low tTSPW TSP Pulse Width High tRSPW RSP Pulse Width High 478 495 ns tC19W C19 Pulse Width High or Low 16 36 ns tF0WL F0 Pulse Width Low 230 258 ns tF8WH F8 Pulse Width High 111 133 ns tF16WL F16 Pulse Width Low 52 70 ns 9 ns 3-14, 21 Output Clock and Frame Pulse Rising or Falling Time tORF 3-14, 21, 39 tS Input Controls Setup Time 100 ns tH Input Controls Hold Time 100 ns * Refer to the Test Conditions on Page 25 for details. Figure 9. Input to Output Timing (Normal State, after RST) t R8D REF 8kH z VT tR W t R15D REF 1.544M H z tR W VT t R2D tR W REF 2.048M H z VT VT F8 Note: Input to output delay values are valid after a RST with no further state changes. PT0106(09/02) 17 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Figure 10. Output Timing tF8WH VT F8 tF0D tF0WL F0 VT tF16D tF16WL F16 tC16WL VT tC16D C16 VT tC8W tC8W tC8D C8 VT tC4D tC4W C4 VT tC4W tC2D tC2W C2 VT tC3D tC3W tC3W C3 VT tC15D tC15W C1.5 VT tC6W tC6D tC6W VT C6 tC19D tC19W C19 VT tC19W Figure 11. Output Timing F8 VT C2 VT tRSPD RSP tTSPW tRSPW TSP PT0106(09/02) tTSPD 18 VT VT Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Figure 12. Setup and Hold Timing of Input Controls VT F8 tS tH MS VT Intrinsic Jitter Unfiltered Table 11. Intrinsic Jitter Unfiltered Sym Descr ip t ion Test C on d it ion s* Instrinsic Jitter at F8 (8kHz) Instrinsic Jitter at F0 (8kHz) 3-14, 21-24, 28 Instrinsic Jitter at F16 (8kHz) Min Typ Ma x Un it s 0.0002 UIpp 0.0002 UIpp 0.0002 UIpp Instrinsic Jitter at C1.5 (1.544MHz) 3-14, 21-24, 29 0.030 UIpp Instrinsic Jitter at C2 (2.048MHz) 3-14, 21-24, 30 0.040 UIpp Instrinsic Jitter at C3 (3.088MHz) 3-14, 21-24, 31 0.060 UIpp Instrinsic Jitter at C4 (4.096MHz) 3-14, 21-24, 32 0.080 UIpp Instrinsic Jitter at C6 (6.312MHz) 3-14, 21-24, 41 0.120 UIpp Instrinsic Jitter at C8 (8.192MHz) 3-14, 21-24, 33 0.160 UIpp Instrinsic Jitter at C16 (16.384MHz) 3-14, 21-24, 34 0.320 UIpp Instrinsic Jitter at C19 (19.44MHz) 3-14, 21-24, 42 0.230 UIpp Instrinsic Jitter at TSP (8kHz) 3-14, 21-24, 28 0.0002 UIpp Instrinsic Jitter at RSP (8kHz) 3-14, 21-24, 28 0.0002 UIpp * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 19 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| C1.5 (1.544MHz) Instrinsic Jitter Filtered Table 12. C1.5 (1.544MHz) Instrinsic Jitter Filtered Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s 0.015 UIpp 0.010 UIpp Instrinsic Jitter (8kHz to 40kHz Filter) 0.010 UIpp Instrinsic Jitter (10Hz to 8kHz Filter) 0.005 UIpp Ma x Un it s 0.015 UIpp 0.010 UIpp Instrinsic Jitter (8kHz to 40kHz Filter) 0.010 UIpp Instrinsic Jitter (10Hz to 8kHz Filter) 0.005 UIpp Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter) 3-14, 21-24, 29 * Refer to the Test Conditions on Page 25 for details. C2 (2.048MHz) Instrinsic Jitter Filtered Table 13. C2 (2.048MHz) Instrinsic Jitter Filtered Sym Descr ip t ion Test C on d it ion s* Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter) Min Typ 3-14, 21-24, 30 * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 20 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 8kHz Input to 8kHz Output Jitter Transfer Table 14. 8kHz Input to 8kHz Output Jitter Transfer Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s Jitter Attenuation for 1Hz with 0.01UIpp Input 0 6 dB Jitter Attenuation for 1Hz with 0.54UIpp Input 6 16 dB 12 22 dB 28 38 dB Jitter Attenuation for 10Hz with 0.10UIpp Input Jitter Attenuation for 60Hz with 0.10UIpp Input 3, 6, 9-14, 21, 22, 24, 28, 35 Jitter Attenuation for 300Hz with 0.10UIpp Input 42 dB Jitter Attenuation for 3600Hz with 0.005UIpp Input 45 dB * Refer to the Test Conditions on Page 25 for details. 1.544MHz Input to 1.544MHz Output Jitter Transfer Table 15. 1.544MHz Input to 1.544MHz Output Jitter Transfer Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s Jitter Attenuation for 1Hz with 20UIpp Input 0 6 dB Jitter Attenuation for 1Hz with 104UIpp Input 6 16 dB Jitter Attenuation for 10Hz with 20UIpp Input 12 22 dB 28 38 dB Jitter Attenuation for 60Hz with 20UIpp Input 3, 7, 9-14, 21, 22, 24, 29, 35 Jitter Attenuation for 300Hz with 20UIpp Input 42 dB Jitter Attenuation for 10kHz with 0.3UIpp Input 45 dB Jitter Attenuation for 100kHz with 0.3UIpp Input 45 dB * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 21 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2.048MHz Input to 2.048MHz Output Jitter Transfer Table 16. 2.048MHz Input to 2.048MHz Output Jitter Transfer Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s 3,8,9-14,21,22,24,30,35 2.9 UIpp 3,8,9-14,21,22,24,30,36 0.09 UIpp 3,8,9-14,21,22,24,30,35 1.3 UIpp 3,8,9-14,21,22,24,30,36 0.10 UIpp 3,8,9-14,21,22,24,30,35 0.80 UIpp 3,8,9-14,21,22,24,30,36 0.10 UIpp 3,8,9-14,21,22,24,30,35 0.40 UIpp 3,8,9-14,21,22,24,30,36 0.10 UIpp 3,8,9-14,21,22,24,30,35 0.06 UIpp 3,8,9-14,21,22,24,30,36 0.05 UIpp 3,8,9-14,21,22,24,30,35 0.04 UIpp 3,8,9-14,21,22,24,30,36 0.03 UIpp 3,8,9-14,21,22,24,30,35 0.04 UIpp 3,8,9-14,21,22,24,30,36 0.02 UIpp Jitter at Output for 1Hz 3.00UIpp Input Jitter at Output for 3Hz 2.33UIpp Input Jitter at Output for 5Hz 2.07UIpp Input Jitter at Output for 10Hz 1.76UIpp Input Jitter at Output for 100Hz 1.50UIpp Input Jitter at Output for 2400Hz 1.50UIpp Input Jitter at Output for 100kHz 0.20UIpp Input * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 22 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 8kHz Input Jitter Tolerance Table 17. 8kHz Input Jitter Tolerance Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s Jitter Tolerance for 1Hz Input 0.80 UIpp Jitter Tolerance for 5Hz Input 0.70 UIpp Jitter Tolerance for 20Hz Input 0.60 UIpp 0.20 UIpp Jitter Tolerance for 400Hz Input 0.15 UIpp Jitter Tolerance for 700Hz Input 0.08 UIpp Jitter Tolerance for 2400Hz Input 0.02 UIpp Jitter Tolerance for 3600Hz Input 0.01 UIpp Jitter Tolerance for 300Hz Input 3,6,9-14,21,22,24-26,28 * Refer to the Test Conditions on Page 25 for details. 1.544MHz Input Jitter Tolerance Table 18. 1.544MHz Input Jitter Tolerance Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s Jitter Tolerance for 1Hz Input 150 UIpp Jitter Tolerance for 5Hz Input 140 UIpp Jitter Tolerance for 20Hz Input 130 UIpp Jitter Tolerance for 300Hz Input 35 UIpp 25 UIpp Jitter Tolerance for 700Hz Input 15 UIpp Jitter Tolerance for 2400Hz Input 4 UIpp Jitter Tolerance for 10kHz Input 1 UIpp Jitter Tolerance for 100kHz Input 0.5 UIpp Jitter Tolerance for 400Hz Input 3,7,9-14,21,22,24-26,29 * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 23 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2.048MHz Input Jitter Tolerance Table 19. 2.048MHz Input Jitter Tolerance Sym Descr ip t ion Test C on d it ion s* Min Typ Ma x Un it s Jitter Tolerance for 1Hz Input 150 UIpp Jitter Tolerance for 5Hz Input 140 UIpp Jitter Tolerance for 20Hz Input 130 UIpp Jitter Tolerance for 300Hz Input 50 UIpp 40 UIpp Jitter Tolerance for 700Hz Input 20 UIpp Jitter Tolerance for 2400Hz Input 5 UIpp Jitter Tolerance for 10kHz Input 1 UIpp Jitter Tolerance for 100kHz Input 1 UIpp Jitter Tolerance for 400Hz Input 3,8,9-14,21,22,24-26,30 * Refer to the Test Conditions on Page 25 for details. OSCi 20MHz Master Clock Input Table 20. OSCi 20MHz Master Clock Input Sym Descr ip t ion Test C on d it ion s* Min 15, 18 Ma x Un it s 0 0 ppm 16, 19 -32 +32 ppm 17, 20 -100 +100 ppm 40 60 % Rising Time 10 ns Falling Time 10 ns Tolerance Duty Cycle Typ * Refer to the Test Conditions on Page 25 for details. PT0106(09/02) 24 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Supply voltage and operation temperature are as per Recommended Operating Conditions. 3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement. Test Conditions: 1. 2. 3. Normal State selected. 4. 5. Free-Run State selected. 6. 8kHz frequency source selected. 7. 1.544MHz frequency source selected. 8. 2.048MHz frequency source selected. 9. Master clock input OSCi at 20MHz ±0ppm. 10. Master clock input OSCi at 20MHz ±32ppm. 11. Master clock input OSCi at 20MHz ±100ppm. 12. Selected reference input at ±0ppm. 13. Selected reference input at ±32ppm. 14. Selected reference input at ±100ppm. 15. For Free-Run State of ±0ppm. 16. For Free-Run State of ±32ppm. 17. For Free-Run State of ±100ppm. 18. For capture range of ±230ppm. 19. For capture range of ±198ppm. 20. For capture range of ±130ppm. 21. 25pF capacitive load. PT0106(09/02) 22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. 25. Minimum applied input jitter magnitude to regain synchronization. 26. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 27. Within 10ms of the state, reference or input change. 28. 1UIpp = 125µs for 8kHz signals. 29. 1UIpp = 648ns for 1.544MHz signals. 30. 1UIpp = 488ns for 2.048MHz signals. 31. 1UIpp = 324ns for 3.088MHz signals. 32. 1UIpp = 244ns for 4.096MHz signals. 33. 1UIpp = 122ns for 8.192MHz signals. 34. 1UIpp = 61ns for 16.384MHz signals. 35. No filter. 36. 40Hz to 100kHz bandpass filter. 37. With respect to reference input signal frequency. 38. After a RST 39. Master clock duty cycle 40% to 60%. 40. In Normal State and phase locked. 41. 1UIpp = 162ns for 6.312MHz signals. 42. 1UIpp = 51ns for 19.44MHz signals. 25 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Specifications Figure 13. 44-pin PLCC PT0106(09/02) 26 Ver:0 Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Note Pericom Technology Inc. Email: [email protected] Web-Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0106(09/02) 27 Ver:0