PT Pericom Technology Inc. PT7A6525/PT7A6526 HDLC Controller |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| General Description (PT7A6526: B channel, PT7A6525:A, B channels) - On-chip clock generation or external clock source - On-chip DPLL for clock recovery for each channel - Two independent baudrate generators (PT7A6526: one generator) - Independent time-slot assignment for each channel with programmable time-slot length (1~256bit) • Provides up to 64 bytes for both transmit FIFO and Receive FIFO • Different modes of data encoding • Modem control lines (RTS,CTS,CD) • Support of bus configuration by collision resolution • Programmable bit inversion • Data rate up to 4Mb/s • Transparent mode selectable Protocol Support • Supports LAPB/LAPD/SDLC/HDLC protocols in auto mode • Handles bit-oriented functions in all modes • Modulo 8 or modulo 128 operations • Programmable maximum packet size checking • Programmable time-out and retry conditions Microprocessor Interface • Efficient transfer of data blocks by DMA or interrupt request • 8-bit demultiplexed or multiplexed bus interface • Suitable for Intel or Motorola microprocessor interfaces PT7A6525/6526 are designed to implement highspeed communication links using HDLC protocols and to reduce the hardware and software overhead needed for serial synchronous communications. The PT7A6525 supports two completely independent full-duplex HDLC channels (channel A and channel B), while the PT7A6526 supports only one (channel B). For each channel, there are Internal Oscillator, Baud-Rate Generator (BRG), Digital Phase Lock Loop (DPLL), Time-Slot Assignment (TSA) circuits and Data Link Controller to support various layer-1 functions. They also directly support the X.25 LAPB, the ISDN LAPD and SDLC (normal response mode) protocols and are capable of handling a large set of layer-2 protocol functions independently. The data link controller handles all functions necessary to establish and maintain a HDLC data link, such as flag insertion and detection, bit stuffing, CRC generation and checking, and address field recognition. Associated with each serial channel is a set of independent command and status registers and 64byte FIFO’s for transmit and receive direction. Besides the interrupt request, the chip can transfer data blocks from/to system memory by DMA. A 4-channel DMA interface with one DMA request line for each transmitter and receiver of both channels can successfully complete the DMA function. Applications • Data link controllers and protocol generators • Digital sets, PBXs and private packet networks • C-channel controller of data network interface circuits • D-channel controller for ISDN basic access • Interprocessor communications The chip’s programmable telecom-specific features allow it to be widely used in time-slot oriented PCM systems, systems designed for packet switching and ISDN applications. Features Serial Interface • Two independent full-duplex HDLC channels 1 Pa r t Nu mb er Pa ck a ge PT7A6525J/PT7A6526J 44-Pin PLCC PT7A6525F/PT7A6526F 44-Pin TQFP PT Pericom Technology Inc. PT7A6525/PT7A6526 HDLC Controller |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Block Diagram A0-A6 Channel A D0-D7 RD/IC1 Transmit FIFO Microprocessor Interface WR/IC0 CS Link Controller Receive FIFO ALE/IM0 INT RxDA TxDA RTSA CTSA/CxDA RxCLKA Collision Detection Clock Controller AxCLKA TxCLKA RES IM1 Channel B DRQTA DRQRA DACKA Transmit FIFO DMA Controller Collision Detection Link Controller RxCLKB Receive FIFO DRQTB DRQRB DACKB RxDB TxDB RTSB CTSB/CxDB Clock Controller AxCLKB TxCLKB Typical Applications Central Office Solution W AN OC-3, STM -1, DS3, E3/T3, E1/T1 Interface DSM Fabric PT7A5020 PT7A9080 & PT7A9085 M aster Processor HDLC PT7A6632 Line Card HDLC PT7A6525/ PT7A6526 Line Card Line Card Line Card System Clock Recovery PT7A4401/ PT7A4402 HDLC PT7A6525/ PT7A6526 Line Card M PU Line Card Subscriber Board M PU Subscriber Board _______________________________ Pericom Technology Inc. ______________________________ Fax-on Demand: (86)-755-5182-760 Email: [email protected] PTI web-site: www.pti.com.cn Sales Office: Unit B-2206, 22/F, Carrianna Friendship Square, 2002 S. Renmin Road, Shenzhen, 518001, China 2