Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| • • • • • Features • • • • • • • • • • • • • • • • • • • • • • • • Complete 2.4GHz High performance Radio Transceiver No external trimming is required in production Bluetooth wireless technology, 2.4 GHz licensefree band Compliant to the Bluetooth™ specification v1.1 Bluetooth Class 2, 3 Level Output Power High Receive sensitivity -85 dBm typ. Communications of up to 10m range in free space Frequency Hopping Spread Spectrum (FHSS) with Gaussian Frequency Shift Keying (GFSK) Transmission scheme TDD – time division duplex. Frequency 2402 to 2480 MHz Channel intervals 1 MHz Number of channels 79 CH Symbol rate 1M symbol/s Compliant to FCC, CE, ETSI and other countries' EMI standards Very good data quality--tolerates blocking by other services Internal 16MHz crystal and clock oscillator Integrated RF bandpass filter SPI interface for installing and configuring the module Low Power standby modes to enable very efficient power management Available for either external antenna or internal patch_antenna Power supply voltage 2.7 V and 3.3V Operation Temperature: 0 ~ 40°C Small size, lightweight, size 33mm X 20mm X 1.5mm Available in small quantities General Descriptions The PT8R2401 is well suited to applications that fall within the 2.4 GHz radio spectrum designated as Industrial, Scientific and Medical (ISM). Transmission scheme TDD – time division duplex. Spreading type FHSS – frequency hopping spread spectrum. Number of channels 79. Channel intervals 1 MHz [(f = 2.402 + k) GHz, k = 0,1,2,…78]. Hop rate 1.6k hops/second. Modulation Method GFSK 0.5BT Gaussian. Support point-to-multipoint functionality. The PT8R2401 control interface consists of a data interface and a control interface for transmitting and receiving data, and a serial interface for programming the internal registers of the PT8R2401. There are two subsections of the interface: • RF data and control path • Register control interface (serial). Six signals are used in the RF data and control path (TXDATA, RXDATA, TXACTIVE, RXACTIVE, TXDATA_EN, SYNCDETECT). Four in the serial register control interface ( TDI, TDO, TMS, TCK), one system clock (DATACLK) and one reset signal (RET). All of the signals are unidirectional. Standard PT8R2401 has built-in antenna. Option PT8R2401N has no built-in antenna. Customer can use external antenna. Application • • • • Personal Digital Assistants (PDAs) Cordless Headsets Digital camera USB Dongle /RS232 adaptor And many other computer peripherals or embedded devices applications, including wireless keyboard, mouse, joystick etc. Laptop and Desktop PCs Computer Accessories (Compact Flash, PCMCIA and SD cards) Cordless game controllers Printers, FAX, WebPAD These modules can be integrated into almost any radio electrical device for wireless data communications, including PDAs, mobile phones, laptop computers, and game pad devices. PT0141(06/03) Ver:0 1 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Ordering Information Description Device Order Number Type Size PT8R2401 Have built-in antenna 33X20X1.5 (mm) PT8R2401MD PT8R2401N No built-in antenna 33X20X1.5 (mm) PT8R2401MD Block Diagram C1 15p C2 15p XTAL1 16M TXACTIVE 100k 22 23 R2 C5 AS169-73 3 C6 2.7p 47p 1 2 3 L3 34 RF_OUT 2.2n 47p RXACTIVE L2 VCC2.7 10n C7 100p TP1 TP2 VCC2.7 39 PA_CNT 3 4 5 6 7 30 HEADER15 RF_VCC VCO_VCC VCO_VCC GND 26 27 VCC2.7 SYNCDETECT MDSEL 38 JP1 SYNCDETECT TMS TDI TDO TCK RESET VCC3.3 DATACLK TXDATA_EN TXDATA RXDATA RXACTIVE TXACTIVE VCC2.7 GND TCLK TMS TDI TDO PT8R1002 TEST_P1 TEST_P2 TEST_P3 TEST_P4 TEST_P5 TEST_P6 C8 100p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESET TXDATA RXDATA TXACTIVE RXACTIVE TXDATA_EN DATACLK R1 10 C9 100p C16 0.1u RESET 16 12 11 9 10 13 14 TXDATA RXDATA TXACTIVE RXACTIVE TXDATA_EN DATACLK 17 20 19 18 TCK TMS TDI TDO SYNCDETECT 21 VCC3.3 40 41 DIG_VCC IO_VCC RF1 GND RF2 8 15 47p V1 RFC V2 AN_VCC AN_VCC 6 5 4 XTALOUT 2.7n SW1 C3 2 24 25 OUT RF_IN AN_VCC AN_VCC IN 37 1 2 1 L1 VCO_VCC VCO_VCC RF_VCC FL1 MDR746F 31 32 33 ANT1 XTALIN IC1 C4 VCC3.3 C13 1n VCC2.7 VCC2.7 C10 100p C14 1n VCC2.7 C17 0.1u VCC2.7 C11 100p C12 1n PT0141(06/03) C15 1n Ver:0 2 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Information Package Diagram Unit: mm 20 33 2 Size 33X20X1.5 (mm) Pin Descriptions Pin PIN Name 1 2 3 4 5 GND VCC2.7 TXACTIVE RXACTIVE RXDATA 6 TXDATA 7 8 9 10 11 12 13 TXDATA_EN DATACLK VCC3.3 RESET TCK TDO TDI 14 15 TYPE Power Power I I O I Description GND 2.7V Power Supply Transmitter enable Receiver enable Receive data Transmit data I O Power I I O I Timing reference of valid data Reference data clock 3.3V Power Supply Reset A serial register interface clock Phy control register serial data output Phy control register serial data input TMS I Control signal of Phy’s TAP controller SYNCDETECT I Indication of SYNC word detection PT0141(06/03) Ver:0 3 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| I/O Description RF interface The radio interface establishes the connection of antenna-to-LNA in receiving mode and antenna-to-power amplifier in transmitting mode. An antenna filter is located between the antenna and SPDT (Single Pole Double Throw) switch. The antenna filter blocks unwanted signals in receive mode and suppresses harmonics in the transmit mode. The filter can be either a discrete component or fully integrated in ceramic substrate. The SPDT switch isolates the transmit path and the receive path and thus impedance can be matched for entire signal path. A matching circuit is placed between LNA_IN pin and SPDT switch to match the 50 ohm source to the complex input impedance of the LNA. Another external matching circuit is required at PA_OUT to transfer maximum power to the antenna. Unidirectional interface The interface connections for unidirectional mode are shown as follows: the unidirectional interface can be split into two subsections: RF data and control path, register control interface. In RF interface, ten signals are used in the RF data and control path, and four in the register control interface. All of the signals are unidirectional. The unidirectional interface requires that the PT8R2401 control registers interface to the Baseband via an IEEE 1149.1 JTAG interface. The unidirectional interface requires that the Baseband portion of the interface is referenced to a Baseband generated clock. Transmit Operation In Unidirectional Interface The primary signal for data transmit is TXACTIVE signal. The actual data transmission starts after TXDATA_EN provided by baseband. During transmit mode, DATACLK is sent from PT8R2401 to baseband as a timing reference. The baseband circuit transmits data to the PT8R2401 at the falling edge of DATACLK, whereas the PT8R2401 latches the data at the rising edge of DATACLK. The state of PT8R2401 transits from the idle state when the baseband drives TXACTIVE HIGH. TXACTIVE enables all the transmit circuitry except for the final output stage. TXACTIVE is driven high at a time TTuningTX before the hop frequency synthesizer has settled to allow any frequency offsets caused by the TX circuitry to be eliminated. Either when, or just before, the TX circuitry has correctly settled on frequency, the baseband drives TXDATA_EN HIGH, which enables the PA stage, and causes the unidirectional interface to enter the transmit data state. The baseband drives data to the PT8R2401 on the falling edge of DATACLK, and the PT8R2401 reads the transmit data on the rising edge. When all the data has been transmitted, the baseband drives TXDATA_EN and TXACTIVE LOW to disable the PA stage and return to the idle state. Idle VCO Tuning Tx-Ramp-Up Tx-Burst Tx-Ramp-Down Idle JTAG Programming HOP CMD TXACTIVE TXDATA_EN TXDATA Tx DATA RXACTIVE SYNCDETECT RXDATA DATACLK tTuningTX tRamp-Up tRamp-Down Figure 2. Transmit procedure timing diagram in unidirectional interface PT0141(06/03) Ver:0 4 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DATACLK(13MHz,O) TXACTIVE(I) TXDATA_EN(I) TXDATA(I) RXACTIVE(I) SYNCDETECT(I) RXDATA(O) PE SYNC WORD PE SYNC WORD TE tRamp-Up HEDER+PAYLOAD PE : Preamble TE : Trailer tRamp-Down Figure 3. Transmit signal timing diagram in unidirectional interface PT0141(06/03) Ver:0 5 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Receive Operation In Unidirectional Interface The primary signal for data reception is RXACTIVE signal. When RXACTIVE goes to high, the RF circuitry starts to operate and send data after fixed time from RXACTIVE. The baseband receives data and searches for the access code. During receive mode, DATACLK is sent from PT8R2401 to baseband as a timing reference. The PT8R2401 circuit sends the data to baseband at the rising edge of DATACLK, where the baseband latches the data at the falling edge of DATACLK. Prior to receiving information over air, the baseband transfers control information including the hop frequency over the JTAG interfaces, and enters PT8R2401 into search access code state after fixed time to turn on receiver circuitry by driving RXACTIVE HIGH. In the search access code state, the baseband performs all of the tasks required to correlate with the access code from the receive data. When the baseband has correlated the access code, then it drives SYNCDETECT HIGH and makes PT8R2401 enter into receive payload state. During the payload, PT8R2401 eliminates any frequency offset between local and remote Bluetooth devices based on its measurement during syncword acquisition. PT8R2401 transmits demodulated data to the baseband at half frequency of DATACLK, which can be read by the baseband using appropriate timing recovery algorithm. The unidirectional interface is returns to the idle state with the baseband driving RXACTIVE LOW after a fixed interval of TRxOff. Idle VCO Tuning Rx-On Search Access Code Rx-Burst Idle JTAG Programming HOP CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT Valid Rx Data RXDATA DATACLK tTuningRX tRxOn tAccessCode tRxOff Figure 4. Receiver procedure timing-diagram in unidirectional interface DATACLK(13MHz,O) TXACTIVE(I) TXDATA_EN(I) TXDATA(I) RXACTIVE(I) SYNCDETECT(I) RXDATA(O) tRxOn tRxOff PE SYNC WORD TE HEADER+PAYLOAD PE : Preamble TE : Trailer Figure 5. Receiver signal timing diagram in unidirectional interface PT0141(06/03) Ver:0 6 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Power-Up Sequence The power-up sequence of PT8R2401 is very simple mechanism. After power is applied to the PT8R2401, the activating RESET signal into LOW for tRESET is the only required operation. After this procedure, PT8R2401 will come into idle mode for waiting transmit or receive operation indicated by Bluetooth baseband. Before this normal operation, all SPI register value should be initialized even though its value is set by the default value. The initialized value will be provided by PTI. After activating RESET signal, 13 or 16MHz baseband reference signal, DATACLK will be activated until execution of external power down command through SPI interface. Power-off RESET Idle VCO Tuning Rx-On Search Access Code POWER RESET Serial Programming SPI initialization for all registers HOP CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK Receiver Operation Figure 6. Power-up sequence procedure timing-diagram PT0141(06/03) Ver:0 7 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Power-Down Sequence The lowest operation power state of PT8R2401 is Sleep state, where all clocks including RF and baseband and circuits in the PT8R2401 is placed in their minimum power mode. In this mode, the control register can be accessed through serial interface logic and retain their programmed value. To enter into Sleep state, power-down command which sets power-down of clock generator including crystal buffer should be programmed through the serial interface. After power-down command, the DATACLK from the PT8R2401 will stop until it comes back to Idle state. To escape from Sleep state, power-up command which sets power-up of clock generator should be programmed through the serial interface. After power-up command, the DATACLK will start again from the PT8R2401 into external baseband. Idle Sleep Idle VCO Tuning Tx-Ramp-Up POWER RESET JTAG Programming Power Down CMD Power Up CMD HOP CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK Transmit Operation Figure 7. Power-down sequence procedure timing-diagram PT0141(06/03) Ver:0 8 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Power Control In the PT8R2401, there are five different states with different current consumption; Sleep, Idle, VCO active, TX active, and RX active. Upon reset, the PT8R2401 stays in the Idle state to wait for the command through serial programming interface from the baseband controller. In the Idle state, there is DATACLK from the radio to the baseband controller. In the Idle mode, all RF circuits are shut down to reduce the static current consumption. Only the reference clock oscillator and DATACLK pump to the baseband is active. After HOP set command through the serial programming, the VCO will operate to lock the programmed channel frequency. Owing to the signal such as RXACTIVE or TXACTIVE, the PT8R2401 will enter into the active state such as TX active state and RX active state. In those state, all RF circuits and GFSK modem will operate and result in the maximum current consumption. In the unidirectional mode, the falling signal of RXACTIVE or TXACTIVE will make the PT8R2401 into Idle state automatically. In the bidirectional mode, the explicit command to stop receive or transmission through serial programming will make the PT8R2401 into Idle state. The PT8R2401 enters into Sleep state by power down command through serial programming. Sleep state is the least power consumption among other states and all clocks include reference oscillator will stop the operation as well as the power down of all RF circuits. In Sleep state, only the serial programming interface logic can operate which uses clock from external device. However, the value of all registers will sustain until the wake up from Sleep state. Following figure shows the state transition in terms of power control. RX active state (IRX) TX active state (ITX) Receive command Transmit command RXACTIVE off VCO active state (IVCO) TXACTIVE off HOP command Idle state (IIdle) Power-Down command Power-Up command Sleep state (ISleep) Figure 8. State transition diagram for power control PT0141(06/03) Ver:0 9 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Serial Programming Interface (JTAG interface) The serial programming interface is a JTAG boundary-scan architecture compliant with IEEE 1149.1. Interconnection between the serial interface and external baseband consists of four 1-bit digital signals : control data input(TDI), control mode select (TMS), control clock (TCK) and control data output (TDO). You must refer to the full IEE std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture document for a complete, definitive description of the operation of the fundamentals of the JTAG interface. PT1002 support TCK up to 16MHz. Table 1. TAP instructions Instruction EXTEST Opcode 0x000000 Description EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR state. Also, when EXTEST is selected, all system input pin states must be loaded into the Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into input latches in the Boundary-Scan register are never used by the processor’s internal logic. SAMPLE / PRELOAD 0x000001 SAMPLE / PRELOAD performs two functions: • When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the rising edge of TCK and provides a snapshot of the component’s normal operation without interfering with that normal operation. The instruction causes Boundary-Scan register cells associated with outputs to SAMPLE the value being driven by or to the processor. • When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to the slave register cells. Typically the slave-latched data is then applied to the system outputs by means of the EXTEST instruction. IDCODE 0x011111 IDCODE is used in conjunction with the device identification register. It connects the identification register between TDI and TDO in the Shift_DR state. When selected, IDCODE parallel-loads the hard-wired identification code (32 bits) on TDO into the identification register on the rising edge of TCK in the Capture_DR state. NOTE: The device identification register is not altered by data being shifted in on TDI. REGISTER PROGRAMMING 0x1SSSSS REGISTER PROGRAMMING instruction select the REGISTER with address indicator SSSSS. • When the TAP controller is in the Capture-DR state, the REGISTER PROGRAMMING instruction occurs on the rising edge of TCK and executes a snapshot of register addressed SSSSS into serial register. • When the TAP controller is in the Update-DR state, the REGISTER PROGRAMMING instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in serial register to register addressed SSSSS. BYPASS 0x111111 BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR state, effectively bypassing the processor’s test logic. 0 is captured in the CAPTURE_DR state. While this instruction is in effect, all other test data registers have no effect on the operation of the system. Test data registers with both test and system functionality perform their system functions when this instruction is selected. PT0141(06/03) Ver:0 10 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| SPI Register Map The values of all registers except read-only are set by default values after rest. The default values can be overrided by accessing each register. Typical register values are subject to change and should be obtained from PTI. During normal operation, SPI access should occur to address the following functions only. z Programming PLL hop frequency of BT_RF_PLL_CTRL0 z Setting Tx power control value of BT_RF_TX_CTRL in the transmit mode z Reading receive signal strength indication of BT_RSSI_STA in the receive mode z Programming TXA or RXA of BT_RF_PLL_CTRL1 to indicate transmit or receive mode in bidirectional interface Table 2. SPI register address map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17~0x1D 0x1E 0x1F Name BT_SOFT_RESET BT_MODEM_CTRL BT_RF_RX_CTRL BT_RF_TX_CTRL BT_RF_BB_CTRL0 BT_RF_BB_CTRL1 BT_RF_PLL_CTRL0 BT_RF_PLL_CTRL1 BT_RF_PLL_CTRL2 BT_RF_PLL_CTRL3 BT_RF_TIM_CTRL0 BT_RF_TIM_CTRL1 BT_RF_TIM_CTRL2 BT_RF_TIM_CTRL3 BT_RF_TIM_CTRL4 BT_RF_TIM_CTRL5 BT_RF_AUX_CTRL0 BT_RF_AUX_CTRL1 BT_RSSI_STA BT_RF_STA BT_DAC_TEST_CTRL BT_PWD_CTRL0 BT_PWD_CTRL1 BT_PWDN IDCODE Attribute write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read read read/write read/write read/write write read Description RESET by serial interface* Modem control register RF receiver control register RF transmitter control register RF baseband control0 register RF baseband control1 register RF PLL control0 register RF PLL control1 register RF PLL control2 register RF PLL control3 register RF timing adjustment configuration0 register RF timing adjustment configuration1 register RF timing adjustment configuration2 register RF timing adjustment configuration3 register RF timing adjustment configuration4 register RF timing adjustment configuration5 register RF auxiliary control0 register RF auxiliary control1 register Modem RSSI register RF status register DAC test register MODEM power detector register0 MODEM power detector register1 Reserved Power down register IDCODE * Equivalent to hardware reset by asserting RESET pin. PT0141(06/03) Ver:0 11 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| * The values in all registers are the recommended initial value to be set by the serial programming interface, since some of them may be different value with the default configuration by hardware after reset. Also, these value can be changed in order to be optimized for special purpose. Please contact PTI semiconductor to get up-to-date configuration. 0x01 15 CKS 0 TEPM 14 BT_MODEM_CTRL 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEPM 00b 01011b 0111b 0 1 1 1 External power amp drive enable mode 00 : off 01 : on 10/11 : on during TXACTIVE is high CKS Reference clock select flag 0 : 13MHz 1 : 16MHz 0x02 BT_RF_RX_CTL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01b 0 01b 1000b 0b 000000b 0x03 BT_RF_TX_CTL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OS TPG TAG 1 0 0111b 11111b 001b OS Output DATACLK PAD strength 0 : The driving capability of DATACLK is low 1 : The driving capability of DATACLK is high TPG External power amp gain control 00000b (1mA) ~ 11111b(0mA) with 32uA step TAG Transmission AGC gain control 000b(-3dB), 001b(-1.5dB), 010b(0dB), 011b(1.5dB), 100b(3dB), 101b(4.5dB), 110(6dB), 111(7.5dB) 0x04 BT_RF_BB_CTRL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 1 11b 0 0011b 0 0x05 BT_RF_BB_CTRL1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1010b 0 111b 011b 0000b 0x06 BT_RF_PLL_CTRL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXA RXA TG CH 0 0 0111111b 0000000b TXA Internal TXACTIVE signal generation in bidirectional interface. Writing HIGH For more detail operation, refer to I/O description of transmit operation. This field does not affect in unidirectional interface. RXA Internal RXACTIVE signal generation in bidirectional interface. For more detail operation, refer to I/O description of receiver operation. This field does not affect in unidirectional interface. TG[6] Internal pre power amp gain control with bias change 1 : gain increase, 0 : gain decrease TG[5:0] Internal pre power amp gain control with driving ability 000000b(minimum gain) ~ 111111b(maximum gain) CH Frequency channel selection 0000000b : 0 channel(2402MHz), 0000001b : 1 channel(2403MHz), … 0x07 BT_RF_PLL_CTRL1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 00000000 00000 0x08 BT_RF_PLL_CTRL2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00b 11b 001b 00b 10b 1 010b 0x09 BT_RF_PLL_CTRL3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1000000000b 00b 00b 0 0 0x0A BT_RF_TIM_CTRL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBD TBD TBD TBD PT0141(06/03) Ver:0 12 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 0x0B 15 BT_RF_TIM_CTRL1 13 12 11 TBD 0x0C BT_RF_TIM_CTRL2 15 14 13 12 11 TBD 0x0D BT_RF_TIM_CTRL3 15 14 13 12 11 TBD 0x0E BT_RF_TIM_CTRL4 15 14 13 12 11 TBD 0x0F BT_RF_TIM_CTRL5 15 14 13 12 11 TBD TBD TBD 0x10 BT_RF_AUX_CTRL0 15 14 13 12 11 0 01b 0 0x11 BT_RF_AUX_CTRL1 15 14 13 12 11 14 1 PVN 000b PVL 0x12 15 14 PVO BT_RSSI_STA 13 12 RSSI_PO3 PVO RSSI_AGC 0x13 15 14 BT_POW_STA 13 12 10 9 8 7 6 TBD 5 4 10 9 8 7 6 TBD 2 9 8 7 5 6 TBD 4 3 9 8 7 4 3 9 4 7 5 3 4 9 8 7 1 6 1 5 4 9 8 7 6 5 4 01b 01b 1 0 0 Pre power amp output power detection enable 0 : disable 1 : enable Pre power amp power detector reference level 000b(-7dBm), 001b(-5dBm), 010b(-3dBm), 011b(-1dBm) 100b(0dBm), 101b(1dBm), 110b(2dBm), 111b(3dBm) 0 TBD 1000b 11 10 9 8 7 11 10 9 8 7 1 0 1 TBD 0 1 0 1 PVL 100b 0 2 3 2 TBD 6 5 4 RSSI_RF 1 : The current power of pre power amp is more than PVL 0 : The current power of pre power amp is less than PVL AGC gain value with 3dB step from –3dB(0000b) to 42dB(1111b) 6 0 TBD 8 TBD 10 1 TBD 5 6 0 2 TBD 10 1 TBD 5 6 TBD 0 2 TBD 10 1 TBD TBD 10 10 3 TBD 5 3 2 000000b 3 PVN 0 3 4 3 4 3 2 2 1 RSSI_AGC 0 2 1 0 2 DACQ 000000b 1 0 1 AFS 1 0 DSS 1 CSS 0x14 15 14 0x15 15 14 0x16 15 14 0x1E 15 14 BT_DAC_TEST_CTRL 13 12 11 DE 0 BT_PWD_CTRL0 13 12 11 BT_PWD_CTRL1 13 12 11 PBD 0 BT_ PWDN 13 12 11 PD 10 9 8 DACI 000000b 7 10 9 8 7 6 5 PWD_START 10000010b 4 3 2 10 9 PWR_TH3 1010b 8 7 6 5 PWR_TH2 0100b 4 3 2 1 PWR_TH1 0110b 10 8 7 6 5 4 3 2 1 0 PD 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 9 6 5 0 1 : Power down mode enable 0 : Power down mode disable 0x1F 31 30 15 14 IDCODE 29 28 13 12 27 26 25 11 10 9 24 23 IDCODE[31:16] 0x0000 8 7 IDCODE[15:0] 0x0001 PT0141(06/03) Ver:0 13 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| JTAG Registers Programming Timing Diagram In Unidirectional Interface 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 …. 28 29 30 31 TCK TMS TDI High-Z TDO A0 A1 A2 A3 A4 H a0 a1 a2 a3 a4 a5 Don’t care D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 …. D14 D15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 …. Q14 Q15 Update register value of Phy Figure 9. Serial register write programming timing diagram in JTAG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ….. 29 30 31 32 TCK TMS TDI TDO High-Z A0 A1 A2 A3 A4 H a0 a1 a2 a3 a4 a5 Don’t care X Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 ….. Q14 Q15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 ….. Q15 X Update register value of BB Figure 10. Serial register read programming timing diagram in JTAG PT0141(06/03) Ver:0 14 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Electrical Specifications Absolute Maximum Rating Parameter Storage Temperature Symbol Test condition Ambient Temperature with Power Applied Supply Voltage (no damage) Min -40 -20 typ 0.8 -0.3 DC Input Voltage DC Voltage applied to Outputs in High-Z State -0.3 Digital Inputs Vcc – 0.4V Static Discharge Voltage (Digital) 1 Static Discharge Voltage (RF) Latch-up Current 1 -200 max 85 65 Unit °C °C 3.9 Vcc +0.3 Vcc +0.3 Vcc+0. 4V 2000 V V 500 200 V mA max 40 95 Unit V V °C % max 60 Unit mA 60 mA 70 mA 70 mA 20 20 mA uA V V V Note: Rating measured using the Human Body Model (HBM). Recommended Operating Conditions Parameter Supply Voltage Symbol Test condition VCC2.7 VCC3.3 Temperature Humidity min typ 2.7 3.3 0 DC/AC Specification Power Consumption Parameter Radio Transmit Current Radio Receive Current Radio Transmit Peak current Radio Receive Peak current Idle Current Deep Sleep Current Symbol Test condition DH1 pakaet with PRBS9 payload, no hops DH1 pakaet with PRBS9 payload, no hops DH1 pakaet with PRBS9 payload, 1.6k hops DH1 pakaet with PRBS9 payload, 1.6k hops Tx and Rx no active Deep Sleep Mode PT0141(06/03) min typ Ver:0 15 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Common Radio Specifications Parameter Operating Frequency symbol Channel intervals Channel Duplexing slot time Test condition f = (2.402 + k) GHz, k = 0,1,2,…78 min 2402 Number of channels Transmission scheme TDD – time division duplex Symbol Rate Modulation Data Polarity “H” “L” typ max 2480 1 79 625 MHz 1M symbol /s us Fc +dF Fc –dF 1600 Hop Rate Antenna interface output impedance Unit MHz hops/s ec ohm 50 Radio Receiver Specifications Parameter Sensitivity Maximum received signal Self channel selectivity Adjacent channel selectivity 2nd adjacent channel selectivity 3rd adjacent channel selectivity Image rejection Maximum level of intermodulation interferes Maximum level of GSM signal at 1.8GHz symbol Test condition 0.1% BER DH1 pakaet with PRBS9 payload,no hops, at 2402,2441,2480 MHz 0.1% BER DH1 pakaet with PRBS9 payload,no hops, at 2402,2441,2480 MHz C/I Co-channel (1) C/I 1MHz (1) C/I 2MHz (1) C/I •3MHz (1) (2) C/I (1) (3) (1) (4) 0.1% BER with wanted input at – 67dBM, and with the RF filter removed from the circuit, DH1 pakaet with PRBS9 payload, 1.6k hops Maximum level of W-CDMA signal at 1.8GHz Maximum level of W-CDMA signal at 2.2GHz min typ -85 -20 -5.0 -39 9 -2.0 -34 -43 -12 -30 -7.0 max -80 Unit dBm dBm 11 0 -30 -40 -9 dBc dBc dBm dBm -9.5 -11 PT0141(06/03) dBm Ver:0 16 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Radio Transmitter Specifications Parameter symbol RF transmit power level RF power control range RF power range control resolution 20 dB bandwidth for modulated carrier Initial Carrier Freq Tolerance Frequency Deviation Zero Crossing Error 2nd adjacent channel transmit power >3rd adjacent channel transmit power Non-harmonically Related Spurious nd 2 Harmonic Spurious rd 3 Harmonic Spurious th 4 Harmonic Spurious Test condition DH1 pakaet with PRBS9 payload,no hops, single slot packets, at 2402,2441,2480 MHz DH1 pakaet with PRBS9 payload,no hops, single slot packe, at 2441 MHz min typ max Unit dBm 16 30 dB 2.0 DH1 pakaet with PRBS9 payload,no hops, single slot packets, at 2402,2480 MHz DH1 pakaet with PRBS9 payload, no hops, single slot packe, at 2441 MHz single slot, Continue 101010 pattern, 11110000 pattern, at 2441 MHz single slot, Continue 101010 pattern, 11110000 pattern, at 2441 MHz Second Channel Power (±2 MHz), DH1 pakaet with PRBS9 payload,no hops, single slot packets at 2441 MHz Third Channel Power (>3 MHz), DH1 pakaet with PRBS9 payload,no hops, single slot packets, at 2441 MHz 900 1000 kHz +/- 25 +/- 75 KHz 90 175 kHz -125 125 ns -52 -20 dBm -57 -40 dBm 30 MHz – 12.75 GHz at 2441 MHz at 2441 MHz at 2441 MHz at 2441 MHz –57 dBm -26 -30 -37 dBm dBm dBm Notes: (1) Measured according to the Bluetooth specification. (2) Up to five spurious responses within Bluetooth limits are allowed (3) At carrier –3MHz. (4) Measured at f1 – f2 = 5MHz. (5) For 0.1% BER with wanted input at –67dBM, and with the RF filter removed from the circuit. PT0141(06/03) Ver:0 17 Preliminary Data Sheet PT8R2401MD 2.4GHz RF Module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Pericom Technology Inc. Email: [email protected] Web Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0141(06/03) Ver:0 18