ST10R172L-B0 ® 16-BIT LOW VOLTAGE ROMLESS MCU ERRATA SHEET 1 INTRODUCTION This errata sheet describes the functional problems known in the step B0 of the ST10R172L-B0. This is the erratasheet of the ST10R172L datasheet version 1.2 of March 2001. 2 FUNCTIONAL PROBLEMS The following malfunctions are known in this step: 2.1 ST_PWRDN.1: EXECUTION OF PWRDN INSTRUCTION WHILE NMI PIN IS HIGH When PWRDN instruction is executed while NMI pin is at a high level, power-down mode should not be entered, and the PWRDN instruction should be ignored. However, under the conditions described below, the PWRDN instruction may not be ignored, and no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This problem will only occur in the following situations: 1) the instructions following the PWRDN instruction are located in an external memory, and a multiplexed bus configuration with memory tristate waitstate (bit MTTCx= 0) is used, 2) the instruction preceding the PWRDN instruction writes to external memory or an XPeripheral (XRAM, CAN), and the instructions following the PWRDN instruction are located in external memory. In this case, the problem will occur for any bus configuration. Note: the on-chip peripherals still work correctly: if the Watchdog Timer is not disabled, it will reset the device upon an overflow. Interrupts and PEC transfers, however, can not be processed. If NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered. No problem will occur if the NMI pin is low: the chip will normally enter power-down mode. Workaround: Ensure that no instruction which writes to external memory or an XPeripheral precedes the PWRDN instruction, otherwise insert e.g. a NOP instruction in front of PWRDN. When a multiplexed bus with memory tristate waitstate is used, the PWRDN instruction should be executed from internal RAM or XRAM. Rev. 1.1 March 2001 1/3 ST10R172L-B0 Errata Sheet 2.2 CORE.4: INCORRECT INSTRUCTION FETCH ON JUMP TO ITSELF The bug happens In the following program sequence: ... ... Label_A: JMPR cc_XX, Label_A Word Intruction 1; Word Intruction 2 Word Intruction 3 ... ... ... In the following conditions: - code is fetched from External Memory, - the loop JMPR cc_XX, Label_A is being executed, - a PEC transfer with PSW as destination triggers a change of the condition cc_XX and so, the loop is finished, the Word Intruction1 is never executed. Workaround: If JMPA is used instead of JMPR, the bug does not occur. 2.3 EBC.3: VISIBLE MODE When visible mode is enabled (syscon.1 = 1), data of a read access to an XBUS peripheral is not driven to the external bus (Port 0). Instead, Port 0 is tri-stated during these read accesses. If all external devices are configured in 8-bit demultiplexed mode, an XBUS-peripheral write can cause a conflict on P0H (Port 0 [8:15]). 2.4 EBC.4: XPERS ACCESS IN XPERSHARE/EMULATION MODE In emulation mode and if the Startup Configuration 8-bit multiplexed mode is selected, P0H (Port 0 [8:15]) is always an output and write accesses to XPERs cannot be done as these would cause a conflict. Workaround: Use a Startup Configuration other than 8-bit multiplexed mode. If HOLD mode is entered (P6.5 = 0) following an 8-bit multiplexed mode access and if Xpershare is enabled, Xper accesses will cause a conflict on the internal XBUS xb_data [15:7] bus. Workaround: None. 2/3 ST10R172L-B0 Errata Sheet 3 HISTORY OF FIXED FUNCTIONAL PROBLEMS OF THE ST10R172L: Functional Problem CPU.17 Short Description fixed in Step Arithmetic Overflow by DIVLU instruction B0 TRAP_B.1 ATOMIC / EXTended sequences in Class B Hardware Trap B0 Kfm_BR03 Pipeline conflict after CoStore operation B0 Kfm_BR04 Wrong PSW value after byte instruction B0 Kfm_BR05 Wrong result for BFLDL/BFLDH instructions B0 CORE.3 Incorrect instruction fetch on Cache Jump B0 CORE.4 Incorrect instruction fetch on Jump to itself B0 CLK.1 ADAPT mode entered during power-up synchronous reset B0 DAD.6 Incorrect PEC source fetch after JMPS instruction B0 DAD.7 Incorrect pipeline dependency detection between DPRAM and (E)SFR address space B0 Information furnished is believed to be accurate and reliable. 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