Errata Sheet LPC2930

INTEGRATED CIRCUITS
ERRATA SHEET
Date:
Document Release:
Device Affected:
2009 February 27
Version 1.0
LPC2930
This errata sheet describes both the known functional problems and any deviations from the electrical
specifications known at the release date of this document.
Each deviation is assigned a number and its history is tracked in a table at the end of the document.
2009 February 27
NXP
Semiconductors
NXP Semiconductors
LPC2930 Erratasheet
Document revision history
Rev
1.0
Date
2009 February 27
2009 February 27
Description
First version
2
NXP Semiconductors
LPC2930 Erratasheet
Identification
The typical LPC2930 devices have the following top-side marking:
LPC2930xxx
xxxxxxx
xxxYYWWR
The last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers the following
revisions of the LPC2930:
Revision Identifier (R)
‘(blank)’
Comment
Initial device revision
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured
during that year.
2009 February 27
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NXP Semiconductors
LPC2930 Erratasheet
Errata Overview - Functional Problems
Functional
Problem
ADC0.1
Short Description
Missing Codes
Device Revision
the problem
occurs in
(blank)
Errata Overview - AC/DC Deviations
AC/DC Deviation
ESD.1
Short Description
The LPC2930 does not meet the NXP QRS ESD
requirements on the Vddosc pin. The Vddosc pin fails ESD HBM at
500 V.
Device Revision
the deviation
occurs in
(blank)
Errata Notes
Notes
N/A
2009 February 27
Short Description
N/A
Device Revision
the note applies
to
N/A
4
NXP Semiconductors
LPC2930 Erratasheet
Functional Problems of LPC2930
ADC0.1
Missing Codes
Introduction:
The LPC2930 has a 10-bit ADC with a 5.0 V measurement range providing a total of up to 24 analog
inputs with conversion times as low as 2.44 µs per channel (FADC = 4.5 MHz). Each channel
provides a compare function to minimize interrupts.
Problem:
On devices with date codes before 0905 and for FADC > 2.5 MHz, the 5 V ADC shows missing
codes.
Work around:
Limit the FADCmax for ADC0 to 2.0 MHz.
2009 February 27
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NXP Semiconductors
LPC2930 Erratasheet
AC/DC Deviations
ESD.1
The LPC2930 does not meet the NXP QRS ESD requirements on the Vddosc pin.
Introduction:
The LPC2930 is rated for 2 kV ESD HBM. The Vddosc pin is the power supply pin for the oscillator
circuit.
Problem:
On devices with date codes before 0905, the LPC2930 does not meet the required 2 kV ESD HBM
specification.
Work around:
Observe proper ESD handling precautions for the LPC2930.
2009 February 27
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