ETC TMS320DM642-600

TMS320DM642 Video/Imaging
Fixed-Point Digital Signal
Processor
Data Manual
Literature Number: SPRS200C
July 2002 − Revised July 2003
! Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated
Revision History
Revision History
This data sheet revision history highlights the technical changes made to the SPRS200B device-specific data
sheet to make it an SPRS200C revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM642 device, have
been incorporated. “TBD” areas, where possible, have been resolved since the last document update. For the
Asynchronous Memory, SDRAM Memory, and BUSREQ timings the AECLKOUT1 signal reference has been
updated with AECLKOUTx meaning that all EMIF timings are measured with respect to either AECLKOUT1 or
AECLKOUT2.
PAGE(s)
NO.
ADDS/CHANGES/DELETES
Global change — Peripheral Reference Guide split:
Updated all references to the “TMS320C6000 Peripheral Reference Guide (literature number SPRU190)”
Updated all references to specific peripheral chapters with new titles and new literature number associations
19
Features, Three Configurable Video Ports bullet:
Deleted subbullets “Supports RAW Video I/O” and “Transport Stream Interface Mode”
21
Description section:
Deleted the sentence “All three Video Port peripherals have the capability to operate as a video-capture port, a video-display
port, or a transport stream interface (TSI) capture port.” from the “The DM642 device has three configurable video port
peripherals ..” paragraph
Deleted the paragraph “For capture operation, the video port can operate ...”
Deleted the paragraph “For display operation, the video port can operate ...”
Deleted “the TMS320DM642 Technical Overview (literature number SPRU615) or” from the “For more details on the Video
Port peripherals, ...” paragraph
36
Table 1−8, Interrupt Selector Registers (C64x):
Deleted the 019C 0200 PDCTL row
Changed the “Reserved” address range from “019C 000C − 019C 01FF” to “019C 000C − 019F FFFF”
Deleted the “Peripheral Power-Down Control Register” table
36
Table 1−9, Ethernet MAC (EMAC) Control Registers:
Changed table title to “Ethernet MAC (EMAC) Control Registers”
Updated/splt Table 1−9, Ethernet MAC (EMAC) Control Registers
Added new EMAC Statistics Registers table (address range: 01C8 0200 − 01C8 05FF) [Table 1−10]
43
Table 1−21, PCI Peripheral Registers:
Changed the 01C0 0004 PMDCSR Power Management DSP control/status register row to “Reserved”
44
Table 1−23, MDIO Registers:
Updated Table 1−23, MDIO Registers
44
Table 1−24, Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers:
Changed the “Video Port Test Logic Global Control Register” and “Video Port MISR Results Register” to “Reserved”
51
Table 1−28, TMS320DM642 EDMA Channel Synchronization Events:
Changed the “EVENT DESCRIPTION” column for EDMA CHANNELs 38, 39, 40, 41, 42, 43, 56, 57 58, 59, 60, and 61
58−60
Figure 1−6, Peripheral Signals (Continued), VP0, VP1 and VP2
Updated “Channel A supports ...” and “Channel B supports ...” footnotes to state video port modes “currently not supported.”
July 2002 − Revised July 2003
SPRS200C
3
Revision History
PAGE(s)
NO.
ADDS/CHANGES/DELETES
62
Peripheral Selection at Device Reset section, Table 2−1, PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9],
PCI, EMAC, MDIO, and VIC):
Deleted “and VIC” from paragraph and Table 2−1 title
Added new row “1 0 x x” for peripheral selection pins
Updated “EEPROM (Internal to PCI)” column to clarify auto-initialization ENABLED (internal PCI registers auto-initialized via
External EEPROM) or DISABLED (internal PCI registers auto-initialized via internal default values)
Changed column title to “EEPROM (Auto-Init)”
“EEPROM (Auto-Init)” column: Changed old “Disabled” to “N/A”
63
Table 2−3, DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, and HD5):
Changed table title to “DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, VDAC/
GP0[8]/PCI66, HD5/AD5, PCI_EN, and MAC_EN)(Continued)”
Added new row for the “VDAC/GP0[8]/PCI66” device configuration pin
65−66
Peripheral Selection After Device Reset:
Table 2−4, Peripheral Configuration (PERCFG) Register Selection Bit Descriptions:
Added Figure 2−2 references in the MCBSP1EN, MCBSP0EN, and MCASP0EN “DESCRIPTIONS“ columnn
Added new figure titled “Figure 2−2, VP1, VP0, McBSP1, McBSP0, and McASP0 Data/Control Pin Muxing“
69
Table 2−7, Device Status (DEVSTAT) Register Selection Bit Descriptions:
Changed the PCI_EN status bit DESCRIPTION from “Shows the status of whether the EMAC peripheral ...” to “... PCI
peripheral ...”
71
Debugging Considerations section:
Added “TOUT1/LENDIAN”, “GP0[3]/PCIEEAI”, and “VDAC/GP0[8]/PCI66” configuration pins to the “It is recommended that
external connections be provided ...” paragraph
72
Table 2−9, DM642 Device Multiplexed Pins, VDAC/GP0[8]/PCI66 pin:
Added “The -500 device supports PCI at 33 MHz only For proper -500 device operation when the PCI peripheral is enabled
(PCI_EN = 1), this pin must be pulled up with a a 1-kΩ resistor at device reset.” to the pin DESCRIPTION
73
Table 2−9, DM642 Device Multiplexed Pins, VP0D[8:2]/McBSP0 pins:
Changed the DEFAULT FUNCTION from “None” to “McBSP0 functions”
80
Terminal Functions table, RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED) section:
Added “The -500 device supports PCI at 33 MHz only. For proper -500 device operation when the PCI peripheral is enabled
(PCI_EN = 1), this pin must be pulled up with a a 1-kΩ resistor at device reset.” to the “VDAC/GP0[8]/PCI66” pin
DESCRIPTION
83
Terminal Functions table, HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR
EMAC (CONTINUED) section:
Added “The -500 device supports PCI at 33 MHz only. For proper -500 device operation when the PCI peripheral is enabled
(PCI_EN = 1), this pin must be pulled up with a a 1-kΩ resistor at device reset.” to the “VDAC/GP0[8]/PCI66” pin
DESCRIPTION
85
Terminal Functions table, EMIFA (64-BIT) − ADDRESS section:
Added “Note: EMIFA address numbering for the DM642 device starts with AEA3 ...” to the description
87−88
4
Terminal Functions table, VIDEO PORT 2 (VP2) section:
Deleted “[default]” from the VP2D[19:0] pins DESCRIPTION; due to Video Ports not being enabled at device reset
Deleted “[default]” from the VP2CLK[1:0] and VP2CTL[2:0] pins DESCRIPTION; due to Video Ports not being enabled at
device reset
Terminal Functions table, VIDEO PORT 1 (VP1) OR MCASP0 DATA section:
Moved “[default]” from “Video port 1 (VP1) data input/output (I/O/Z)” to “McBSP1 data input/output (I/O/Z)”
Added “and the Device Configurations section of this data sheet.” to “For more details on the ...” pin DESCRIPTION
paragraph
Deleted “[default]” from the VP1CLK[1:0] and VP1CTL[2:0] pins DESCRIPTION; due to Video Ports not being enabled at
device reset
SPRS200C
July 2002 − Revised July 2003
Revision History
PAGE(s)
NO.
ADDS/CHANGES/DELETES
89
Terminal Functions table, VIDEO PORT 0 (VP0) OR MCASP0 CONTROL section:
Moved “[default]” from “Video port 0 (VP0) data input/output (I/O/Z)” to “McBSP0 data input/output (I/O/Z)”
Added “and the Device Configurations section of this data sheet.” to “For more details on the ...” pin DESCRIPTION
paragraph
Deleted “[default]” from the VP0CLK[1:0] and VP0CTL[2:0] pins DESCRIPTION; due to Video Ports not being enabled at
device reset
90
Terminal Functions table, MULTICHANNEL BUFFERED SERIAL PORT 1 (MCBSP1) section:
Moved “[default]” from “VP1 input/output data ‘x’ pin (I/O/Z)” to McBSP1 pins
Terminal Functions table, MULTICHANNEL BUFFERED SERIAL PORT 0 (MCBSP0) section:
Moved “[default]” from “VP0 input/output data ‘x’ pin (I/O/Z)” to McBSP0 pins
91
Terminal Functions table, MULTICHANNEL AUDIO SERIAL PORT 0 (MCASP0) CONTROL and MULTICHANNEL AUDIO
SERIAL PORT 0 (MCASP0) DATA sections:
Deleted “[default]” from the VP0D[19:12] muxed pins DESCRIPTION because neither the Video Ports nor the McASP0
Control are enabled at device reset
Deleted “[default]” from the VP1D[19:12] muxed pins DESCRIPTION because neither the Video Ports nor the McASP0 Data
are enabled at device reset
112
Video Port section:
Added “[TSI currently not supported]” to the “The video port peripheral can operate ...” paragraph
Added “[Raw Video Capture currently not supported]” and “[currently not supported]” to the “The port consists of two
channels ...” paragraph
Added “[currently not supported]” to the “For video capture operation, the video port ...” paragraph
Added “For more detailed information on the DM642 Video Port peripherals, see the ...” paragraph
113
VIC section:
Added “[currently not supported]” to the “When the video port is used in transport stream interface (TSI) mode ...“ paragraph
Added “For more detailed information on the DM642 VCXO interpolated control (VIC) peripherals, see ...” paragraph
114
EMAC section:
Added rerefence paragraph “For more detailed information on the DM642 EMAC peripheral, see the TMS320C6000 DSP
Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature
number SPRU628).”
115
MDIO section:
Added rerefence paragraph “For more detailed information on the DM642 MDIO peripheral, see the TMS320C6000 DSP
Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature
number SPRU628).”
116
General-Purpose Input/Output (GPIO) section:
Added new GPIO section with device-specific GPEN register
119
IEEE 1149.1 JTAG Compatibility Statement section:
Added rerefence paragraph “For more detailed information on the DM642 JTAG emulation, see the TMS320C6000 DSP
Designing for JTAG Emulation Reference Guide (literature number SPRU641).
119
EMIF Device Speed section:
Changed “bank” to “chip-enable (CE) space” in the “1 bank (maximum of 2 chips) of SDRAM connected to EMIF” sub−bullet
Changed “bank” to “CE space” in the “up to 1 bank of buffers connected to EMIF” sub−bullet
Changed the “183-MHz SDRAM for 133-MHz operation” bullet to “166-MHz SDRAM for 133-MHz operation”
Added rerefence paragraph “For more detailed information on the DM642 EMIF peripheral, see the TMS320C6000 DSP
External Memory Interface (EMIF) Reference Guide (literature number SPRU266).
120
Bootmode section:
Deleted the sentence “If SDRAM is used in the system, the CPU is internally “stalled” until the SDRAM initialization is
complete.”
July 2002 − Revised July 2003
SPRS200C
5
Revision History
PAGE(s)
NO.
ADDS/CHANGES/DELETES
121
Absolute Maximum Ratings Over Operating Case Temperature Range section:
Changed the Supply Voltage Ranges for CVDD from “−0.3 V to 2.3 V” to “−0.3 V to 1.8 V”
121
Recommended Operating Conditions table:
Changed the footnote from “Future variants of the C641x DSPs may operate at voltages ranging from 1.2 V to 1.4 V ...” to
“Future variants of the C641x DSPs may operate at voltages ranging from 0.9 V to 1.4 V ...”
122
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature table:
Added “Video Ports,” to the IOH, High-level output current parameter for “Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]),
McBSP”
Added a row for “SCL0 and SDA0” to the IOH, High-level output current parameter with a MAX value of “−10 mA”
Added “Video Ports,” to the IOL, Low-level output current parameter for “Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]),
McBSP”
Added a row for “SCL0 and SDA0” to the IOL, Low-level output current parameter with a MAX value of “10 mA”
Updated the title “... the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811)”
in the footnote
122
Recommended Clock and Control Signal Transition Behavior section:
Added new section with the statement “All clocks and control signals must transition between VIH and VIL (or between VIL
and VIH) in a monotonic manner.”
126
Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 table:
Deleted tc(CKO4) parameter
Added tJ(CKO4) parameter with a MIN parameter value of 0 ps and a MAX parameter value of ±175 ps
Updated Figure 5−2 CLKOUT4 Timing
126
Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 table:
Deleted tc(CKO6) parameter
Added tJ(CKO6) parameter with a MIN parameter value of 0 ps and a MAX parameter value of ±175 ps
Updated Figure 5−3 CLKOUT6 Timing
127
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for EMIFA Module table:
Deleted tc(EKO1) parameter
Added tJ(EKO1) parameter with a MIN parameter value of 0 ps and a MAX parameter value of ±175 ps
Added footnote about cycle-to-cycle jitter measurement
Updated Figure 5−5 AECLKOUT1 Timing for EMIFA Module
128
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for EMIFA Module table:
Deleted tc(EKO2) parameter
Added tJ(EKO2) parameter with a MIN parameter value of 0 ps and a MAX parameter value of ±175 ps
Added footnote about cycle-to-cycle jitter measurement
Updated Figure 5−6 AECLKOUT2 Timing for the EMIFA Module
129−131
ASYNCHRONOUS MEMORY TIMING section:
timing requirements for asynchronous memory cycles for EMIFA module table:
Changed “AECLKOUT1” to “ECLKOUTx” for parameters NO. 6 and 7
switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFA module table:
Changed “AECLKOUT1” to “AECLKOUTx” for parameters NO. 5 and 10
Figure 6−1, Asynchronous Memory Read Timing for EMIFA module:
Changed the “AECLKOUT1” signal name to “AECLKOUTx”
Figure 6−2, Asynchronous Memory Write Timing for EMIFA module:
Changed the “AECLKOUT1” signal name to “AECLKOUTx”
6
SPRS200C
July 2002 − Revised July 2003
Revision History
PAGE(s)
NO.
136−141
ADDS/CHANGES/DELETES
SYNCHRONOUS DRAM TIMING section:
timing requirements for synchronous DRAM cycles for EMIFA module table:
Changed “AECLKOUT1” to “AECLKOUTx” for parameters NO. 6 and 7
switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA module table:
Changed “AECLKOUT1” to “AECLKOUTx” for parameters NO. 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, and 14
Figure 8−1, SDRAM Read Command (CAS Latency 3) for EMIFA through Figure 8−8, SDRAM Self-Refresh Timing for
EMIFA:
Changed the “AECLKOUT1” signal name to “AECLKOUTx”
142
HOLD/HOLDA TIMING section:
Figure 9−1, HOLD/HOLDA Timing:
Updated the two “AECLKOUTx” signal names to include the “EKxHZ” bit value
Added/copied the EKxHZ footnote from the switching characteristics table
143
BUSREQ TIMING section:
switching characteristics over recommended operating conditions for the BUSREQ cycles for EMIFA module table:
Changed “AECLKOUT1” to “AECLKOUTx” for parameter NO. 1
Figure 10−1, BUSREQ Timing for EMIFA:
Changed the “AECLKOUT1” signal name to “AECLKOUTx”
146
EXTERNAL INTERRUPT TIMING section:
timing requirements for external interrupts table:
Split the descriptions of NMI and EXT_INT interrupts pulse low/high
Changed MIN value of “Width of the EXT_INT interrupt pulse low” (parameter #1) from “4P” to “8P”
Changed MIN value of “Width of the EXT_INT interrupt pulse high” (parameter #2) from “4P” to “8P”
172
Ethernet Media Access Controller (EMAC) Timing section:
timing requirements for MRCLK table:
Changed MIN value of parameter #1 from “25” to “40” ns
Changed MIN value of parameter #2 from “11” to “14” ns
Changed MIN value of parameter #3 from “11” to “14” ns
timing requirements for MTCLK table:
Changed MIN value of parameter #1 from “400” to “40” ns
Changed MIN value of parameter #2 from “180” to “14” ns
Changed MIN value of parameter #3 from “180” to “14” ns
Changed MAX value of parameter #4 from “5” to “3” ns
July 2002 − Revised July 2003
SPRS200C
7
Revision History
8
SPRS200C
July 2002 − Revised July 2003
Contents
Contents
Section
Page
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1
Device Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7
Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8
EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9
Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10
Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.1
Peripheral Selection at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.2
Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3
Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.4
Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.5
Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.6
JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.7
Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.8
Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.9
Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.10
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.11
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2.12
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2.13
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.14
Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.15
Multichannel Audio Serial Port (McASP0) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.15.1
McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.16
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.17
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.18
Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.19
VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.20
EMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.21
MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.22
general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.23
Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.23.1
Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.24
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.25
Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
2.26
IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.27
EMIF Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.28
Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
July 2002 − Revised July 2003
SPRS200C
19
20
20
21
23
24
24
26
29
31
50
51
53
9
Contents
Section
3
Electrical
3.1
3.2
3.3
3.4
Page
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended clock and control signal transition behavior . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
122
4
Parameter
4.1
4.2
4.3
5
Input and Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6
Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7
Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8
Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9
HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10
BUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13
Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14
Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
15
Host-Port Interface (HPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16
Peripheral Component Interconnect (PCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
17
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10
SPRS200C
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
121
123
123
123
124
July 2002 − Revised July 2003
Contents
Section
18
Page
Video Port Timing (VP0, VP1, VP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.1
VCLKIN timing (Video Capture Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2
STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3
Video Data and Control Timing (Video Capture Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4
VCLKIN Timing (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5
Video Control Input/Output and Video Display Data Output Timing With Respect
to VPxCLKINx and VPxCLKOUTx (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6
Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx) . . . . . . . . . . . . . . . . . .
167
167
167
168
169
169
171
19
Ethernet Media Access Controller (EMAC) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
20
Management Data Input/Output (MDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
21
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
22
General-Purpose Input/Output (GPIO) Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
23
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
24
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
24.1
Ball Grid Array Mechanical Data Drawing (GDK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
24.2
Ball Grid Array Mechanical Data Drawing (GNZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
July 2002 − Revised July 2003
SPRS200C
11
Figures
List of Figures
Figure
Page
1−1
1−2
1−3
1−4
1−5
1−6
GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C64x CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−10
2−11
2−12
2−13
2−14
2−15
2−16
Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003] . . . . 64
VP1, VP0, McBSP1, McBSP0, and McASP0 Data/Control Pin Muxing . . . . . . . . . . . . . . . . . . . . . . . . . 66
Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses . . . . . . . . 68
Device Status Register (DEVSTAT) Description − 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
JTAG ID Register Description − TMS320DM642 Register Value − 0x0007 902F . . . . . . . . . . . . . . . . . 70
Configuration Example A (3 20-Bit Video Ports + HPI + EMAC + MDIO + I2C0 +
EMIF + 3 Timers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Configuration Example B (2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO +
I2C0 + EMIF) [Possible Video IP Phone Application] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Configuration Example C (2 10-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF)
[Possible Set-Top Box Application] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TMS320DM64x DSP Device Nomenclature (Including the TMS320DM642 Device) . . . . . . . . . . . . . 103
External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . 106
McASP0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I2C0 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4−1
4−2
4−3
4−4
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . 123
Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5−1
5−2
5−3
5−4
5−5
5−6
CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2−8
2−9
12
SPRS200C
20
20
25
28
53
54
July 2002 − Revised July 2003
Figures
Figure
Page
6−1
6−2
Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7−1
7−2
7−3
Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) . . . . . . . . . 133
Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) . . . . . . . . . 134
Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) . . . . . . . . . 135
8−1
8−2
8−3
8−4
8−5
8−6
8−7
8−8
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
9−1
HOLD/HOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10−1
BUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11−1
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12−1
External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13−1
13−2
McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14−1
14−2
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15−1
15−2
15−3
15−4
15−5
15−6
15−7
HPI16 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
HPI16 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
HPI16 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
HPI16 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
HPI32 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
HPI32 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
HPI32 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
July 2002 − Revised July 2003
SPRS200C
13
Figures
Figure
Page
15−8
HPI32 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16−1
PCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16−2
PCI Reset (PRST) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16−3
PCI Input Timing (33-/66-MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16−4
PCI Output Timing (33-/66-MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16−5
PCI Serial EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17−1
McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17−2
FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17−3
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17−4
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 164
17−5
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 165
17−6
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18−1
Video Port Capture VPxCLKINx TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
18−2
STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
18−3
Video Port Capture Data and Control Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
18−4
Video Port Display VPxCLKINx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
18−5
Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
18−6
Video Port Dual-Display Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
19−1
MRCLK Timing (EMAC − Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
19−2
MTCLK Timing (EMAC − Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
19−3
EMAC Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
19−4
EMAC Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
20−1
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
20−2
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
21−1
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
22−1
GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
23−1
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
14
SPRS200C
July 2002 − Revised July 2003
Tables
List of Tables
Table
Page
1−1
1−2
1−3
1−4
1−5
1−6
1−7
1−8
1−9
1−10
1−11
1−12
1−13
1−14
1−15
1−16
1−17
1−18
1−19
1−20
1−21
1−22
1−23
1−24
1−25
1−26
1−27
1−28
1−29
Characteristics of the DM642 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320DM642 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet MAC (EMAC) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAC Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EWRAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCXO Interpolated Control (VIC) Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320DM642 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM642 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1
PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC,
MDIO, and VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HPI vs. EMAC Peripheral Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI,
VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and MAC_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 65
PCFGLOCK Register Selection Bit Descriptions − Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PCFGLOCK Register Selection Bit Descriptions − Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DM642 Device Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
TMS320DM642 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical
Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
2−10
2−11
4−1
23
29
31
31
33
34
35
36
36
39
40
40
40
41
41
42
42
42
42
43
43
43
44
44
46
49
49
50
52
Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
July 2002 − Revised July 2003
SPRS200C
15
Tables
Table
5−1
5−2
5−3
5−4
5−5
5−6
5−7
Page
Timing Requirements for CLKIN for −500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Timing Requirements for CLKIN for −600 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . 126
Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . 126
Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1
for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2
for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6−1
6−2
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . 129
Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7−1
7−2
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . 132
Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8−1
8−2
Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 136
Switching Characteristics Over Recommended Operating Conditions for Synchronous
DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9−1
9−2
Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . 142
Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10−1
Switching Characteristics Over Recommended Operating Conditions for the BUSREQ
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11−1
11−2
Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . 144
12−1
Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13−1
13−2
Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . 147
14−1
14−2
Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15−1
15−2
Timing Requirements for Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16
SPRS200C
July 2002 − Revised July 2003
Tables
Table
Page
16−1
16−2
16−3
16−4
16−5
16−6
Timing Requirements for PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Timing Requirements for PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Timing Requirements for PCI Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Switching Characteristics Over Recommended Operating Conditions for PCI Outputs . . . . . . . . . . . 158
Timing Requirements for Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17−1
17−2
17−3
17−4
17−5
Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . 161
Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . 163
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . 164
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . 165
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . 166
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
17−6
17−7
17−8
17−9
17−10
17−11
18−1
18−2
18−3
18−4
18−5
18−6
18−7
Timing Requirements for Video Capture Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Timing Requirments for STCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Timing Requirements in Video Capture Mode for Video Data and Control Inputs . . . . . . . . . . . . . . . . 168
Timing Requirements for Video Display Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Timing Requirements in Video Display Mode for Video Control Input Shown With Respect
to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUT . . . . . . . 170
Timing Requirements for Dual-Display Sync Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
19−1
19−2
19−3
19−4
Timing Requirements for MRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Timing Requirements for MTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Timing Requirements for EMAC MII Receive 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
20−1
20−2
Timing Requirements for MDIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Switching Characteristics Over Recommended Operating Conditions for MDIO Output . . . . . . . . . . 174
21−1
21−2
Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . 175
July 2002 − Revised July 2003
SPRS200C
17
Tables
Table
Page
22−1
22−2
Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . 176
23−1
23−2
Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . 177
24−1
24−2
Thermal Resistance Characteristics (S-PBGA Package) [GDK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Thermal Resistance Characteristics (S-PBGA Package) [GNZ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
18
SPRS200C
July 2002 − Revised July 2003
Features
Features
D High-Performance Digital Media Processor
D
D
D
D
D
(TMS320DM642)
− 2-, 1.67-ns Instruction Cycle Time
− 500-, 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 4000, 4800 MIPS
− Fully Software-Compatible With C64x
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
− 1024M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
− IEEE 802.3 Compliant
− Media Independent Interface (MII)
− 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
Management Data Input/Output (MDIO)
Three Configurable Video Ports
− Providing a Glueless I/F to Common
Video Decoder and Encoder Devices
− Supports Multiple Resolutions and Video
Standards
VCXO Interpolated Control Port (VIC)
− Supports Audio/Video Synchronization
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
Multichannel Audio Serial Port (McASP)
− Eight Serial Data Pins
− Wide Variety of I2S and Similar Bit
Stream Format
− Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
Inter-Integrated Circuit (I2C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package
(GDK Suffix), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package
(GNZ Suffix), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (-600)
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
July 2002 − Revised July 2003
SPRS200C
19
PRODUCT PREVIEW
1
Features
1.1
GDK BGA Package (Bottom View)
GDK 548-PIN BALL GRID ARRAY (BGA) PACKAGE
( BOTTOM VIEW )
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
PRODUCT PREVIEW
D
C
B
A
1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
Figure 1−1. GDK BGA Package (Bottom View)
1.2
GNZ BGA Package (Bottom View)
GNZ 548-PIN BALL GRID ARRAY (BGA) PACKAGE
( BOTTOM VIEW )
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
Figure 1−2. GNZ BGA Package (Bottom View)
20
SPRS200C
July 2002 − Revised July 2003
Description
1.3
Description
The TMS320C64x DSPs (including the TMS320DM642 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000 DSP platform. The TMS320DM642 (DM642) device is based on the
second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture
(VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media
applications. The C64x is a code-compatible member of the C6000 DSP platform.
The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet
MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one
multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two
multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit
or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin
general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit
glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and
asynchronous memories and peripherals.
The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port
peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video
port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU−BT.656, BT.1120,
SMPTE 125M, 260M, 274M, and 296M).
These three video port peripherals are configurable and can support either video capture and/or video display
modes. Each video port consists of two channels — A and B with a 5120-byte capture/display buffer that is
splittable between the two channels.
For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated
Control (VIC) Port Reference Guide (literature number SPRU629).
The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a
192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins
simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user
data and channel status fields.
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
July 2002 − Revised July 2003
SPRS200C
21
PRODUCT PREVIEW
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM642
device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight
highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—
with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions
to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI
architecture. The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of
2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The
DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals
similar to the other C6000 DSP platform devices.
Description
The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to
up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port,
see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature
number SPRU629).
The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core
processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second
(Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS)
support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data
transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media
Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature
number SPRU628).
PRODUCT PREVIEW
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO
module transparently monitors its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device
without continuously performing costly MDIO accesses. For more details on the MDIO, see the
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628).
The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
Windows is a registered trademark of the Microsoft Corporation.
22
SPRS200C
July 2002 − Revised July 2003
Device Characteristics
1.4
Device Characteristics
Table 1−1 provides an overview of the DM642 DSP. The table shows significant features of the DM642 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−1. Characteristics of the DM642 Processor
Peripherals
Not all peripherals pins are
available at the same time
(For more detail, see the
Device Configuration
section).
EMIFA (64-bit bus width)
(clock source = AECLKIN)
1
EDMA (64 independent channels)
1
McASP0 (uses Peripheral Clock [AUXCLK])
1
I2C0 (uses Peripheral Clock)
1
HPI (32- or 16-bit user selectable)
1 (HPI16 or HPI32)
PCI (32-bit), 66-MHz/33-MHz
[DeviceID Register value 0x9065]
1
McBSPs
(internal clock source = CPU/4 clock frequency)
2
Configurable Video Ports (VP0, VP1, VP2)
3
10/100 Ethernet MAC (EMAC)
1
Management Data Input/Output (MDIO)
1
VCXO Interpolated Control Port (VIC)
1
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
3
General-Purpose Input/Output Port (GP0)
Size (Bytes)
On-Chip Memory
DM642
PRODUCT PREVIEW
HARDWARE FEATURES
16
288K
16K-Byte (16KB) L1 Program (L1P) Cache
Organization
16KB L1 Data (L1D) Cache
256KB Unified Mapped RAM/Cache (L2)
CPU ID + CPU Rev ID
Control Status Register (CSR.[31:16])
JTAG BSDL_ID
JTAGID register (address location: 0x01B3F008)
Frequency
MHz
Cycle Time
Voltage
ns
Core (V)
I/O (V)
PLL Options
BGA Package
0x0C01
0x0007902F
500, 600
2 ns (DM642-500)
[500 MHz CPU, 100 MHz EMIF†, 33 MHz PCI port]
1.67 ns (DM642-600)
[600 MHz CPU, 133 MHz EMIF†, 66 MHz PCI port]
1.2 V (-500)
1.4 V (-600)
3.3 V
CLKIN frequency multiplier
Bypass (x1), x6, x12
23 x 23 mm
548-Pin BGA (GDK)
27 x 27 mm
548-Pin BGA (GNZ)
Process Technology
µm
Product Status‡
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
Device Part Numbers
(For more details on the C6000 DSP part
numbering, see Figure 2−10)
0.13 µm
PP
TMX320DM642GDK, TMX320DM642GNZ
† On this DM64x device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡ PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
July 2002 − Revised July 2003
SPRS200C
23
Device Compatibility
1.4.1
Device Compatibility
The DM642 device is a code-compatible member of the C6000 DSP platform.
The C64x DSP generation of devices has a diverse and powerful set of peripherals.
For more detailed information on the device compatibility and similarities/differences among the DM642 and
other C64x devices, see the TMS320DM642 Technical Overview (literature number SPRU615).
1.4.2
Functional Block Diagram
PRODUCT PREVIEW
Figure 1−3 shows the functional block diagram of the DM642 device.
24
SPRS200C
July 2002 − Revised July 2003
Functional Block Diagram
64
SBSRAM
TMS320DM642
EMIF A
Timer 2
ZBT SRAM
L1P Cache
Direct-Mapped
16K Bytes Total
Timer 1
FIFO
Timer 0
SRAM
VCXO
Interpolated
Control Port
(VIC)
ROM/FLASH
C64x DSP Core
Instruction Fetch
Control
Registers
I/O Devices
Video Port 2
(VP2)
Instruction Dispatch
Advanced Instruction Packet
Video Port 0
(VP0)
OR
Data Path A
A Register File
A31−A16
A15−A0
8/10-bit VP0
AND
McBSP0†
OR
McASP0
Control
Video Port 1
(VP1)
OR
Control
Logic
Instruction Decode
.L1
Enhanced
DMA
Controller
(edma)
.S1
.M1 .D1
Data Path B
Test
B Register File
B31−B16
B15−B0
.D2 .M2 .S2
Advanced
In-Circuit
Emulation
Interrupt
Control
.L2
L2
Cache
Memory
256kBytes
PRODUCT PREVIEW
SDRAM
L1D Cache 2-Way Set-Associative
16K Bytes Total
8/10-bit VP1
AND
McBSP1†
See Note A
OR
PLL
(x1, x6, x12)
McASP0
Data
Power-Down
Logic
PCI-66
OR
HPI32
OR
HPI16
AND
EMAC
Boot Configuration
MDIO
16
GP0
16
I2C0
† McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video Port 1 (VP1)
peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is muxed with the HPI(32/16), EMAC,
and MDIO peripherals. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data
sheet.
Figure 1−3. Functional Block Diagram
July 2002 − Revised July 2003
SPRS200C
25
CPU (DSP Core) Description
1.5
CPU (DSP Core) Description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP
VelociTI architecture. These enhancements include:
PRODUCT PREVIEW
•
•
•
•
•
•
Register file enhancements
Data path extensions
Quad 8-bit and dual 16-bit extensions with data flow enhancements
Additional functional unit hardware
Increased orthogonality of the instruction set
Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the
C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 1−4]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key
factor for video and imaging applications.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
26
SPRS200C
July 2002 − Revised July 2003
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
•
•
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
July 2002 − Revised July 2003
SPRS200C
27
PRODUCT PREVIEW
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
CPU (DSP Core) Description
src1
.L1
src2
dst
long dst
long src
ST1b (Store Data)
ST1a (Store Data)
8
8
32 MSBs
32 LSBs
long src
long dst
dst
.S1 src1
Data Path A
8
8
Register
File A
(A0−A31)
src2
See Note A
See Note A
long dst
dst
.M1 src1
src2
PRODUCT PREVIEW
LD1b (Load Data)
LD1a (Load Data)
32 MSBs
32 LSBs
DA1 (Address)
.D1
dst
src1
src2
2X
1X
src2
.D2
DA2 (Address)
LD2a (Load Data)
LD2b (Load Data)
src1
dst
32 LSBs
32 MSBs
src2
.M2 src1
dst
See Note A
See Note A
long dst
Register
File B
(B0− B31)
src2
Data Path B
.S2
src1
dst
long dst
long src
ST2a (Store Data)
ST2b (Store Data)
8
8
32 MSBs
32 LSBs
long src
long dst
dst
8
8
.L2 src2
src1
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1−4. TMS320C64x CPU (DSP Core) Data Paths
28
SPRS200C
July 2002 − Revised July 2003
Memory Map Summary
1.6
Memory Map Summary
Table 1−2 shows the memory map address ranges of the DM642 device. Internal memory is always located
at address 0 and can be used as both program and data memory. The external memory address ranges in
the DM642 device begin at the hex address location 0x8000 0000 for EMIFA.
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
Internal RAM (L2)
256K
0000 0000 – 0003 FFFF
Reserved
768K
0004 0000 – 000F FFFF
Reserved
23M
0010 0000 – 017F FFFF
External Memory Interface A (EMIFA) Registers
256K
0180 0000 – 0183 FFFF
L2 Registers
256K
0184 0000 – 0187 FFFF
HPI Registers
256K
0188 0000 – 018B FFFF
McBSP 0 Registers
256K
018C 0000 – 018F FFFF
McBSP 1 Registers
256K
0190 0000 – 0193 FFFF
Timer 0 Registers
256K
0194 0000 – 0197 FFFF
Timer 1 Registers
256K
0198 0000 – 019B FFFF
Interrupt Selector Registers
256K
019C 0000 – 019F FFFF
EDMA RAM and EDMA Registers
256K
01A0 0000 – 01A3 FFFF
Reserved
512K
01A4 0000 – 01AB FFFF
Timer 2 Registers
256K
01AC 0000 – 01AF FFFF
MEMORY BLOCK DESCRIPTION
GP0 Registers
256K − 4K
01B0 0000 – 01B3 EFFF
Device Configuration Registers
4K
01B3 F000 – 01B3 FFFF
I2C0 Data and Control Registers
16K
01B4 0000 – 01B4 3FFF
Reserved
32K
01B4 4000 – 01B4 BFFF
McASP0 Control Registers
16K
01B4 C000 – 01B4 FFFF
Reserved
192K
01B5 0000 – 01B7 FFFF
Reserved
256K
01B8 0000 – 01BB FFFF
Emulation
256K
01BC 0000 – 01BF FFFF
PCI Registers
256K
01C0 0000 – 01C3 FFFF
VP0 Control
16K
01C4 0000 – 01C4 3FFF
VP1 Control
16K
01C4 4000 – 01C4 7FFF
VP2 Control
16K
01C4 8000 – 01C4 BFFF
VIC Control
16K
01C4 C000 – 01C4 FFFF
Reserved
192K
01C5 0000 – 01C7 FFFF
EMAC Control
4K
01C8 0000 – 01C8 0FFF
EMAC Wrapper
8K
01C8 1000 – 01C8 2FFF
EWRAP Registers
2K
01C8 3000 – 01C8 37FF
MDIO Control Registers
2K
01C8 3800 – 01C8 3FFF
3.5M
01C8 4000 – 01FF FFFF
Reserved
QDMA Registers
Reserved
McBSP 0 Data
July 2002 − Revised July 2003
52
0200 0000 – 0200 0033
928M – 52
0200 0034 – 2FFF FFFF
64M
3000 0000 – 33FF FFFF
SPRS200C
PRODUCT PREVIEW
Table 1−2. TMS320DM642 Memory Map Summary
29
Memory Map Summary
Table 1−2. TMS320DM642 Memory Map Summary (Continued)
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
McBSP 1 Data
64M
3400 0000 – 37FF FFFF
Reserved
64M
3800 0000 – 3BFF FFFF
MEMORY BLOCK DESCRIPTION
PRODUCT PREVIEW
McASP0 Data
1M
3C00 0000 – 3C0F FFFF
Reserved
64M − 1M
3C10 0000 – 3FFF FFFF
Reserved
832M
4000 0000 – 73FF FFFF
VP0 Channel A Data
32M
7400 0000 – 75FF FFFF
VP0 Channel B Data
32M
7600 0000 – 77FF FFFF
VP1 Channel A Data
32M
7800 0000 – 79FF FFFF
VP1 Channel B Data
32M
7A00 0000 – 7BFF FFFF
VP2 Channel A Data
32M
7C00 0000 – 7DFF FFFF
VP2 Channel B Data
32M
7E00 0000 – 7FFF FFFF
EMIFA CE0
256M
8000 0000 – 8FFF FFFF
EMIFA CE1
256M
9000 0000 – 9FFF FFFF
EMIFA CE2
256M
A000 0000 – AFFF FFFF
EMIFA CE3
256M
B000 0000 – BFFF FFFF
1G
C000 0000 – FFFF FFFF
Reserved
30
SPRS200C
July 2002 − Revised July 2003
Peripheral Register Descriptions
1.7
Peripheral Register Descriptions
Table 1−3 through Table 1−27 identify the peripheral registers for the DM642 device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP
Peripherals Overview Reference Guide (literature number SPRU190).
Table 1−3. EMIFA Registers
HEX ADDRESS RANGE
ACRONYM
0180 0000
GBLCTL
EMIFA global control
REGISTER NAME
0180 0004
CECTL1
EMIFA CE1 space control
0180 0008
CECTL0
EMIFA CE0 space control
0180 000C
−
0180 0010
CECTL2
EMIFA CE2 space control
0180 0014
CECTL3
EMIFA CE3 space control
COMMENTS
0180 0018
SDCTL
EMIFA SDRAM control
0180 001C
SDTIM
EMIFA SDRAM refresh control
0180 0020
SDEXT
EMIFA SDRAM extension
0180 0024 − 0180 0040
−
0180 0044
CESEC1
EMIFA CE1 space secondary control
0180 0048
CESEC0
EMIFA CE0 space secondary control
PRODUCT PREVIEW
Reserved
Reserved
0180 004C
−
0180 0050
CESEC2
Reserved
EMIFA CE2 space secondary control
0180 0054
CESEC3
EMIFA CE3 space secondary control
0180 0058 − 0183 FFFF
–
Reserved
Table 1−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE
ACRONYM
0184 0000
CCFG
0184 2000
L2ALLOC0
L2 allocation register 0
0184 2004
L2ALLOC1
L2 allocation register 1
0184 2008
L2ALLOC2
L2 allocation register 2
0184 200C
L2ALLOC3
L2 allocation register 3
0184 4000
L2FBAR
L2 flush base address register
0184 4004
L2FWC
L2 flush word count register
0184 4010
L2CBAR
L2 clean base address register
0184 4014
L2CWC
L2 clean word count register
0184 4020
L1PFBAR
L1P flush base address register
0184 4024
L1PFWC
L1P flush word count register
0184 4030
L1DFBAR
L1D flush base address register
0184 4034
L1DFWC
L1D flush word count register
−
−
−
REGISTER NAME
Reserved
Reserved
Reserved
0184 5000
L2FLUSH
L2 flush register
0184 5004
L2CLEAN
L2 clean register
July 2002 − Revised July 2003
COMMENTS
Cache configuration register
SPRS200C
31
Peripheral Register Descriptions
Table 1−4. L2 Cache Registers (C64x) (Continued)
PRODUCT PREVIEW
HEX ADDRESS RANGE
32
ACRONYM
REGISTER NAME
−
Reserved
0184 8000 −0184 81FC
MAR0 to
MAR127
Reserved
0184 8200
MAR128
Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
0184 8204
MAR129
Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
0184 8208
MAR130
Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
0184 820C
MAR131
Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
0184 8210
MAR132
Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
0184 8214
MAR133
Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
0184 8218
MAR134
Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
0184 821C
MAR135
Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
0184 8220
MAR136
Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
0184 8224
MAR137
Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
0184 8228
MAR138
Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
0184 822C
MAR139
Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
0184 8230
MAR140
Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
0184 8234
MAR141
Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
0184 8238
MAR142
Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
0184 823C
MAR143
Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
0184 8240
MAR144
Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
0184 8244
MAR145
Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
0184 8248
MAR146
Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
0184 824C
MAR147
Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
0184 8250
MAR148
Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
0184 8254
MAR149
Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
0184 8258
MAR150
Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
0184 825C
MAR151
Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
0184 8260
MAR152
Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
0184 8264
MAR153
Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
0184 8268
MAR154
Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
0184 826C
MAR155
Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
0184 8270
MAR156
Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
0184 8274
MAR157
Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
0184 8278
MAR158
Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
0184 827C
MAR159
Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
0184 8280
MAR160
Controls EMIFA CE2 range A000 0000 − A0FF FFFF
0184 8284
MAR161
Controls EMIFA CE2 range A100 0000 − A1FF FFFF
0184 8288
MAR162
Controls EMIFA CE2 range A200 0000 − A2FF FFFF
0184 828C
MAR163
Controls EMIFA CE2 range A300 0000 − A3FF FFFF
0184 8290
MAR164
Controls EMIFA CE2 range A400 0000 − A4FF FFFF
0184 8294
MAR165
Controls EMIFA CE2 range A500 0000 − A5FF FFFF
0184 8298
MAR166
Controls EMIFA CE2 range A600 0000 − A6FF FFFF
SPRS200C
COMMENTS
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−4. L2 Cache Registers (C64x) (Continued)
ACRONYM
0184 829C
MAR167
Controls EMIFA CE2 range A700 0000 − A7FF FFFF
REGISTER NAME
0184 82A0
MAR168
Controls EMIFA CE2 range A800 0000 − A8FF FFFF
0184 82A4
MAR169
Controls EMIFA CE2 range A900 0000 − A9FF FFFF
0184 82A8
MAR170
Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
0184 82AC
MAR171
Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
0184 82B0
MAR172
Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
0184 82B4
MAR173
Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
0184 82B8
MAR174
Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
0184 82BC
MAR175
Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
0184 82C0
MAR176
Controls EMIFA CE3 range B000 0000 − B0FF FFFF
0184 82C4
MAR177
Controls EMIFA CE3 range B100 0000 − B1FF FFFF
0184 82C8
MAR178
Controls EMIFA CE3 range B200 0000 − B2FF FFFF
0184 82CC
MAR179
Controls EMIFA CE3 range B300 0000 − B3FF FFFF
0184 82D0
MAR180
Controls EMIFA CE3 range B400 0000 − B4FF FFFF
0184 82D4
MAR181
Controls EMIFA CE3 range B500 0000 − B5FF FFFF
0184 82D8
MAR182
Controls EMIFA CE3 range B600 0000 − B6FF FFFF
0184 82DC
MAR183
Controls EMIFA CE3 range B700 0000 − B7FF FFFF
0184 82E0
MAR184
Controls EMIFA CE3 range B800 0000 − B8FF FFFF
0184 82E4
MAR185
Controls EMIFA CE3 range B900 0000 − B9FF FFFF
0184 82E8
MAR186
Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
0184 82EC
MAR187
Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
0184 82F0
MAR188
Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
0184 82F4
MAR189
Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
0184 82F8
MAR190
Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
0184 82FC
MAR191
Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 8300 −0184 83FC
MAR192 to
MAR255
Reserved
0184 8400 −0187 FFFF
−
Reserved
COMMENTS
PRODUCT PREVIEW
HEX ADDRESS RANGE
Table 1−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
ACRONYM
0200 0000
QOPT
QDMA options parameter register
REGISTER NAME
0200 0004
QSRC
QDMA source address register
0200 0008
QCNT
QDMA frame count register
0200 000C
QDST
QDMA destination address register
0200 0010
QIDX
QDMA index register
0200 0014 − 0200 001C
Reserved
0200 0020
QSOPT
QDMA pseudo options register
0200 0024
QSSRC
QDMA psuedo source address register
0200 0028
QSCNT
QDMA psuedo frame count register
0200 002C
QSDST
QDMA destination address register
0200 0030
QSIDX
QDMA psuedo index register
July 2002 − Revised July 2003
SPRS200C
33
Peripheral Register Descriptions
PRODUCT PREVIEW
Table 1−6. EDMA Registers (C64x)
34
HEX ADDRESS RANGE
ACRONYM
01A0 0800 − 01A0 FF98
−
REGISTER NAME
Reserved
01A0 FF9C
EPRH
Event polarity high register
01A0 FFA4
CIPRH
Channel interrupt pending high register
01A0 FFA8
CIERH
Channel interrupt enable high register
01A0 FFAC
CCERH
Channel chain enable high register
01A0 FFB0
ERH
Event high register
01A0 FFB4
EERH
Event enable high register
01A0 FFB8
ECRH
Event clear high register
01A0 FFBC
ESRH
Event set high register
01A0 FFC0
PQAR0
Priority queue allocation register 0
01A0 FFC4
PQAR1
Priority queue allocation register 1
01A0 FFC8
PQAR2
Priority queue allocation register 2
01A0 FFCC
PQAR3
Priority queue allocation register 3
01A0 FFDC
EPRL
Event polarity low register
01A0 FFE0
PQSR
Priority queue status register
01A0 FFE4
CIPRL
Channel interrupt pending low register
01A0 FFE8
CIERL
Channel interrupt enable low register
01A0 FFEC
CCERL
Channel chain enable low register
01A0 FFF0
ERL
Event low register
01A0 FFF4
EERL
Event enable low register
01A0 FFF8
ECRL
Event clear low register
01A0 FFFC
ESRL
Event set low register
01A1 0000 − 01A3 FFFF
–
SPRS200C
Reserved
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−7. EDMA Parameter RAM (C64x)†
ACRONYM
REGISTER NAME
01A0 0000 − 01A0 0017
−
Parameters for Event 0 (6 words)
01A0 0018 − 01A0 002F
−
Parameters for Event 1 (6 words)
01A0 0030 − 01A0 0047
−
Parameters for Event 2 (6 words)
01A0 0048 − 01A0 005F
−
Parameters for Event 3 (6 words)
01A0 0060 − 01A0 0077
−
Parameters for Event 4 (6 words)
01A0 0078 − 01A0 008F
−
Parameters for Event 5 (6 words)
01A0 0090 − 01A0 00A7
−
Parameters for Event 6 (6 words)
01A0 00A8 − 01A0 00BF
−
Parameters for Event 7 (6 words)
01A0 00C0 − 01A0 00D7
−
Parameters for Event 8 (6 words)
01A0 00D8 − 01A0 00EF
−
Parameters for Event 9 (6 words)
01A0 00F0 − 01A0 00107
−
Parameters for Event 10 (6 words)
01A0 0108 − 01A0 011F
−
Parameters for Event 11 (6 words)
01A0 0120 − 01A0 0137
−
Parameters for Event 12 (6 words)
01A0 0138 − 01A0 014F
−
Parameters for Event 13 (6 words)
01A0 0150 − 01A0 0167
−
Parameters for Event 14 (6 words)
01A0 0168 − 01A0 017F
−
Parameters for Event 15 (6 words)
01A0 0150 − 01A0 0167
−
Parameters for Event 16 (6 words)
01A0 0168 − 01A0 017F
−
Parameters for Event 17 (6 words)
...
COMMENTS
Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
PRODUCT PREVIEW
HEX ADDRESS RANGE
...
01A0 05D0 − 01A0 05E7
−
Parameters for Event 62 (6 words)
01A0 05E8 − 01A0 05FF
−
Parameters for Event 63 (6 words)
01A0 0600 − 01A0 0617
−
Reload/link parameters for Event 0 (6 words)
01A0 0618 − 01A0 062F
−
Reload/link parameters for Event 1 (6 words)
...
Reload/Link Parameters for
other Event 0−15
...
01A0 07E0 − 01A0 07F7
−
Reload/link parameters for Event 20 (6 words)
01A0 07F8 − 01A0 07FF
−
Reload/link parameters for Event 21 (6 words)
01A0 0800 − 01A0 0817
−
Reload/link parameters for Event 22 (6 words)
...
...
01A0 13C8 − 01A0 13DF
−
Reload/link parameters for Event 147 (6 words)
01A0 13E0 − 01A0 13F7
−
Reload/link parameters for Event 148 (6 words)
01A0 13F8 − 01A0 13FF
−
Scratch pad area (2 words)
01A0 1400 − 01A3 FFFF
−
Reserved
† The DM64x device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that
can be used to reload/link EDMA transfers.
July 2002 − Revised July 2003
SPRS200C
35
Peripheral Register Descriptions
Table 1−8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0004
MUXL
Interrupt multiplexer low
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
019C 0008
EXTPOL
External interrupt polarity
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 000C − 019F FFFF
−
Reserved
PRODUCT PREVIEW
Table 1−9. Ethernet MAC (EMAC) Control Registers
36
HEX ADDRESS RANGE
ACRONYM
01C8 0000
TXIDVER
01C8 0004
TXCONTROL
01C8 0008
TXTEARDOWN
01C8 000F
−
01C8 0010
RXIDVER
01C8 0014
RXCONTROL
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown Register
Reserved
Receive Identification and Version Register
Receive Control Register
01C8 0018
RXTEARDOWN
01C8 001C − 01C8 00FF
−
01C8 0100
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel
Enable Register
01C8 0104
RXUNICASTSET
Receive Unicast Set Register
01C8 0108
RXUNICASTCLEAR
01C8 010C
RXMAXLEN
01C8 0110
RXBUFFEROFFSET
01C8 0114
RXFILTERLOWTHRESH
Receive Teardown Register
Reserved
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
Receive Filter Low Priority Packets Threshold Register
01C8 0118 − 01C8 011F
−
01C8 0120
RX0FLOWTHRESH
Reserved
Receive Channel 0 Flow Control Threshold Register
01C8 0124
RX1FLOWTHRESH
Receive Channel 1 Flow Control Threshold Register
01C8 0128
RX2FLOWTHRESH
Receive Channel 2 Flow Control Threshold Register
01C8 012C
RX3FLOWTHRESH
Receive Channel 3 Flow Control Threshold Register
01C8 0130
RX4FLOWTHRESH
Receive Channel 4 Flow Control Threshold Register
01C8 0134
RX5FLOWTHRESH
Receive Channel 5 Flow Control Threshold Register
01C8 0138
RX6FLOWTHRESH
Receive Channel 6 Flow Control Threshold Register
01C8 013C
RX7FLOWTHRESH
Receive Channel 7 Flow Control Threshold Register
01C8 0140
RX0FREEBUFFER
Receive Channel 0 Free Buffer Count Register
01C8 0144
RX1FREEBUFFER
Receive Channel 1 Free Buffer Count Register
01C8 0148
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
01C8 014C
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
01C8 0150
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
01C8 0154
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
01C8 0158
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
01C8 015C
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
01C8 0160
MACCONTROL
MAC Control Register
01C8 0164
MACSTATUS
MAC Status Register
01C8 0168 − 01C8 016C
−
SPRS200C
Reserved
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−9. Ethernet MAC (EMAC) Control Registers (Continued)
ACRONYM
01C8 0170
TXINTSTATRAW
01C8 0174
TXINTSTATMASKED
01C8 0178
TXINTMASKSET
01C8 017C
TXINTMASKCLEAR
01C8 0180
MACINVECTOR
REGISTER NAME
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
01C8 0184 − 01C8 018F
−
01C8 0190
RXINTSTATRAW
Reserved
01C8 0194
RXINTSTATMASKED
01C8 0198
RXINTMASKSET
01C8 019C
RXINTMASKCLEAR
01C8 01A0
MACINTSTATRAW
01C8 01A4
MACINTSTATMASKED
01C8 01A8
MACINTMASKSET
01C8 01AC
MACINTMASKCLEAR
01C8 01B0
MACADDRL0
MAC Address Channel 0 Lower Byte Register
01C8 01B4
MACADDRL1
MAC Address Channel 1 Lower Byte Register
01C8 01B8
MACADDRL2
MAC Address Channel 2 Lower Byte Register
01C8 01BC
MACADDRL3
MAC Address Channel 3 Lower Byte Register
01C8 01C0
MACADDRL4
MAC Address Channel 4 Lower Byte Register
01C8 01C4
MACADDRL5
MAC Address Channel 5 Lower Byte Register
01C8 01C8
MACADDRL6
MAC Address Channel 6 Lower Byte Register
01C8 01CC
MACADDRL7
MAC Address Channel 7 Lower Byte Register
01C8 01D0
MACADDRM
MAC Address Middle Byte Register
01C8 01D4
MACADDRH
MAC Address High Bytes Register
01C8 01D8
MACHASH1
MAC Address Hash 1 Register
01C8 01DC
MACHASH2
MAC Address Hash 2 Register
01C8 01E0
BOFFTEST
Backoff Test Register
01C8 01E4
TPACETEST
Transmit Pacing Test Register
01C8 01E8
RXPAUSE
Receive Pause Timer Register
01C8 01EC
TXPAUSE
Transmit Pause Timer Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
01C8 01F0 − 01C8 01FF
−
01C8 0200 − 01C8 05FF
(see Table 1−10)
01C8 0600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer
Register
01C8 0604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer
Register
01C8 0608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer
Register
01C8 060C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer
Register
01C8 0610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer
Register
01C8 0614
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer
Register
July 2002 − Revised July 2003
PRODUCT PREVIEW
HEX ADDRESS RANGE
Reserved
EMAC Statistics Registers
SPRS200C
37
Peripheral Register Descriptions
PRODUCT PREVIEW
Table 1−9. Ethernet MAC (EMAC) Control Registers (Continued)
38
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
01C8 0618
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer
Register
01C8 061C
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer
Register
01C8 0620
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer
Register
01C8 0624
RX1HDP
Receive Channel 1 DMA Head Descriptor Pointer
Register
01C8 0628
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer
Register
01C8 062C
RX3HDP
Receive Channel 3 DMA Head Descriptor Pointer
Register
01C8 0630
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer
Register
01C8 0634
RX5HDP
Receive Channel 5 DMA Head Descriptor Pointer
Register
01C8 0638
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer
Register
01C8 063C
RX7HDP
Receive Channel 7 DMA Head Descriptor Pointer
Register
01C8 0640
TX0INTACK
Transmit Channel 0 Interrupt Acknowledge Register
01C8 0644
TX1INTACK
Transmit Channel 1 Interrupt Acknowledge Register
01C8 0648
TX2INTACK
Transmit Channel 2 Interrupt Acknowledge Register
01C8 064C
TX3INTACK
Transmit Channel 3 Interrupt Acknowledge Register
01C8 0650
TX4INTACK
Transmit Channel 4 Interrupt Acknowledge Register
01C8 0654
TX5INTACK
Transmit Channel 5 Interrupt Acknowledge Register
01C8 0658
TX6INTACK
Transmit Channel 6 Interrupt Acknowledge Register
01C8 065C
TX7INTACK
Transmit Channel 7 Interrupt Acknowledge Register
01C8 0660
RX0INTACK
Receive Channel 0 Interrupt Acknowledge Register
01C8 0664
RX1INTACK
Receive Channel 1 Interrupt Acknowledge Register
01C8 0668
RX2INTACK
Receive Channel 2 Interrupt Acknowledge Register
01C8 066C
RX3INTACK
Receive Channel 3 Interrupt Acknowledge Register
01C8 0670
RX4INTACK
Receive Channel 4 Interrupt Acknowledge Register
01C8 0674
RX5INTACK
Receive Channel 5 Interrupt Acknowledge Register
01C8 0678
RX6INTACK
Receive Channel 6 Interrupt Acknowledge Register
01C8 067C
RX7INTACK
Receive Channel 7 Interrupt Acknowledge Register
01C8 0680 − 01C8 0FFF
−
SPRS200C
Reserved
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−10. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
01C8 0200
RXGOODFRAMES
Good Receive Frames Register
01C8 0204
RXBCASTFRAMES
Broadcast Receive Frames Register
01C8 0208
RXMCASTFRAMES
Multicast Receive Frames Register
01C8 020C
RXPAUSEFRAMES
Pause Receive Frames Register
RXCRCERRORS
01C8 0214
RXALIGNCODEERRORS
Receive CRC Errors Register
Receive Alignment/Code Errors Register
01C8 0218
RXOVERSIZED
01C8 021C
RXJABBER
Receive Oversized Frames Register
01C8 0220
RXUNDERSIZED
Receive Undersized Frames Register
01C8 0224
RXFRAGMENTS
Receive Frame Fragments Register
01C8 0228
RXFILTERED
01C8 022C
RXQOSFILTERED
Receive Jabber Frames Register
Filtered Receive Frames Register
Receive QOS Filtered Frames Register
01C8 0230
RXOCTETS
Receive Octet Frames Register
01C8 0234
TXGOODFRAMES
Good Transmit Frames Register
01C8 0238
TXBCASTFRAMES
Broadcast Transmit Frames Register
01C8 023C
TXMCASTFRAMES
Multicast Transmit Frames Register
01C8 0240
TXPAUSEFRAMES
Pause Transmit Frames Register
01C8 0244
TXDEFERRED
Deferred Transmit Frames Register
01C8 0248
TXCOLLISION
Collision Register
01C8 024C
TXSINGLECOLL
01C8 0250
TXMULTICOLL
01C8 0254
TXEXCESSIVECOLL
01C8 0258
TXLATECOLL
01C8 025C
TXUNDERRUN
01C8 0260
TXCARRIERSLOSS
01C8 0264
TXOCTETS
01C8 0268
FRAME64
PRODUCT PREVIEW
01C8 0210
REGISTER NAME
Single Collision Transmit Frames Register
Multiple Collision Transmit Frames Register
Excessive Collisions Register
Late Collisions Register
Transmit Underrun Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
01C8 026C
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
01C8 0270
FRAME128T255
Transmit and Receive 128 to 255 Octet Frames Register
01C8 0274
FRAME256T511
Transmit and Receive 256 to 511 Octet Frames Register
01C8 0278
FRAME512T1023
Transmit and Receive 512 to 1023 Octet Frames Register
01C8 027C
FRAME1024TUP
Transmit and Receive 1024 or Above Octet Frames
Register
01C8 0280
NETOCTETS
Network Octet Frames Register
01C8 0284
RXSOFOVERRUNS
Receive Start of Frame Overruns Register
01C8 0288
RXMOFOVERRUNS
Receive Middle of Frame Overruns Register
01C8 028C
RXDMAOVERRUNS
Receive DMA Overruns Register
01C8 0290 − 01C8 05FF
−
July 2002 − Revised July 2003
Reserved
SPRS200C
39
Peripheral Register Descriptions
Table 1−11. EMAC Wrapper
HEX ADDRESS RANGE
ACRONYM
01C8 1000 − 01C8 1FFF
REGISTER NAME
EMAC Control Module Descriptor Memory
01C8 2000 − 01C8 2FFF
−
Reserved
Table 1−12. EWRAP Registers
HEX ADDRESS RANGE
ACRONYM
01C8 3000
EWTRCTRL
01C8 3004
EWCTL
01C8 3008
EWINTTCNT
01C8 300C − 01C8 37FF
−
REGISTER NAME
TR control
Interrupt control register
Interrupt timer count
Reserved
Table 1−13. Device Configuration Registers
PRODUCT PREVIEW
HEX ADDRESS RANGE
40
ACRONYM
REGISTER NAME
COMMENTS
01B3 F000
PERCFG
Peripheral Configuration Register
Enables or disables specific
peripherals. This register is also
used for power-down of disabled
peripherals.
01B3 F004
DEVSTAT
Device Status Register
Read-only. Provides status of
the User’s device configuration
on reset.
01B3 F008
JTAGID
JTAG Identification Register
Read-only. Provides
JTAG ID of the device.
01B3 F00C − 01B3 F014
−
01B3 F018
PCFGLOCK
01B3 F01C − 01B3 FFFF
−
SPRS200C
32-bit
Reserved
Peripheral Configuration Lock Register
Reserved
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−14. McBSP 0 Registers
ACRONYM
REGISTER NAME
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
DRR0
McBSP0 data receive register via Peripheral Bus
018C 0004
DXR0
McBSP0 data transmit register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
DXR0
McBSP0 data transmit register via Peripheral Bus
018C 0008
SPCR0
018C 000C
RCR0
McBSP0 receive control register
018C 0010
XCR0
McBSP0 transmit control register
018C 0014
SRGR0
018C 0018
MCR0
018C 001C
RCERE00
McBSP0 enhanced receive channel enable register 0
018C 0020
XCERE00
McBSP0 enhanced transmit channel enable register 0
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
McBSP0 serial port control register
McBSP0 sample rate generator register
McBSP0 multichannel control register
018C 0024
PCR0
018C 0028
RCERE10
McBSP0 pin control register
McBSP0 enhanced receive channel enable register 1
018C 002C
XCERE10
McBSP0 enhanced transmit channel enable register 1
018C 0030
RCERE20
McBSP0 enhanced receive channel enable register 2
018C 0034
XCERE20
McBSP0 enhanced transmit channel enable register 2
018C 0038
RCERE30
McBSP0 enhanced receive channel enable register 3
018C 003C
XCERE30
McBSP0 enhanced transmit channel enable register 3
018C 0040 − 018F FFFF
–
Reserved
Table 1−15. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0190 0000
DRR1
McBSP1 data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF
DRR1
McBSP1 data receive register via peripheral bus
0190 0004
DXR1
McBSP1 data transmit register via configuration bus
0x3400 0000 − 0x37FF FFFF
DXR1
McBSP1 data transmit register via peripheral bus
0190 0008
SPCR1
0190 000C
RCR1
McBSP1 receive control register
0190 0010
XCR1
McBSP1 transmit control register
0190 0014
SRGR1
The CPU and EDMA controller
can only read this register; they
cannot write to it.
McBSP1 serial port control register
McBSP1 sample rate generator register
0190 0018
MCR1
0190 001C
RCERE01
McBSP1 enhanced receive channel enable register 0
0190 0020
XCERE01
McBSP1 enhanced transmit channel enable register 0
0190 0024
PCR1
0190 0028
RCERE11
McBSP1 enhanced receive channel enable register 1
0190 002C
XCERE11
McBSP1 enhanced transmit channel enable register 1
0190 0030
RCERE21
McBSP1 enhanced receive channel enable register 2
0190 0034
XCERE21
McBSP1 enhanced transmit channel enable register 2
McBSP1 multichannel control register
McBSP1 pin control register
0190 0038
RCERE31
McBSP1 enhanced receive channel enable register 3
0190 003C
XCERE31
McBSP1 enhanced transmit channel enable register 3
0190 0040 − 0193 FFFF
–
July 2002 − Revised July 2003
COMMENTS
Reserved
SPRS200C
41
PRODUCT PREVIEW
HEX ADDRESS RANGE
Peripheral Register Descriptions
Table 1−16. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0194 0000
CTL0
Timer 0 control register
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0004
PRD0
Timer 0 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0008
CNT0
Timer 0 counter register
Contains the current value of the incrementing counter.
0194 000C − 0197 FFFF
−
Reserved
Table 1−17. Timer 1 Registers
PRODUCT PREVIEW
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0198 0000
CTL1
Timer 1 control register
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0004
PRD1
Timer 1 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0008
CNT1
Timer 1 counter register
Contains the current value of the incrementing counter.
0198 000C − 019B FFFF
−
Reserved
Table 1−18. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
01AC 0000
CTL2
Timer 2 control register
Determines the operating mode of the timer, monitors the
timer status.
01AC 0004
PRD2
Timer 2 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
01AC 0008
CNT2
Timer 2 counter register
Contains the current value of the incrementing counter.
01AC 000C − 01AF FFFF
−
Reserved
Table 1−19. HPI Registers
HEX ADDRESS RANGE
ACRONYM
−
HPID
HPI data register
REGISTER NAME
Host read/write access only
COMMENTS
0188 0000
HPIC
HPI control register
HPIC has both Host/CPU read/write access
0188 0004
HPIA
(HPIAW)†
HPI address register
(Write)
0188 0008
HPIA
(HPIAR)†
HPI address register
(Read)
HPIA has both Host/CPU read/write access
0188 0001 − 018B FFFF
−
Reserved
† Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
42
SPRS200C
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−20. GP0 Registers
HEX ADDRESS RANGE
ACRONYM
01B0 0000
GPEN
GP0 enable register
REGISTER NAME
01B0 0004
GPDIR
GP0 direction register
01B0 0008
GPVAL
GP0 value register
01B0 000C
−
Reserved
01B0 0010
GPDH
GP0 delta high register
01B0 0014
GPHM
GP0 high mask register
01B0 0018
GPDL
GP0 delta low register
01B0 001C
GPLM
GP0 low mask register
01B0 0020
GPGC
GP0 global control register
01B0 0024
GPPOL
GP0 interrupt polarity register
01B0 0028 − 01B3 EFFF
−
Reserved
Table 1−21. PCI Peripheral Registers
ACRONYM
01C0 0000
RSTSRC
01C0 0004
–
REGISTER NAME
PRODUCT PREVIEW
HEX ADDRESS RANGE
DSP Reset source/status register
Reserved
01C0 0008
PCIIS
PCI interrupt source register
01C0 000C
PCIIEN
PCI interrupt enable register
01C0 0010
DSPMA
DSP master address register
01C0 0014
PCIMA
PCI master address register
01C0 0018
PCIMC
PCI master control register
01C0 001C
CDSPA
Current DSP address register
01C0 0020
CPCIA
Current PCI address register
01C0 0024
CCNT
Current byte count register
01C0 0028
−
Reserved
01C0 002C − 01C1 FFEF
–
Reserved
0x01C1 FFF0
HSR
0x01C1 FFF4
HDCR
Host status register
Host-to-DSP control register
DSP page register
0x01C1 FFF8
DSPP
0x01C1 FFFC
−
01C2 0000
EEADD
EEPROM address register
01C2 0004
EEDAT
EEPROM data register
01C2 0008
EECTL
EEPROM control register
01C2 000C − 01C2 FFFF
–
01C3 0000
PCI_TRCNTL
01C3 0004 − 01C3 FFFF
–
Reserved
Reserved
PCI transfer request control register
Reserved
Table 1−22. VCXO Interpolated Control (VIC) Port Registers
HEX ADDRESS RANGE
ACRONYM
01C4 C000
VICCTL
01C4 C004
VICIN
VIC input register
01C4 C008
VPDIV
VIC clock divider register
01C4 C00C − 01C4 FFFF
−
July 2002 − Revised July 2003
REGISTER NAME
VIC control register
Reserved
SPRS200C
43
Peripheral Register Descriptions
PRODUCT PREVIEW
Table 1−23. MDIO Registers
HEX ADDRESS RANGE
ACRONYM
01C8 3800
VERSION
MDIO Version Register
01C8 3804
CONTROL
MDIO Control Register
01C8 3808
ALIVE
01C8 380C
LINK
01C8 3810
LINKINTRAW
01C8 3814
LINKINTMASKED
REGISTER NAME
MDIO PHY Alive Indication Register
MDIO PHY Link Status Register
MDIO Link Status Change Interrupt Register
MDIO Link Status Change Interrupt (Masked) Register
01C8 3818
USERINTRAW
01C8 381C
USERINTMASKED
MDIO User Command Complete Interrupt Register
MDIO User Command Complete Interrupt (Masked) Register
01C8 3820
USERINTMASKSET
MDIO User Command Complete Interrupt Mask Set Register
01C8 3824
USERINTMASKCLEAR
01C8 3828
USERACCESS0
MDIO User Access Register 0
01C8 382C
USERACCESS1
MDIO User Access Register 1
01C8 3830
USERPHYSEL0
MDIO User PHY Select Register 0
01C8 3834
USERPHYSEL1
MDIO User PHY Select Register 1
01C8 3838 − 01C8 3FFF
−
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
Table 1−24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers
HEX ADDRESS RANGE
44
ACRONYM
DESCRIPTION
VP0
VP1
VP2
01C4 0000
01C4 4000
01C4 8000
VP_PIDx
Video Port Peripheral Identification Register
01C4 0004
01C4 4004
01C4 8004
VP_PCRx
Video Port Peripheral Control Register
01C4 0008
01C4 4008
01C4 8008
−
Reserved
01C4 000C
01C4 400C
01C4 800C
−
Reserved
01C4 0020
01C4 4020
01C4 8020
VP_PFUNCx
Video Port Pin Function Register
01C4 0024
01C4 4024
01C4 8024
VP_PDIRx
Video Port Pin Direction Register
01C4 0028
01C4 4028
01C4 8028
VP_PDINx
Video Port Pin Data Input Register
01C4 002C
01C4 402C
01C4 802C
VP_PDOUTx
Video Port Pin Data Output Register
01C4 0030
01C4 4030
01C4 8030
VP_PDSETx
Video Port Pin Data Set Register
01C4 0034
01C4 4034
01C4 8034
VP_PDCLRx
Video Port Pin Data Clear Register
01C4 0038
01C4 4038
01C4 8038
VP_PIENx
Video Port Pin Interrupt Enable Register
01C4 003C
01C4 403C
01C4 803C
VP_PIPOx
Video Port Pin Interrupt Polarity Register
01C4 0040
01C4 4040
01C4 8040
VP_PISTATx
Video Port Pin Interrupt Status Register
01C4 0044
01C4 4044
01C4 8044
VP_PICLRx
Video Port Pin Interrupt Clear Register
01C4 00C0
01C4 40C0
01C4 80C0
VP_CTLx
Video Port Control Register
01C4 00C4
01C4 40C4
01C4 80C4
VP_STATx
Video Port Status Register
01C4 00C8
01C4 40C8
01C4 80C8
VP_IEx
Video Port Interrupt Enable Register
01C4 00CC
01C4 40CC
01C4 80CC
VP_ISx
Video Port interrupt Status Register
01C4 0100
01C4 4100
01C4 8100
VC_STATx
Video Capture Channel A Status Register
01C4 0104
01C4 4104
01C4 8104
VC_CTLx
Video Capture Channel A Control Register
01C4 0108
01C4 4108
01C4 8108
VC_ASTRTx
Video Capture Channel A Field 1 Start Register
01C4 010C
01C4 410C
01C4 810C
VC_ASTOPx
Video Capture Channel A Field 2 Stop Register
01C4 0110
01C4 4110
01C4 8110
VC_ASTRTx
Video Capture Channel A Field 2 Start Register
01C4 0114
01C4 4114
01C4 8114
VC_ASTOPx
Video Capture Channel A Field 1 Stop Register
SPRS200C
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (Continued)
HEX ADDRESS RANGE
VP1
VP2
ACRONYM
DESCRIPTION
01C4 0118
01C4 4118
01C4 8118
VC_AVINTx
01C4 011C
01C4 411C
01C4 811C
VC_ATHRLDx
Video Capture Channel A Vertical Interrupt Register
Video Capture Channel A Threshold Register
01C4 0120
01C4 4120
01C4 8120
VC_AEVTCTx
Video Capture Channel A Event Count Register
01C4 0140
01C4 4140
01C4 8140
VC_BSTATx
Video Capture Channel B Status Register
01C4 0144
01C4 4144
01C4 8144
VC_BCTLx
Video Capture Channel B Control Register
01C4 0148
01C4 4148
01C4 8148
VC_BSTRTx
Video Capture Channel B Field 1 Start Register
01C4 014C
01C4 414C
01C4 814C
VC_BSTOPx
Video Capture Channel B Field 1 Stop Register
01C4 0150
01C4 4150
01C4 8150
VC_BSTRTx
Video Capture Channel B Field 2 Start Register
01C4 0154
01C4 4154
01C4 8154
VC_BSTOPx
Video Capture Channel B Field 2 Stop Register
Video Capture Channel B Vertical Interrupt Register
01C4 0158
01C4 4158
01C4 8158
VC_BVINTx
01C4 015C
01C4 415C
01C4 815C
VC_BTHRLDx
Video Capture Channel B Threshold Register
01C4 0160
01C4 4160
01C4 8160
VC_BEVTCTx
Video Capture Channel B Event Count Register
01C4 0180
01C4 4180
01C4 8180
TSI_CTLx
01C4 0184
01C4 4184
01C4 8184
TSI_CLKINITLx
TCI Clock Initialization LSB Register
TCI Capture Control Register
01C4 0188
01C4 4188
01C4 8188
TSI_CLKINITMx
TCI Clock Initialization MSB Register
01C4 018C
01C4 418C
01C4 818C
TSI_STCLKLx
TCI System Time Clock LSB Register
01C4 0190
01C4 4190
01C4 8190
TSI_STCLKMx
TCI System Time Clock MSB Register
01C4 0194
01C4 4194
01C4 8194
TSI_STCMPLx
TCI System Time Clock Compare LSB Register
01C4 0198
01C4 4198
01C4 8198
TSI_STCMPMx
TCI System Time Clock Compare MSB Register
01C4 019C
01C4 419C
01C4 819C
TSI_STMSKLx
TCI System Time Clock Compare Mask LSB Register
01C4 01A0
01C4 41A0
01C4 81A0
TSI_STMSKMx
TCI System Time Clock Compare Mask MSB Register
01C4 01A4
01C4 41A4
01C4 81A4
TSI_TICKSx
01C4 0200
01C4 4200
01C4 8200
VD_STATx
Video Display Status Register
01C4 0204
01C4 4204
01C4 8204
VD_CTLx
Video Display Control Register
01C4 0208
01C4 4208
01C4 8208
VD_FRMSZx
Video Display Frame Size Register
01C4 020C
01C4 420C
01C4 820C
VD_HBLNKx
Video Display Horizontal Blanking Register
01C4 0210
01C4 4210
01C4 8210
VD_VBLKS1x
Video Display Field 1 Vertical Blanking Start Register
01C4 0214
01C4 4214
01C4 8214
VD_VBLKE1x
Video Display Field 1 Vertical Blanking End Register
TCI System Time Clock Ticks Interrupt Register
01C4 0218
01C4 4218
01C4 8218
VD_VBLKS2x
Video Display Field 2 Vertical Blanking Start Register
01C4 021C
01C4 421C
01C4 821C
VD_VBLKE2x
Video Display Field 2 Vertical Blanking End Register
01C4 0220
01C4 4220
01C4 8220
VD_IMGOFF1x
01C4 0224
01C4 4224
01C4 8224
VD_IMGSZ1x
Video Display Field 1 Image Offset Register
Video Display Field 1 Image Size Register
01C4 0228
01C4 4228
01C4 8228
VD_IMGOFF2x
01C4 022C
01C4 422C
01C4 822C
VD_IMGSZ2x
01C4 0230
01C4 4230
01C4 8230
VD_FLDT1x
Video Display Field 1 Timing Register
01C4 0234
01C4 4234
01C4 8234
VD_FLDT2x
Video Display Field 2 Timing Register
01C4 0238
01C4 4238
01C4 8238
VD_THRLDx
Video Display Threshold Register
01C4 023C
01C4 423C
01C4 823C
VD_HSYNCx
Video Display Horizontal Synchronization Register
01C4 0240
01C4 4240
01C4 8240
VD_VSYNS1x
Video Display Field 1 Vertical Synchronization Start Register
01C4 0244
01C4 4244
01C4 8244
VD_VSYNE1x
Video Display Field 1 Vertical Synchronization End Register
01C4 0248
01C4 4248
01C4 8248
VD_VSYNS2x
Video Display Field 2 Vertical Synchronization Start Register
July 2002 − Revised July 2003
PRODUCT PREVIEW
VP0
Video Display Field 2 Image Offset Register
Video Display Field 2 Image Size Register
SPRS200C
45
Peripheral Register Descriptions
Table 1−24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (Continued)
PRODUCT PREVIEW
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP0
VP1
VP2
01C4 024C
01C4 424C
01C4 824C
VD_VSYNE2x
Video Display Field 2 Vertical Synchronization End Register
01C4 0250
01C4 4250
01C4 8250
VD_RELOADx
Video Display Counter Reload Register
01C4 0254
01C4 4254
01C4 8254
VD_DISPEVTx
Video Display Display Event Register
01C4 0258
01C4 4258
01C4 8258
VD_CLIPx
01C4 025C
01C4 425C
01C4 825C
VD_DEFVALx
01C4 0260
01C4 4260
01C4 8260
VD_VINTx
Video Display Vertical Interrupt Register
01C4 0264
01C4 4264
01C4 8264
VD_FBITx
Video Display Field Bit Register
01C4 0268
01C4 4268
01C4 8268
VD_VBIT1x
Video Display Field 1Vertical Blanking Bit Register
01C4 026C
01C4 426C
01C4 826C
VD_VBIT2x
Video Display Field 2Vertical Blanking Bit Register
7400 000
7800 0000
7C00 0000
Y_RSCA
7400 0008
7800 0008
7C00 0008
CB_SRCA
CB FIFO Source Register A
7400 0010
7800 0010
7C00 0010
CR_SRCA
CR FIFO Source Register A
7400 0020
7800 0020
7C00 0020
Y_DSTA
Y FIFO Designation Register A
7400 0028
7800 0028
7C00 0028
CB_DST
CB FIFO Designation Register
7400 0030
7800 0030
7C00 0030
CR_DST
CR FIFO Designation Register
7600 0000
7A00 0000
7E00 0000
Y_SRCB
Y FIFO Source Register B
7600 0008
7A00 0008
7E00 0008
CB_SRCB
CB FIFO Source Register b
7600 0010
7A00 0010
7E00 0010
CR_SRCB
CR FIFO Source Register B
7600 0020
7A00 0020
7E00 0020
Y_DSTB
Video Display Clipping Register
Video Display Default Display Value Register
Y FIFO Source Register A
Y FIFO Destination Register B
Table 1−25. McASP0 Control Registers
HEX ADDRESS RANGE
ACRONYM
01B4 C000
PID
REGISTER NAME
01B4 C004
PWRDEMU
01B4 C008
−
Reserved
01B4 C00C
−
Reserved
01B4 C010
PFUNC
Pin function register
01B4 C014
PDIR
Pin direction register
01B4 C018
PDOUT
Pin data out register
01B4 C01C
PDIN/PDSET
Peripheral Identification register [Register value: 0x0010 0101]
Power down and emulation management register
Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
01B4 C020
PDCLR
01B4 C024 − 01B4 C040
−
01B4 C044
GBLCTL
Global control register
01B4 C048
AMUTE
Mute control register
01B4 C04C
DLBCTL
Digital Loop-back control register
01B4 C050
DITCTL
DIT mode control register
01B4 C054 − 01B4 C05C
−
01B4 C060
RGBLCTL
46
SPRS200C
Pin data clear register
Reserved
Reserved
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−25. McASP0 Control Registers (Continued)
ACRONYM
01B4 C064
RMASK
01B4 C068
RFMT
01B4 C06C
AFSRCTL
01B4 C070
ACLKRCTL
01B4 C074
AHCLKRCTL
01B4 C078
RTDM
01B4 C07C
RINTCTL
REGISTER NAME
Receiver format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
High-frequency receive clock control register
Receive TDM slot 0−31 register
Receiver interrupt control register
01B4 C080
RSTAT
Status register − Receiver
01B4 C084
RSLOT
Current receive TDM slot register
01B4 C088
RCLKCHK
01B4 C08C − 01B4 C09C
−
01B4 C0A0
XGBLCTL
01B4 C0A4
XMASK
Receiver clock check control register
Reserved
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
Transmit format unit bit mask register
01B4 C0A8
XFMT
01B4 C0AC
AFSXCTL
01B4 C0B0
ACLKXCTL
01B4 C0B4
AHCLKXCTL
01B4 C0B8
XTDM
Transmit TDM slot 0−31 register
01B4 C0BC
XINTCTL
Transmit interrupt control register
01B4 C0C0
XSTAT
Status register − Transmitter
01B4 C0C4
XSLOT
Current transmit TDM slot
01B4 C0C8
XCLKCHK
Transmit clock check control register
Transmit bit stream format register
Transmitter DMA control register
Transmit frame sync control register
Transmit clock control register
High-frequency Transmit clock control register
01B4 C0CC
XEVTCTL
01B4 C0D0 − 01B4 C0FC
−
01B4 C100
DITCSRA0
Left (even TDM slot) channel status register file
01B4 C104
DITCSRA1
Left (even TDM slot) channel status register file
Reserved
01B4 C108
DITCSRA2
Left (even TDM slot) channel status register file
01B4 C10C
DITCSRA3
Left (even TDM slot) channel status register file
01B4 C110
DITCSRA4
Left (even TDM slot) channel status register file
01B4 C114
DITCSRA5
Left (even TDM slot) channel status register file
01B4 C118
DITCSRB0
Right (odd TDM slot) channel status register file
01B4 C11C
DITCSRB1
Right (odd TDM slot) channel status register file
01B4 C120
DITCSRB2
Right (odd TDM slot) channel status register file
01B4 C124
DITCSRB3
Right (odd TDM slot) channel status register file
01B4 C128
DITCSRB4
Right (odd TDM slot) channel status register file
01B4 C12C
DITCSRB5
Right (odd TDM slot) channel status register file
01B4 C130
DITUDRA0
Left (even TDM slot) user data register file
01B4 C134
DITUDRA1
Left (even TDM slot) user data register file
01B4 C138
DITUDRA2
Left (even TDM slot) user data register file
01B4 C13C
DITUDRA3
Left (even TDM slot) user data register file
01B4 C140
DITUDRA4
Left (even TDM slot) user data register file
July 2002 − Revised July 2003
PRODUCT PREVIEW
HEX ADDRESS RANGE
SPRS200C
47
Peripheral Register Descriptions
PRODUCT PREVIEW
Table 1−25. McASP0 Control Registers (Continued)
HEX ADDRESS RANGE
ACRONYM
01B4 C144
DITUDRA5
Left (even TDM slot) user data register file
REGISTER NAME
01B4 C148
DITUDRB0
Right (odd TDM slot) user data register file
01B4 C14C
DITUDRB1
Right (odd TDM slot) user data register file
01B4 C150
DITUDRB2
Right (odd TDM slot) user data register file
01B4 C154
DITUDRB3
Right (odd TDM slot) user data register file
01B4 C158
DITUDRB4
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
01B4 C15C
DITUDRB5
01B4 C160 − 01B4 C17C
−
01B4 C180
SRCTL0
Serializer 0 control register
01B4 C184
SRCTL1
Serializer 1 control register
01B4 C188
SRCTL2
Serializer 2 control register
01B4 C18C
SRCTL3
Serializer 3 control register
01B4 C190
SRCTL4
Serializer 4 control register
01B4 C194
SRCTL5
Serializer 5 control register
01B4 C198
SRCTL6
Serializer 6 control register
01B4 C19C
SRCTL7
Serializer 7 control register
Reserved
01B4 C1A0 − 01B4 C1FC
−
01B4 C200
XBUF0
Reserved
Transmit Buffer for Serializer 0
01B4 C204
XBUF1
Transmit Buffer for Serializer 1
01B4 C208
XBUF2
Transmit Buffer for Serializer 2
01B4 C20C
XBUF3
Transmit Buffer for Serializer 3
01B4 C210
XBUF4
Transmit Buffer for Serializer 4
01B4 C214
XBUF5
Transmit Buffer for Serializer 5
01B4 C218
XBUF6
Transmit Buffer for Serializer 6
Transmit Buffer for Serializer 7
01B4 C21C
XBUF7
01B4 C220 − 01B4 C27C
−
01B4 C280
RBUF0
Receive Buffer for Serializer 0
01B4 C284
RBUF1
Receive Buffer for Serializer 1
01B4 C288
RBUF2
Receive Buffer for Serializer 2
01B4 C28C
RBUF3
Receive Buffer for Serializer 3
01B4 C290
RBUF4
Receive Buffer for Serializer 4
01B4 C294
RBUF5
Receive Buffer for Serializer 5
Reserved
01B4 C298
RBUF6
Receive Buffer for Serializer 6
01B4 C29C
RBUF7
Receive Buffer for Serializer 7
01B4 C2A0 − 01B4 FFFF
−
48
SPRS200C
Reserved
July 2002 − Revised July 2003
Peripheral Register Descriptions
Table 1−26. McASP0 Data Registers
HEX ADDRESS RANGE
3C00 0000 − 3C0F FFFF
ACRONYM
RBUF/XBUFx
REGISTER NAME
COMMENTS
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
registers, respectively].)
Table 1−27. I2C0 Registers
ACRONYM
REGISTER NAME
01B4 0000
I2COAR0
I2C0 own address register
01B4 0004
I2CIER0
I2C0 interrupt enable register
01B4 0008
I2CSTR0
I2C0 interrupt status register
01B4 000C
I2CCLKL0
I2C0 clock low-time divider register
01B4 0010
I2CCLKH0
I2C0 clock high-time divider register
01B4 0014
I2CCNT0
I2C0 data count register
01B4 0018
I2CDRR0
I2C0 data receive register
01B4 001C
I2CSAR0
I2C0 slave address register
01B4 0020
I2CDXR0
I2C0 data transmit register
01B4 0024
I2CMDR0
I2C0 mode register
01B4 0028
I2CISRC0
I2C0 interrupt source register
01B4 002C
−
01B4 0030
I2CPSC0
I2C0 prescaler register
01B4 0034
I2CPID10
I2C0 Peripheral Identification register 1 [Value: 0x0000 0101]
01B4 0038
I2CPID20
I2C0 Peripheral Identification register 2 [Value: 0x0000 0005]
01B4 003C − 01B4 3FFF
−
July 2002 − Revised July 2003
PRODUCT PREVIEW
HEX ADDRESS RANGE
Reserved
Reserved
SPRS200C
49
EDMA Channel Synchronization Events
1.8
EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 1−28 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM642 device, the association of an event to a channel is fixed; each of the EDMA
channels has one specific event associated with it. These specific events are captured in the EDMA event
registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The
priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter
RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access
(EDMA) Controller Reference Guide (literature number SPRU234).
PRODUCT PREVIEW
Table 1−28. TMS320DM642 EDMA Channel Synchronization Events†
EDMA
CHANNEL
EVENT NAME
0
DSP_INT
1
TINT0
Timer 0 interrupt
2
TINT1
Timer 1 interrupt
3
SD_INTA
4
GPINT4/EXT_INT4
GP0 event 4/External interrupt pin 4
5
GPINT5/EXT_INT5
GP0 event 5/External interrupt pin 5
6
GPINT6/EXT_INT6
GP0 event 6/External interrupt pin 6
7
GPINT7/EXT_INT7
GP0 event 7/External interrupt pin 7
8
GPINT0
GP0 event 0
9
GPINT1
GP0 event 1
10
GPINT2
GP0 event 2
11
GPINT3
GP0 event 3
12
XEVT0
McBSP0 transmit event
13
REVT0
McBSP0 receive event
14
XEVT1
McBSP1 transmit event
15
REVT1
McBSP1 receive event
16
VP0EVTYA
VP0 Channel A Y event DMA request
17
VP0EVTUA
VP0 Channel A Cb event DMA request
18
VP0EVTVA
VP0 Channel A Cr event DMA request
19
TINT2
EVENT DESCRIPTION
HPI/PCI-to-DSP interrupt
EMIFA SDRAM timer interrupt
Timer 2 interrupt
20−23
–
24
VP0EVTYB
None
VP0 Channel B Y event DMA request
25
VP0EVTUB
VP0 Channel B Cb event DMA request
26
VP0EVTVB
VP0 Channel B Cr event DMA request
27−31
–
None
32
AXEVTE0
McASP0 transmit even event
33
AXEVTO0
McASP0 transmit odd event
34
AXEVT0
McASP0 transmit event
35
AREVTE0
McASP0 receive even event
36
AREVTO0
McASP0 receive odd event
37
AREVT0
McASP0 receive event
† In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
50
SPRS200C
July 2002 − Revised July 2003
Interrupt Sources and Interrupt Selector
Table 1−28. TMS320DM642 EDMA Channel Synchronization Events† (Continued)
EVENT NAME
EVENT DESCRIPTION
38
VP1EVTYB
VP1 Channel B Y event DMA request
39
VP1EVTUB
VP1 Channel B Cb event DMA request
40
VP1EVTVB
VP1 Channel B Cr event DMA request
41
VP2EVTYB
VP2 Channel B Y event DMA request
42
VP2EVTUB
VP2 Channel B Cb event DMA request
43
VP2EVTVB
VP2 Channel B Cr event DMA request
44
ICREVT0
I2C0 receive event
45
ICXEVT0
I2C0 transmit event
46−47
–
48
GPINT8
None
GP0 event 8
49
GPINT9
GP0 event 9
50
GPINT10
GP0 event 10
51
GPINT11
GP0 event 11
52
GPINT12
GP0 event 12
53
GPINT13
GP0 event 13
54
GPINT14
GP0 event 14
55
GPINT15
GP0 event 15
56
VP1EVTYA
VP1 Channel A Y event DMA request
57
VP1EVTUA
VP1 Channel A Cb event DMA request
58
VP1EVTVA
VP1 Channel A Cr event DMA request
59
VP2EVTYA
VP2 Channel A Y event DMA request
60
VP2EVTUA
VP2 Channel A Cb event DMA request
61
VP2EVTVA
VP2 Channel A Cr event DMA request
62−63
–
None
† In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
1.9
Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 1−29. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 1−29. The interrupt source for interrupts 4−15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
July 2002 − Revised July 2003
SPRS200C
51
PRODUCT PREVIEW
EDMA
CHANNEL
Interrupt Sources and Interrupt Selector
Table 1−29. DM642 DSP Interrupts
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
INT_00†
INT_01†
−
−
RESET
−
−
NMI
INT_02†
INT_03†
−
−
Reserved
Reserved. Do not use.
−
−
Reserved
Reserved. Do not use.
INT_04‡
INT_05‡
MUXL[4:0]
00100
GPINT4/EXT_INT4
GP0 interrupt 4/External interrupt pin 4
MUXL[9:5]
00101
GPINT5/EXT_INT5
GP0 interrupt 5/External interrupt pin 5
INT_06‡
INT_07‡
MUXL[14:10]
00110
GPINT6/EXT_INT6
GP0 interrupt 6/External interrupt pin 6
MUXL[20:16]
00111
GPINT7/EXT_INT7
GP0 interrupt 7/External interrupt pin 7
INT_08‡
INT_09‡
MUXL[25:21]
01000
EDMA_INT
EDMA channel (0 through 63) interrupt
MUXL[30:26]
01001
EMU_DTDMA
INT_10‡
INT_11‡
MUXH[4:0]
00011
SD_INTA
MUXH[9:5]
01010
EMU_RTDXRX
EMU real-time data exchange (RTDX) receive
INT_12‡
INT_13‡
MUXH[14:10]
01011
EMU_RTDXTX
EMU RTDX transmit
MUXH[20:16]
00000
DSP_INT
INT_14‡
INT_15‡
MUXH[25:21]
00001
TINT0
Timer 0 interrupt
MUXH[30:26]
00010
TINT1
Timer 1 interrupt
−
−
01100
XINT0
McBSP0 transmit interrupt
−
−
01101
RINT0
McBSP0 receive interrupt
−
−
01110
XINT1
McBSP1 transmit interrupt
−
−
01111
RINT1
McBSP1 receive interrupt
−
−
10000
GPINT0
−
−
10001
Reserved
Reserved. Do not use.
−
−
10010
Reserved
Reserved. Do not use.
−
−
10011
TINT2
−
−
10100
Reserved
Reserved. Do not use.
−
−
10101
Reserved
Reserved. Do not use.
−
−
10110
ICINT0
−
−
10111
Reserved
Reserved. Do not use.
−
−
11000
EMAC_MDIO_INT
EMAC/MDIO interrupt
−
−
11001
VPINT0
VP0 interrupt
−
−
11010
VPINT1
VP1 interrupt
−
−
11011
VPINT2
VP2 interrupt
−
−
11100
AXINT0
McASP0 transmit interrupt
−
−
11101
ARINT0
McASP0 receive interrupt
PRODUCT PREVIEW
CPU
INTERRUPT
NUMBER
INTERRUPT SOURCE
EMU DTDMA
EMIFA SDRAM timer interrupt
HPI/PCI-to-DSP interrupt
GP0 interrupt 0
Timer 2 interrupt
I2C0 interrupt
−
−
11110 − 11111
Reserved
Reserved. Do not use.
† Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 1−29 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
52
SPRS200C
July 2002 − Revised July 2003
Signal Groups Description
CLKIN
CLKOUT4/GP0[1]†
CLKOUT6/GP0[2]†
CLKMODE1
CLKMODE0
PLLV
TMS
TDO
TDI
TCK
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
Clock/PLL
Reset and
Interrupts
RESET
NMI
GP0[7]/EXT_INT7‡
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
Reserved
RSV
RSV
RSV
RSV
RSV
RSV
IEEE Standard
1149.1
(JTAG)
Emulation
Peripheral
Control/Status
PRODUCT PREVIEW
1.10 Signal Groups Description
PCI_EN
TOUT0/MAC_EN
Control/Status
GP0[15]/PRST§
GP0[14]/PCLK§
GP0[13]/PINTA§
GP0[12]/PGNT§
GP0[11]/PREQ§
GP0[10]/PCBE3§
GP0[9]/PIDSEL§
VDAC/GP0[8]/PCI66§
GP0
GP0[7]/EXT_INT7‡
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
GP0[3]/PCIEEAI
CLKOUT6/GP0[2]†
CLKOUT4/GP0[1]†
GP0[0]
General-Purpose Input/Output 0 (GP0) Port
† These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these
muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured.
For more details, see the Device Configurations section of this data sheet.
‡ These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
§ These GP0 pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with both the GPIO
and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 1−5. CPU and Peripheral Signals
July 2002 − Revised July 2003
SPRS200C
53
Signal Groups Description
64
Data
AED[63:0]
AECLKIN
ACE3
ACE2
Memory Map
Space Select
ACE1
ACE0
20
AEA[22:3]
External
Memory I/F
Control
Address
ABE7
ABE6
ABE5
ABE4
Byte Enables
ABE3
ABE2
PRODUCT PREVIEW
ABE1
ABE0
Bus
Arbitration
AECLKOUT1
AECLKOUT2
ASDCKE
AARE/ASDCAS/ASADS/ASRE
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
ASOE3
APDT
AHOLD
AHOLDA
ABUSREQ
EMIFA (64-bit)
Data
VDAC/GP0[8]/PCI66
VCXO Interpolated
Control Port (VIC)
Figure 1−6. Peripheral Signals
54
SPRS200C
July 2002 − Revised July 2003
Signal Groups Description
32
Data
HD[15:0]/AD[15:0]
HD[31:16]/AD[31:16] §
HCNTL0/PSTOP
HCNTL1/PDEVSEL
HPI†
(Host-Port Interface)
Register Select
Control
Half-Word
Select
HHWIL/PTRDY
(HPI16 ONLY)
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HINT/PFRAME
32
GP0[10]/PCBE3
HR/W/PCBE2
HDS2/PCBE1
PCBE0
GP0[12]/PGNT
Data/Address
Command
Byte Enable
Clock
Control
Arbitration
Error
GP0[11]/PREQ
Serial
EEPROM
GP0[14]/PCLK
GP0[9]/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
GP0[13]/PINTA
HAS/PPAR
GP0[15]/PRST
HRDY/PIRDY
HCNTL0/PSTOP
HHWIL/PTRDY
PRODUCT PREVIEW
HD[15:0]/AD[15:0]
HD[31:16]/AD[31:16] §
HDS1/PSERR
HCS/PPERR
XSP_DO/MDIO
XSP_CS
XSP_CLK/MDCLK
XSP_DI
PCI Interface‡
† These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins,
see the Device Configurations section of this data sheet.
‡ These PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI or MDIO or GP0 peripherals. By default, these signals function
as HPI and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet.
§ These HPI/PCI data pins (HD[31:16/AD[31:16]) are muxed with the EMAC peripheral. By default, these pins function as HPI. For more
details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral signals section and the terminal functions table portions
of this data sheet.
Figure 1−6. Peripheral Signals (Continued)
July 2002 − Revised July 2003
SPRS200C
55
Signal Groups Description
McBSP1
McBSP0
Transmit
VP0D[2]/CLKX0†
VP0D[3]/FSX0†
VP0D[4]/DX0†
Receive
Receive
VP0D[8]/CLKR0†
VP0D[7]/FSR0†
VP0D[6]/DR0†
Clock
Clock
VP0D[5]/CLKS0†
VP1D[2]/CLKX1†
VP1D[3]/FSX1†
VP1D[4]/DX1†
Transmit
VP1D[8]/CLKR1†
VP1D[7]/FSR1†
VP1D[6]/DR1†
VP1D[5]/CLKS1†
PRODUCT PREVIEW
McBSPs
(Multichannel Buffered
Serial Ports)
TOUT1/LENDIAN
TINP1
TOUT0/MACEN
TINP0
Timer 0
Timer 1
Timer 2
Timers
SCL0
I2C0
SDA0
I2C0
† These McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals, respectively. By
default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations
section of this data sheet.
Figure 1−6. Peripheral Signals (Continued)
56
SPRS200C
July 2002 − Revised July 2003
Signal Groups Description
EMAC
HD16/AD16/MTXD0†
HD17/AD17/MTXD1†
HD18/AD18/MTXD2†
HD19/AD19/MTXD3†
Transmit
HD24/AD24/MRXD0†
HD25/AD25/MRXD1†
HD26/AD26/MRXD2†
HD27/AD27/MRXD3†
Receive
HD20/AD20/MTXEN†
HD29/AD29/MRXER†
HD28/AD28/MRXDV†
HD21/AD21/MCOL†
HD30/AD30/MCRS†
Error Detect
and Control
HD22/AD22/MTCLK†
HD31/AD31/MRCLK†
Clocks
MDIO
Clock
XSP_DO/MDIO‡
XSP_CLK/MDCLK‡
PRODUCT PREVIEW
Input/Output
Ethernet MAC (EMAC)
and MDIO
† These EMAC pins are muxed with the upper data pins of the HPI or PCI peripherals. By default, these signals function as HPI. For
more details on these muxed pins, see the Device Configurations section of this data sheet.
‡ These MDIO pins are muxed with the PCI peripherals. By default, these signals function as PCI. For more details on these muxed
pins, see the Device Configurations section of this data sheet.
Figure 1−6. Peripheral Signals (Continued)
July 2002 − Revised July 2003
SPRS200C
57
Signal Groups Description
STCLK§
VP0CLK0
VP0CLK1
VP0CTL0
VP0CTL1
VP0CTL2
PRODUCT PREVIEW
VP0D[0]
VP0D[1]
VP0D[2]/CLKX0
VP0D[3]/FSX0
VP0D[4]/DX0
VP0D[5]/CLKS0
VP0D[6]/DR0
VP0D[7]/FSR0
VP0D[8]/CLKR0
VP0D[9]
Timing and
Control Logic
VP0D[10]
VP0D[11]
VP0D[12]/ACLKR0
VP0D[13]/AFSR0
VP0D[14]/AHCLKR0
VP0D[15]/AMUTEIN0
VP0D[16]/AMUTE0
VP0D[17]/ACLKX0
VP0D[18]/AFSX0
VP0D[19]/AHCLKX0
Capture/Display
Buffer
(2560 Bytes)
Channel A†
Channel B uses only
the VP0D[19:10]
bidirectional pins
Capture/Display
Buffer
(2560 Bytes)
Channel B‡
Video Port 0 (VP0)
† Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes and BT.656
(8/10-bit), Y/C Video (16/20-bit), capture pipeline modes [RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes −
currently not supported].
‡ Channel B supports: BT.656 (8/10-bit) capture pipeline mode, [RAW Video (8/10-bit) capture pipeline mode − currently
not supported] and can display synchronized RAW Video data with Channel A.
§ The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1−6. Peripheral Signals (Continued)
58
SPRS200C
July 2002 − Revised July 2003
Signal Groups Description
VP1D[0]
VP1D[1]
VP1D[2]/CLKX1
VP1D[3]/FSX1
VP1D[4]/DX1
VP1D[5]/CLKS1
VP1D[6]/DR1
VP1D[7]/FSR1
VP1D[8]/CLKR1
VP1D[9]
Timing and
Control Logic
VP1D[10]
VP1D[11]
VP1D[12]/AXR0[0]
VP1D[13]/AXR0[1]
VP1D[14]/AXR0[2]
VP1D[15]/AXR0[3]
VP1D[16]/AXR0[4]
VP1D[17]/AXR0[5]
VP1D[18]/AXR0[6]
VP1D[19]/AXR0[7]
Capture/Display
Buffer
(2560 Bytes)
PRODUCT PREVIEW
STCLK§
VP1CLK0
VP1CLK1
VP1CTL0
VP1CTL1
VP1CTL2
Channel A†
Channel B uses only
the VP1D[19:10]
bidirectional pins
Capture/Display
Buffer
(2560 Bytes)
Channel B‡
Video Port 1 (VP1)
† Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes and BT.656
(8/10-bit), Y/C Video (16/20-bit), capture pipeline modes [RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes −
currently not supported].
‡ Channel B supports: BT.656 (8/10-bit) capture pipeline mode, [RAW Video (8/10-bit) capture pipeline mode − currently
not supported] and can display synchronized RAW Video data with Channel A.
§ The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1−6. Peripheral Signals (Continued)
July 2002 − Revised July 2003
SPRS200C
59
Signal Groups Description
STCLK§
VP2CLK0
VP2CLK1
VP2CTL0
VP2CTL1
VP2CTL2
PRODUCT PREVIEW
VP2D[0]
VP2D[1]
VP2D[2]
VP2D[3]
VP2D[4]
VP2D[5]
VP2D[6]
VP2D[7]
VP2D[8]
VP2D[9]
Timing and
Control Logic
VP2D[10]
VP2D[11]
VP2D[12]
VP2D[13]
VP2D[14]
VP2D[15]
VP2D[16]
VP2D[17]
VP2D[18]
VP2D[19]
Capture/Display
Buffer
(2560 Bytes)
Channel A†
Channel B uses only
the VP2D[19:10]
bidirectional pins
Capture/Display
Buffer
(2560 Bytes)
Channel B‡
Video Port 2 (VP2)
† Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes and BT.656
(8/10-bit), Y/C Video (16/20-bit), capture pipeline modes [RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes −
currently not supported].
‡ Channel B supports: BT.656 (8/10-bit) capture pipeline mode, [RAW Video (8/10-bit) capture pipeline mode − currently
not supported] and can display synchronized RAW Video data with Channel A.
§ The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1−6. Peripheral Signals (Continued)
60
SPRS200C
July 2002 − Revised July 2003
Signal Groups Description
(Transmit/Receive Data Pins)
(Transmit/Receive Data Pins)
VP1D[12]/AXR0[0]
VP1D[13]/AXR0[1]
VP1D[14]/AXR0[2]
VP1D[15]/AXR0[3]
VP1D[16]/AXR0[4]
VP1D[17]/AXR0[5]
VP1D[18]/AXR0[6]
VP1D[19]/AXR0[7]
8-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
(Transmit Bit Clock)
(Receive Bit Clock)
Receive Clock
Generator
(Receive Master Clock)
VP0D[13]/AFSR0
(Receive Frame Sync or
Left/Right Clock)
VP0D[17]/ACLKX0
VP0D[19]/AHCLKX0
(Transmit Master Clock)
Receive Clock
Check Circuit
Transmit
Clock Check
Circuit
Receive
Frame Sync
Transmit
Frame Sync
Error Detect
(see Note A)
Auto Mute
Logic
VP0D[18]/AFSX0
(Transmit Frame Sync or
Left/Right Clock)
VP0D[16]/AMUTE0
VP0D[15]/AMUTEIN0
McASP0
(Multichannel Audio Serial Port 0)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 1−6. Peripheral Signals (Continued)
July 2002 − Revised July 2003
SPRS200C
61
PRODUCT PREVIEW
VP0D[12]/ACLKR0
VP0D[14]/AHCLKR0
Transmit
Clock
Generator
Device Configurations
2
Device Configurations
On the DM642 device, bootmode and certain device configurations/peripheral selections are determined at
device reset, while other device configurations/peripheral selections are software-configurable via the
peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
2.1
Peripheral Selection at Device Reset
Some DM642 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,
general-purpose input/output pins GP0[15:9], PCI and its internal EEPROM, EMAC, and MDIO). Other
DM642 peripherals (i.e., the Timers, I2C0, and the GP0[7:0] pins), are always available.
•
HPI, GP0[15:9], PCI, EEPROM (internal to PCI), EMAC, and VIC peripherals
The PCI_EN and MAC_EN pins are latched at reset. They determine specific peripheral selection,
summarized in Table 2−1.
Table 2−1. PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC, and MDIO)
PERIPHERAL SELECTION†
PERIPHERALS SELECTED
PCI_EEAI
Pin [L5]
HD5
Pin [Y1]
MAC_EN
Pin [C5]
HPI Data
Lower
HPI Data
Upper
32-Bit PCI
EEPROM
(Auto-Init)
EMAC and
MDIO
GP0[15:9]
0
0
0
0
√
Hi-Z
Disabled
N/A
Disabled
√
0
0
0
1
√
Hi-Z
Disabled
N/A
√
√
0
0
1
0
√
√
Disabled
N/A
Disabled
√
0
0
1
1
Disabled
N/A
√
√
Disabled
Disabled
Disabled
Disabled
PRODUCT PREVIEW
PCI_EN
Pin [E2]
Disabled
1
1
X
X
Disabled
√
Enabled
(via External
EEPROM)
1
0
X
X
Disabled
√
Disabled
(default values)
•
If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and based on the HD5 and MAC_EN
pin configuration at reset, HPI16 mode or EMAC and MDIO can be selected. When the PCI is disabled
(PCI_EN = 0), the GP0[15:9] pins can also be programmed as GPIO, provided the GPxEN and GPxDIR
bits are properly configured.
This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and
XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GP0/PCI pins can be used as GPIO with the proper
software configuration of the GPIO enable and direction registers (for more details, see Table 2−9).
•
If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled.
This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GP0/PCI pins function as
PCI pins (for more details, see Table 2−9).
•
The MAC_EN pin, in combination with the PCI_EN and HD5 pins, controls the selection of the EMAC and
MDIO peripherals (for more details, see Table 2−2).
•
The PCI_EN pin (= 1) and the PCI_EEAI pin control the whether the PCI initializes its internal registers
via external EEPROM (PCI_EEAI = 1) or if the internal default values are used instead (PCI_EEAI = 0).
Table 2−2. HPI vs. EMAC Peripheral Pin Selection
CONFIGURATION SELECTION†
62
PERIPHERALS SELECTED
GP0[0] (Pin [M5])
HD5 (Pin [Y1])
MAC_EN (Pin [C5])
HD[15:0]
0
0
0
HPI16
Hi-Z
0
0
1
HPI16
used for EMAC
0
1
0
0
1
1
SPRS200C
HD[31:16]
HPI32 (HD[31:0])
Hi-Z
used for EMAC
July 2002 − Revised July 2003
Device Configurations
2.2
Device Configuration at Device Reset
Table 2−3 describes the DM642 device configuration pins, which are set up via external pullup/pulldown
resistors through the specified EMIFA address bus pins (AEA[22:19]), and the TOUT1/LENDIAN,
GP0[3]/PCIEEAI, and the HD5 pins (all of which are latched during device reset).
Table 2−3. DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI,
VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and MAC_EN)
NO.
TOUT1/LENDIAN
B5
AEA[22:21]
AEA[20:19]
GP0[3]/PCIEEAI
FUNCTIONAL DESCRIPTION
Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 − System operates in Little Endian mode (default)
[U23,
V24]
Bootmode [1:0]
00 – No boot (default mode)
01 − HPI/PCI boot (based on PCI_EN pin)
10 − Reserved
11 − EMIFA boot
[V25,
V26]
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
L5
PRODUCT PREVIEW
CONFIGURATION
PIN
PCI EEPROM Auto-Initialization (PCIEEAI)
PCI auto-initialization via external EEPROM
0 − PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified
PCI default values (default).
1 − PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured
through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral
Component Interconnect (PCI) Reference Guide (literature number SPRU581).
VDAC/GP0[8]/PCI66
AD1
PCI frequency selection (PCI66) [PCI peripheral needs be enabled (PCI_EN = 1) to use this function]
Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating frequency is selected at
reset via the pullup/pulldown resistor on the PCI66 pin:
0 − PCI operates at 66 MHz (default).
1 − PCI operates at 33 MHz.
The -500 speed device supports PCI at 33 MHz only. For proper -500 device operation when the PCI is
enabled (PCI_EN = 1), this pin must be pulled up with a 1-kΩ resistor at device reset.
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
HD5/AD5
Y1
HPI peripheral bus width (HPI_WIDTH)
0 − HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the Hi-Z state.)
1 − HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
(Also see the PCI_EN; TOUT0/MAC_EN functional description in this table)
Peripheral Selection
PCI_EN;
TOUT0/MAC_EN
[E2; C5]
July 2002 − Revised July 2003
00
01
10
11
–
−
−
−
HPI (default mode) [HPI32, if HD5 = 1; HPI16 if HD5 = 0
EMAC and MDIO; HPI16, if HD5 = 0; HPI disabled, if HD5 = 1
PCI
Reserved
SPRS200C
63
Device Configurations
2.3
Peripheral Selection After Device Reset
Video Ports, McBSP1, McBSP0, McASP0 and I2C0
The DM642 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
Video Ports (VP0, VP1, VP2) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more detailed
information on the PERCFG register control bits, see Figure 2−1 and Table 2−4.
31
24
Reserved
R-0
16
23
PRODUCT PREVIEW
Reserved
R-0
8
15
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
VP2EN
VP1EN
VP0EN
I2C0EN
MCBSP1EN
MCBSP0EN
MCASP0EN
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003]
64
SPRS200C
July 2002 − Revised July 2003
Device Configurations
Table 2−4. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
NAME
Reserved
6
5
4
3
2
1
0
DESCRIPTION
Reserved. Read-only, writes have no effect.
VP2EN
VP2 Enable bit.
Determines whether the VP2 peripheral is enabled or disabled.
(This feature allows power savings by disabling the peripheral when not in use.)
0 = VP2 is disabled, and the module is powered down (default).
1 = VP2 is enabled.
VP1EN
VP1 Enable bit.
Determines whether the VP1 peripheral is enabled or disabled.
0 = VP1 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP1 is enabled.
VP0EN
VP0 Enable bit.
Determines whether the VP0 peripheral is enabled or disabled.
0 = VP0 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP0 is enabled.
I2C0EN
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
0 = I2C0 is disabled, and the module is powered down (default).
1 = I2C0 is enabled.
MCBSP1EN
Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit.
Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the
remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
MCBSP0EN
Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.
Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the
remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
MCASP0EN
McASP0 vs. VP0/VP1 upper-data pins select bit.
Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.
0 = McASP0 is disabled; VP0 and VP1 upper-data pins are enabled; and the VP0 and VP1
lower-data pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and
VP1EN bits, respectively.
1 = McASP0 is enabled; VP0 and VP1 upper-data pins are disabled; and the VP0 and VP1
lower-data pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and
VP1EN bits, respectively.
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
July 2002 − Revised July 2003
SPRS200C
PRODUCT PREVIEW
BIT
31:7
65
Device Configurations
McBSP0EN [PERCFG.1]
VP0
Lower Data (10 pins)
VP0D[8:2] Muxed†
VP0D[9,1,0] Standalone
1
McBSP0
0
VP0 (Channel A)
McBSP1EN [PERCFG.2]
VP1
Lower Data (10 pins)
VP1D[8:2] Muxed‡
VP1D[9,1,0] Standalone
1
McBSP1
0
VP1 (Channel A)
1
VP0 (Channel A)
PRODUCT PREVIEW
McBSP0EN [PERCFG.1]
McASP0EN [PERCFG.0]
VP0
Upper Data (10 pins)
VP0D[19:12] Muxed§
VP0D[11:10] Standalone
McASP0EN [PERCFG.0]
0
1
McASP0 Control
0
VP0 (Channel B)
McBSP1EN [PERCFG.2]
McASP0EN [PERCFG.0]
VP1
Upper Data (10 pins)
VP1D[19:12] Muxed¶
VP1D[11:10] Standalone
1
VP1 (Channel A)
McASP0EN [PERCFG.0]
0
1
McASP0 Data
0
VP1 (Channel B)
† Consists of: VP0D[8]/CLKR0, VP0D[7]/FSR0, VP0D[6]/DR0, VP0D[5]/CLKS0, VP0D[4]/DX0, VP0D[3]/FSX0, VP0D[2]/CLKX0.
‡ Consists of: VP1D[8]/CLKR1, VP1D[7]/FSR1, VP1D[6]/DR1, VP1D[5]/CLKS1, VP1D[4]/DX1, VP1D[3]/FSX1, VP1D[2]/CLKX1.
§ Consists of: VP0D[19]/AHCLKX0, VP0D[18]/AFSX0, VP0D[17]/ACLKX0, VP0D[16]/AMUTE0, VP0D[15]/AMUTEIN0,
VP0D[14]/AHCLKR0, VP0D[13]/AFSR0, VP0D[12]/ACLKR0
¶ Consists of: VP1D[19:12]/AXR0[7:0]
Figure 2−2. VP1, VP0, McBSP1, McBSP0, and McASP0 Data/Control Pin Muxing
66
SPRS200C
July 2002 − Revised July 2003
Device Configurations
2.4
Peripheral Configuration Lock
By default, the McASP0, VP0, VP1, VP2, and I2C peripherals are disabled on power up. In order to use these
peripherals on the DM642 device, the peripheral must first be enabled in the Peripheral Configuration register
(PERCFG). Software muxed pins should not be programmed to switch functionalities during run-time.
Care should also be taken to ensure that no accesses are being performed before disabling the
peripherals. To help minimize power consumption in the DM642 device, unused peripherals may be disabled.
Figure 2−3 shows the flow needed to enable (or disable) a given peripheral on the DM642 device.
Unlock the PERCFG Register
Using the PCFGLOCK Register
PRODUCT PREVIEW
Write to
PERCFG Register
to Enable/Disable Peripherals
Read from
PERCFG Register
Wait 128 CPU Cycles Before
Accessing Enabled Peripherals
Figure 2−3. Peripheral Enable/Disable Flow Diagram
A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register
(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register
determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT
bit = 0), see Figure 2−4. A peripheral can only be enabled when the PERCFG register is “unlocked”
(LOCKSTAT bit = 0).
July 2002 − Revised July 2003
SPRS200C
67
Device Configurations
Read Accesses
31
1
0
Reserved
LOCKSTAT
R-0
R-1
Write Accesses
31
0
LOCK
W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses
PRODUCT PREVIEW
Table 2−5. PCFGLOCK Register Selection Bit Descriptions − Read Accesses
BIT
NAME
31:1
Reserved
0
LOCKSTAT
DESCRIPTION
Reserved. Read-only, writes have no effect.
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0 = Unlocked, read accesses to the PERCFG register allowed.
1 = Locked, write accesses to the PERCFG register do not modify the register state [default].
Reads are unaffected by Lock Status.
Table 2−6. PCFGLOCK Register Selection Bit Descriptions − Write Accesses
BIT
31:0
NAME
LOCK
DESCRIPTION
Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a
peripheral while it is disabled.
68
SPRS200C
July 2002 − Revised July 2003
Device Configurations
2.5
Device Status Register Description
The device status register depicts the status of the device peripheral selection. For the actual register bit
names and their associated bit field descriptions, see Figure 2−5 and Table 2−7.
31
24
Reserved
R-0
16
23
Reserved
R-0
15
11
10
9
8
Reserved
MAC_EN
HPI_WIDTH
PCI_EEAI
PCI_EN
R-0
R-x
R-x
R-x
R-x
14
13
12
6
5
4
3
2
1
0
Reserved
CLKMODE1
CLKMODE0
LENDIAN
BOOTMODE1
BOOTMODE0
AECLKINSEL1
AECLKINSEL0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
PRODUCT PREVIEW
7
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−5. Device Status Register (DEVSTAT) Description − 0x01B3 F004
Table 2−7. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT
NAME
31:12
Reserved
Reserved. Read-only, writes have no effect.
MAC_EN
EMAC enable bit.
Shows the status of whether EMAC peripheral is enabled or disabled (default).
0 = EMAC is disabled, and the module is powered down (default).
1 = EMAC is enabled.
This bit has no effect if the PCI peripheral is enabled (PCI_EN = 1).
11
10
HPI_WIDTH
DESCRIPTION
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
0 = HPI operates in 16-bit mode. (default).
1 = HPI operates in 32-bit mode.
PCI EEPROM auto-initialization bit (PCI auto-initialization via external EEPROM).
Shows the status of whether the PCI module initializes internal registers via external EEPROM or if the
internal PCI default values are used instead (default).
9
PCI_EEAI
8
PCI_EN
7
Reserved
0 = PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified
PCI default values (default).
1 = PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured
through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
PCI enable bit.
Shows the status of whether the PCI peripheral is enabled or disabled (default).
0 = PCI disabled. (default).
1 = PCI enabled.
Global select for the PCI vs. HPI/EMAC/MDIO/GPIO peripherals.
July 2002 − Revised July 2003
Reserved. Read-only, writes have no effect.
SPRS200C
69
Device Configurations
Table 2−7. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
PRODUCT PREVIEW
BIT
NAME
6
CLKMODE1
5
CLKMODE0
4
LENDIAN
3
BOOTMODE1
2
BOOTMODE0
1
AECLKINSEL1
0
AECLKINSEL0
2.6
DESCRIPTION
Clock mode select bits
Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6,
or x12.
Clock mode select for CPU clock frequency (CLKMODE[1:0])
00 – Bypass (x1) (default mode)
01 − x6
10 − x12
11 − Reserved
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this
data sheet.
Device Endian mode (LEND)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).
0 – System is operating in Big Endian mode
1 − System is operating in Little Endian mode (default)
Bootmode configuration bits
Shows the status of what device bootmode configuration is operational.
Bootmode [1:0]
00 – No boot (default mode)
01 − HPI/PCI boot (based on PCI_EN pin)
10 − Reserved
11 − EMIFA boot
EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for the EMIF.
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the DM642
device, the JTAG ID register resides at address location 0x01B3 F004. The register hex value for the DM642
device is: 0x0007 902F. For the actual register bit names and their associated bit field descriptions, see
Figure 2−6 and Table 2−8.
31−28
27−12
11−1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-0000
R-0000 0000 0111 1001
R-0000 0010 111
R-1
Legend: R = Read only; -n = value after reset
Figure 2−6. JTAG ID Register Description − TMS320DM642 Register Value − 0x0007 902F
Table 2−8. JTAG ID Register Selection Bit Descriptions
70
BIT
NAME
31:28
VARIANT
27:12
PART NUMBER
11−1
MANUFACTURER
0
LSB
SPRS200C
DESCRIPTION
Variant (4-Bit) value. DM642 value: 0000.
Part Number (16-Bit) value. DM642 value: 0000 0000 0111 1001.
Manufacturer (11-Bit) value. DM642 value: 0000 0010 111.
LSB. This bit is read as a “1” for DM642.
July 2002 − Revised July 2003
Device Configurations
2.7
Multiplexed Pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should not be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 2−9 identifies the multiplexed pins on the DM642 device; shows the default (primary) function and the
default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed
functions.
2.8
Debugging Considerations
Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do not
oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown
resistors. If an external controller provides signals to these non-configuration pins, these signals must be
driven to the default state of the pins at reset, or not be driven at all.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
July 2002 − Revised July 2003
SPRS200C
71
PRODUCT PREVIEW
It is recommended that external connections be provided to device configuration pins, including
TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and
TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on these pins, providing external
connectivity adds convenience to the user in debugging and flexibility in switching operating modes.
Device Configurations
Table 2−9. DM642 Device Multiplexed Pins†
MULTIPLEXED PINS
NAME
NO.
DEFAULT
FUNCTION
DEFAULT
SETTING
CLKOUT4/GP0[1]
D6
CLKOUT4
GP1EN = 0 (disabled)
CLKOUT6/GP0[2]
C6
CLKOUT6
GP2EN = 0 (disabled)
DESCRIPTION
These pins are software-configurable. To use these pins as
GPIO pins, the GPxEN bits in the GPIO Enable Register and
the GPxDIR bits in the GPIO Direction Register must be
properly configured.
GPxEN = 1:
GPx pin enabled
GPxDIR = 0:
GPx pin is an input
GPxDIR = 1:
GPx pin is an output
To use the PCI auto−initialization EEPROM (PCIEEAI) the
PCI needs to be enabled (PCI_EN = 1):
0 − PCI auto-init through EEPROM disabled (default).
1 − PCI auto-init through EEPROM is enabled.
PRODUCT PREVIEW
GP0[3]/PCIEEAI
L5
PCIEEAI
GP3EN = 0 (disabled)
To use GP0[3] as a GPIO pin, the PCI needs to be disabled
(PCI_EN = 0), the GP3EN bits in the GPIO Enable Register
and the GP3DIR bits in the GPIO Direction Register must be
properly configured.
GP3EN = 1:
GP3 pin enabled
GP3DIR = 0:
GP3 pin is an input
GP3DIR = 1:
GP3 pin is an output
The VDAC output pin function is default.
VDAC/GP0[8]/PCI66
AD1
PCI66
GP8EN = 0 (disabled)
MAC_EN = 0 (disabled)
To use GP0[8] as a GPIO pin, the PCI needs to be disabled
(PCI_EN = 0), the GPxEN bits in the GPIO Enable Register
and the GPxDIR bits in the GPIO Direction Register must be
properly configured.
GP8EN = 1:
GP8 pin enabled
GP8DIR = 0:
GP8 pin is an input
GP8DIR = 1:
GP8 pin is an output
To use the PCI66 pin function, which changes the PCI
operating frequency selection, the PCI needs to be enabled
(PCI_EN = 1):
0 − PCI operates at 66 MHz (default).
1 − PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper
-500 device operation when the PCI peripheral is enabled
(PCI_EN = 1), this pin must be pulled up with a a 1-kΩ
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin
must not be pulled up.
GP0[9]/PIDSEL
K3
GP0[10]/PCBE3
J2
GP0[11]/PREQ
F1
GP0[12]/PGNT
H4
GP0[13]/PINTA
G4
GP0[14]/PCLK
C1
None
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)†
To use GP0[15:9] as GPIO pins, the PCI needs to be disabled
(PCI_EN = 0), the GPxEN bits in the GPIO Enable Register
and the GPxDIR bits in the GPIO Direction Register must be
properly configured.
GPxEN = 1:
GPx pin enabled
GPxDIR = 0:
GPx pin is an input
GPxDIR = 1:
GPx pin is an output
GP0[15]/PRST
G3
† All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
‡ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
72
SPRS200C
July 2002 − Revised July 2003
Device Configurations
Table 2−9. DM642 Device Multiplexed Pins† (Continued)
MULTIPLEXED PINS
VP1D[19]/AXR0[7]
NO.
AB11
VP1D[17]/AXR0[5]
AC11
VP1D[16]/AXR0[4]
AD11
VP1D[15]/AXR0[3]
AE11
VP1D[14]/AXR0[2]
AC10
VP1D[13]/AXR0[1]
AD10
VP1D[12]/AXR0[0]
AC9
VP1D[8]/CLKR1
AD8
VP1D[7]/FSR1
AC7
VP1D[6]/DR1
AD7
VP1D[5]/CLKS1
AE7
VP1D[4]/DX1
AC6
VP1D[3]/FSX1
AD6
AC12
VP0D[18]/AFSX0
AD12
VP0D[17]/ACLKX0
AB13
VP0D[16]/AMUTE0
AC13
VP0D[15]/AMUTEIN0
AD13
VP0D[14]/AHCLKR0
AB14
VP0D[13]/AFSR0
AC14
VP0D[12]/ACLKR0
AD14
VP0D[8]/CLKR0
AE15
VP0D[7]/FSR0
AB16
VP0D[6]/DR0
AC16
VP0D[5]/CLKS0
AD16
VP0D[4]/DX0
AE16
VP0D[3]/FSX0
AF16
VP0D[2]/CLKX0
AF17
None
VP1EN bit = 0
(disabled)
MCASP0EN bit = 0
(disabled)
By default, no function is enabled upon reset.
To enable the Video Port 1 data pins, the VP1EN bit in the
PERCFG register must be set to a 1. (McASP0 data pins are
disabled).
To enable the McASP0[7:0] data pins, the MCASP0EN bit in
the PERCFG register must be set to a 1. (VP1 upper data
pins are disabled).
McBSP1
functions
VP1EN bit = 0
(disabled)
MCBSP1EN bit = 1
(enabled)
By default, the McBSP1 peripheral, function is enabled upon
reset (MCBSP1EN bit = 1).
To enable the Video Port 1 data pins, the VP1EN bit in the
PERCFG register must be set to a 1.
None
VP0EN bit = 0
(disabled)
MCASP0EN bit = 0
(disabled)
By default, no function is enabled upon reset.
To enable the Video Port 0 data pins, the VP0EN bit in the
PERCFG register must be set to a 1. (McASP0 control pins
are disabled).
To enable the McASP0 control pins, the MCASP0EN bit in
the PERCFG register must be set to a 1. (VP0 upper data
pins are disabled).
McBSP0
functions
VP0EN bit = 0
(disabled)
MCBSP0EN bit = 1
(enabled)
By default, the McBSP0 peripheral function is enabled upon
reset (MCBSP0EN bit = 1).
To enable the Video Port 0 data pins, the VP0EN bit in the
PERCFG register must be set to a 1.
PCI_EN = 0 (disabled)†
MAC_EN = 0
(disabled)†
By default, no functions enabled upon reset (PCI is
disabled).
To enable the PCI peripheral, an external pullup resistor
(1 kΩ) must be provided on the PCI_EN pin (setting
PCI_EN = 1 at reset)
To enable the MDIO peripheral (which also enables the
EMAC peripheral), an external pullup resistor (1 kΩ) must be
provided on the MAC_EN pin (setting MAC_EN = 1 at reset)
R5
None
XSP_DO/MDIO
DESCRIPTION
AE6
VP0D[19]/AHCLKX0
XSP_CLK/MDCLK
DEFAULT
SETTING
AB12
VP1D[18]/AXR0[6]
VP1D[2]/CLKX1
DEFAULT
FUNCTION
P5
† All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
‡ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
July 2002 − Revised July 2003
SPRS200C
73
PRODUCT PREVIEW
NAME
Configuration Examples
Table 2−9. DM642 Device Multiplexed Pins† (Continued)
MULTIPLEXED PINS
NAME
HAS/PPAR
DEFAULT
FUNCTION
P3
HAS
HCNTL1/PDEVSEL
P1
HCNTL1
HCNTL0/PSTOP
R3
HCNTL0
HDS1/PSERR
R2
HDS1
HDS2/PCBE1
T2
HDS2
HR/W/PCBE2
M1
HR/W
HHWIL/PTRDY
N3
HHWIL
(HPI16 only)
HINT/PFRAME
N4
HINT
HCS/PPERR
R1
HCS
HRDY/PIRDY
N1
HRDY
HD[23,15:0]/AD[23,15:0]
PRODUCT PREVIEW
NO.
‡
HD[23, 15:0]
HD31/AD31/MRCLK
G1
HD31
HD30/AD30/MCRS
H3
HD30
HD29/AD29/MRXER
G2
HD29
HD28/AD28/MRXDV
J4
HD28
HD27/AD27/MRXD3
H2
HD27
HD26/AD26/MRXD2
J3
HD26
HD25/AD25/MRXD1
J1
HD25
HD24/AD24/MRXD0
K4
HD24
HD22/AD22/MTCLK
L4
HD22
HD21/AD21/MCOL
K2
HD21
HD20/AD20/MTXEN
L3
HD20
HD19/AD19/MTXD3
L2
HD19
HD18/AD18/MTXD2
M4
HD18
HD17/AD17/MTXD1
M2
HD17
DEFAULT
SETTING
DESCRIPTION
PCI_EN = 0 (disabled)†
By default, HPI is enabled upon reset (PCI is disabled).
To enable the PCI peripheral, an external pullup resistor
(1 kΩ) must be provided on the PCI_EN pin (setting
PCI_EN = 1 at reset).
PCI_EN = 0 (disabled)†
By default, HPI is enabled upon reset (PCI is disabled).
To enable the PCI peripheral, an external pullup resistor
(1 kΩ) must be provided on the PCI_EN pin (setting
PCI_EN = 1 at reset).
PCI_EN = 0 (disabled)†
MAC_EN = 0
(disabled)†
By default, HPI is enabled upon reset (PCI is disabled).
To enable the PCI peripheral, an external pullup resistor
(1 kΩ) must be provided on the PCI_EN pin (setting
PCI_EN = 1 at reset).
To enable the EMAC peripheral, an external pullup resistor
(1 kΩ) must be provided on the MAC_EN pin (setting
MAC_EN = 1 at reset).
HD16/AD16/MTXD0
M3
HD16
† All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
‡ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
2.9
Configuration Examples
Figure 2−7 through Figure 2−9 illustrate examples of peripheral selections that are configurable on the DM642
device.
74
SPRS200C
July 2002 − Revised July 2003
Configuration Examples
64
AED[63:0]
PCI
HD[15:0]
16
HPI
(16-Bit)
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
EMIFA
Clock
and
System
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
TIMER2
MDIO
TIMER1
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
CLKOUT4, CLKOUT6, PLLV
TINP1
MDIO, MDCLK
STCLK†
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[19:0]
PRODUCT PREVIEW
TOUT1/LENDIAN
TINP0
VP0
(20-Bit)
TIMER0
McBSP0
GP0
and
EXT_INT
TOUT0/MACEN
McASP0 Control
GP0[15:9, 3:0]
GP0[7:4]
SCL0
I2C0
SDA0
McASP0 Data
McBSP1
VIC
VP1
(20-Bit)
VP2
(20-Bit)
STCLK†
VDAC/GP0[8]/PCI66
STCLK†
VP1CLK0
VP1CLK1,
VP1CTL[2:0],
VP1D[19:0]
VP2CLK0
VP2CLK1,
VP2CTL[2:0],
VP2D[19:0]
Shading denotes a peripheral module not available for this configuration.
† STCLK supports all three video ports (VP2, VP1, and VP0).
PERCFG Register Value:
External Pins:
0x0000 0078
PCI_EN = 0
GP0[3]/PCIEEAI = 0
HD5 = 0 TOUT0/MAC_EN = 1
Figure 2−7. Configuration Example A
(3 20-Bit Video Ports + HPI + EMAC + MDIO + I2C0 + EMIF + 3 Timers)
July 2002 − Revised July 2003
SPRS200C
75
Configuration Examples
64
AED[63:0]
PCI
HD[15:0]
16
HPI
(16-Bit)
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
Clock
and
System
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
TIMER2
MDIO
TIMER1
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
PRODUCT PREVIEW
TOUT1/LENDIAN
STCLK†
TINP0
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[19:10]
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
VP0
(10-Bit)
TIMER0
McBSP0
GP0
and
EXT_INT
TOUT0/MACEN
GP0[15:9, 3:0]
GP0[7:4]
McASP0 Control
SCL0
I2C0
SDA0
McASP0 Data
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
McBSP1
VIC
VP1
(10-Bit)
VP2
(20-Bit)
VDAC/GP0[8]/PCI66
STCLK†
STCLK†
VP1CLK0
VP2CLK0
VP2CLK1,
VP2CTL[2:0],
VP2D[19:0]
VP1CLK1,
VP1CTL[2:0],
VP1D[19:10]
Shading denotes a peripheral module not available for this configuration.
† STCLK supports all three video ports (VP2, VP1, and VP0)
PERCFG Register Value:
Extenal Pins:
0x0000 007E
PCI_EN = 0
GP0[3]/PCIEEAI = 0
HD5 = 0
TOUT0/MAC_EN = 1
Figure 2−8. Configuration Example B
(2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO + I2C0 + EMIF)
[Possible Video IP Phone Application]
76
SPRS200C
July 2002 − Revised July 2003
Configuration Examples
64
AED[63:0]
PCI
HD[15:0]
EMIFA
16
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
Clock
and
System
HPI
(16-Bit)
HRDY, HINT
AECLKIN, AARDY, AHOLD
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
TIMER2
MDIO
TIMER1
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
STCLK†
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[9:0]
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
PRODUCT PREVIEW
TOUT1/LENDIAN
TINP0
VP0
(10-Bit)
TIMER0
McBSP0
GP0
and
EXT_INT
TOUT0/MACEN
GP0[15:9, 3:0]
GP0[7:4]
McASP0 Control
SCL0
I2C0
SDA0
McASP0 Data
AXR0[7:0]
McBSP1
VIC
VP1
(10-Bit)
VP2
(20-Bit)
VDAC/GP0[8]/PCI66
STCLK†
STCLK†
VP1CLK0
VP1CLK1,
VP1CTL[2:0],
VP1D[9:0]
VP2CLK0
VP2CLK1,
VP2CTL[2:0],
VP2D[19:0]
Shading denotes a peripheral module not available for this configuration.
† STCLK supports all three video ports (VP2, VP1, and VP0).
PERCFG Register Value:
Extenal Pins:
0x0000 0079
PCI_EN = 0
GP0[3]/PCIEEAI = 0
HD5 = 0
TOUT0/MAC_EN = 1
Figure 2−9. Configuration Example C
(2 10-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF)
[Possible Set-Top Box Application]
July 2002 − Revised July 2003
SPRS200C
77
Terminal Functions
2.10 Terminal Functions
PRODUCT PREVIEW
The terminal functions table (Table 2−10) identifies the external signal names, the associated pin (ball)
numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has
any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
78
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions
SIGNAL
NAME
TYPE†
IPD/
IPU‡
AC2
I
IPD
Clock Input. This clock is the input to the on-chip PLL.
CLKOUT4/GP0[1]§
D6
I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 1 pin (I/O/Z).
CLKOUT6/GP0[2]§
C6
I/O/Z
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
CLKMODE1
AE4
I
IPD
CLKMODE0
AA2
I
IPD
V6
A#
NO.
DESCRIPTION
CLOCK/PLL CONFIGURATION
CLKIN
PLLV¶
Clock mode select
• Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6,
or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL section of this data sheet.
PLL voltage supply
TMS
E15
I
IPU
JTAG test-port mode select
TDO
B18
O/Z
IPU
JTAG test-port data out
TDI
A18
I
IPU
JTAG test-port data in
TCK
A16
I
IPU
JTAG test-port clock
TRST
D14
I
IPD
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
EMU11
D17
I/O/Z
IPU
Emulation pin 11. Reserved for future use, leave unconnected.
EMU10
C17
I/O/Z
IPU
Emulation pin 10. Reserved for future use, leave unconnected.
EMU9
B17
I/O/Z
IPU
Emulation pin 9. Reserved for future use, leave unconnected.
EMU8
D16
I/O/Z
IPU
Emulation pin 8. Reserved for future use, leave unconnected.
EMU7
A17
I/O/Z
IPU
Emulation pin 7. Reserved for future use, leave unconnected.
EMU6
C16
I/O/Z
IPU
Emulation pin 6. Reserved for future use, leave unconnected.
EMU5
B16
I/O/Z
IPU
Emulation pin 5. Reserved for future use, leave unconnected.
EMU4
D15
I/O/Z
IPU
Emulation pin 4. Reserved for future use, leave unconnected.
EMU3
C15
I/O/Z
IPU
Emulation pin 3. Reserved for future use, leave unconnected.
EMU2
B15
I/O/Z
IPU
EMU1
C14
I/O/Z
IPU
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation pin 1||
EMU0
A15
I/O/Z
IPU
Emulation pin 0||
RESET
P4
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
I
Device reset
NMI
B4
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
# A = Analog signal (PLL Filter)
|| The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ
resistor.
July 2002 − Revised July 2003
SPRS200C
79
PRODUCT PREVIEW
JTAG EMULATION
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
PRODUCT PREVIEW
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED)
GP0[7]/EXT_INT7
E1
I/O/Z
IPU
GP0[6]/EXT_INT6
F2
I/O/Z
IPU
GP0[5]/EXT_INT5
F3
I/O/Z
IPU
GP0[4]/EXT_INT4
F4
I/O/Z
IPU
GP0[15]/PRST§
G3
General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I). No function at
default.
GP0[14]/PCLK§
GP0[13]/PINTA§
C1
GP0 14 pin (I/O/Z) or PCI clock (I). No function at default.
G4
GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GP0[12]/PGNT§
GP0[11]/PREQ§
H4
GP0 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GP0[10]/PCBE3§
GP0[9]/PIDSEL§
J2
GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
K3
GP0 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
L5
IPD
GP0 3 pin (I/O/Z) and PCI EEPROM Auto-Initialization (EEAI).
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
0 − PCI auto-initialization through EEPROM is disabled (default).
1 − PCI auto-initialization through EEPROM is enabled.
IPD
GP0 0 pin (I/O/Z) [default] or device selection (I) [default]
The general-purpose 0 pin (GP0[0]) (I/O/Z) can be programmed as GPIO 0 (input
only) [default] or as GP0[0] (output only) pin or output as a general-purpose interrupt
(GP0INT) signal (output only). This pin must remain low during device reset.
F1
GP0[3]/PCIEEAI
GP0[0]
M5
GP0 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
I/O/Z
I/O/Z
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only).
The default after reset setting is GPIO enabled as input-only.
• When these pins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
AD1
I/O/Z
IPD
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC)
output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or
PCI frequency selection (PCI66).
If the PCI peripheral is enabled (PCI_EN pin = 1), then:
0 − PCI operates at 66 MHz (default).
1 − PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper -500 device operation when
the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up with a a 1-kΩ
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
CLKOUT6/
GP0[2]§
C6
I/O/Z
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
CLKOUT4/
GP0[1]§
D6
I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 1 pin (I/O/Z).
VDAC/
GP0[8]/PCI66§
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC
PCI_EN
E2
I
IPD
PCI enable pin. This pin and the MAC_EN pin control the selection (enable/disable) of
the HPI, EMAC, MDIO, and GP0[15:8], or PCI peripherals. The pins work in conjunction
to enable/disable these peripherals (for more details, see the Device Configurations
section of this data sheet).
HINT/PFRAME§
N4
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
80
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HCNTL1/
PDEVSEL§
P1
I/O/Z
Host control − selects between control, address, or data registers (I) [default] or PCI
device select (I/O/Z).
HCNTL0/
PSTOP§
R3
I/O/Z
Host control − selects between control, address, or data registers (I) [default] or PCI
stop (I/O/Z)
HHWIL/PTRDY§
N3
I/O/Z
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
HR/W/PCBE2§
M1
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
HAS/PPAR§
P3
I/O/Z
Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR§
R1
I/O/Z
Host chip select (I) [default] or PCI parity error (I/O/Z)
HDS1/PSERR§
R2
I/O/Z
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
HDS2/PCBE1§
T2
I/O/Z
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
HRDY/PIRDY§
N1
I/O/Z
Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
HD31/AD31/MRCLK§
HD30/AD30/MCRS§
G1
HD29/AD29/MRXER§
HD28/AD28/MRXDV§
G2
HD27/AD27/MRXD3§
HD26/AD26/MRXD2§
H2
HD25/AD25/MRXD1§
HD24/AD24/MRXD0§
J1
K4
HD23/AD23§
K1
HD22/AD22/MTCLK§
HD21/AD21/MCOL§
L4
H3
J4
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC
transmit/receive or control pins
J3
As HPI data bus (PCI_EN pin = 0)
• Used for transfer of data, address, and control
• Host-Port bus width user-configurable at device reset via a 10-kΩ resistor pullup/
pulldown resistor on the HD5 pin:
K2
HD20/AD20/MTXEN§
HD19/AD19/MTXD3§
L3
HD18/AD18/MTXD2§
HD17/AD17/MTXD1§
M4
HD16/AD16/MTXD0§
HD15/AD15§
M3
HD14/AD14§
HD13/AD13§
U1
HD12/AD12§
HD11/AD11§
U2
HD10/AD10§
HD9/AD9§
V1
HD8/AD8§
HD7/AD7§
V2
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
L2
M2
T3
U3
U4
I/O/Z
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
As PCI data-address bus (PCI_EN pin = 1)
• Used for transfer of data and address
For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can also
function as EMAC transmit/receive or control pins (when PCI_EN pin = 0; MAC_EN
pin = 1). For more details on the EMAC pin functions, see the Ethernet MAC (EMAC)
peripheral section of this table and for more details on how to configure the EMAC pin,
see the device configuration section of this data sheet.
V3
W2
HD6/AD6§
W4
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
81
PRODUCT PREVIEW
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED)
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED)
HD5/AD5§
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC
transmit/receive or control pins
Y1
HD4/AD4§
W3
HD3/AD3§
Y2
As HPI data bus (PCI_EN pin = 0)
• Used for transfer of data, address, and control
• Host-Port bus width user-configurable at device reset via a 10-kΩ resistor pullup/
pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
I/O/Z
PRODUCT PREVIEW
HD2/AD2§
HD1/AD1§
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
Y4
As PCI data-address bus (PCI_EN pin = 1)
• Used for transfer of data and address
AA1
For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can also
function as EMAC transmit/receive or control pins (when PCI_EN pin = 0; MAC_EN
pin = 1). For more details on the EMAC pin functions, see the Ethernet MAC (EMAC)
peripheral section of this table and for more details on how to configure the EMAC pin,
see the device configuration section of this data sheet.
HD0/AD0§
Y3
PCBE0
V4
I/O/Z
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is
tied-off.
GP0[15]/PRST§
G3
I/O/Z
General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I). No function at
default.
XSP_CS
T4
O
IPD
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is
tied-off.
XSP_CLK/MDCLK§
R5
I/O/Z
IPD
PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z).
XSP_DI
R4
I
IPU
PCI serial interface data in (I) [default]. In PCI mode, this pin is connected to the output
data pin of the serial PROM.
XSP_DO/MDIO§
P5
I/O/Z
IPU
PCI serial interface data out (O) [default] or MDIO serial data input/output (I/O/Z). In PCI
mode, this pin is connected to the input data pin of the serial PROM.
GP0[14]/PCLK§
GP0[13]/PINTA§
C1
GP0 14 pin (I/O/Z) or PCI clock (I). No function at default.
G4
GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
I/O/Z
GP0[12]/PGNT§
H4
GP0 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
82
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED)
GP0[11]/PREQ§
F1
GP0 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
K3
GP0[3]/PCIEEAI
L5
VDAC/
GP0[8]/PCI66§
J2
AD1
GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
I/O/Z
GP0 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
I/O/Z
I/O/Z
IPD
GP0 3 pin (I/O/Z) and PCI EEPROM Auto-Initialization (EEAI).
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
0 − PCI auto-initialization through EEPROM is disabled (default).
1 − PCI auto-initialization through EEPROM is enabled.
IPD
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC)
output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or
PCI frequency selection (PCI66).
If the PCI peripheral is enabled (PCI_EN pin = 1), then:
0 − PCI operates at 66 MHz (default).
1 − PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper -500 device operation when
the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up with a a 1-kΩ
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
EMIFA (64-BIT) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3
L26
O/Z
IPU
ACE2
K23
O/Z
IPU
ACE1
K24
O/Z
IPU
ACE0
K25
O/Z
IPU
ABE7
T22
O/Z
IPU
ABE6
T23
O/Z
IPU
ABE5
R25
O/Z
IPU
ABE4
R26
O/Z
IPU
ABE3
M25
O/Z
IPU
ABE2
M26
O/Z
IPU
ABE1
L23
O/Z
IPU
ABE0
L24
O/Z
IPU
APDT
M22
O/Z
IPU
AHOLDA
N22
O
IPU
EMIFA hold-request-acknowledge to the host
AHOLD
W24
I
IPU
EMIFA hold request from the host
EMIFA memory space enables
• Enabled by bits 28 through 31 of the word address
• Only one pin is asserted during any external data access
EMIFA byte-enable control
• Decoded from the low-order address bits. The number of address bits or byte
enables
used depends on the width of external memory.
• Byte-write enables for most types of memory
• Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFA peripheral data transfer, allows direct transfer between external peripherals
EMIFA (64-BIT) − BUS ARBITRATION
ABUSREQ
P22
O
IPU
EMIFA bus request output
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
83
PRODUCT PREVIEW
GP0[10]/PCBE3§
GP0[9]/PIDSEL§
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
PRODUCT PREVIEW
EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
AECLKIN
H25
I
IPD
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
J23
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
J26
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
AARE/
ASDCAS/
ASADS/ASRE
J25
O/Z
IPU
EMIFA
asynchronous
memory
read-enable/SDRAM
column-address
strobe/programmable synchronous interface-address strobe or read-enable
• For programmable synchronous interface, the RENEN field in the CE Space
Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
J24
O/Z
IPU
EMIFA
asynchronous
memory
output-enable/SDRAM
strobe/programmable synchronous interface output-enable
AAWE/
ASDWE/
ASWE
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
ASDCKE
L25
O/Z
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode).
• If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
R22
O/Z
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
row-address
AARDY
L22
I
IPU
Asynchronous memory ready input
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
84
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIFA (64-BIT) − ADDRESS
U23
AEA21
V24
AEA20
V25
AEA19
V26
AEA18
V23
AEA17
U24
AEA16
U25
AEA15
U26
AEA14
T24
AEA13
T25
AEA12
R23
AEA11
R24
AEA10
P23
AEA9
P24
AEA8
P26
AEA7
N23
AEA6
N24
AEA5
N26
AEA4
M23
AEA3
M24
EMIFA external address (doubleword address)
Note: EMIFA address numbering for the DM642 device starts with AEA3 to maintain
signal name compatibility with other C64x devices (e.g., C6414, C6415, and C6416)
[see the 64-bit EMIF addressing scheme in the TMS320C6000 DSP External Memory
Interface (EMIF) Reference Guide (literature number SPRU266)].
•
O/Z
IPD
Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI/PCI boot (based on PCI_EN pin)
10 − Reserved
11 − EMIFA boot
− EMIF clock select
PRODUCT PREVIEW
AEA22
− AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
For more details, see the Device Configurations section of this data sheet.
EMIFA (64-BIT) − DATA
AED63
AF24
AED62
AF23
AED61
AE23
AED60
AD23
AED59
AD22
AED58
AE22
AED57
AD21
AED56
AE21
AED55
AC21
AED54
AF21
AED53
AD20
AED52
AE20
AED51
AC20
AED50
AF20
AED49
AC19
AED48
AD19
AED47
W23
I/O/Z
IPU
EMIFA external data
AED46
Y26
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
85
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
PRODUCT PREVIEW
EMIFA (64-BIT) − DATA (CONTINUED)
AED45
Y23
AED44
Y25
AED43
Y24
AED42
AA26
AED41
AA23
AED40
AA25
AED39
AA24
AED38
AB23
AED37
AB25
AED36
AB24
AED35
AC26
AED34
AC25
AED33
AD25
AED32
AD26
AED31
C26
AED30
C25
AED29
D26
AED28
D25
AED27
E24
AED26
E25
AED25
F24
AED24
F25
AED23
F23
AED22
F26
AED21
G24
AED20
G25
AED19
G23
AED18
G26
AED17
H23
AED16
H24
AED15
C19
AED14
D19
AED13
A20
AED12
D20
AED11
B20
AED10
C20
AED9
A21
AED8
D21
I/O/Z
IPU
EMIFA external data
AED7
B21
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
86
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIFA (64-BIT) − DATA (CONTINUED)
AED6
C21
AED5
A23
AED4
C22
AED3
B22
AED2
B23
AED1
A24
AED0
B24
XSP_CLK/MDCLK§
R5
I/O/Z
IPD
PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z).
XSP_DO/MDIO§
P5
I/O/Z
IPU
PCI serial interface data out (O) [default] or MDIO serial data input/output (I/O/Z). In PCI
mode, this pin is connected to the input data pin of the serial PROM.
I/O/Z
IPU
EMIFA external data
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
VDAC/
GP0[8]/PCI66§
AD1
I/O/Z
IPD
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC)
output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or
PCI frequency selection (PCI66).
If the PCI peripheral is enabled (PCI_EN pin = 1), then:
0 − PCI operates at 66 MHz (default).
1 − PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper -500 device operation when
the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up with a a 1-kΩ
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
VIDEO PORTS (VP0, VP1, AND VP2)
STCLK
AC1
I
IPD
The STCLK signal drives the hardware counter on the video ports.
VIDEO PORT 2 (VP2)
VP2D[19]
E13
VP2D[18]
E12
VP2D[17]
D12
VP2D[16]
C12
VP2D[15]
B12
VP2D[14]
E11
VP2D[13]
D11
VP2D[12]
C11
VP2D[11]
B11
VP2D[10]
A11
VP2D[9]
D10
VP2D[8]
C10
VP2D[7]
B10
VP2D[6]
A10
I/O/Z
IPD
Video port 2 (VP2) data input/output (I/O/Z)
VP2D[5]
D9
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
87
PRODUCT PREVIEW
VCXO INTERPOLATED CONTROL PORT (VIC)
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
VIDEO PORT 2 (VP2) (CONTINUED)
VP2D[4]
C9
VP2D[3]
B9
VP2D[2]
A9
VP2D[1]
D8
I/O/Z
IPD
Video port 2 (VP2) data input/output (I/O/Z)
VP2D[0]
C8
VP2CLK1
A13
I/O/Z
IPD
VP2 clock 1 (I/O/Z)
VP2CLK0
A7
I
IPD
VP2 clock 0 (I)
VP2CTL2
C7
VP2CTL1
D7
VP2CTL0
B8
VP2 control 2 (I/O/Z)
I/O/Z
IPD
VP2 control 1 (I/O/Z)
VP2 control 0 (I/O/Z)
PRODUCT PREVIEW
VIDEO PORT 1 (VP1) OR MCASP0 DATA
VP1D[19]/AXR0[7]§
VP1D[18]/AXR0[6]§
AB12
VP1D[17]/AXR0[5]§
VP1D[16]/AXR0[4]§
AC11
VP1D[15]/AXR0[3]§
VP1D[14]/AXR0[2]§
AB11
AD11
AE11
AC10
VP1D[13]/AXR0[1]§
VP1D[12]/AXR0[0]§
AD10
VP1D[11]
AD9
VP1D[10]
AE9
VP1D[9]
AC8
VP1D[8]/CLKR1§
VP1D[7]/FSR1§
AD8
VP1D[6]/DR1§
AD7
VP1D[5]/CLKS1§
VP1D[4]/DX1§
AC6
VP1D[3]/FSX1§
AD6
VP1D[2]/CLKX1§
AE6
VP1D[1]
AF6
AC9
I/O/Z
IPD
Video port 1 (VP1) data input/output (I/O/Z) or McASP0 data pins (I/O/Z) or McBSP1
data input/output (I/O/Z) [default]
For more details on the McBSP1 pin functions or the McASP0 data pin functions, see
McBSP1 or McASP0 data sections of this table and the Device Configurations section
of this data sheet.
AC7
AE7
VP1D[0]
AF5
VP1CLK1
AF10
I/O/Z
IPD
VP1 clock 1 (I/O/Z)
VP1CLK0
AF8
I
IPD
VP1 clock 0 (I)
VP1CTL2
AD5
VP1CTL1
AE5
I/O/Z
IPD
VP1 control 2 (I/O/Z)
VP1 control 1 (I/O/Z)
VP1CTL0
AF4
VP1 control 0 (I/O/Z)
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
88
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
VIDEO PORT 0 (VP0) OR MCASP0 CONTROL
VP0D[19]/AHCLKX0§
VP0D[18]/AFSX0§
AC12
VP0D[17]/ACLKX0§
VP0D[16]/AMUTE0§
AB13
AD12
AC13
VP0D[15]/AMUTEIN0§
VP0D[14]/AHCLKR0§
AD13
VP0D[13]/AFSR0§
AC14
VP0D[12]/ACLKR0§
AD14
VP0D[11]
AB15
VP0D[10]
AC15
VP0D[9]
AD15
VP0D[8]/CLKR0§
VP0D[7]/FSR0§
AE15
VP0D[6]/DR0§
AC16
VP0D[5]/CLKS0§
VP0D[4]/DX0§
AD16
VP0D[3]/FSX0§
AF16
AB14
I/O/Z
IPD
Video port 0 (VP0) data input/output (I/O/Z) or McASP0 control pins (I/O/Z) or McBSP0
data input/output (I/O/Z) [default]
For more details on the McBSP0 pin functions or the McASP0 control pin functions, see
McBSP0 or McASP0 control sections of this table and the Device Configurations
section of this data sheet.
PRODUCT PREVIEW
AB16
AE16
VP0D[2]/CLKX0§
AF17
VP0D[1]
AE18
VP0D[0]
AF18
VP0CLK1
AF12
I/O/Z
IPD
VP0 clock 1 (I/O/Z)
VP0CLK0
AF14
I
IPD
VP0 clock 0 (I)
VP0CTL2
AD17
VP0CTL1
AC17
I/O/Z
IPD
VP0CTL0
AE17
VP0 control 2 (I/O/Z)
VP0 control 1 (I/O/Z)
VP0control 0 (I/O/Z)
TIMER 2
−
No external pins. The timer 2 peripheral pins are not pinned out as external pins.
TIMER 1
TOUT1/LENDIAN
B5
O/Z
IPU
Timer 1 output (O/Z) or device endian mode (I).
Also controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode
0 – Big Endian
1 − Little Endian (default)
For more details on LENDIAN, see the Device Configurations section of this data sheet.
TINP1
A5
I
IPD
Timer 1 or general-purpose input
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
89
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
TIMER 0
TOUT0/MAC_EN
C5
O/Z
IPD
Timer 0 output (O/Z) or MAC enable select bit (I)
MAC enable pin. This pin and the MAC_EN pin control the selection (enable/disable) of
the HPI, EMAC, MDIO, and GP0[15:9], or PCI peripherals. The pins work in conjunction
to enable/disable these peripherals (for more details, see the Device Configurations
section of this data sheet).
For more details, see the Device Configurations section of this data sheet.
TINP0
A4
I
IPD
Timer 0 or general-purpose input
SCL0
E4
I/O/Z
—
I2C0 clock.
SDA0
D3
I/O/Z
—
I2C0 data.
INTER-INTEGRATED CIRCUIT 0 (I2C0)
PRODUCT PREVIEW
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
VP1D[8]/CLKR1§
AD8
I/O/Z
IPD
Video Port 1 (VP1) input/output data 8 pin (I/O/Z) or McBSP1 receive clock (I/O/Z)
[default]
VP1D[7]/FSR1§
VP1D[6]/DR1§
AC7
I/O/Z
IPD
VP1 input/output data 7 pin (I/O/Z) or McBSP1 receive frame sync (I/O/Z) [default]
AD7
I
IPD
VP1 input/output data 6 pin (I/O/Z) or McBSP1 receive data (I) [default]
VP1D[5]/CLKS1§
AE7
I
IPD
VP1 input/output data 5 pin (I/O/Z) or McBSP1 external clock source (I) (as opposed to
internal) [default]
VP1D[4]/DX1§
VP1D[3]/FSX1§
AC6
I/O/Z
IPD
VP1 input/output data 4 pin (I/O/Z) or McBSP1 transmit data (O/Z) [default]
AD6
I/O/Z
IPD
VP1 input/output data 3 pin (I/O/Z) or McBSP1 transmit frame sync (I/O/Z) [default]
VP1D[2]/CLKX1§
AE6
I/O/Z
IPD
VP1 input/output data 2 pin (I/O/Z) or McBSP1 transmit clock (I/O/Z) [default]
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
VP0D[8]/CLKR0§
AE15
I/O/Z
IPD
Video Port 0 (VP0) input/output data 8 pin (I/O/Z) or McBSP0 receive clock (I/O/Z)
[default]
VP0D[7]/FSR0§
VP0D[6]/DR0§
AB16
I/O/Z
IPD
VP0 input/output data 7 pin (I/O/Z) or McBSP0 receive frame sync (I/O/Z) [default]
AC16
I
IPU
VP0 input/output data 6 pin (I/O/Z) or McBSP0 receive data (I) [default]
VP0D[5]/CLKS0§
AD16
I
IPD
VP0 input/output data 5 pin (I/O/Z) or McBSP0 external clock source (I) (as opposed to
internal) [default]
VP0D[4]/DX0§
VP0D[3]/FSX0§
AE16
O/Z
IPU
VP0 input/output data 4 pin (I/O/Z) or McBSP0 transmit data (O/Z) [default]
AF16
I/O/Z
IPD
VP0 input/output data 3 pin (I/O/Z) or McBSP0 transmit frame sync (I/O/Z) [default]
VP0D[2]/CLKX0§
AF17
I/O/Z
IPD
VP0 input/output data 2 pin (I/O/Z) or McBSP0 transmit clock (I/O/Z) [default]
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
90
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HD31/AD31/MRCLK§
G1
I
HD30/AD30/MCRS§
H3
I
HD29/AD29/MRXER§
G2
I
HD28/AD28/MRXDV§
J4
I
HD27/AD27/MRXD3§
H2
I
HD26/AD26/MRXD2§
J3
I
HD25/AD25/MRXD1§
J1
I
HD24/AD24/MRXD0§
K4
I
HD22/AD22/MTCLK§
L4
I
HD21/AD21/MCOL§
K2
I
HD20/AD20/MTXEN§
L3
O/Z
HD19/AD19/MTXD3§
L2
O/Z
HD18/AD18/MTXD2§
M4
O/Z
HD17/AD17/MTXD1§
M2
O/Z
HD16/AD16/MTXD0§
M3
O/Z
EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive.
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]).
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network collision.
During full-duplex operation, transmission of new frames will not begin if this pin is
asserted.
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]).
and MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL
VP0D[19]/AHCLKX0§
AC12
I/O/Z
IPD
VP0 input/output data 19 pin (I/O/Z) or McASP0 transmit high-frequency
master clock (I/O/Z).
VP0D[18]/AFSX0§
AD12
I/O/Z
IPD
VP0 input/output data 18 pin (I/O/Z) or McASP0 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
VP0D[17]/ACLKX0§
AB13
I/O/Z
IPD
VP0 input/output data 17 pin (I/O/Z) or McASP0 transmit bit clock (I/O/Z).
VP0D[16]/AMUTE0§
AC13
O/Z
IPD
VP0 input/output data 16 pin (I/O/Z) or McASP0 mute output (O/Z).
VP0D[15]/AMUTEIN0§
AD13
I/O/Z
IPD
VP0 input/output data 15 pin (I/O/Z) or McASP0 mute input (I/O/Z).
VP0D[14]/AHCLKR0§
AB14
I/O/Z
IPD
VP0 input/output data 14 pin (I/O/Z) or McASP0 receive high-frequency master clock
(I/O/Z).
VP0D[13]/AFSR0§
AC14
I/O/Z
IPD
VP0 input/output data 13 pin (I/O/Z) or McASP0 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
VP0D[12]/ACLKR0§
AD14
I/O/Z
IPD
VP0 input/output data 12 pin (I/O/Z) or McASP0 receive bit clock (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA
VP1D[19]/AXR0[7]§
VP1D[18]/AXR0[6]§
AB12
VP1D[17]/AXR0[5]§
VP1D[16]/AXR0[4]§
AC11
VP1D[15]/AXR0[3]§
VP1D[14]/AXR0[2]§
AE11
VP1D[13]/AXR0[1]§
VP1D[12]/AXR0[0]§
AB11
AD11
I/O/Z
IPD
VP0 input/output data pins [19:12] (I/O/Z) or McASP0 TX/RX data pins [7:0] (I/O/Z).
AC10
AD10
AC9
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
July 2002 − Revised July 2003
SPRS200C
91
PRODUCT PREVIEW
ETHERNET MAC (EMAC)
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
RESERVED FOR TEST
RSV
H7
Reserved. This pin must be connected directly to CVDD for proper device operation.
RSV
R6
Reserved. This pin must be connected directly to DVDD for proper device operation.
E14
W7
AA3
AB3
RSV
Reserved (leave unconnected, do not connect to power or ground)
AC4
AD3
AF3
SUPPLY VOLTAGE PINS
PRODUCT PREVIEW
A2
A25
B1
B2
B14
B25
B26
C3
C24
D4
D23
E5
E7
E8
DVDD
S
3.3-V supply voltage
E10
E17
E19
E20
E22
F9
F12
F15
F18
G5
G22
H5
H22
J6
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
92
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
J21
K5
K22
M6
M21
N2
P25
R21
U5
U22
PRODUCT PREVIEW
V21
W5
W22
W25
Y5
DVDD
Y22
S
3.3-V supply voltage
AA9
AA12
AA15
AA18
AB5
AB7
AB8
AB10
AB17
AB19
AB20
AB22
AC23
AD24
AE1
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
July 2002 − Revised July 2003
SPRS200C
93
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
AE2
AE13
AE25
DVDD
AE26
S
3.3-V supply voltage
S
1.2-V supply voltage (-500 device)
1.4 V supply voltage (-600 devices)
AF2
AF25
F6
F7
F20
PRODUCT PREVIEW
F21
G6
G7
G8
G10
G11
G13
G14
G16
G17
G19
CVDD
G20
G21
H20
K7
K20
L7
L20
M12
M14
N7
N13
N15
N20
P7
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
94
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
P12
P14
P20
R13
R15
T7
T20
U7
U20
W20
PRODUCT PREVIEW
Y6
Y7
Y8
CVDD
Y10
S
1.2-V supply voltage (-500 device)
1.4 V supply voltage (-600 devices)
Y11
Y13
Y14
Y16
Y17
Y19
Y20
Y21
AA6
AA7
AA20
AA21
GROUND PINS
A1
A3
A6
A8
VSS
A12
GND
Ground pins
A14
A19
A22
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
July 2002 − Revised July 2003
SPRS200C
95
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
GROUND PINS (CONTINUED)
A26
B3
B6
B7
B13
B19
C2
C4
C13
PRODUCT PREVIEW
C18
C23
D1
D2
D5
D13
D18
VSS
GND
Ground pins
D22
D24
E3
E6
E9
E16
E18
E21
E23
E26
F5
F8
F10
F11
F13
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
96
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
GROUND PINS (CONTINUED)
F14
F16
F17
F19
F22
G9
G12
G15
G18
H1
PRODUCT PREVIEW
H6
H21
H26
J5
J7
J20
VSS
J22
GND
Ground pins
K6
K21
L1
L6
L21
M7
M13
M15
M20
N5
N6
N12
N14
N21
N25
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
July 2002 − Revised July 2003
SPRS200C
97
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
GROUND PINS (CONTINUED)
P2
P6
P13
P15
P21
R7
R12
R14
R20
PRODUCT PREVIEW
T1
T5
T6
T21
T26
U6
U21
VSS
GND
Ground pins
V5
V7
V20
V22
W1
W6
W21
W26
Y9
Y12
Y15
Y18
AA4
AA5
AA8
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
98
SPRS200C
July 2002 − Revised July 2003
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
GROUND PINS (CONTINUED)
AA10
AA11
AA13
AA14
AA16
AA17
AA19
AA22
AB1
AB2
AB4
PRODUCT PREVIEW
AB6
AB9
AB18
AB21
AB26
VSS
AC3
GND
Ground pins
AC5
AC18
AC22
AC24
AD2
AD4
AD18
AE3
AE8
AE10
AE12
AE14
AE19
AE24
AF1
AF7
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
July 2002 − Revised July 2003
SPRS200C
99
Terminal Functions
Table 2−10. Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
GROUND PINS (CONTINUED)
AF9
AF11
AF13
AF15
VSS
GND
Ground pins
AF19
AF22
AF26
PRODUCT PREVIEW
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
100
SPRS200C
July 2002 − Revised July 2003
Development Support
2.11
Development Support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software
needed to support any DSP application.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
July 2002 − Revised July 2003
SPRS200C
101
PRODUCT PREVIEW
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
Device and Development-Support Tool Nomenclature
2.12 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
PRODUCT PREVIEW
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GDK), the temperature range (for example, blank is the default commercial temperature
range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 2−10 provides a
legend for reading the complete device name for any TMS320C6000 DSP platform member.
TMS320 is a trademark of Texas Instruments.
102
SPRS200C
July 2002 − Revised July 2003
Device and Development-Support Tool Nomenclature
TMX 320 DM642 GDK
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
SMX= Experimental device, MIL
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
320 = TMS320t DSP family
( )
600
DEVICE SPEED RANGE
500 (500-MHz CPU, 100-MHz EMIF, 33-MHz PCI)
600 (600-MHz CPU, 133-MHz EMIF, 66-MHz PCI)
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)†
Blank = 0°C to 90°C, commercial temperature
A
= −40°C to 105°C, extended temperature
PACKAGE TYPE‡
GDK = 548-pin plastic BGA
GNZ = 548-pin plastic BGA
DEVICE
DM64x DSP:
642
641
PRODUCT PREVIEW
† For more details, see the recommended operating conditions portion of this data sheet.
‡ BGA = Ball Grid Array
Figure 2−10. TMS320DM64x DSP Device Nomenclature (Including the TMS320DM642 Device)
July 2002 − Revised July 2003
SPRS200C
103
Documentation Support
2.13 Documentation Support
Extensive documentation supports all TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets, such as this document, with design specifications; complete user’s reference guides for all devices
and tools; technical briefs; development-support tools; on-line help; and hardware and software applications.
The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
PRODUCT PREVIEW
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x
digital signal processor, and discusses the application areas that are enhanced by the C64x DSP
VelociTI.2 VLIW architecture.
The TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629) describes the functionality of the Video Port and VIC Port peripherals.
The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripheral.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
describes the functionality of the I2C peripheral.
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO
peripherals.
TMS320DM642 Technical Overview (literature number SPRU615) describes the TMS320DM642 architecture
including details of its peripherals. This document also shows several example applications such as using the
DM642 device in development of IP phones, video-on-demand set-top boxes, and surveillance digital video
recorders.
The TMS320DM642 Digital Signal Processor Silicon Errata (literature number SPRZ196) describes the
known exceptions to the functional specifications for particular silicon revisions of the TMS320DM642 device.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
104
SPRS200C
July 2002 − Revised July 2003
Clock PLL
2.14 Clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed.
Figure 2−11 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
PRODUCT PREVIEW
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
July 2002 − Revised July 2003
SPRS200C
105
Clock PLL
3.3 V
CPU Clock
EMI
filter
C1
C2
10 µF
0.1 µF
/2
Peripheral Bus, EDMA
Clock, L2 Clock
/8
Timer Internal Clock
PLLV
CLKMODE0
CLKMODE1
PLLMULT
/4
CLKOUT4, Peripheral Clock
(AUXCLK for McASP),
McBSP Internal Clock
/6
CLKOUT6
PLL
x6, x12
CLKIN
PLLCLK
1
00 01 10
/4
PRODUCT PREVIEW
0
/2
ECLKIN
AEA[20:19]
Internal to DM642
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 9.)
EMIF
00 01 10
ECLKOUT1
ECLKOUT2
EK2RATE
(GBLCTL.[19,18])
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 2−11. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
106
SPRS200C
July 2002 − Revised July 2003
Clock PLL
Table 2−11. TMS320DM642 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time†‡
GDK PACKAGE − 23 x 23 mm BGA,
GNZ PACKAGE − 27 x 27 mm BGA
CLKMODE1 CLKMODE0
CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
TYPICAL
LOCK TIME
(µs)§
N/A
0
0
Bypass (x1)
30−75
30−75
7.5−18.8
5−12.5
0
1
x6
30−75
180−450
45−112.5
30−75
1
0
x12
30−50
360−600
90−150
60−100
75
PRODUCT PREVIEW
1
1
Reserved
−
−
−
−
−
† These clock frequency range values are applicable to a DM642−600 speed device. For −500 device speed values, see the CLKIN timing
requirements table for the specific device speed.
‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM642 device to one of the valid PLL multiply
clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1
(bypass).
§ Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
July 2002 − Revised July 2003
SPRS200C
107
Multichannel Audio Serial Port (McASP0) Peripheral
2.15 Multichannel Audio Serial Port (McASP0) Peripheral
The TMS320DM642 device includes one multichannel audio serial port (McASP) interface peripheral
(McASP0). The McASP is a serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely independently
with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit
and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that
may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
PRODUCT PREVIEW
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio
data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as
well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP
Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
2.15.1
McASP Block Diagram
Figure 2−12 illustrates the major blocks along with external signals of the TMS320DM642 McASP0 peripheral;
and shows the 8 serial data [AXR] pins. The McASP also includes full general-purpose I/O (GPIO) control,
so any pins not needed for serial transfers can be used for general-purpose I/O.
108
SPRS200C
July 2002 − Revised July 2003
Multichannel Audio Serial Port (McASP0) Peripheral
McASP0
DIT
RAM
Transmit
Frame Sync
Generator
Transmit
Clock Check
(HighFrequency)
Transmit
Clock
Generator
Receive
Clock
Generator
Transmit
Data
Formatter
Receive
Frame Sync
Generator
AHCLKR0
ACLKR0
AFSR0
Serializer 0
AXR0[0]
Serializer 1
AXR0[1]
Serializer 2
AXR0[2]
Serializer 3
AXR0[3]
Serializer 4
AXR0[4]
Serializer 5
AXR0[5]
Serializer 6
AXR0[6]
Serializer 7
AXR0[7]
PRODUCT PREVIEW
Receive
Clock Check
(HighFrequency)
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
DMA Transmit
DMA Receive
AHCLKX0
ACLKX0
AMUTE0
AMUTEIN0
Error
Detect
Receive
Data
Formatter
AFSX0
GPIO
Control
Figure 2−12. McASP0 Configuration
July 2002 − Revised July 2003
SPRS200C
109
I2C
2.16 I2C
The I2C module on the TMS320DM642 may be used by the DSP to control local peripherals ICs (DACs, ADCs,
etc.) while the other may be used to communicate with other controllers in a system or to implement a user
interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
PRODUCT PREVIEW
Figure 2−13 is a block diagram of the I2C0 module.
I2C0 Module
Clock
Prescale
Peripheral Clock
(CPU/4)
I2CPSCx
SCL
Noise
Filter
I2C Clock
Bit Clock
Generator
Control
I2CCLKHx
I2COARx
Own
Address
I2CSARx
Slave
Address
I2CMDRx
Mode
I2CCNTx
Data
Count
I2CCLKLx
Transmit
I2CXSRx
Transmit
Shift
I2CDXRx
Transmit
Buffer
Interrupt/DMA
SDA
I2C Data
Noise
Filter
Receive
I2CIERx
Interrupt
Enable
I2CDRRx
Receive
Buffer
I2CSTRx
Interrupt
Status
I2CRSRx
Receive
Shift
I2CISRCx
Interrupt
Source
NOTE A: Shading denotes control/status registers.
Figure 2−13. I2C0 Module Block Diagram
110
SPRS200C
July 2002 − Revised July 2003
PCI
2.17 PCI
On the DM642 device, the PCI interface is multiplexed with the 32-bit Host Port Interface (HPI), or with a
combination of 16-bit HPI and EMAC/MDIO. This provides the following flexibility options to the user:
•
•
•
32-bit 66 MHz PCI bus
32-bit HPI
Combination of 16-bit HPI and EMAC/MDIO
The PCI port for the TMS320C600 supports connection of the DSP to a PCI host via the integrated PCI
master/slave bus interface. For the C64x devices, like the DM642, the PCI port interfaces to the DSP via the
EDMA internal address generation hardware. This architecture allows for both PCI Master and Slave
transactions, while keeping the EDMA channel resources available for other applications.
PRODUCT PREVIEW
For more details on the PCI port peripheral module, see the TMS320C6000 DSP Peripheral Component
Interconnect (PCI) Reference Guide (literature number SPRU581).
July 2002 − Revised July 2003
SPRS200C
111
Video Port
2.18 Video Port
The TMS320DM642 device has three video port peripherals.
The video port peripheral can operate as a video capture port, video display port, or as a transport stream
interface (TSI) capture port [TSI currently not supported].
The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the two
channels. The entire port (both channels) is always configured for either video capture or display only.
Separate data pipelines control the parsing and formatting of video capture or display data for each of the
BT.656, Y/C, raw video [Raw Video Capture currently not supported], and TSI modes [currently not supported].
For video capture operation, the video port may operate as two 8/10-bit channels of BT.656 or raw video
capture [currently not supported]; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video [currently not
supported], 16/20-bit Y/C video, 16/20-bit raw video [currently not supported], or 8-bit TSI [currently not
supported].
PRODUCT PREVIEW
For video display operation, the video port may operate as a single channel of 8/10-bit BT.656; or as a single
channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20 bit Y/C video, or 16/20-bit raw video. It may also operate
in a two channel 8/10-bit raw mode in which the two channels are locked to the same timing. Channel B is not
used during single channel operation.
For more detailed information on the DM642 Video Port peripherals, see the TMS320C64x DSP Video
Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).
112
SPRS200C
July 2002 − Revised July 2003
VIC
2.19 VIC
The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits
to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).
Typical D/A converters provide a discrete output level for every value of the digital word that is being converted.
This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by
choosing a few widely spaced output levels and interpolating values between them. The interpolating
mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output
represents the value of input code.
In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to
interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent
on the resolution needed.
When the video port is used in transport stream interface (TSI) mode [currently not supported], the VIC port
is used to control the system clock, VCXO, for MPEG transport stream.
•
•
•
Single interpolation for D/A conversion
Programmable precision from 9-to-16 bits
Interface for register accesses
For more detailed information on the DM642 VCXO interpolated control (VIC) peripheral, see the
TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629).
July 2002 − Revised July 2003
SPRS200C
113
PRODUCT PREVIEW
The VIC supports the following features:
EMAC
2.20 EMAC
The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core
processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second
(Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS)
support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data
transmission and reception.
The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient
data transmission and reception. This custom interface is referred to as the EMAC control module, and is
considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset,
interrupts, and system priority.
PRODUCT PREVIEW
For more detailed information on the DM642 EMAC peripheral, see the TMS320C6000 DSP Ethernet Media
Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature
number SPRU628).
114
SPRS200C
July 2002 − Revised July 2003
MDIO
2.21 MDIO
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module
to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation
results, and configure required parameters in the EMAC module for correct operation. The module is designed
to allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor.
PRODUCT PREVIEW
For more detailed information on the DM642 MDIO peripheral, see the TMS320C6000 DSP Ethernet Media
Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature
number SPRU628).
July 2002 − Revised July 2003
SPRS200C
115
general-purpose input/output (GPIO)
2.22 general-purpose input/output (GPIO)
To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
1
GP[x] pin is enabled
GPxDIR =
0
GP[x] pin is an input
GPxDIR =
1
GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 2−14 shows the GPIO enable bits in the GPEN register for the DM642 device. To use any of the GPx
pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled).
Default values are device-specific, so refer to Figure 2−14 for the DM642 default configuration.
31
24 23
16
Reserved
PRODUCT PREVIEW
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP15
EN
GP14
EN
GP13
EN
GP12
EN
GP11
EN
GP10
EN
GP9
EN
GP8
EN
GP7
EN
GP6
EN
GP5
EN
GP4
EN
GP3
EN
GP2
EN
GP1
EN
GP0
EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 2−14. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 2−15 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO
pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register.
By default, all the GPIO pins are configured as input pins.
31
24 23
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP15
DIR
GP14
DIR
GP13
DIR
GP12
DIR
GP11
DIR
GP10
DIR
GP9
DIR
GP8
DIR
GP7
DIR
GP6
DIR
GP5
DIR
GP4
DIR
GP3
DIR
GP2
DIR
GP1
DIR
GP0
DIR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 2−15. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
116
SPRS200C
July 2002 − Revised July 2003
Power-Supply Sequencing
2.23 Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
2.23.1
Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 2−16).
I/O Supply
DVDD
Schottky
Diode
CVDD
VSS
GND
Figure 2−16. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the
other supply is below the proper operating voltage.
2.24 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the
core supply and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,
therefore physically smaller capacitors should be used while maintaining the largest available capacitance
value. As with the selection of any component, verification of capacitor availability over the product’s
production lifetime should be considered.
July 2002 − Revised July 2003
SPRS200C
117
PRODUCT PREVIEW
C6000
DSP
Core Supply
Power-Down Operation
2.25 Power-Down Operation
The DM642 device can be powered down in three ways:
•
•
•
Power-down due to pin configuration
Power-down due to software configuration − relates to the default state of the peripheral configuration bits
in the PERCFG register.
Power-down during run-time via software configuration
On the DM642 device, the HPI, PCI, and EMAC and MDIO peripherals are controlled (selected) at the pin level
during chip reset (e.g., PCI_EN, HD5, and MAC_EN pins).
The McASP0, McBSP0, McBSP1, VP0, VP1, VP2, and I2C0 peripheral functions are selected via the
peripheral configuration (PERCFG) register bits.
PRODUCT PREVIEW
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
118
SPRS200C
July 2002 − Revised July 2003
IEEE 1149.1 JTAG Compatibility Statement
2.26 IEEE 1149.1 JTAG Compatibility Statement
The TMS320DM642 DSP requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are
required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise
the DSP’s boundary scan functionality.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive
TRST high before attempting any emulation or boundary scan operations. Following the release of RESET,
the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins
configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see
the terminal functions section of this data sheet.
For more detailed information on the DM642 JTAG emulation, see the TMS320C6000 DSP Designing for
JTAG Emulation Reference Guide (literature number SPRU641).
2.27 EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
•
•
•
•
•
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
166-MHz SDRAM for 133-MHz operation
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the DM642 EMIF peripheral, see the TMS320C6000 DSP External Memory
Interface (EMIF) Reference Guide (literature number SPRU266).
July 2002 − Revised July 2003
SPRS200C
119
PRODUCT PREVIEW
For maximum reliability, the TMS320DM642 DSP includes an internal pulldown (IPD) on the TRST pin to
ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always
be properly initialized.
Bootmode
2.28 Bootmode
The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in reset
and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states
of device pins during reset. The release of RESET starts the processor running with the prescribed device
configuration and boot mode.
The DM642 has three types of boot modes:
•
Host boot
PRODUCT PREVIEW
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the DM642 device, the HPI peripheral is used for host boot if PCI_EN =
0, and the PCI peripheral is used if PCI_EN = 1. Once the host is finished with all necessary initialization, it
must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot
configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address
0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally
“stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All
memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if
required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more
DSPINTs can be received.
•
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
•
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
120
SPRS200C
July 2002 − Revised July 2003
Electrical Specifications
3
Electrical Specifications
3.1
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)†
Supply voltage ranges:
CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V
DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Input voltage ranges:
(except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V
Output voltage ranges:
(except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), VOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V
Operating case temperature ranges, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
3.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
1.14
1.2
1.26
V
CVDD
Supply voltage, Core (-500 device)‡
Supply voltage, Core (-600 device)‡
1.36
1.4
1.44
V
DVDD
Supply voltage, I/O
3.14
3.3
3.46
V
VSS
VIH
Supply ground
0
0
0
V
High-level input voltage (except PCI)
2
VIL
VIP
Low-level input voltage (except PCI)
VIHP
VILP
High-level input voltage (PCI)
CVDD
Input voltage (PCI)
V
0.8
V
−0.5
DVDD + 0.5
V
0.5DVDD
−0.5
DVDD + 0.5
V
Low-level input voltage (PCI)
0.3DVDD
V
TC
Operating case temperature
0
90
_C
‡ Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices.
July 2002 − Revised July 2003
SPRS200C
121
PRODUCT PREVIEW
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
Electrical Specifications
3.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
TEST CONDITIONS†
PARAMETER
VOH
VOHP
High-level output voltage (except PCI)
VOL
VOLP
Low-level output voltage (except PCI)
High-level output voltage (PCI)
Low-level output voltage (PCI)
DVDD = MIN,
IOHP = −0.5 mA,
IOH = MAX
DVDD = 3.3 V
DVDD = MIN,
IOLP = 1.5 mA,
IOL = MAX
DVDD = 3.3 V
MIN
TYP
2.4
IIP
PRODUCT PREVIEW
IOH
Input current (except PCI)
Input leakage current (PCI)§
High-level output current
V
0.4
0.1DVDD¶
ICDD
Core supply current#
IDDD
Ci
I/O supply current#
uA
150
uA
VI = VSS to DVDD opposing internal
pulldown resistor‡
−150
−100
−50
uA
0 < VIP < DVDD = 3.3 V
±10
uA
EMIF, CLKOUT4, CLKOUT6, EMUx
−16
mA
Video Ports, Timer, TDO, GPIO
(Excluding GP[15:9, 2, 1]), McBSP
−8
mA
−10
−0.5¶
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
mA
Video Ports, Timer, TDO, GPIO
(Excluding GP[15:9, 2, 1]), McBSP
8
mA
10
1.5¶
mA
±10
uA
PCI/HPI
Off-state output current
±10
100
SCL0 and SDA0
IOZ
V
50
PCI/HPI
Low-level output current
V
VI = VSS to DVDD opposing internal
pullup resistor‡
SCL0 and SDA0
IOL
UNIT
V
0.9DVDD¶
VI = VSS to DVDD no opposing internal
resistor
II
MAX
VO = DVDD or 0 V
CVDD = 1.4 V, CPU clock = 600 MHz
CVDD = 1.2 V, CPU clock = 500 MHz
DVDD = 3.3 V, CPU clock = 600 MHz
Input capacitance
mA
mA
TBD
mA
TBD
mA
TBD
mA
10
pF
Co
Output capacitance
10
pF
† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§ PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
¶ These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
# Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core
and I/O activity, refer to the TMS320C6414/5/6 Power Consumption Summary application report (literature number SPRA811).
3.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
122
SPRS200C
July 2002 − Revised July 2003
Electrical Specifications
4
Parameter Information
Tester Pin Electronics
42 Ω
Data Sheet Timing Reference Point
Output
Under
Test
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
4.0 pF
Device Pin
(see note)
1.85 pF
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 4−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
4.1
Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 4−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN
for PCI output clocks.
Vref = VIH MIN (or VOH MIN or
VIHP MIN or VOHP MIN)
Vref = VIL MAX (or VOL MAX or
VILP MAX or VOLP MAX)
Figure 4−3. Rise and Fall Transition Time Voltage Reference Levels
4.2
Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
July 2002 − Revised July 2003
SPRS200C
123
PRODUCT PREVIEW
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Electrical Specifications
4.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers
may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device
and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time
margin, but also tends to improve the input hold time margins (see Table 4−1 and Figure 4−4).
Figure 4−4 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 4−1. Board-Level Timing Example (see Figure 4−4)
PRODUCT PREVIEW
NO.
DESCRIPTION
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
ECLKOUTx
(Output from DSP)
1
ECLKOUTx
(Input to External Device)
Control Signals†
(Output from DSP)
2
3
4
5
Control Signals
(Input to External Device)
6
7
Data Signals‡
(Output from External Device)
8
10
Data Signals‡
(Input to DSP)
9
11
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 4−4. Board-Level Input/Output Timings
124
SPRS200C
July 2002 − Revised July 2003
Input and Output Clocks
5
Input and Output Clocks
Table 5−1. Timing Requirements for CLKIN for −500 Devices†‡§ (see Figure 5−1)
−500
PLL MODE x12
NO.
1
2
3
PLL MODE x6
x1 (BYPASS)
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
24
33.3
13.3
33.3
13.3
33.3
tc(CLKIN)
tw(CLKINH)
Cycle time, CLKIN
Pulse duration, CLKIN high
0.4C
0.4C
0.45C
ns
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
0.4C
0.4C
0.45C
ns
4
Transition time, CLKIN
5
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
5
1
ns
ns
Table 5−2. Timing Requirements for CLKIN for −600 Devices†‡§ (see Figure 5−1)
−600
1
2
3
4
MIN
MAX
20
33.3
tc(CLKIN)
tw(CLKINH)
Cycle time, CLKIN
Pulse duration, CLKIN high
0.4C
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
0.4C
PLL MODE x6
x1 (BYPASS)
MIN
MAX
13.3
33.3
0.4C
5
MAX
13.3
33.3
0.45C
0.4C
Transition time, CLKIN
UNIT
MIN
ns
0.45C
5
ns
ns
1
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
1
4
2
CLKIN
3
4
Figure 5−1. CLKIN Timing
July 2002 − Revised July 2003
SPRS200C
125
PRODUCT PREVIEW
PLL MODE x12
NO.
Input and Output Clocks
Table 5−3. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4†‡§
(see Figure 5−2)
−500
−600
NO.
PARAMETER
CLKMODE = x1, x6, x12
MIN
1
2
3
4
UNIT
MAX
tJ(CKO4)
tw(CKO4H)
Cycle-to-cycle jitter, CLKOUT4
0
±175
ps
Pulse duration, CLKOUT4 high
2P − 0.7
2P + 0.7
ns
tw(CKO4L)
tt(CKO4)
Pulse duration, CLKOUT4 low
2P − 0.7
2P + 0.7
ns
1
ns
Transition time, CLKOUT4
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§ P = 1/CPU clock frequency in nanoseconds (ns)
1
4
PRODUCT PREVIEW
2
CLKOUT4
3
4
Figure 5−2. CLKOUT4 Timing
Table 5−4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6†‡§
(see Figure 5−3)
−500
−600
NO.
PARAMETER
CLKMODE = x1, x6, x12
MIN
1
2
3
4
UNIT
MAX
tJ(CKO6)
tw(CKO6H)
Cycle-to-cycle jitter, CLKOUT6
0
±175
ps
Pulse duration, CLKOUT6 high
3P − 0.7
3P + 0.7
ns
tw(CKO6L)
tt(CKO6)
Pulse duration, CLKOUT6 low
3P − 0.7
3P + 0.7
ns
1
ns
Transition time, CLKOUT6
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§ P = 1/CPU clock frequency in nanoseconds (ns)
1
4
2
CLKOUT6
3
4
Figure 5−3. CLKOUT6 Timing
126
SPRS200C
July 2002 − Revised July 2003
Input and Output Clocks
Table 5−5. Timing Requirements for AECLKIN for EMIFA†‡§ (see Figure 5−4)
−500
−600
NO.
1
2
3
4
tc(EKI)
tw(EKIH)
Cycle time, AECLKIN
MIN
6¶
Pulse duration, AECLKIN high
3.38
tw(EKIL)
tt(EKI)
Pulse duration, AECLKIN low
3.38
UNIT
MAX
16P
ns
ns
ns
Transition time, AECLKIN
2
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§ Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
On the 600 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 devices,
100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
1
AECLKIN
3
4
Figure 5−4. ECLKIN Timing for EMIFA
Table 5−6. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module¶#|| (see Figure 5−5)
NO.
−500
−600
PARAMETER
MIN
1
2
3
4
5
6
UNIT
tJ(EKO1)
tw(EKO1H)
Cycle-to-cycle jitter, AECLKOUT1
0
MAX
±175k
Pulse duration, AECLKOUT1 high
EH − 0.7
EH + 0.7
ns
tw(EKO1L)
tt(EKO1)
Pulse duration, AECLKOUT1 low
EL − 0.7
EL + 0.7
ns
1
ns
td(EKIH-EKO1H)
td(EKIL-EKO1L)
Delay time, AECLKIN high to AECLKOUT1 high
1
8
ns
Delay time, AECLKIN low to AECLKOUT1 low
1
8
ns
Transition time, AECLKOUT1
ps
¶ The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
# E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
|| EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
k This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
AECLKIN
1
6
5
3
2
4
4
AECLKOUT1
Figure 5−5. AECLKOUT1 Timing for the EMIFA Module
July 2002 − Revised July 2003
SPRS200C
127
PRODUCT PREVIEW
4
2
Input and Output Clocks
Table 5−7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module†‡ (see Figure 5−6)
NO.
−500
−600
PARAMETER
UNIT
MIN
1
2
3
4
5
6
MAX
0
±175§
ps
Pulse duration, AECLKOUT2 high
0.5NE − 0.7
0.5NE + 0.7
ns
tw(EKO2L)
tt(EKO2)
Pulse duration, AECLKOUT2 low
0.5NE − 0.7
0.5NE + 0.7
ns
1
ns
td(EKIH-EKO2H)
td(EKIH-EKO2L)
Delay time, ECLKIN high to AECLKOUT2 high
3
8
ns
Delay time, ECLKIN high to AECLKOUT2 low
3
8
ns
tJ(EKO2)
tw(EKO2H)
Cycle-to-cycle jitter, ECLKOUT2
Transition time, AECLKOUT2
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
§ This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
PRODUCT PREVIEW
5
6
AECLKIN
1
3
4
2
4
AECLKOUT2
Figure 5−6. AECLKOUT2 Timing for the EMIFA Module
128
SPRS200C
July 2002 − Revised July 2003
Asynchronous Memory Timing
6
Asynchronous Memory Timing
Table 6−1. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module†‡
(see Figure 6−1 and Figure 6−2)
−500
−600
NO.
MIN
3
4
6
7
UNIT
MAX
tsu(EDV-AREH)
th(AREH-EDV)
Setup time, AEDx valid before AARE high
6.5
ns
Hold time, AEDx valid after AARE high
1
ns
tsu(ARDY-EKO1H)
th(EKO1H-ARDY)
Setup time, AARDY valid before AECLKOUTx high
3
ns
Hold time, AARDY valid after AECLKOUTx high
1
ns
† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
NO.
PARAMETER
−500
−600
MIN
1
2
5
8
9
10
tosu(SELV-AREL)
toh(AREH-SELIV)
Output setup time, select signals valid to AARE low
RS * E − 1.5
Output hold time, AARE high to select signals invalid
RH * E − 1.9
td(EKO1H-AREV)
tosu(SELV-AWEL)
Delay time, AECLKOUTx high to AARE valid
Output setup time, select signals valid to AAWE low
WS * E − 1.7
toh(AWEH-SELIV)
td(EKO1H-AWEV)
Output hold time, AAWE high to select signals invalid
WH * E − 1.8
Delay time, AECLKOUTx high to AAWE valid
1
ns
ns
7
ns
ns
ns
ns
‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§ E = ECLKOUT1 period in ns for EMIFA
¶ Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
July 2002 − Revised July 2003
1.3
UNIT
MAX
7.1
SPRS200C
129
PRODUCT PREVIEW
Table 6−2. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module‡§¶ (see Figure 6−1 and Figure 6−2)
Asynchronous Memory Timing
Setup = 2
Strobe = 3
Not Ready
Hold = 2
AECLKOUTx
1
2
1
2
ACEx
ABE[7:0]
BE
2
1
AEA[22:3]
Address
3
4
AED[63:0]
1
2
Read Data
AAOE/ASDRAS/ASOE†
PRODUCT PREVIEW
5
5
AARE/ASDCAS/ASADS/ASRE†
AAWE/ASDWE/ASWE†
7
7
6
6
AARDY
† AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 6−1. Asynchronous Memory Read Timing for EMIFA
130
SPRS200C
July 2002 − Revised July 2003
Asynchronous Memory Timing
Setup = 2
Strobe = 3
Hold = 2
Not Ready
AECLKOUTx
9
8
ACEx
9
8
ABE[7:0]
BE
9
8
AEA[22:3]
Address
9
8
AED[63:0]
Write Data
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/ASRE†
AAWE/ASDWE/ASWE†
7
6
7
6
AARDY
† AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 6−2. Asynchronous Memory Write Timing for EMIFA
July 2002 − Revised July 2003
SPRS200C
131
PRODUCT PREVIEW
10
10
Programmable Synchronous Interface Timing
7
Programmable Synchronous Interface Timing
Table 7−1. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7−1)
−500
NO.
6
7
MIN
tsu(EDV-EKOxH)
th(EKOxH-EDV)
−600
MAX
MIN
MAX
UNIT
Setup time, read AEDx valid before AECLKOUTx high
3.1
2
ns
Hold time, read AEDx valid after AECLKOUTx high
1.5
1.5
ns
Table 7−2. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module† (see Figure 7−1−Figure 7−3)
−500
NO.
1
2
3
PRODUCT PREVIEW
4
5
8
9
10
11
12
PARAMETER
−600
UNIT
MIN
MAX
MIN
MAX
1.3
6.4
1.3
4.9
ns
4.9
ns
td(EKOxH-CEV)
td(EKOxH-BEV)
Delay time, AECLKOUTx high to ACEx valid
td(EKOxH-BEIV)
td(EKOxH-EAV)
Delay time, AECLKOUTx high to ABEx invalid
td(EKOxH-EAIV)
td(EKOxH-ADSV)
Delay time, AECLKOUTx high to AEAx invalid
1.3
Delay time, AECLKOUTx high to ASADS/ASRE valid
1.3
6.4
1.3
4.9
ns
td(EKOxH-OEV)
td(EKOxH-EDV)
Delay time, AECLKOUTx high to, ASOE valid
1.3
6.4
1.3
4.9
ns
4.9
ns
td(EKOxH-EDIV)
td(EKOxH-WEV)
Delay time, AECLKOUTx high to AEDx invalid
1.3
Delay time, AECLKOUTx high to ASWE valid
1.3
Delay time, AECLKOUTx high to BEx valid
6.4
1.3
Delay time, AECLKOUTx high to AEAx valid
1.3
6.4
Delay time, AECLKOUTx high to AEDx valid
ns
4.9
1.3
6.4
ns
1.3
SPRS200C
1.3
ns
ns
† The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
132
6.4
ns
4.9
July 2002 − Revised July 2003
Programmable Synchronous Interface Timing
READ latency = 2
AECLKOUTx
1
1
ACEx
ABE[7:0]
2
BE1
3
BE2
BE3
BE4
4
AEA[22:3]
EA1
5
EA3
EA2
6
AED[63:0]
EA4
7
Q1
Q2
Q3
Q4
8
8
AARE/ASDCAS/ASADS/
ASRE§
9
9
AAOE/ASDRAS/ASOE§
† The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§ AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−1. Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2)†‡
July 2002 − Revised July 2003
SPRS200C
133
PRODUCT PREVIEW
AAWE/ASDWE/ASWE§
Programmable Synchronous Interface Timing
AECLKOUTx
1
1
ACEx
3
ABE[7:0]
2
BE1
AEA[22:3]
4
EA1
EA2
EA3
EA4
10
Q1
Q2
Q3
Q4
10
AED[63:0]
AARE/ASDCAS/ASADS/ASRE§
BE2
BE3
BE4
5
11
8
8
AAOE/ASDRAS/ASOE§
12
12
PRODUCT PREVIEW
AAWE/ASDWE/ASWE§
† The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§ AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−2. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0)†‡§
134
SPRS200C
July 2002 − Revised July 2003
Programmable Synchronous Interface Timing
Write
Latency =
1‡
AECLKOUTx
1
1
ACEx
ABE[7:0]
2
BE1
AEA[22:3]
4
EA1
10
AED[63:0]
3
BE2
BE3
BE4
EA2
10
EA3
EA4
Q1
Q2
Q3
5
11
Q4
8
8
AARE/ASDCAS/ASADS/
ASRE§
AAOE/ASDRAS/ASOE§
12
12
† The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
§ AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−3. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1)†‡
July 2002 − Revised July 2003
SPRS200C
135
PRODUCT PREVIEW
AAWE/ASDWE/ASWE§
Synchronous DRAM Timing
8
Synchronous DRAM Timing
Table 8−1. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 8−1)
−500
NO.
6
7
MIN
tsu(EDV-EKO1H)
th(EKO1H-EDV)
−600
MAX
MIN
MAX
UNIT
Setup time, read AEDx valid before AECLKOUTx high
2.1
0.6
ns
Hold time, read AEDx valid after AECLKOUTx high
2.5
1.8
ns
Table 8−2. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 8−1−Figure 8−8)
−500
NO.
1
−600
UNIT
MIN
MAX
MIN
MAX
1.3
6.4
1.3
4.9
ns
4.9
ns
td(EKO1H-CEV)
td(EKO1H-BEV)
Delay time, AECLKOUTx high to ACEx valid
td(EKO1H-BEIV)
td(EKO1H-EAV)
Delay time, AECLKOUTx high to ABEx invalid
td(EKO1H-EAIV)
td(EKO1H-CASV)
Delay time, AECLKOUTx high to AEAx invalid
1.3
Delay time, AECLKOUTx high to ASDCAS valid
1.3
td(EKO1H-EDV)
td(EKO1H-EDIV)
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
1.3
Delay time, AECLKOUTx high to ASDWE valid
1.3
6.4
1.3
4.9
ns
12
td(EKO1H-WEV)
td(EKO1H-RAS)
Delay time, AECLKOUTx high to ASDRAS valid
1.3
6.4
1.3
4.9
ns
13
td(EKO1H-ACKEV)
Delay time, AECLKOUTx high to ASDCKE valid
1.3
6.4
1.3
4.9
ns
14
td(EKO1H-PDTV)
Delay time, AECLKOUTx high to PDT valid
1.3
6.4
1.3
4.9
ns
2
3
4
5
PRODUCT PREVIEW
PARAMETER
8
9
10
11
136
SPRS200C
Delay time, AECLKOUTx high to ABEx valid
6.4
1.3
Delay time, AECLKOUTx high to AEAx valid
1.3
6.4
ns
4.9
1.3
6.4
1.3
6.4
ns
ns
4.9
ns
4.9
ns
1.3
ns
July 2002 − Revised July 2003
Synchronous DRAM Timing
READ
AECLKOUTx
1
1
ACEx
2
BE1
ABE[7:0]
4
Bank
5
AEA[22:14]
4
Column
5
AEA[12:3]
4
3
BE2
BE3
BE4
5
AEA13
6
D1
AED[63:0]
7
D2
D3
D4
AARE/ASDCAS/ASADS/
ASRE†
8
8
AAWE/ASDWE/ASWE†
14
14
PDT‡
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
‡ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 8−1.
Figure 8−1. SDRAM Read Command (CAS Latency 3) for EMIFA
July 2002 − Revised July 2003
SPRS200C
137
PRODUCT PREVIEW
AAOE/ASDRAS/ASOE†
Synchronous DRAM Timing
WRITE
AECLKOUTx
1
2
2
4
ACEx
ABE[7:0]
BE1
4
3
BE2
BE3
BE4
D2
D3
D4
5
Bank
AEA[22:14]
5
4
Column
AEA[12:3]
4
5
AEA13
9
AED[63:0]
10
9
D1
PRODUCT PREVIEW
AAOE/ASDRAS/ASOE†
8
8
11
11
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
14
14
PDT‡
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as AsDCAS, ASDWE, and ASDRAS, respectively,
during SDRAM accesses.
‡ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 8−2.
Figure 8−2. SDRAM Write Command for EMIFA
138
SPRS200C
July 2002 − Revised July 2003
Synchronous DRAM Timing
ACTV
AECLKOUTx
1
1
ACEx
ABE[7:0]
4
Bank Activate
5
AEA[22:14]
4
Row Address
5
AEA[12:3]
4
Row Address
5
AEA13
AED[63:0]
12
12
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−3. SDRAM ACTV Command for EMIFA
DCAB
AECLKOUTx
1
1
4
5
12
12
11
11
ACEx
ABE[7:0]
AEA[22:14, 12:3]
AEA13
AED[63:0]
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−4. SDRAM DCAB Command for EMIFA
July 2002 − Revised July 2003
SPRS200C
139
PRODUCT PREVIEW
AAOE/ASDRAS/ASOE†
Synchronous DRAM Timing
DEAC
AECLKOUTx
1
1
ACEx
ABE[7:0]
4
5
Bank
AEA[22:14]
AEA[12:3]
4
5
12
12
11
11
AEA13
AED[63:0]
AAOE/ASDRAS/ASOE†
PRODUCT PREVIEW
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−5. SDRAM DEAC Command for EMIFA
REFR
AECLKOUTx
1
1
12
12
8
8
ACEx
ABE[7:0]
AEA[22:14, 12:3]
AEA13
AED[63:0]]
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−6. SDRAM REFR Command for EMIFA
140
SPRS200C
July 2002 − Revised July 2003
Synchronous DRAM Timing
MRS
AECLKOUTx
1
1
4
MRS value
5
12
12
8
8
11
11
ACEx
ABE[7:0]
AEA[22:3]
AED[63:0]
AAOE/ASDRAS/
ASOE†
AARE/ASDCAS/ASADS/
ASRE†
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−7. SDRAM MRS Command for EMIFA
≥ TRAS cycles
End Self-Refresh
Self Refresh
AECLKOUTx
ACEx
ABE[7:0]
AEA[22:14, 12:3]
AEA13
AED[63:0]
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/ASRE†
AAWE/ASDWE/ASWE†
13
13
ASDCKE
† AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 8−8. SDRAM Self-Refresh Timing for EMIFA
July 2002 − Revised July 2003
SPRS200C
141
PRODUCT PREVIEW
AAWE/ASDWE/ASWE†
HOLD/HOLDA Timing
9
HOLD/HOLDA Timing
Table 9−1. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module† (see Figure 9−1)
−500
NO.
MIN
3
toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low
† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
−600
MAX
E
MIN
MAX
E
UNIT
ns
Table 9−2. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module†‡§ (see Figure 9−1)
−500
NO.
1
2
4
5
PRODUCT PREVIEW
6
7
PARAMETER
MIN
−600
MIN
UNIT
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
Delay time, HOLD low to EMIFA Bus high impedance
2E
MAX
¶
2E
MAX
¶
Delay time, EMIF Bus high impedance to HOLDA low
0
2E
0
2E
ns
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
Delay time, HOLD high to EMIF Bus low impedance
2E
7E
2E
7E
ns
Delay time, EMIFA Bus low impedance to HOLDA high
0
0
Delay time, HOLD low to AECLKOUTx high impedance
2E
2E
2E
¶
ns
td(HOLDL-EKOHZ)
td(HOLDH-EKOLZ)
2E
¶
Delay time, HOLD high to AECLKOUTx low impedance
2E
7E
2E
7E
ns
ns
ns
† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
‡ EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
§ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 9−1.
¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
Owns Bus
DSP Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus†
1
4
DM642
DM642
AECLKOUTx‡
(EKxHZ = 0)
AECLKOUTx‡
(EKxHZ = 1)
6
7
† EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
‡ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 9−1.
Figure 9−1. HOLD/HOLDA Timing for EMIFA
142
SPRS200C
July 2002 − Revised July 2003
BUSREQ Timing
10
BUSREQ Timing
Table 10−1. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 10−1)
−500
NO.
1
PARAMETER
td(AEKO1H-ABUSRV)
Delay time, AECLKOUTx high to ABUSREQ valid
−600
MIN
MAX
MIN
MAX
0.6
7.1
1
5.5
UNIT
ns
AECLKOUTx
1
1
ABUSREQ
PRODUCT PREVIEW
Figure 10−1. BUSREQ Timing for EMIFA
July 2002 − Revised July 2003
SPRS200C
143
Reset Timing
11
Reset Timing
Table 11−1. Timing Requirements for Reset (see Figure 11−1)
−500
−600
NO.
MIN
1
16
tw(RST)
tsu(boot)
Width of the RESET pulse
Setup time, boot configuration bits valid before RESET high†
Hold time, boot configuration bits valid after RESET high†
UNIT
MAX
250
µs
4E or 4C‡
4E or 4C‡
ns
17
th(boot)
ns
† AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5 are the boot configuration pins during device reset.
‡ E = 1/ECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
Table 11−2. Switching Characteristics Over Recommended Operating Conditions During Reset§¶#
(see Figure 11−1)
PRODUCT PREVIEW
NO.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PARAMETER
−500
−600
UNIT
MIN
MAX
td(RSTL-ECKI)
td(RSTH-ECKI)
Delay time, RESET low to ECLKIN synchronized internally
2E
3P + 20E
ns
Delay time, RESET high to ECLKIN synchronized internally
2E
8P + 20E
ns
td(RSTL-ECKO1HZ)
td(RSTH-ECKO1V)
Delay time, RESET low to ECLKOUT1 high impedance
2E
td(RSTL-EMIFZHZ)
td(RSTH-EMIFZV)
Delay time, RESET low to EMIF Z high impedance
td(RSTL-EMIFHIV)
td(RSTH-EMIFHV)
Delay time, RESET low to EMIF high group invalid
td(RSTL-EMIFLIV)
td(RSTH-EMIFLV)
Delay time, RESET low to EMIF low group invalid
td(RSTL-LOWIV)
td(RSTH-LOWV)
Delay time, RESET low to low group invalid
td(RSTL-ZHZ)
td(RSTH-ZV)
Delay time, RESET low to Z group high impedance
Delay time, RESET high to ECLKOUT1 valid
Delay time, RESET high to EMIF Z valid
ns
2E
3P + 4E
ns
16E
8P + 20E
ns
2E
Delay time, RESET high to EMIF high group valid
ns
8P + 20E
2E
Delay time, RESET high to EMIF low group valid
8P + 20E
ns
ns
11P
0
2P
ns
ns
0
Delay time, RESET high to low group valid
Delay time, RESET high to Z group valid
ns
8P + 20E
ns
ns
8P
ns
§ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
¶ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
# EMIF Z group consists of:
AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO; all of which apply only when PCI EEPROM is enabled
(with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the
Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0,
VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0,
VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1,
VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA,
GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0],
VP1D[19:9, 6,5,1,0], and VP2D[19:0].
144
SPRS200C
July 2002 − Revised July 2003
Reset Timing
CLKOUT4
CLKOUT6
1
RESET
2
3
4
5
6
7
AECLKIN
AECLKOUT1
AECLKOUT2
EMIF Z Group†‡
8
9
10
11
EMIF Low Group†
12
13
14
15
Low Group†
Z Group†‡
17
Boot and Device
Configuration Inputs§
16
† EMIF Z group consists of:
AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO; all of which apply only when PCI EEPROM is enabled
(with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the
Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0,
VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0,
VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1,
VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA,
GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0],
VP1D[19:9, 6,5,1,0], and VP2D[19:0].
‡ If AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure
no timing contention between parameters 6, 7, 14, 15, 16, and 17.
§ Boot and Device Configurations Inputs (during reset) include: AEA[22:19],LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
Figure 11−1. Reset Timing†
July 2002 − Revised July 2003
SPRS200C
145
PRODUCT PREVIEW
EMIF High Group†
External Interrupt Timing
12
External Interrupt Timing
Table 12−1. Timing Requirements for External Interrupts† (see Figure 12−1)
−500
−600
NO.
MIN
1
tw(ILOW)
2
tw(IHIGH)
UNIT
MAX
Width of the NMI interrupt pulse low
4P
ns
Width of the EXT_INT interrupt pulse low
8P
ns
Width of the NMI interrupt pulse high
4P
ns
Width of the EXT_INT interrupt pulse high
8P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
1
2
EXT_INTx, NMI
PRODUCT PREVIEW
Figure 12−1. External/NMI Interrupt Timing
146
SPRS200C
July 2002 − Revised July 2003
Multichannel Audio Serial Port (McASP) Timing
13
Multichannel Audio Serial Port (McASP) Timing
Table 13−1. Timing Requirements for McASP (see Figure 13−1 and Figure 13−2)
−500
−600
MIN
1
2
3
4
5
tc(AHCKRX)
tw(AHCKRX)
Cycle time, AHCLKR/X
20
ns
Pulse duration, AHCLKR/X high or low
10
ns
tc(CKRX)
tw(CKRX)
Cycle time, ACLKR/X
ACLKR/X ext
33
ns
Pulse duration, ACLKR/X high or low
ACLKR/X ext
16.5
ns
ACLKR/X int
5
ns
ACLKR/X ext
5
ns
ACLKR/X int
5
ns
ACLKR/X ext
5
ns
tsu(FRXC-KRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
7
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
8
UNIT
MAX
th(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X int
5
ns
ACLKR/X ext
5
ns
ACLKR/X int
5
ns
ACLKR/X ext
5
ns
Table 13−2. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 13−1 and Figure 13−2)
NO.
−500
−600
PARAMETER
MIN
9
10
11
12
UNIT
MAX
tc(AHCKRX)
tw(AHCKRX)
Cycle time, AHCLKR/X
20
ns
Pulse duration, AHCLKR/X high or low
10
ns
tc(CKRX)
tw(CKRX)
Cycle time, ACLKR/X
ACLKR/X int
33
ns
Pulse duration, ACLKR/X high or low
ACLKR/X int
16.5
ACLKR/X int
0
10
ns
ACLKR/X ext
0
10
ns
13
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(CKRX-AXRV)
Delay time, ACLKR/X transmit edge to AXR output valid
15
tdis(CKRX−AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
July 2002 − Revised July 2003
ns
ACLKR/X int
0
10
ns
ACLKR/X ext
0
10
ns
ACLKR/X int
0
10
ns
ACLKR/X ext
0
10
ns
SPRS200C
147
PRODUCT PREVIEW
NO.
Multichannel Audio Serial Port (McASP) Timing
2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (Falling Edge Polarity)
ACLKR/X (Rising Edge Polarity)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
PRODUCT PREVIEW
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0
A1
A30 A31 B0 B1
B30 B31 C0 C1
C2 C3
C31
Figure 13−1. McASP Input Timings
148
SPRS200C
July 2002 − Revised July 2003
Multichannel Audio Serial Port (McASP) Timing
10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (Falling Edge Polarity)
ACLKR/X (Rising Edge Polarity)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
PRODUCT PREVIEW
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
13
13
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
14
AFSR/X (Slot Width, 2 Bit Delay)
14
14
14
15
14
14
AXR[n] (Data Out/Transmit)
A0
A1
A30 A31 B0 B1
B30 B31 C0
C1 C2 C3
C31
Figure 13−2. McASP Output Timings
July 2002 − Revised July 2003
SPRS200C
149
Inter-Integrated Circuits (I2C) Timing
14
Inter-Integrated Circuits (I2C) Timing
Table 14−1. Timing Requirements for I2C Timings† (see Figure 14−1)
−500
−600
STANDARD
MODE
NO.
MIN
1
tc(SCL)
2
Setup time, SCL high before SDA low (for a repeated START
tsu(SCLH-SDAL)
condition)
3
Hold time, SCL low after SDA low (for a START and a repeated
th(SCLL-SDAL)
START condition)
4
tw(SCLL)
tw(SCLH)
5
6
PRODUCT PREVIEW
7
8
9
10
11
12
Cycle time, SCL
Pulse duration, SCL low
Pulse duration, SCL high
13
14
MIN
UNIT
MAX
10
2.5
µs
4.7
0.6
µs
4
0.6
µs
4.7
1.3
µs
4
0.6
100‡
0§
µs
250
0§
tw(SDAH)
tr(SDA)
Pulse duration, SDA high between STOP and START conditions
4.7
Rise time, SDA
1000
tr(SCL)
tf(SDA)
Rise time, SCL
1000
tw(SP)
Cb#
15
MAX
tsu(SDAV-SDLH) Setup time, SDA valid before SCL high
th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices)
Fall time, SDA
300
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
FAST
MODE
300
ns
0.9¶
µs
1.3
20 + 0.1Cb#
20 + 0.1Cb#
20 + 0.1Cb#
20 + 0.1Cb#
4
ns
300
ns
300
ns
300
ns
µs
0
Capacitive load for each bus line
300
0.6
Pulse duration, spike (must be suppressed)
µs
400
50
ns
400
pF
† The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
‡ A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA−SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
§ A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
¶ The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
# Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 14−1. I2C Receive Timings
150
SPRS200C
July 2002 − Revised July 2003
Inter-Integrated Circuits (I2C) Timing
Table 14−2. Switching Characteristics for I2C Timings† (see Figure 14−2)
−500
−600
STANDARD
MODE
PARAMETER
MIN
16
17
18
19
20
21
22
23
24
25
26
27
28
MAX
FAST
MODE
MIN
UNIT
MAX
10
2.5
µs
4.7
0.6
µs
4
0.6
µs
4.7
1.3
µs
4
0.6
µs
td(SDAV-SDLH) Delay time, SDA valid to SCL high
tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices)
250
100
ns
0
0
tw(SDAH)
tr(SDA)
Pulse duration, SDA high between STOP and START conditions
4.7
Rise time, SDA
1000
1.3
20 + 0.1Cb†
tr(SCL)
tf(SDA)
Rise time, SCL
1000
Fall time, SDA
300
tc(SCL)
Cycle time, SCL
td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition)
Delay time, SDA low to SCL low (for a START and a repeated
td(SDAL-SCLL)
START condition)
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
tf(SCL)
Fall time, SCL
td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
300
4
0.9
µs
µs
300
ns
20 + 0.1Cb†
20 + 0.1Cb†
300
ns
300
ns
20 + 0.1Cb†
0.6
300
29
Cp
Capacitance for each I2C pin
10
† Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
10
26
ns
µs
pF
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 14−2. I2C Transmit Timings
July 2002 − Revised July 2003
SPRS200C
151
PRODUCT PREVIEW
NO.
Host-Port Interface (HPI) Timing
15
Host-Port Interface (HPI) Timing
Table 15−1. Timing Requirements for Host-Port Interface Cycles†‡ (see Figure 15−1 through Figure 15−8)
−500
−600
NO.
MIN
1
2
3
4
10
11
PRODUCT PREVIEW
12
tsu(SELV-HSTBL)
th(HSTBL-SELV)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
tw(HSTBL)
tw(HSTBH)
Pulse duration, HSTROBE low
tsu(SELV-HASL)
th(HASL-SELV)
13
tsu(HDV-HSTBH)
th(HSTBH-HDV)
14
th(HRDYL-HSTBL)
18
tsu(HASL-HSTBL)
th(HSTBL-HASL)
19
UNIT
MAX
5
ns
2.4
4P¶
ns
4P
ns
5
ns
Hold time, select signals§ valid after HAS low
2
ns
Setup time, host data valid before HSTROBE high
5
ns
2.8
ns
2
ns
2
ns
2.1
ns
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
ns
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§ Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
¶ Select the parameter value of 4P or 12.5 ns, whichever is larger.
Table 15−2. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles†‡ (see Figure 15−1 through Figure 15−8)
NO.
−500
−600
PARAMETER
6
td(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high#
7
td(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an HPI read
8
9
td(HDV-HRDYL)
toh(HSTBH-HDV)
15
td(HSTBH-HDHZ)
Delay time, HSTROBE high to HD high impedance
UNIT
MIN
MAX
1.3
4P + 8
ns
2
ns
Delay time, HD valid to HRDY low
−3
ns
Output hold time, HD valid after HSTROBE high
1.5
ns
12
ns
16
td(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 only)
4P + 8
ns
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
# This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
152
SPRS200C
July 2002 − Revised July 2003
Host-Port Interface (HPI) Timing
HAS
1
1
2
2
HCNTL[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
4
3
HSTROBE†
3
HCS
15
9
7
15
9
16
HD[15:0] (output)
1st half-word
6
2nd half-word
8
HRDY
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
PRODUCT PREVIEW
Figure 15−1. HPI16 Read Timing (HAS Not Used, Tied High)
HAS†
19
11
19
10
11
10
HCNTL[1:0]
11
11
10
10
HR/W
11
11
10
10
HHWIL
4
3
HSTROBE‡
18
18
HCS
15
7
9
15
16
9
HD[15:0] (output)
6
1st half-word
8
2nd half-word
HRDY
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 15−2. HPI16 Read Timing (HAS Used)
July 2002 − Revised July 2003
SPRS200C
153
Host-Port Interface (HPI) Timing
HAS
1
1
2
2
HCNTL[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
3
3
4
HSTROBE†
HCS
12
12
13
13
HD[15:0] (input)
1st half-word
2nd half-word
6
14
PRODUCT PREVIEW
HRDY
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 15−3. HPI16 Write Timing (HAS Not Used, Tied High)
19
HAS†
19
11
11
10
10
HCNTL[1:0]
11
11
10
10
HR/W
11
11
10
10
HHWIL
3
4
HSTROBE‡
18
18
HCS
12
13
12
13
HD[15:0] (input)
1st half-word
6
2nd half-word
14
HRDY
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 15−4. HPI16 Write Timing (HAS Used)
154
SPRS200C
July 2002 − Revised July 2003
Host-Port Interface (HPI) Timing
HAS
1
2
1
2
HCNTL[1:0]
HR/W
3
HSTROBE†
HCS
7
9
15
HD[31:0] (output)
6
8
HRDY
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
PRODUCT PREVIEW
Figure 15−5. HPI32 Read Timing (HAS Not Used, Tied High)
19
HAS†
11
10
HCNTL[1:0]
11
10
HR/W
18
3
HSTROBE‡
HCS
7
9
15
HD[31:0] (output)
6
8
HRDY
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 15−6. HPI32 Read Timing (HAS Used)
July 2002 − Revised July 2003
SPRS200C
155
Host-Port Interface (HPI) Timing
HAS
1
2
1
2
HCNTL[1:0]
HR/W
3
HSTROBE†
HCS
12
13
HD[31:0] (input)
6
14
HRDY
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
PRODUCT PREVIEW
Figure 15−7. HPI32 Write Timing (HAS Not Used, Tied High)
19
HAS†
11
10
HCNTL[1:0]
11
10
HR/W
3
18
HSTROBE‡
HCS
12
13
HD[31:0] (input)
6
14
HRDY
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 15−8. HPI32 Write Timing (HAS Used)
156
SPRS200C
July 2002 − Revised July 2003
Peripheral Component Interconnect (PCI) Timing
16
Peripheral Component Interconnect (PCI) Timing
Table 16−1. Timing Requirements for PCLK†‡ (see Figure 16−1)
−500 [33 MHz]
NO.
1
2
3
4
MIN
−600 [66 MHz]
MAX
30 (or 4P§)
MIN
15 (or 4P§)
tc(PCLK)
tw(PCLKH)
Cycle time, PCLK
Pulse duration, PCLK high
11
6
tw(PCLKL)
tsr(PCLK)
Pulse duration, PCLK low
11
6
∆v/∆t slew rate, PCLK
1
MAX
4
UNIT
ns
ns
ns
1.5
4
V/ns
† For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.
‡ P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns.
§ Select the parameter value, whichever is larger.
1
0.4 DVDD V MIN
Peak to Peak for
3.3V signaling
4
2
3
4
Figure 16−1. PCLK Timing
Table 16−2. Timing Requirements for PCI Reset (see Figure 16−2)
−500
−600
NO.
MIN
1
2
tw(PRST)
tsu(PCLKA-PRSTH)
Pulse duration, PRST
Setup time, PCLK active before PRST high
UNIT
MAX
1
ms
100
µs
PCLK
1
PRST
2
Figure 16−2. PCI Reset (PRST) Timing
July 2002 − Revised July 2003
SPRS200C
157
PRODUCT PREVIEW
PCLK
Peripheral Component Interconnect (PCI) Timing
Table 16−3. Timing Requirements for PCI Inputs (see Figure 16−3)
−500
33 MHz
NO.
MIN
4
tsu(IV-PCLKH)
th(IV-PCLKH)
5
−600
66 MHz
MAX
MIN
UNIT
MAX
Setup time, input valid before PCLK high
7
3
ns
Hold time, input valid after PCLK high
0
0
ns
PCLK
4
5
PCI Input
Inputs Valid
PRODUCT PREVIEW
Figure 16−3. PCI Input Timing (33-/66-MHz)
Table 16−4. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs
(see Figure 16−4)
−500
NO.
1
−600
33 MHz
PARAMETER
66 MHz
UNIT
MIN
MAX
MIN
MAX
11
2
6
td(PCLKH-OV)
td(PCLKH-OLZ)
Delay time, PCLK high to output valid
2
2
Delay time, PCLK high to output low impedance
2
3
td(PCLKH-OHZ)
Delay time, PCLK high to output high impedance
2
28
ns
ns
14
ns
PCLK
1
1
PCI Output
2
3
Figure 16−4. PCI Output Timing (33-/66-MHz)
158
SPRS200C
July 2002 − Revised July 2003
Peripheral Component Interconnect (PCI) Timing
Table 16−5. Timing Requirements for Serial EEPROM Interface (see Figure 16−5)
−500
−600
NO.
MIN
8
tsu(DIV-CLKH)
th(CLKH-DIV)
9
Setup time, XSP_DI valid before XSP_CLK high
UNIT
MAX
50
ns
0
ns
Hold time, XSP_DI valid after XSP_CLK high
Table 16−6. Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM
Interface† (see Figure 16−5)
−500
−600
PARAMETER
MIN
1
2
3
4
5
6
tw(CSL)
td(CLKL-CSL)
Pulse duration, XSP_CS low
td(CSH-CLKH)
tw(CLKH)
tw(CLKL)
tosu(DOV-CLKH)
UNIT
TYP
MAX
4092P
ns
0
ns
Delay time, XSP_CS high to XSP_CLK high
2046P
ns
Pulse duration, XSP_CLK high
2046P
ns
Pulse duration, XSP_CLK low
2046P
ns
Output setup time, XSP_DO valid after XSP_CLK high
2046P
ns
2046P
ns
Delay time, XSP_CLK low to XSP_CS low
7
toh(CLKH-DOV)
Output hold time, XSP_DO valid after XSP_CLK high
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
XSP_CS
3
4
5
XSP_CLK
6
7
XSP_DO
8
9
XSP_DI
Figure 16−5. PCI Serial EEPROM Interface Timing
July 2002 − Revised July 2003
SPRS200C
159
PRODUCT PREVIEW
NO.
Multichannel Buffered Serial Port (McBSP) Timing
17
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−1. Timing Requirements for McBSP†‡ (see Figure 17−1)
−500
−600
NO.
2
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
3
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
PRODUCT PREVIEW
CLKR int
MIN
4P§
0.5tc(CKRX) − 1¶
9
CLKR ext
1.3
CLKR int
6
CLKR ext
3
CLKR int
8
CLKR ext
0.9
CLKR int
3
CLKR ext
3.1
CLKX int
9
CLKX ext
1.3
CLKX int
6
CLKX ext
3
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§ The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for −600 devices and 66 MHz for −500 devices; therefore, the minimum
CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for −600 devices [or 15 ns (66 MHz) for −500 devices],
whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master
of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data
delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave.
¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
160
SPRS200C
July 2002 − Revised July 2003
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−2. Switching Characteristics Over Recommended Operating Conditions for McBSP†‡
(see Figure 17−1)
−500
−600
PARAMETER
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
UNIT
MIN
MAX
1.4
10
4P§¶
C − 1#
C + 1#
ns
ns
1
td(CKSH-CKRXH)
2
Cycle time, CLKR/X
CLKR/X int
3
tc(CKRX)
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
−2.1
3
CLKX int
−1.7
3
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
1.7
9
−3.9
4
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
CLKX int
12
CLKX ext
CLKX int
−2.1
−3.9 + D1||
9
4 + D2||
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
−2.1 + D1||
9 + D2||
14
td(FXH-DXV)
ns
ns
Delay time, FSX high to DX valid
FSX int
−2.3
5.6
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9
9
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
¶ The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for −600 devices and 66 MHz for −500 devices; therefore, the minimum
CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for −600 devices [or 15 ns (66 MHz) for −500 devices],
whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master
of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data
delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave.
# C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
|| Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
July 2002 − Revised July 2003
SPRS200C
161
PRODUCT PREVIEW
NO.
Multichannel Buffered Serial Port (McBSP) Timing
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
DR
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
PRODUCT PREVIEW
11
10
FSX (ext)
FSX (XDATDLY=00b)
14
13
Bit(n-1)
12
DX
Bit 0
13
(n-2)
(n-3)
Figure 17−1. McBSP Timing
Table 17−3. Timing Requirements for FSR When GSYNC = 1 (see Figure 17−2)
−500
−600
NO.
MIN
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
UNIT
MAX
Setup time, FSR high before CLKS high
4
ns
Hold time, FSR high after CLKS high
4
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 17−2. FSR Timing When GSYNC = 1
162
SPRS200C
July 2002 − Revised July 2003
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−4. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0†‡ (see Figure 17−3)
−500
−600
NO.
MASTER
MIN
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
UNIT
SLAVE
MAX
MIN
MAX
12
2 − 12P
ns
4
5 + 24P
ns
Hold time, DR valid after CLKX low
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 17−5. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 17−3)
−500
−600
PARAMETER
MASTER§
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
8
td(FXL-DXV)
Delay time, FSX low to DX valid
1
UNIT
SLAVE
MIN
MAX
T−2
T+3
MIN
MAX
ns
L−2
L+3
ns
−2
4
L−2
L+3
12P + 2.8
20P + 17
ns
ns
4P + 3
12P + 17
ns
8P + 1.8
16P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 17−3. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
July 2002 − Revised July 2003
SPRS200C
163
PRODUCT PREVIEW
NO.
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−6. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0†‡ (see Figure 17−4)
−500
−600
NO.
MASTER
MIN
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
UNIT
SLAVE
MAX
MIN
MAX
12
2 − 12P
ns
4
5 + 24P
ns
Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 17−7. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 17−4)
−500
−600
PRODUCT PREVIEW
NO.
PARAMETER
MASTER§
MIN
UNIT
SLAVE
MAX
MIN
MAX
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
−2
4 12P + 4
20P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
−2
4 12P + 3
20P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
16P + 17
ns
1
L−2
L+3
T−2
T+3
H−2
H+4
ns
ns
8P + 2
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 17−4. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
164
SPRS200C
July 2002 − Revised July 2003
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−8. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1†‡ (see Figure 17−5)
−500
−600
NO.
MASTER
MIN
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
UNIT
SLAVE
MAX
MIN
MAX
12
2 − 12P
ns
4
5 + 24P
ns
Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 17−9. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 17−5)
−500
−600
PARAMETER
MASTER§
MIN
UNIT
SLAVE
MAX
MIN
MAX
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
4P + 3
12P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2
16P + 17
ns
1
T−2
T+3
ns
H−2
H+3
ns
−2
H−2
4 12P + 4
20P + 17
H+3
ns
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 17−5. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
July 2002 − Revised July 2003
SPRS200C
165
PRODUCT PREVIEW
NO.
Multichannel Buffered Serial Port (McBSP) Timing
Table 17−10. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1†‡ (see Figure 17−6)
−500
−600
NO.
MASTER
MIN
4
tsu(DRV-CKXH)
th(CKXH-DRV)
5
Setup time, DR valid before CLKX high
UNIT
SLAVE
MAX
MIN
MAX
12
2 − 12P
ns
4
5 + 24P
ns
Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 17−11. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 17−6)
−500
−600
PRODUCT PREVIEW
NO.
PARAMETER
MASTER§
UNIT
SLAVE
MIN
MAX
MIN
MAX
H−2
H+3
ns
T−2
T+1
ns
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
−2
4 12P + 4
20P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
−2
4 12P + 3
20P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
16P + 17
ns
1
L−2
L+4
8P + 2
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
6
DX
7
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 17−6. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
166
SPRS200C
July 2002 − Revised July 2003
Video Port Timing (VP0, VP1, VP2)
18
Video Port Timing (VP0, VP1, VP2)
18.1 VCLKIN timing (Video Capture Mode)
Table 18−1. Timing Requirements for Video Capture Mode for VPxCLKINx† (see Figure 18−1)
−500
−600
NO.
MIN
1
2
3
4
UNIT
MAX
tc(VKI)
tw(VKIH)
Cycle time, VPxCLKINx
12.5
ns
Pulse duration, VPxCLKINx high
5.4
ns
tw(VKIL)
tt(VKI)
Pulse duration, VPxCLKINx low
5.4
ns
Transition time, VPxCLKINx
2
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
3
2
VPxCLKINx
4
Figure 18−1. Video Port Capture VPxCLKINx TIming
18.2 STCLK Timing
Table 18−2. Timing Requirments for STCLK† (see Figure 18−2)
−500
−600
NO.
MIN
1
2
3
4
tc(STCLK)
tw(STCLKH)
Cycle time, STCLK
tw(STCLKL)
tt(STCLK)
UNIT
MAX
33.3
ns
Pulse duration, STCLK high
16
ns
Pulse duration, STCLK low
16
ns
Transition time, STCLK
2
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
STCLK
4
Figure 18−2. STCLK Timing
July 2002 − Revised July 2003
SPRS200C
167
PRODUCT PREVIEW
4
1
Video Port Timing (VP0, VP1, VP2)
18.3 Video Data and Control Timing (Video Capture Mode)
Table 18−3. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 18−3)
−500
−600
NO.
MIN
1
2
3
4
UNIT
MAX
tsu(VDATV-VKIH) Setup time, VPxDx valid before VPxCLKINx high
th(VDATV-VKIH) Hold time, VPxDx valid after VPxCLKINx high
2.4
ns
0.5
ns
tsu(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high
th(VCTLV-VKIH) Hold time, VPxCTLx valid after VPxCLKINx high
2.4
ns
0.5
ns
VPxCLKINx
1
PRODUCT PREVIEW
2
VPxD[19:0] (Input)
3
4
VPxCTLx (Input)
Figure 18−3. Video Port Capture Data and Control Input Timing
168
SPRS200C
July 2002 − Revised July 2003
Video Port Timing (VP0, VP1, VP2)
18.4 VCLKIN Timing (Video Display Mode)
Table 18−4. Timing Requirements for Video Display Mode for VPxCLKINx† (see Figure 18−4)
−500
−600
NO.
MIN
1
2
3
4
UNIT
MAX
tc(VKI)
tw(VKIH)
Cycle time, VPxCLKINx
9
ns
Pulse duration, VPxCLKINx high
4.1
ns
tw(VKIL)
tt(VKI)
Pulse duration, VPxCLKINx low
4.1
Transition time, VPxCLKINx
ns
2
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
4
Figure 18−4. Video Port Display VPxCLKINx Timing
18.5 Video Control Input/Output and Video Display Data Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx (Video Display Mode)
Table 18−5. Timing Requirements in Video Display Mode for Video Control Input Shown With
Respect to VPxCLKINx and VPxCLKOUTx (see Figure 18−5)
−500
−600
NO.
MIN
13
14
15
UNIT
MAX
tsu(VCTLV-VKIH)
th(VCTLV-VKIH)
Setup time, VPxCTLx valid before VPxCLKINx high
2.4
ns
Hold time, VPxCTLx valid after VPxCLKINx high
0.5
ns
tsu(VCTLV-VKOH)
th(VCTLV-VKOH)
Setup time, VPxCTLx valid before VPxCLKOUTx high‡
Hold time, VPxCTLx valid after VPxCLKOUTx high‡
7.4
ns
−0.9
ns
16
‡ Assuming non-inverted VPxCLKOUTx signal.
July 2002 − Revised July 2003
SPRS200C
169
PRODUCT PREVIEW
VPxCLKINx
Video Port Timing (VP0, VP1, VP2)
Table 18−6. Switching Characteristics Over Recommended Operating Conditions in Video
Display Mode for Video Data and Control Output Shown With Respect to
VPxCLKINx and VPxCLKOUTx†‡ (see Figure 18−5)
NO.
−500
−600
PARAMETER
MIN
1
2
3
4
5
6
7
8
9
10
PRODUCT PREVIEW
11
UNIT
MAX
tc(VKO)
tw(VKOH)
Cycle time, VPxCLKOUTx
V − 0.7
V + 0.7
ns
Pulse duration, VPxCLKOUTx high
VH − 0.7
VH + 0.7
ns
tw(VKOL)
tt(VKO)
Pulse duration, VPxCLKOUTx low
VL − 0.7
VL + 0.7
ns
1
ns
td(VKIH-VKOH)
td(VKIL-VKOL)
Delay time, VPxCLKINx high to VPxCLKOUTx high§
Delay time, VPxCLKINx low to VPxCLKOUTx low§
1.4
5
ns
1.4
5
ns
td(VKIH-VKOL)
td(VKIL-VKOH)
Delay time, VPxCLKINx high to VPxCLKOUTx low
1.4
5
ns
Delay time, VPxCLKINx low to VPxCLKOUTx high
1.4
5
ns
td(VKIH-VPOUTV)
td(VKIH-VPOUTIV)
Delay time, VPxCLKINx high to VPxOUT valid¶
9
ns
td(VKOH-VPOUTV)
td(VKOH-VPOUTIV)
Transition time, VPxCLKOUTx
Delay time, VPxCLKINx high to VPxOUT invalid¶
Delay time, VPxCLKOUTx high to VPxOUT valid†¶
1.7
ns
4
ns
Delay time, VPxCLKOUTx high to VPxOUT invalid†¶
12
−0.2
† V = the video input clock (VPxCLKINx) period in ns.
‡ VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
§ Assuming non-inverted VPxCLKOUTx signal.
¶ VPxOUT consists of VPxCTLx and VPxD[19:0]
ns
VPxCLKINx
5
2
1
4
4
7
8
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
12
11
VPxCTLx,
VPxD[19:0]
(Outputs)
6
3
VPxCLKOUTx
[VCLK2P = 0]
10
9
15
16
14
13
VPxCTLx
(Input)
Figure 18−5. Video Port Display Data Output Timing and Control Input/Output Timing
With Respect to VPxCLKINx and VPxCLKOUTx
170
SPRS200C
July 2002 − Revised July 2003
Video Port Timing (VP0, VP1, VP2)
18.6 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
Table 18−7. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 18−6)
−500
−600
NO.
MIN
1
tskr(VKI)
Skew rate, VPxCLKINx before VPyCLKINy
UNIT
MAX
±500
ps
VPxCLKINx
1
VPyCLKINy
PRODUCT PREVIEW
Figure 18−6. Video Port Dual-Display Sync Timing
July 2002 − Revised July 2003
SPRS200C
171
Ethernet Media Access Controller (EMAC) Timing
19
Ethernet Media Access Controller (EMAC) Timing
Table 19−1. Timing Requirements for MRCLK (see Figure 19−1)
−500
−600
NO.
MIN
1
2
3
4
UNIT
MAX
tc(MRCLK)
tw(MRCLKH)
Cycle time, MRCLK
40
ns
Pulse duration, MRCLK high
14
ns
tw(MRCLKL)
tt(MRCLK)
Pulse duration, MRCLK low
Transition time, MRCLK†
14
ns
3
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
3
2
PRODUCT PREVIEW
MRCLK
4
Figure 19−1. MRCLK Timing (EMAC − Receive)
Table 19−2. Timing Requirements for MTCLK (see Figure 19−1)
−500
−600
NO.
MIN
1
2
3
4
UNIT
MAX
tc(MTCLK)
tw(MTCLKH)
Cycle time, MTCLK
40
ns
Pulse duration, MTCLK high
14
ns
tw(MTCLKL)
tt(MTCLK)
Pulse duration, MTCLK low
Transition time, MTCLK†
14
ns
3
ns
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
MTCLK
4
Figure 19−2. MTCLK Timing (EMAC − Transmit)
172
SPRS200C
July 2002 − Revised July 2003
Ethernet Media Access Controller (EMAC) Timing
Table 19−3. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 19−3)
NO.
1
MIN
tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high
2
th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high
† Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER.
MAX
UNIT
8
ns
8
ns
MRXD3−MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3−MRXD0 timing must be met
during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on the falling
edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00−01).
1
2
MRCLK (Input)
Figure 19−3. EMAC Receive Interface Timing
Table 19−4. Switching Characteristics Over Recommended Operating Conditions for EMAC
MII Transmit 10/100 Mbit/s‡ (see Figure 19−4)
NO.
PARAMETER
1
td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid
‡ Transmit selected signals include: MTXD3−MTXD0, and MTXEN.
MIN
MAX
5
25
UNIT
ns
MTXD3−MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and
deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 19−4. EMAC Transmit Interface Timing
July 2002 − Revised July 2003
SPRS200C
173
PRODUCT PREVIEW
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Management Data Input/Output (MDIO) Timing
20
Management Data Input/Output (MDIO) Timing
Table 20−1. Timing Requirements for MDIO Input (see Figure 20−1 and Figure 20−2)
NO.
1
MIN
MAX
UNIT
Cycle time, MDCLK
400
ns
2
tc(MDCLK)
tw(MDCLK)
Pulse duration, MDCLK high/low
180
ns
3
tt(MDCLK)
Transition time, MDCLK
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
ns
5
ns
1
MDCLK
4
PRODUCT PREVIEW
5
MDIO
(input)
Figure 20−1. MDIO Input Timing
Table 20−2. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 20−2)
NO.
7
PARAMETER
td(MDCLKL-MDIO)
MIN
Delay time, MDCLK low to MDIO data output valid
MAX
UNIT
100
ns
1
MDCLK
7
MDIO
(output)
Figure 20−2. MDIO Output Timing
174
SPRS200C
July 2002 − Revised July 2003
Timer Timing
21
Timer Timing
Table 21−1. Timing Requirements for Timer Inputs† (see Figure 21−1)
−500
−600
NO.
MIN
1
2
tw(TINPH)
tw(TINPL)
UNIT
MAX
Pulse duration, TINP high
8P
ns
Pulse duration, TINP low
8P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Table 21−2. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs†
(see Figure 21−1)
NO.
−500
−600
PARAMETER
MIN
3
4
tw(TOUTH)
tw(TOUTL)
UNIT
MAX
Pulse duration, TOUT high
8P −3
ns
Pulse duration, TOUT low
8P −3
ns
PRODUCT PREVIEW
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
TINPx
4
3
TOUTx
Figure 21−1. Timer Timing
July 2002 − Revised July 2003
SPRS200C
175
General-Purpose Input/Output (GPIO) Port Timing
22
General-Purpose Input/Output (GPIO) Port Timing
Table 22−1. Timing Requirements for GPIO Inputs†‡ (see Figure 22−1)
−500
−600
NO.
MIN
1
2
tw(GPIH)
tw(GPIL)
UNIT
MAX
Pulse duration, GPIx high
8P
ns
Pulse duration, GPIx low
8P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
Table 22−2. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs†
(see Figure 22−1)
NO.
−500
−600
PARAMETER
PRODUCT PREVIEW
MIN
3
4
tw(GPOH)
tw(GPOL)
UNIT
MAX
Pulse duration, GPOx high
32P
ns
Pulse duration, GPOx low
32P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
GPIx
4
3
GPOx
Figure 22−1. GPIO Port Timing
176
SPRS200C
July 2002 − Revised July 2003
JTAG Test-Port Timing
23
JTAG Test-Port Timing
Table 23−1. Timing Requirements for JTAG Test Port (see Figure 23−1)
−500
−600
NO.
MIN
1
UNIT
MAX
tc(TCK)
tsu(TDIV-TCKH)
Cycle time, TCK
35
ns
3
Setup time, TDI/TMS/TRST valid before TCK high
10
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
9
ns
Table 23−2. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 23−1)
2
−500
−600
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
UNIT
MIN
MAX
–3
18
ns
PRODUCT PREVIEW
NO.
1
TCK
2
2
TDO
4
3
TDI/TMS/TRST
Figure 23−1. JTAG Test-Port Timing
July 2002 − Revised July 2003
SPRS200C
177
Mechanical Data
24
Mechanical Data
24.1 Ball Grid Array Mechanical Data Drawing (GDK)
GDK (S−PBGA−N548)
PLASTIC BALL GRID ARRAY
23,10
SQ
22,90
20,00 TYP
21,10
SQ
20,90
0,80
0,40
AF
AE
AD
AC
AB
AA
Y
W
V
U
0,80
T
R
PRODUCT PREVIEW
P
N
M
L
0,40
K
A1 Corner
J
H
G
F
E
D
C
B
A
1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
Bottom View
2,80 MAX
0,50 NOM
Seating Plane
0,55
0,45
0,10
0,45
0,35
0,12
4203481-3/B 07/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
178
SPRS200C
July 2002 − Revised July 2003
Mechanical Data
Table 24−1. Thermal Resistance Characteristics (S-PBGA Package) [GDK]
°C/W
Air Flow (m/s†)
Junction-to-case
3.3
N/A
Junction-to-board
7.92
N/A
18.2
0.00
15.3
0.5
1
2
RΘJC
RΘJB
3
4
5
RΘJA
Junction-to-free air
6
7
8
PsiJT
PsiJB
Junction-to-package top
Junction-to-board
13.7
1.0
12.2
2.00
0.37
0.00
0.47
0.5
0.57
1.0
0.7
2.00
11.4
0.00
11
0.5
10.7
1.0
10.2
2.00
PRODUCT PREVIEW
NO
† m/s = meters per second
July 2002 − Revised July 2003
SPRS200C
179
Mechanical Data
24.2 Ball Grid Array Mechanical Data Drawing (GNZ)
GNZ (S−PBGA−N548)
PLASTIC BALL GRID ARRAY
27,20
SQ
26,80
25,00 TYP
1,00
PRODUCT PREVIEW
25,20
SQ
24,80
0,50
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1,00
0,50
1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
Bottom View
2,80 MAX
0,50 NOM
Seating Plane
0,70
0,50
0,10
0,60
0,40
0,15
4202595-5/E 12/02
NOTES: A.
B.
C.
D.
180
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Flip chip application only.
Substrate color may vary.
SPRS200C
July 2002 − Revised July 2003
Mechanical Data
Table 24−2. Thermal Resistance Characteristics (S-PBGA Package) [GNZ]
°C/W
Air Flow (m/s†)
Junction-to-case
3.3
N/A
Junction-to-board
7.46
N/A
17.4
0.00
14.0
0.5
1
2
RΘJC
RΘJB
3
4
5
RΘJA
Junction-to-free air
6
7
8
PsiJT
PsiJB
Junction-to-package top
Junction-to-board
12.3
1.0
10.8
2.00
0.37
0.00
0.47
0.5
0.57
1.0
0.7
2.00
11.4
0.00
11
0.5
10.7
1.0
10.2
2.00
PRODUCT PREVIEW
NO
† m/s = meters per second
July 2002 − Revised July 2003
SPRS200C
181