ETC Z90T361PZ016SC

Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
Product Specification
PS005901-1100
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAmilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
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© 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
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PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
iii
Table of Contents
1
Overview ........................................................................................... 1
1.1
1.2
1.3
1.4
2
Operation .......................................................................................... 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
3
Block Diagram ................................................................................. 3
Pin Assignments .............................................................................. 4
Pin Descriptions ............................................................................... 5
Development Tools .......................................................................... 7
CPU Description .............................................................................. 8
Memory (ROM and RAM) .............................................................. 14
Clock Circuit Description ................................................................ 16
Reset Conditions ........................................................................... 18
Power Management ....................................................................... 20
I/O Port Configurations .................................................................. 20
Interrupts ........................................................................................ 22
Timers ............................................................................................ 23
ADC ............................................................................................... 24
Pulse Width Modulation ................................................................. 26
I2C Interface .................................................................................. 27
On-Screen Display (OSD) ............................................................. 32
Cursor ............................................................................................ 39
Color Palette Assignment .............................................................. 43
Other Functions ............................................................................. 44
Register Groups .............................................................................. 46
3.1
3.2
3.3
3.4
3.5
Register Description ...................................................................... 47
Bank0 (I/O Ports, I2C Interface, PLL Frequency, Cursor)
Control Registers .................................................................. 48
Bank1 (Control Registers) ............................................................. 53
Bank2 (PWM Registers) ................................................................ 67
Bank3 (On Screen Display [OSD] registers) .................................. 69
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
iv
4
Instruction Set ................................................................................. 81
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Instruction Summary ...................................................................... 81
Instruction Operands ..................................................................... 84
Instruction Format .......................................................................... 86
Instruction Bit Codes ...................................................................... 87
Instruction Format Examples ......................................................... 91
Instruction Timing .......................................................................... 97
Instruction Op Codes ..................................................................... 98
5
System Design Considerations ..................................................... 169
6
Electrical Characteristics ............................................................... 171
6.1
6.2
6.3
DC Peripherals ............................................................................ 172
AC Characteristics ....................................................................... 174
ANALOG RGB ............................................................................. 175
7
Packaging ..................................................................................... 176
8
Ordering Information ..................................................................... 178
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
v
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Block Diagram.............................................................................................. 3
52-Pin SDIP Pinout ...................................................................................... 4
Code Development Environment ................................................................. 7
AR Register Format ...................................................................................12
RAM, ROM, and Pointer Architecture ........................................................14
ROM Map ...................................................................................................15
RAM Allocation ..........................................................................................16
Clock Switching Block Diagram (8 -16 MHz) .............................................17
32 KHz Oscillator Recommended Circuit ...................................................17
Bidirectional Port Pins ................................................................................21
Bidirectional Pins Multiplexed with I2C Port ...............................................21
Bidirectional Pins Multiplexed with ADC Inputs .........................................22
IR Capture Register Block Diagram ...........................................................23
Z90T361/6 ADC Block Diagram .................................................................25
ADC Data Packing .....................................................................................26
Master Mode ..............................................................................................30
Slave Mode ................................................................................................31
Data Flow ..................................................................................................33
Blank and R, G, B Outputs in Digital Mode ................................................33
R, G, and B Outputs in Analog (Palette) Mode ..........................................34
Character Expansion .................................................................................35
Table Settings ............................................................................................37
Cursor ........................................................................................................39
Programmable Palette Control at AR Register ..........................................43
IR Capture Register Input ..........................................................................44
Loop Filter Pin Configuration .....................................................................44
Pipeline Execution .....................................................................................97
System Block Diagram .............................................................................170
Recommended Application Schematics ..................................................175
52-Pin SDIP Package Dimensions ..........................................................176
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
vi
List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Z90T366 or Z90T361 Pin Description ......................................................... 5
Internal Registers ........................................................................................ 9
Status Register ........................................................................................... 9
Ram Pointer Loop Description .................................................................. 10
Additional Control Registers ..................................................................... 13
Reset Conditions ...................................................................................... 18
ADC Inputs Typical Range ....................................................................... 24
Master I2C Bus Bit Rates ......................................................................... 27
Master I2C Bus Interface Commands ....................................................... 28
Slave I2C Bus Interface Commands ......................................................... 29
Character Expansion Register .................................................................. 36
Attribute Assignment ................................................................................. 38
Cursor Parameters ................................................................................... 40
Memory Allocation for Cursor Bitmap ....................................................... 41
Fixed Palette Color Assignment ............................................................... 43
R4(1)<e:d> Settings .................................................................................. 45
Register Summary .................................................................................... 46
Bank Assignments .................................................................................... 47
Register1, Bank0, Cursor Palette ............................................................. 48
Register2, Bank0, PLL Frequency Data Register ..................................... 48
Register3, Bank0, I2C Interface Register ................................................. 50
Register5, Bank0, Port 1 Data Register .................................................... 51
Register4, Bank0, Port 0 Data Register .................................................... 51
Register6, Bank0, Port 0 Direction Register ............................................. 52
Register7, Bank0, Port 1 Direction Register ............................................. 52
Register0, Bank1, Clamp Position Register .............................................. 53
Register1, Bank1, Speed Control Register ............................................... 55
Register2, Bank1, WDT/STOP (write only) and
9-bit Counter (read only) Control Register ....................................... 58
Register3, Bank1, Standard Control Register ........................................... 58
Register4, Bank1, ADC Control Register .................................................. 60
Register5, Bank1,Timer Control Register ................................................. 61
Register6, Bank1, Clock Switch Control Register ..................................... 63
Register7, Bank1, Interrupts/WDT/SMR Control Register ........................ 66
Interrupt Priority ........................................................................................ 67
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
vii
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Register0–Register5, Bank 2, PWM 1–6 Registers .................................. 67
Register6, Bank 2, Shadow Control Register ........................................... 68
Register7, Bank 2, CGROM Offset Register ........................................... 69
Register0–Register1, Bank 3, Write Operation, Shift Registers ............... 70
Register0–Register2, Bank 3, Read Operation,
Character Multiple Registers ............................................................. 70
Register2, Bank 3, Attributes Register, Write Operation .......................... 71
Register3, Bank 3, Write Operation, Attribute Data Register .................... 73
Register3, Bank 3, Read Operation, Attributes Register ........................ 73
Register 3, Bank 3, Display Character Format for
Attribute Data Register, OSD Mode Write Operation ........................ 74
Register 3, Bank 3, Control Character Format for
Attribute Data Register, OSD Mode Write Operation ........................ 75
Register 3, Bank 3, Display Character Format for
Attribute Data Register, Write Operation CCD Mode ........................ 76
Register 3, Bank 3, Control Character Format for
Attribute Data Register, CCD Mode, Write Operation ....................... 76
Register4, Bank 3, OSD Control Register ................................................ 77
Register5, Bank 3, Capture Register, Read Operation ............................. 78
Register6, Bank 3, Palette Control Register ............................................. 79
Register7, Bank 3, Output Palette Control Register ................................. 80
Instruction Format Mnemonics ................................................................. 81
Accumulator Modification Instructions ...................................................... 82
Arithmetic Instructions .............................................................................. 82
Bit Manipulation Instructions ..................................................................... 82
Load Instructions ...................................................................................... 83
Logical Instructions ................................................................................... 83
Program Control Instructions .................................................................... 83
Rotate and Shift Instructions ..................................................................... 83
Instruction Operand Summary .................................................................. 84
Instruction Mnemonics/Operands ............................................................. 85
Condition Code Bits .................................................................................. 87
Accumulator Modification Bits ................................................................... 88
Flag Modification Bits ................................................................................ 89
Register Pointer/ Data Pointer Bits ........................................................... 90
Register Bits ............................................................................................. 90
General Instruction Format ....................................................................... 93
Accumulator Modification Format ............................................................. 93
Flag Modification Format ........................................................................... 94
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
viii
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Direct Internal Addressing Format ............................................................ 95
Short Immediate Addressing Format ........................................................ 95
Long Immediate Addressing Format ......................................................... 96
Jump and Call Instruction Formats ........................................................... 96
Instruction Op Codes ................................................................................ 98
Instruction Descriptions .......................................................................... 103
Instruction Format Mnemonics ............................................................... 103
Absolute Maximum and Minimum Ratings ............................................. 171
DC Characteristics .................................................................................. 171
R, G, and B Analog Output ..................................................................... 172
ADC0/Small Range* ............................................................................... 173
AC Characteristics .................................................................................. 174
ADC1-ADC4/Full range .......................................................................... 174
RGB Voltage Specification ..................................................................... 175
RGB Time Specification .......................................................................... 175
Controlling Dimensions ........................................................................... 177
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
1
Z90T366 ROM and Z90T361 OTP eZVision
64 KWord Television Controller with OSD
1
Overview
The eZVision Z90T366 and Z90T361 are the ROM and one-time programmable
(OTP) versions of a Television Controller with On-Screen Display (OSD) that
contains 64 KWords of program memory and 1 Kword of RAM.
ZiLOG’s eZVision Z90T366 TV controller with On-Screen Display (OSD) is a
highly-integrated solution for television design. The Z90T366 boasts
a high-speed 16-bit, advanced Digital Signal Processor (DSP) and powerful OSD
engine. Flexible and sophisticated, the OSD includes video display attributes,
semi-transparency, programmable color palettes, and a hardware cursor for easy
user interface. The Z90T366 supports parental control, closed captioning, and
Extended Data System (XDS).
The Z90T366 is an ideal choice for mainstream television sets for both PAL and
NTSC standards.
The Z90T36x family consists of the following two basic devices:
•
•
the Z90T366 masked ROM
the Z90T361 One Time Programmable (OTP) device
In addition, Zilog provides a comprehensive development suite for television
system developers including an emulator capable of OTP programming, OSD
evaluation board, C-compiler, Application Programmer Interface (API), ZiLOG’s
Developer Studio (ZDS) software, and Graphics User Interface (GUI) OSD screen
design tools. These tools enable TV developers to work efﬁciently and effectively
to bring new products to market.
•
The eZVision Z90T361 is the OTP controller used to develop code and
prototypes for speciﬁc television applications or initial limited production.
Program ROM and Character Generation ROM (CGROM) in the Z90T361
are both programmable.
•
The eZVision Z90T366 incorporates the ROM code developed by the
customer with the Z90T361. Customer code is masked into both program
ROM and CGROM.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
2
The Z90T366 Television Controller with OSD is based on ZiLOG’s Z89C00
processor core. The Z89C00 is a 16-bit, fractional, two’s complement CMOS
Digital Signal Processor (DSP). Most instructions are accomplished in a single
clock cycle. This processor features a 24-bit Arithmetic Logic Unit (ALU) and a
24-bit Accumulator. The processor also contains a six-level stack and three
vectored interrupts.
The Z90T366 contains 64 KWords of program ROM and 1 KWord of on-chip data
RAM. Program ROM space can hold an unlimited number of characters with a
16x16, 16x18, and 16x20 programmable matrix in relocated Character
Generation ROM (CGROM), which is only restricted by the available ROM. In
addition, the Z90T366 contains four external register banks with eight registers
each. Additional Control Registers (AR) are available to control new peripherals
like palette banks and memory management.
An internal 24-MHz/2 system clock has a Phase Lock Loop (PLL) driven by an
external 32.768-KHz crystal.
Six-channels of 4-bit Analog to Digital Converters (ADC) support the following:
•
•
•
Analog control front panel buttons
Audio level input
Vertical Blank Interval (VBI) data capture
Six Pulse Width Modulator (PWM) outputs allow low-cost digital-to-analog
conversion. The PWMs have 8-bit resolution to control video and audio attributes.
A Master/Slave I2C (Inter Integrated Circuit) bus interface provides serial system
interconnect to common peripheral functions.
Twenty-four programmable I/O pins provide ﬂexibility for other digital input/output
functions.
An IR (InfraRed) remote capture register facilitates reliable remote data capture.
On-chip Horizontal Synchronization (HSYNC) and Vertical Synchronization
(VSYNC) circuits generate a video time base (typically used for VCR and set-top
applications) in the absence of an available video signal.
Micro-programmable OSD generation logic provides ﬂexibility to tailor OSD
features and functions. In addition to normal OSD functions, Closed Caption is
supported in accordance with FCC Report and Order on GEN Docket No. 91-1,
dated April 12, 1991. Expanded Data Service (XDS) capability is supported as
well.
The Z90T366 is packaged in a 52-pin SDIP package.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
3
Figure 1 is a block diagram of the internal structure of the chip. Figure 2 illustrates
the pin locations, and Table 1 describes the function of each pin.
1.1
Block Diagram
IR
IR IN
PWM
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
4-bit
ADC
Port00
Port02
Port03
Port04
Port05
Port06
Port07
Port08
Port09
Port0A
Port0B
Port0C
Port0D
I2 C
I2CMC1
I2CMD1
I2CMC2
I2CMD2
OSD
Engine
R
G
B
OVL
SOVL
Control
Reg Addr/Data
RAM
Address
1
Data
Figure 1
Port 1
Port10
Port11
Port12
Port13
Port14
Port15
Port16
Port17
Port18
Port 0X
XTAL1
XTAL2
LPF
HSYNC
VSYNC
RESET
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CPU
Core
ROM Addr
ROM Data
OTP/
ROM
Block Diagram
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
4
1.2
Pin Assignments
Port03
Port0B/I2CMC1
Port0C/I2CMD1
Port0D
Port12/I2CMD2
Port11/I2CMC2
Port0E
Port10/R0
ADC5
GND
VCC
CVI/ADC0
LPF
AGND
Port04/ADC0
Port13/G1
Port14/B0
Port05/ADC3
HSYNC
VSYNC
Port00/ADC2
Port17/ADC1
Port15/B1
IRIN
Port16/SCLK
Port18/G0
Figure 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Z90T366
or
Z90T361
Top View
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PWM5
Port0A
Port09
PWM4
PWM3
Port08/R1
PWM2
PWM1
VCC
GND
Port0F/SOVL
OVL
B
G
R
AVCC
AGND
XTAL2
XTAL1
Reset
Port02
PWM6
VCC
GND
Port07/CSYNC
Port06/Counter
52-Pin SDIP Pinout
For simplicity, both the Z90T366 and Z90T361 will be referred to as the Z90T366.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
5
1.3
Pin Descriptions
Table 1 Z90T366 or Z90T361 Pin Description
Symbol
Pin #
Function
Port03
1
Port 03
2
Direction
I/O
2
Port0B/I CMC1
2
Port 0B or Master1 I C clock
I/O
Port0C/I2CMD1
3
Port 0C or Master1 I2C data
I/O
Port0D
4
Port 0D
I/O
Port12/I2CMD2
5
Port 12 or Master2 I2C data
2
2
I/O
Port11/I CMC2
6
Port 11 or Master1 I C clock
I/O
Port0E
7
Port 0E
I/O
Port10/R0
8
Port 10 or digital RGB output, red
I/O
ADC5
9
ADC5 input
I
GND
10
Digital ground
Power
VCC
11
Digital Vcc
Power
CVI/ADC0
12
ADC0 input or Composite Video Input
AI
LPF
13
Loop ﬁlter
AI/AO
AGND
14
Analog ground
Power
Port04/ADC0
15
Port 04 or ADC0 input
I/O or AI
Port13/G1
16
Port 13 or digital RGB output, green
I/O
Port14/B0
17
Port 14 or digital RGB output, blue
I/O
Port05/ADC3
18
Port 05 or ADC3 input
I/O or AI
HSYNC
19
Horizontal sync
I/O
VSYNC
20
Vertical sync
I/O
Port00/ADC2
21
Port 00 or ADC2 input
I/O or AI
Port17/ADC1
22
Port 17 or ADC1 input
I/O or AI
Port15/B1
23
Port 15 or digital RGB output, blue
I/O
IRIN
24
Infrared remote capture input
I
Port16/SCLK
25
Port 16 or internal process SCLK
I/O
Port18/G0
26
Port 18 or digital RGB output, green
I/O
Port06/CNTR
27
Port 06 or counter input
I/O
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
6
Table 1 Z90T366 or Z90T361 Pin Description (Continued)
Symbol
Pin #
Function
Direction
Port07/CSYNC
28
Port 07 or composite sync output
I/O
GND
29
Digital ground
Power
VCC
30
Digital Vcc
Power
PWM6
31
8-bit PWM output
O
Port02
32
Port 02
I/O
RESET
33
Reset
I
XTAL1
34
Crystal oscillator input
AI
XTAL2
35
Crystal oscillator output
AO
AGND
36
Analog ground
Power
AVCC
37
Analog Vcc
Power
R
38
OSD video output to drive Red
O/AO
G
39
OSD video output to drive Green
O/ AO
B
40
OSD video output to drive Blue
O/AO
OVL
41
OSD overlay output
O
Port0F/SOVL
42
Port 0F or OSD semi-transparency overlay output I/O
GND
43
Digital ground
Power
VCC
44
Digital Vcc
Power
PWM1
45
8-bit PWM output
O
PWM2
46
8-bit PWM output
O
Port08/R1
47
Port 08 or digital RGB output, red
I/O
PWM3
48
8-bit PWM output
O
PWM4
49
8-bit PWM output
O
Port09
50
Port 09
I/O
Port0A
51
Port 0A
I/O
PWM5
52
8-bit PWM output
O
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
7
1.4
Development Tools
The Z90T361 requires ZiLOG’s Z90369ZEM Emulator with its proprietary ZiLOG
Developer Studio (ZDS) software for programing. To view code effects, the
emulator uses a ZiLOG On-Screen Display (ZOSD) board that connects directly
to a television screen. Refer to Figure 3.
Z90369 In-Circuit
Emulation Kit
Z9034600ZCO
ZOSD Board
Z90379
Z90T361
Develop
code on PC
Download Code to
Z90379 ICE chip
Converts to
Video Display
Review Code
on TV Display
Program the
Z90T361 OTP
Figure 3
Code Development Environment
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
8
2
Operation
2.1
CPU Description
The Z89C00 core is a high-performance DSP that has a modiﬁed Harvard-type
architecture with separate program and data memories. The design has been
optimized for processing power.
The Z89C00 used in the Z90T366 device has been modiﬁed. The multiplier is
disabled. However, the X and Y registers in the multiplier are still available and
can be used as general-purpose registers. Refer to ZiLOG’s Z89C00
documentation.
ALU
The 24-bit ALU has two input ports, one of which is connected to the output of the
24-bit Accumulator. The other input is connected to the 24-bit P-Bus; the upper
16 bits are connected to the 16-bit D-Bus.
Instruction Timing
Several instructions are executed in one machine cycle. Lenghty immediate
instructions and Jump or Call instructions are executed in two machine cycles.
When the program memory is referenced in internal RAM indirect mode, it
requires three machine cycles. An additional machine cycle is required if the
program counter (PC) is selected as the destination of a data transfer instruction.
This only occurs with a register indirect branch instruction.
Hardware Stack
A six-level hardware stack is connected to the D-Bus to hold subroutine return
addresses or data. The CALL instruction pushes PC+2 onto the stack. The RET
instruction returns the contents of the stack to the program counter.
CPU Registers
The Z90T366 has 11 physical internal registers and four banks of eight external
registers. In addition, it has nine virtual registers. The 11 internal registers are
deﬁned in Table 2, and the status register is deﬁned in Table 3.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
9
Internal Registers
Table 2
Internal Registers
Register
Register Deﬁnition
Size
X
General purpose register
16 bits
Y
General purpose register
16 bits
A
Accumulator
24 bits
SR
Status Register
16 bits
Pn:b
Six RAM Address Pointers
8 bits each
PC
Program Counter
16 bits
Table 3
Status Register
Bit/Field
Bit Position
R/W
Description
N
15
R
ALU Negative
OV
14
R
ALU Overﬂow
Z
13
R
ALU Zero
C
12
R
Carry
Reserved
11
R
Reserved
Reserved
10
R
Reserved
Reserved
9
R
Reserved
OP
8
R/W
Overﬂow Protection
IE
7
R/W
Interrupt Enable
Register Bank Selector
6,5
R/W
00 Register Bank 0
01 Register Bank 1
10 Register Bank 2
11 Register Bank 3
SFD
4,3
R/W
“Short Form Direct” Bits
RPL
2-0
R/W
RAM Pointer Loop Size
X and Y are 16-bit general purpose registers.
A is a 24-bit Accumulator. The output of the ALU is sent to this register. When
16-bit data are transferred into this register, it goes into the 16 MSBs and the least
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
10
signiﬁcant eight bits are set to zero. Only the upper 16 bits are transferred to the
destination register when the Accumulator is selected as a source register in
transfer instruction.
SR is the Status Register that contains the ALU status and the control bits listed in
Table 3. The status register is always read in its entirety. S15-S12 are set/reset by
the hardware and can only be read through software. They are set or reset by the
ALU after an operation.
S8-S0 can be written by software. S8, if 0 (reset), allows the hardware to overﬂow.
If S8 is set, the hardware clamps at maximum positive or negative values instead
of overﬂowing. S7 enables interrupts. S6–S5 are used for “short form direct”
addresses, which are described below. The deﬁnitions of S2-S0 are listed in
Table 4.
Table 4
Ram Pointer Loop Description
S2
S1
S0
Loop Size
0
0
0
256
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Pn:b are the pointer registers for accessing data RAM.
(n= 0, 1, 2 refer to the pointer number)
(b = 0, 1 refers to RAM bank 0 or 1).
They can be read from or written to directly and can point directly to locations in
data RAM or indirectly to Program Memory.
PC is the Program Counter. When this register is assigned as a destination
register, one NOP machine cycle is automatically added to adjust the pipeline
timing.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
11
External Registers
The Z90T366 module is capable of accessing eight external registers directly
using only the three external register address signals that are normally available.
Two user bits (Status register S6-S5) are combined with the register address
signals to provide the ability to address four banks of eight registers each. The
registers most critical for speed are located together in Bank 3. In this
speciﬁcation, all external registers are referred to
RX(Y)<Z>
where:
X is a register number within a register bank;
Y is a bank number; and
Z is a bit ﬁeld number
An external register bank can be selected by setting bits 6 and 5 in the status
register to deﬁne the bank, then specifying the address of the register on the
external register address bus.
External registers reside on the chip and are used to control the operation of all
the peripheral modules in the device. By reading or writing to the ﬁelds in the
external registers, the user can interact with the peripheral devices on the chip.
Virtual Registers
BUS is a read-only register that, when accessed, returns the contents of the DBus. It is a virtual register. (Physical RAM does not exist on the chip.)
Dn:b These eight data pointers refer to possible locations in RAM that can be
used as pointers to locations in program memory. The programmer decides which
location to choose two bits from in the status register and which two bits in the
operand. This means only the lower 16 possible locations in RAM can be
speciﬁed. At any one time there are eight usable pointers, four per bank, and the
four pointers are in consecutive locations in RAM.
For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refers
to locations 4/5/6/7 in RAM bank 0.
Note: When the data pointers are being written to, a number is
actually being loaded to Data RAM, so they can be used as a
limited method for writing to RAM.
Additional Control Registers (AR)
Additional Control Registers (AR) control new peripheral blocks like palette banks
and memory management. To activate ARs, R0(1)<b> must be set to “1.” ARs can
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
12
be disabled by setting R0(1)<b> = 0, (POR) for software backward compatibility or
if access to RAM location 1FFh is required.
The 128 eight-bit control registers (referred as AR or ARx<y:z>) use RAMmapped I/O access. Location 1FFh in RAM is used to address up to 128 bytewidth ARs. The AR number and written data are encoded into the data ﬁeld as
illustrated in Figure 4.
15
14
8
DWB
7
AR number
Figure 4
0
Data
AR Register Format
When writing to address 1FFh, the Data Write Bit (DWB) and AR number are
latched, depending on whether the DWB data ﬁeld is either written to the selected
port (latched) or discarded (not latched). The AR number and corresponding data
are read after reading from the previously latched DWB address 1FFh.
To write to the AR, the data must be written to address 1FFh; DWB must be set to
“1,” the port number must be speciﬁed in bits 8–14, and actual data must be
speciﬁed in bits 0–7.
Example
LD
LD
A, #(%8000 | 29 <<8 | %57); write 57 (hex) into the AR29
%1FF, A;
The DWB and port number are latched for further reading if necessary.
To read from the AR, the address must be previously latched by writing it to
address 1FFh with DWB set to “0.” Bits 0–7 have no meaning. Because the bits
are not going to be written in this mode, only the port number is latched.
Example
LD
LD
LD
A, #(%0 | 30<<8 | %0); DWB=0, latch AR30, data is not written
%1FF, A;
A, %1FF; read from AR30-%1EXX, where XX is current content
At least one cycle delay (NOP) is required between two consecutive accesses to
the AR. If access is performed by a two-cycle instruction, no delay is necessary.
External memory must exhibit access times of less than 60 ns. Table 5 lists the
additional control registers.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
13
Table 5
Additional Control Registers
AR #
Name
Bit position
Data
Function
0
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color0—R1R0G1G0B1B0
1
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color1—R1R0G1G0B1B0
2
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color2—R1R0G1G0B1B0
3
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color3—R1R0G1G0B1B0
4
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color4—R1R0G1G0B1B0
5
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color5—R1R0G1G0B1B0
6
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color6—R1R0G1G0B1B0
7
Palette_8
76-------543210
Dh
DDh
Reserved
Palette8/Color7—R1R0G1G0B1B0
8–15
Palette_9
76543210
DDh
Same as AR 0–7 for Palette9
16–23
Palette_10
76543210
DDh
Same as AR 0–7 for Palette10
24–31
Palette_11
76543210
DDh
Same as AR 0–7 for Palette11
32–39
Palette_12
76543210
DDh
Same as AR 0–7 for Palette12
40–47
Palette_13
76543210
DDh
Same as AR 0–7 for Palette13
48–55
Palette_14
76543210
DDh
Same as AR 0–7 for Palette14
56–63
Palette_15
76543210
DDh
Same as AR 0–7 for Palette15
64–123
124
Reserved
PgLocation0
7-------6------
125
PgLocation1
PgLocation2
Page0 is located internally–POR
Page0 is located externally
Internal ROM is enabled–POR
Internal ROM is disabled (low power
consumption)
Page0—external (physical) page number
--543210
DDh
7-------
0
1
0
1
DDh
Page1 is located internally–POR
Page1 is located externally
Reserved
Page1—external (physical) page number
DDh
Same as above for Page2
-6-------543210
126
0
1
0
1
76543210
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
14
Table 5
Additional Control Registers (Continued)
AR #
Name
Bit position
Data
Function
127
PgLocation3
76543210
DDh
Same as above for Page3
RAM Addressing
The addresses in RAM can be speciﬁed in one of three ways: RAM, ROM,
Pointers. Refer to Figure 5.
RAM Pointers
P0:0
P1:0
P2:0
RAM 0
FF h
256X16-bit
37H
RAM Pointers
RAM1
FFh
P0:1
256X16-BIT
P1:1
P2:1
@P1:0
37h
0321h
0321h
04h
S4/S3 = 01
00h
00h
Data Pointers
Internal ROM
8000h
D0:0
64Kx16-bit
@@P1:0
0321h
1234h
0321h
D0:1
D1:0
D1:1
D2:0
D2:1
D3:0
D3:1
@D0:1
0000h
Figure 5
2.2
RAM, ROM, and Pointer Architecture
Memory (ROM and RAM)
The Z90T366 has 64K words of Read Only Memory (ROM) and 1K words of
Random Access Memory (RAM).
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
15
ROM
The 64K words mask ROM is designed to provide storage for both program codes
and Character set Graphic pixel matrices (CGROM). The address boundary
between these applications is dependent on the storage required for character
graphics.
The Program ROM (PGMROM) section can, in theory, be accessed anywhere in
the addressable ROM space; however, because CGROM usually starts at
location 0000h, program ROM resides in the higher address locations. The
maximum available ROM space for program memory depends on the ROM
reserved for CGROM (for an application).
CGROM can be placed anywhere in the 64K ROM address space by setting the
CGROM address offset register R7(2). This offset is added to the character
address before accessing ROM. By modifying the CGROM offset, several fonts
can be accessed (limited by ROM size only). When reset, R7(2) =0 (no offset) for
backward compatibility with existing software. Refer to Figure 6.
64K
Int0 vector
Int1 vector
Int2 vector
Reset vector
FFFFh
FFFEh
FFFDh
FFFCh
FFFBh
Program ROM or CGROM
Up to 5K
CGROM—Bank 0, Scan lines 19, 20
Up to 4.5K
or Bank1 or Program ROM
CGROM—Bank 0, Scan lines 17, 18
or Bank 1, or Program ROM
4K
Program ROM
Up to 4K
CGROM-Bank 0 (n Characters)
Scan lines 1-16
Figure 6
1400h
13FFh
1200h
11FFh
1000h
0FFFh
10*nh
10*nh-1
0000h
ROM Map
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
16
RAM
The 1K words RAM is organized in four banks of 256 words consisting of 16 bits
each. Bank1.0 is always accessible. Bank0.0 is mapped to other bank(s); only
one page from 0.X is active through bit selection. See Figure 7.
256
256
256
words
Bank1.0
Figure 7
2.3
256
words
Bank0.2
Bank0.1
Bank0.0
RAM Allocation
Clock Circuit Description
The processor is able to operate from several clock sources:
•
•
•
Primary Phase Lock Loop VCO source (PVCO)
Secondary Phase Lock Loop (SVCO)
32.768-KHz oscillator clock (OSC)
In addition, the processor clock can be halted temporarily to select the clock
source or access ROM without disrupting normal operation of the processor.
An external crystal controls the internal 32.768-KHz oscillator. The crystal is used
as the clock reference for the internal Phase Locked Loop (PLL). The PLL
provides the internal PVCO clock for processor operation. The System Clock
(SCLK) is generated internally by dividing the frequency of an appropriate
oscillator (PVCO) by 2. The frequency of the SCLK after Power On Reset (POR)
is 12.058 MHz.
The SCLK signal can be sent to the Port16 output pin under software control by
setting bit 9 in register R3(1). The SVCO must be used as the system clock when
the OSD is generated.
The clock switch control register R6(1) deﬁnes the source of the SCLK for the
Z90T366 core. The block diagram in Figure 8 represents the clock switch circuit.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
17
Clock switching is not recommended. This feature is only for
Note: advanced users.
12-MHz
SVCO
SVCO/PVCO
SWITCH1
32.768-KHz
oscillator
12 MHz
PVCO
PLL
Fast/Slow
No_Switch
1
2
0
1
PLL
Filter
2
0
1
SCLK
2
Divider
R6(1)<5>
Figure 8
SWITCH3
SWITCH2
0
R6(1)<4>
R1(1)<0>
Clock Switching Block Diagram (8 -16 MHz)
Note: Clock switching is discouraged. It is only for advanced users.
Input/Drive Circuits
47 pF
Figure 9
32.768 KHz
22 pF
10 MΩ
The 32 KHz oscillator circuit in Figure 9 is suggested for proper clock operation.
XTAL1
Z90T361/6
XTAL2
68 KΩ
32 KHz Oscillator Recommended Circuit
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
18
2.4
Reset Conditions
Reset conditions including addresses and registers are listed in Table 6.
Table 6
Addr
Register
Reset Conditions
----------------------------- Reset Condition ------------------------- Comments
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R0(0) reserved
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Not available
R1(0) Cursor Palette
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
Cursor palette
gauge
R2(0) pll_freq
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0 PLL frequency
control
R3(0) I2C_int
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
I2C interface
register
R4(0) port0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16-bit I/O port 0
R5(0) port1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
9-bit I/O port 1
R6(0) dir0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 16-bit port 0
direction
R7(0) dir1
x
x
x
x
x
x
x
1
1
1
1
1
1
1
1
1 9-bit port 1 direction
R0(1) clamp_pos
1
1
1
1
0
0
0
0
0
x
x
x
x
x
x
x
R1(1) sclk_freq
x
0
0
0
0
0
0
0
x
x
x
0
0
0
0
0 Stop/sleep/normal
mode
R2(1) 9-bit cntr
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0 Stop and WDT, 9bit counter
R3(1) standard_ctl
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0 Output H/VSYNC/
Blink Control
R4(1) ADC_ctl
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
A/D converter
control
R5(1) cap_1s_ctl
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
Counter timers
control
R6(1) clock_ctl
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
Clock control
(switch VCO/DOT)
R7(1) wdt_smr_ctl
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SMR and WDT
control/interrupt
position of video
clamp pulse
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
19
Table 6
Addr
Register
Reset Conditions (Continued)
----------------------------- Reset Condition ------------------------- Comments
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R0(2) pwm_data1
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 1 data
R1(2) pwm_data2
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 2 data
R2(2) pwm_data3
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 3 data
R3(2) pwm_data4
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 4 data
R4(2) pwm_data5
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 5 data
R5(2) pwm_data6
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
8-bit PWM 6 data
R6(2) Shadow Ctrl
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
Shadow color ctrl
R7(2) CGROM offset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 CGROM offset
register
R0(3) hi_x2_hi_x3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character multiple/
current data
R1(3) lo_x2_mid_x3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character multiple/
next or previous
data
R2(3) Ch_x1_lo_x3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character multiple/
character graphics
attribute
R3(3) attr_data
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character attribute/
video RAM data
R4(3) osd_cntl
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
On screen display
control
R5(3) cap_data
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Capture register
data
R6(3) palette_color
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Display palette
color/underline
color
R7(3) output palette
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Output palette
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
20
2.5
Power Management
There are two low-power operating modes for Z90T366: SLEEP mode and STOP
mode.
SLEEP Mode
In SLEEP mode, the controller uses the 32.768-KHz clock for the SCLK to reduce
power consumption.
STOP Mode
In STOP mode, the processor is suspended, and the power consumption is
minimized.
2.6
I/O Port Configurations
User control can be monitored either through the front panel keypad scanning port
or the 16-bit remote control capture register.
Two input/output port blocks are available for general-purpose digital I/O
application. Each port bit can be programmed to be either an input or output port.
To conserve the device pin count, some port pins are mapped to provide I/O to the
ADC converter block and I2C interface block.
The 24 conﬁgurable I/O pins are general-purpose pins for functions such as serial
data I/O, LED On/Off control, key scanning, power control and monitoring, and
I2C serial data communications.
Port 0 and 1 directions are deﬁned in R6(0) and R7(0), respectively. R4(0)
and R5(0) are data registers for both Ports 0 and 1. Figure 10, Figure 11, and
Figure 12 indicate I/O conﬁguration and sharing with other functional units.
Note: Port01 must be conﬁgured as an input in the user mode even
though it is not called out in the device speciﬁcation.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
21
Direction
1—IN
0—OUT
VCC
Pad
Output
20 Ω
Input
Figure 10 Bidirectional Port Pins
Direction
1- IN
0- OUT
VCC
PAD
I2 C
Output
Output
20 Ω
Input
Figure 11 Bidirectional Pins Multiplexed with I2C Port
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
22
Direction
1—IN
0—OUT
VCC
PAD
Output
20 Ω
Input
Analog
MUX
Figure 12 Bidirectional Pins Multiplexed with ADC Inputs
2.7
Interrupts
The Z90T366 has three external interrupt signals. There are four interrupt sources
as follows:
•
•
•
•
Horizontal sync (HSYNC)
Vertical sync (VSYNC)
IR Capture timer
External event (Port09)
}
multiplexed
All interrupts are vectored. The capture timer and Port09 are multiplexed to the
same interrupt.
Interrupt priorities are programmable. Each interrupt can be masked by setting
ﬁelds in the external registers.
When the Z90T366 receives an interrupt request from one of the interrupt
sources, it executes the interrupt service routine directly for that source.
External register R7(1) controls interrupts.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
23
2.8
Timers
Watch-Dog Timer
The watch-dog timer resets the CPU when it times out.
External register R7(1) controls the watch-dog timer.
Real Time Clock
A clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms.
External register R5(1) controls the real time clock.
IR Capture Timer
A capture timer measures time between edges of the IR signal. This timer can be
programmed to measure timing from rising-to-rising, falling-to-rising, rising-tofalling, or falling-to-falling edges.
The IR capture timer is controlled by External register R5(1). Figure 13 is a
block diagram of the IR capture register structure.
CAP_Glitch
IR
Glitch
Filter
Prescaler
CAP_Edge
Edge
Detector
Halt capture timer
R5(1)<6>
Capture
Time
Capture
Register
Capture
Flags
CAP_speed
R5(1)<1:0>
Captured data
R5(3)
Falling edge is captured
Reset R5(1)<e>
Rising edge is captured/
Reset R5(1)<f>
Timeout/
Reset R5(1)<c>
Figure 13 IR Capture Register Block Diagram
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
24
2.9
ADC
This function employs a 4-bit resolution, ﬂash A-to-D converter. The six-to-one
analog input multiplexor and conversion start circuits are controlled by the user
program. The 4-bit conversion result is available to be read by the CPU at the end
of each conversion.
One input channel (ADC0) is dedicated for quantizing VBI (vertical blanking
interval) data for subsequent digital signal processing. Another channel, ADC5, is
typically used for VSYNC separation from the composite TV signal. These
channels (ADC0 and ADC5) feature a special video clamp circuit that provides DC
restoration of the composite video input signal. Typical VBI applications include
Line 21 Closed Caption, Electronic Data Services, and StarSight Telecast. The
range of ADC0 and ADC5 is from 1.5 to 2.0 V.
The four remaining channels of ADC (ADC1, ADC2, ADC3, and ADC4) are
general purpose. They are typically used for tuner automatic frequency control
and analog key entry. The range of ADC1–ADC4 is from 0 to 5.0 V.
The 4-bit ADC in the Z90T366 features six multiplexed inputs.
The allowed range for input signals differs for various ADC inputs according to
Table 7.
Table 7
ADC Inputs Typical Range
Input
Range (V)
Clamping
Typical application
CVI/ADC0
1.5–2.0
Yes (Ref–)
CCD sampling input
ADC1/Port17
0–5.0
No
AFC input
ADC2/Port00
0–5.0
No
Key scanning input
ADC3/Port05
0–5.0
No
Key scanning input
ADC4/Port04
0–5.0
No
Key scanning input
ADC5
1.5–2.0
Yes (Ref+)
VSYNC decoder
sampling input
Reference voltages that have been generated internally deﬁne the maximum
range of the input signal for the ADC.
Nominal values are as follows:
Ref+ = 2.0 V
Ref– = 1.5 V @ VCC = 5.0 V
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
25
For other VCC values, the reference voltages must be prorated as follows:
Ref+ = 0.4 * VCC
Ref– = 0.3 * VCC
The maximum sampling rate of the ADC converter is 3 MHz. It takes 4 SCLK
cycles for valid output data from the ADC to become available. This is especially
important if the application uses the single-shot mode.
The ADC exhibits monotonous conversion characteristics with a nonlinearity of
less than 0.5 LSB. ADC0. The ADC has a range of 0.5V (from 1.5V to 2.0V) and is
directly multiplexed to the input of the ADC. The remaining ADC inputs (ranging
from 0V to 5V) use AGND and AVCC voltage as a reference.
Figure 14 is a block diagram of the ADC inner structure, and Figure 15 illustrates
ADC input circuits.
.
Z90T366
REF+
CLAMP
ADC5 (VSYNC decoder)
ADC4/Port04
ADC3/Port05
ADC2/Port00
ADC1/Port17
6 to1
MUX
ANALOG
TO DIGITAL
4
CONVERTER
ADC0 (CCD decoder)
CLAMP
REF–
Figure 14 Z90T361/6 ADC Block Diagram
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
26
ADC Data Packing
Up to four 4-bit ADC data samples can be packed into one 16-bit word without
software overhead. If R4(1)<9> = 1, every reading of R4(1) returns the result,
where the High 12 bits are the three previous ADC samples and the Low 4 bits
are the current one, as illustrated in Figure 15.
15
12 11
ADC sample (T-3)
8 7
ADC sample (T-2)
4 3
ADC sample (T-1)
0
ADC sample (T)
Figure 15 ADC Data Packing
The following routine shows ADC packing:
LD
LD
OR
LD
LD
LD
LD
LD
LD
SR,%#20; select RegBank1
A,EXT4; turn “ADC data packing” mode on
A, #%0200; set R4(1)<9>
EXT4, A;
A, EXT4; read ﬁrst ADC sample, A = %0005
A, EXT4; read second ADC sample, A = %005E
A, EXT4; read third ADC sample, A = %05E7
A, EXT4; read forth ADC sample, A= %5E74
A, EXT4; read ﬁfth ADC sample, ﬁrst sample is thrown away, A = %E741
The ADC is controlled by the external register R4(1).
2.10 Pulse Width Modulation
Pulse Width Modulation (PWM) is used in conjunction with external low-pass
ﬁlters to perform digital-to-analog conversion. Six PWMs (8-bit resolution each)
generate signals for the control for video and sound attributes. In case of a
chassis employing a frequency synthesis tuner, these PWMs can also control
video or sound attributes. PWM’s can also be used to acknowledge tones for
remote or keyboard commands.
Each PWM circuit features a data register whose contents are set under program
control. The data in the register determines the ratio of PWM High to PWM Low
time. PWM data registers are not initialized when reset. In order to eliminate a
potential glitch on a PWM output, it is recommended to initialize PWM data
registers before enabling the VCOs.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
27
External registers R0(2) to R5(2) are data registers for PWM1 to PWM6
accordingly.
2.11 I2C Interface
There are two hardware modules that support standard I2C bus protocol
according to the I2C bus speciﬁcation published by Philips in 1992, titled I2C
Peripherals for Microcontrollers Data Handbook.
The ﬁrst module, the Master, can be conﬁgured for fast (400 KHz) or slow (100
KHz) bit rates and can be used in applications with a single master.
The Z90T366 adds two additional non-standard bit rates (50 KHz and 10 KHz)
and an additional multiplexed master port that is controlled by the I 2CM_mux
control bit.
Table 8 lists the bit rates for the Master I2C Bus.
Table 8
Master I2C Bus Bit Rates
Mode
I2C mode
Bit Rate
Actual Bit Rate
LO/Slow
—
0–10 KHz
10 KHz
HI/Slow
—
0–50 KHz
44 KHz
LO/Fast
Slow
0–100 KHz
91 KHz
HI/Fast
Fast
0–400 KHz
334 KHz
To suppress possible problems on both data (SDA) and clock (SCL) lines, digital
ﬁlters are available for all inputs of the I2C bus interface. These ﬁlters exhibit a
time constant equal to 3TSCLK = 250 ns.
If the Master I2C interface is enabled, corresponding I/Os, Port11 and Port12,
must be assigned as outputs.
Master and Slave modules cannot be used simultaneously because of the shared
I2C data register (see the Register 3(0) data ﬁeld). The software activates I 2C
modules by writing appropriate commands into the control register. To control the
I2C bus interface, the control register R3(0) toggle bit <c> must point to an
appropriate interface (Master or Slave).
M_disable or S_disable bits allow either the Master or Slave I2C interface to be
disabled so as not to interfere with any activity associated with the Port pins. At
Power-on Reset (POR), both I2C interfaces are enabled. To use the I2C interface,
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
28
the corresponding Port pin (multiplexed with the I2C Data and Clock) must be
conﬁgured as an output, while M_disable or S_disable bits must be reset to 0.
External register R3(0) controls the I2C. Table 9 lists the Master I2C bus interface
commands. Table 10 lists the Slave I2C bus interface commands. Figure 16 and
Figure 17 are ﬂow charts of the Master and Slave modes.
Table 9
Master I2C Bus Interface Commands
Command
Notes/Function
000
This command sends a start bit, followed by an address byte speciﬁed in
the “data” ﬁeld (bits <7:0>), then fetches an acknowledgment in bit <0>.
This command initializes communication and generates 9 SCL cycles.
001
This command sends one byte of data speciﬁed in the “data” ﬁeld (bits
<7:0>), then fetches an acknowledgment in bit <0>. This command is
used in a WRITE frame and generates 9 SCL cycles.
010
This command sends bit <7> as an acknowledgment (ACK = 0, NAK =
1), then receives a data byte. This command is used in a READ frame
when the next data byte is expected and generates 9 SCL cycles.
Received data appears in the “data” ﬁeld (bits <7:0>).
011
This command sends bit <7> as an acknowledgment (ACK = 0, NAK =
1). This command is used in a READ frame to terminate data transfer
and generates one SCL cycle.
100
101
A NULL operation. This command must be used with a “RESET” bit <b>
and/or a “TOGGLE” bit <c>.
Using the “RESET” and/or “TOGGLE” bits with any other command
interferes with the logic of the I2C interface.
110
This command receives one data byte. It is used in a READ frame to
receive the ﬁrst data byte after the address byte is transmitted. It
generates 8 SCL cycles.
111
This command sends a stop bit and generates one SCL cycle.
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
29
Table 10 Slave I2C Bus Interface Commands
Command
Notes/Function
0 0 0
Reserved. Cannot be used.
0 0 1
This command sends bit <7> as an acknowledgment (ACK = 0 only),
then receives one data byte. This command is used in a WRITE frame
and requires 9 SCL cycles. Received data is read as a “data” ﬁeld (bits
<7:0>).
0 1 0
This command sends one byte of data speciﬁed in a “data” ﬁeld (bits
<7:0>), then fetches an acknowledgment in bit <0>. This command is
used in a READ frame and requires 9 SCL cycles.
0 1 1
Reserved. Cannot be used.
1 0 0
1 0 1
A NULL operation. This command must be used with a “RESET” bit <b>
and/or “TOGGLE” bit <c>.
Using the “RESET” and/or “TOGGLE” bits with any other command
interferes with the logic of the I2C interface.
1 1 0
This command sends a bit <7> as a not acknowledgment (NAK = 1 only)
in a WRITE or READ frame. This command terminates I2C
communication and requires one SCL cycle. The “Sulfonamide” bit <a>
is automatically reset when a “busy” bit <9> goes Low.
This command sends a bit <7> as an acknowledgment (ACK = 0 only) in
a READ frame and requires one SCL cycle. The Send data command
(010) must be executed next. This command acknowledges an address
byte in a READ frame.
1 1 1
Reserved. Cannot be used.
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
30
START
no
yes
Read R3(0)<8>
“Busy” ==0?
Send a start bit followed
by a 7-bit Address byte
Write R3(0)
{0000,0xxx,Addr,R/W}
no
yes
“Busy”==1
Read R3(0)<0>
(Read Ack bit)
no (Nak)
R3(0)<0>==0?
yes(Ack)
Write frame
More bytes
to send?
Write R3(0)
{1100,0xxx,xxxx,xxxx}
(Ask slave to send Data byte)
no
yes
Write R3(0)
{0010,0xxx,Data}
(Send Data byte)
Read frame
yes
“Busy”==1?
no
no
“Busy”==1?
Write R3(0)
{0110,0xxx,0xxx,xxxx}
(Ack Data byte)
Read R3(0)
{xxxx,xxxx,Data}
(Read Data byte)
yes
Write R3(0)
{0110,0xxx,1xxx,xxxx}
(Nak Data byte)
no
Receive more bytes?
yes
yes
“Busy”==1?
Note:
Shaded blocks are executed in software
no
Write R3(0)
{0100,0xxx,0xxx,xxxx}
(Acknowledge Data byte)
Write R3(0)
{1110,0xxx,xxxx,xxxx}
(Send a “Stop” bit)
Figure 16 Master Mode
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
31
START
no
“Start” condition
detected
yes
Set R3(0)<9>
Reset R3(0)<9>
yes
no
Address matches
Reset R3(0)<a>
Set slave modeR3(0)<a>
Hold the bus
Stretch clock
Reset slave busyR3(0)<9>
(Nak Master)
Write R3(0)
{1100,0xxx,1xxx,xxxx}
Ignore master
Read frame
R3(0)<0>=1
(Ack Master)
Write R3(0)
{1100,0xxx,0xxx,xxxx}
no
Slave = 1,Busy = 0
R3(0)<a:9>
Wait here for “send
first byte” command
yes
no
Wait for Ack
from master
Ack master
Write frame
R3(0)<0>=0
Read R3(0)<0>
(R/W bit)
(Nak master)
(Ack master)
Write R3(0)
Write R3(0)
1100,0xxx,1xxx,xxxx 0010,0xxx,0xxx,xxxx
no
Slave = 1,Busy = 0
R3(0)<a:9>
yes
(Send data)
Write R3(0)
{0100,0xxx,Data}
hold the bus
stretch clock
Slave = 1,Busy = 0
R3(0)<a:9>
(Get Data)
Read R3(0)
yes
no (Nak)
Read R3(0)<0>
Ack==0?
goto Ack Master
yes (Ack)
hold the bus
stretch clock
Note:
Shaded blocks are executed in software
If a “Stop” condition is detected at any point, the hardware resets the “Slave”
bit (R3(0)<a>) and releases the I2C bus.
Figure 17
Slave Mode
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
32
2.12 On-Screen Display (OSD)
The Z90T366 provides sophisticated on-screen display features. On-Screen
Display has the following two modes:
•
•
OSD
Used to generate TV control OSD
CCD
Used to display Closed Caption information
OSD mode provides access to the full set of control attributes including latched
and unlatched attributes. Unlatched attributes can be modiﬁed on a character-bycharacter basis. Control characters change latched attributes.
Any 256-character set can be displayed with many display attributes, including
underlining, italics, blinking, eight foreground and background colors, character
position offset delay, and background transparency. A 16-bit display character
represents foreground color, background color, and underline attributes, which
can be modiﬁed character by character. In addition, the Z90T361 supports eight
ﬁxed plus eight programmable color palettes out of 64 colors, independent left
and right shadows with color control. Shadows are available on transparent and
nontransparent backgrounds. Semi-transparency is supported on a character-bycharacter basis. A character’s pixel array is stored as 16, 18, or 20 words in
Character Generation ROM (CGROM).
Additional hardware provides the capability to display characters at two and three
times normal size. The smoothing logic contained in the on-screen display
improves the appearance of two and three times normal size characters.
Shadows can be activated to improve the visibility of characters by adding a
border (one pixel wide) on each side.
The Z90T366 provides RGB signals and a video blank signal. RGB outputs are
available in two modes: digital and analog. In digital mode, the output RGB
signals correspond to a primary colors palette. Analog mode supports 15 different
palettes, which can be chosen under software control. In analog mode, each RGB
output is generated by a 2-bit digital-to-analog converter. The user can switch the
2-bit digital inputs of the digital-to-analog converter to Port pins (Port10, Port13,
Port14, Port15, Port18 and Port08) under software control by setting bit9 in
register R3(1).
Video synchronization is normally obtained from H_FLYBACK and V_FLYBACK
but can be generated by the Z90T366 and driven to the external deﬂection unit
using the bidirectional HSYNC and VSYNC ports when external video
synchronization signals are not present.
OSD is completely software controlled. Hardware supports the optimum
generation of the character-based OSD; however, the CPU can bypass it and
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
33
generate pixels and attributes directly. The block diagram in Figure 18 illustrates
the OSD data ﬂow.
Figure 19 and Figure 20 indicate the R, G, B, and Blank output circuits.
P
a
l
e
t
t
e
s
R7(3)
R6(3)
R0(3)
R1(3)
R2(3)
R0(3)
R1(3)
R2(3)
Attribute
R3(3)
R4(3)
Memory Rd
Figure 18
Shift
Register
CGROM
Pixels: 1x
2x
3x
Full attrib
R3(3)
Video RAM
OSD:At7Ch8
or Attr15
CCD:Char7
orAttr7
3
x
D
A
C
R
G
B
CPU
Data Flow
VCC
P
PAD
Output
N
Figure 19 Blank and R, G, B Outputs in Digital Mode
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
34
VCC
VCC
VCC
I ≈ 800 mA
I/2
I/4
R,G or B <1>
R,G or B <0>
PAD
R ≈ 3 KOhms
Figure 20 R, G, and B Outputs in Analog (Palette) Mode
Closed Caption Data Capture
Closed-caption text can be decoded directly from the composite video signal
using the processor’s digital signal processing capabilities and displayed on the
screen. The character representation in this mode provides simple attribute
control by inserting control characters. Each word of video RAM speciﬁes two
displayed characters.
The 4-bit ﬂash A/D converter, with proper clamping, provides the ability to receive
the composite video signal directly and process the closed-caption text embedded
in the signal. Signal processing can be applied directly to the signal to improve
decoder performance.
CGROM Relocation
CGROM can be placed anywhere in the 64K ROM address space by setting the
CGROM address offset register R7(2). This offset is added to the CGROM
address before accessing the ROM. By modifying the CGROM offset, several
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
35
fonts can be accessed (limited only by ROM size). When reset, R7(2) = 0 (no
offset), making the Z90T366 backward-compatible with existing OSD control
software.
The character scan line from CGROM addressed by the character register is
fetched and stored into the CGROM capture register. If a pixel is set to 1, it
displays the foreground color. If a pixel is set to 0, it displays the background
color. The scan line can be stretched by the character multiplier to be two or three
times normal character size by duplicating each bit in the word.
Controlling Character Expansion
The character size can be stretched to two or three times the size of the scan line.
Hardware fetches data from CGROM and stretches the data to be read from
registers R0(3), R1(3), and R2(3). Figure 21 is a block diagram of the structure of
the character expansion multiplexor, and Table 11 lists bit functions.
16
ROM data
CGROM data
capture register
16
Character
Expansion
Multiplexor
control
x1, x2, x3
48
R0(3)
16
char_mult_high
R1(3)
16
char_mult_mid
R2(3)
16
char_mult_low
Processor EXTERNAL bus
Figure 21 Character Expansion
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
36
Table 11 Character Expansion Register
Capture
Register
Contents
Char_mult_high
x1 operation
abcdefghijklmnop
x2 operation
aabbccddeeffgghh
iijjkkllmmnnoopp
x3 operation
aaabbbcccdddeeef
ffggghhhiiijjjkk klllmmmnnnoooppp
Char_mult_mid
Char_mult_low
Displayed Data Formats
The Z90T366 hardware supports the following two different data formats:
•
•
OSD mode, R4(3)<d> = 1 supports a standard OSD with full set of features.
CCD mode, R4(3)<d> = 0 supports reduced features which comply with the
recommendations of the FCC on Closed Caption support.
In CCD mode, the background color of the characters cannot be changed and is
always preset to BLACK.
OSD Mode
In OSD mode, each character occupies a 16-bit word in VRAM. There are two
possible character formats deﬁned: a “display” character and a “control”
character. The code stored in “display” character format deﬁnes a character code
and up to 7 attributes of the character.
The “control” character deﬁnes latched attributes and is presented on-screen as a
space character. The combination of “display” and “control” characters provides
versatile OSD generation.
Smoothing is supported for double-size (x2) and triple-size (x3) characters only.
CCD Mode
In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD
characters must be mapped into a 16-bit VRAM data ﬁeld. The hardware supports
compressed placement of characters in VRAM. Each word in VRAM is
represented by a High byte and a Low byte. A currently active byte is selected by
R4(3)<c>. The format and data representation in both bytes is exactly the same.
There are two possible character formats deﬁned: a “display” character and a
“control” character. The code stored in “display” character format deﬁnes a
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
37
character code. The “control” character deﬁnes up to ﬁve attributes (foreground
color, italic, underline, blinking, and transparent). It is presented on screen as a
space character. The combination of Display and Control characters provides the
basis for a speciﬁed range of attributes deﬁned by FCC speciﬁcations for CCD.
Shadows
Shadows, if enabled, are active on both transparent and nontransparent
backgrounds. Two bits in the AttributeWR and AttributeRD registers, (R2(3)<1:0>
and R3(3)<1:0>), control the type of shadow. Refer to Figure 22.
Background
R2(3)<1:0>,
R3(3)<1:0>
Function
00
01
10
11
No shadows
Left shadow
Right shadow
Both shadows
Foreground
Right shadow
Left shadow
Figure 22 Table Settings
The smoothing attribute has been moved to R7(3)<5>.
The bit assignment in the Latched Attribute follows the bit assignment in R2(3).
The left and right shadow colors are independently controlled by R6(2)<d:b> and
R6(2)<a:8>.
The smoothing control bit R7(3)<5> must be set to a “1” in
order to activate fringing.
Semi-Transparent
Both semi-transparency (pin name SOVL) and transparency (pin name OVL)
attributes are supported. The semi-transparency mode can be enabled through
either latched or unlatched attributes. Latched attributes remain set until they are
reset. Unlatched attributes remain set for only one character, which means the
attribute must be constantly refreshed on a character-by-character basis.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
38
Activation
To activate semi-transparency output, two bits must be set properly. Port 0F must
be in output mode [R6(0)<f> = 0], and the SOVL/Port0F control bit must be in
SOVL mode [R3(1)<6> = 1].
Latched Semi-Transparency
The latched semi-transparency attribute is controlled by bit [R2(3)<6>].
Unlatched Semi-Transparency
The unlatched semi-transparency attribute is controlled by bit [R3(3)<8>]. This bit
has one of four possible assignments depending on how it is set up in
[R7(3)<7:6>]. The four assignments are underline, semi-transparency, blinking,
and CGROM bank select.
Notes:
1.
The semi-transparency signal (SOVL), when active, is only valid with the
background color. With the foreground color, SOVL is inactive. Therefore,
characters do NOT take on a semi-transparent appearance (only the
background does). This condition allows characters to be read without
interference.
2.
If both the transparency (background and foreground color are equal) and
semi-transparency are activated, the OVL signal is High, and the SOVL
signal is Low.
Attribute Assignment
Depending on R7(3)<7:6>, bit 8 of the Attribute_Data register, R3(3) (in character
mode) can be assigned to control either “1st underline,” “semi-transparency,”
“blinking,” or “CGROM bank select,” as indicated in Table 12.
Table 12 Attribute Assignment
R7(3)<7:6>
R3(3)<8>
00
1st underline (POR)
01
Semi-transparency
10
Blinking
11
CGROM bank1 select
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
39
2.13 Cursor
The cursor buffer ( a one-line pixel buffer) is loaded via the DMA on every line
where the cursor is displayed (no software support is required). Horizontal size is
programmable at 16, 32, or 48 pixels wide, and vertical size is programmable from
1 to 63 lines per ﬁeld. The color depth is 2 bits per pixel, 3 programmable colors
and the transparency. Depending on R1(0)<d>, the cursor’s colors can be
selected either from a current palette (R1(0)<d> = 0) or from Palette #6 (R1(0)<d>
= 1). Refer to Table 15. The cursor image is stored in ROM as a bitmap. The
number of cursors is limited by available ROM size.
The cursor is positioned by initializing cursor parameters in the beginning of every
ﬁeld.
Initialization occurs by setting the Cursor_Info_Load bit R7(3)<4> to 1, then
writing sequentially to the R3(3) 16-bit parameters (COLOR, HPARAM, VPARAM
and CADDR, respectively).
The cursor buffer is loaded from ROM at the leading edge of H SYNC wherever the
horizontal line requires a cursor. This process halts the CPU for 3/5/7 cycles
depending on the cursor’s horizontal size. The cursor bitmap address pointer
(CADDR) is incremented automatically.
Though the cursor can be displayed anywhere on the screen, limiting the cursor to
the OSD area is best. Outside of the OSD area, the cursor can jitter or become
distorted.
The cursor bitmap is organized as pixel data placed sequentially in the ROM. The
data format is described below.
For the interlaced mode, even and odd cursor bitmaps must be deﬁned
separately. Proper selection occurs during the cursor initialization at the beginning
of every ﬁeld. See Figure 23, Table 13, and Table 14.
Focus
(X,Y)
Vertical
position
(Y: 1–1023)
(00) transparent
(01) color 1
(10) color 2
(11) color 3
Horizontal position (X: 1–1023)
63 lines max
(2*63 in progressive
scan mode)
48 pixels max
Figure 23 Cursor
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
40
Example
LD
OR
LD
LD
LD
LD
AND
SR,%#60 ; select RegBank3
EXT7,#%0010; enable Cursor_Info_Load
EXT3,#(3*64 + 7*8 + 2); load CCOLOR: color3 = 3, color2 = 7, color1 = 2
EXT3,#(2*1024 + 120); load HPARAM: hsize = 2 (32 pixels), hpos = 120
EXT3,#(28*1024 + 55); load VPARAM: vsize = 28, vpos = 55
EXT3,#%6000; load CADDR—cursor bitmap address
EXT7,#%FFEF; disable Cursor_Info_Load, ready for OSD
Table 13 Cursor Parameters
Parameter Reg ﬁeld Bit position
Data
Description
CADDR
CADDR fedcba9876543210 D
Cursor bitmap address
(pointer to cursor bitmap in ROM)
VPARAM
VSIZE
fedcba---------- 1–63
Vertical size (lines in one ﬁeld)
VPOS
------9876543210 1–1023
Vertical position (lines in one ﬁeld)
n/a
fedc------------ n/a
Reserved
HSIZE
----ba---------- 00
01
10
11
No cursor
16 pixels wide
32 pixels wide
48 pixels wide
HPOS
------9876543210 1–1023
Horizontal position (pixels from
trailing edge of HSYNC)
n/a
fedcba9--------- n/a
Reserved
Color3
-------876------ 0–7
Cursor Color 2 assignment
Color2
----------543--- 0–7
Cursor Color 1 assignment
Color1
-------------210 0–7
Cursor Color 0 assignment
HPARAM
CCOLOR
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
41
Table 14 Memory Allocation for Cursor Bitmap
16 Pixels Wide Mode
AddrN:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
L0_P0_B0
AddrN+1:
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+2:
L1_P15_B0, L1_P14_B0, L1_P13_B0, ... , L1_P1_B0,
L1_P0_B0
AddrN+3:
L1_P15_B1, L1_P14_B1, L1_P13_B1, ... , L1_P1_B1,
L1_P0_B1
..................................................
AddrN+2n:
Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+2n+1:
Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
32 Pixels Wide Mode
AddrN:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+1:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
AddrN+2:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
L0_P0_B0
AddrN+3:
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+4:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+5:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
..................................................
AddrN+4n:
Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
AddrN+4n+1:
Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
AddrN+4n+2:
Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+4n+3:
Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
48 Pixels Wide Mode
AddrN:
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P13_B0, L0_P32_B0
AddrN+1:
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
AddrN+2:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+3:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
AddrN+4:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
L0_P0_B0
AddrN+5:
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+6:
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P33_B0, L0_P32_B0
AddrN+7:
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
..................................................
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
42
Table 14 Memory Allocation for Cursor Bitmap (Continued)
AddrN+6n:
Ln_P47_B0, Ln_P46_B0, Ln_P45_B0, ... , Ln_P33_B0, Ln_P32_B0
AddrN+6n+1:
Ln_P47_B1, Ln_P46_B1, Ln_P45_B1, ... , Ln_P33_B1, Ln_P32_B1
AddrN+6n+2:
Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
AddrN+6n+3:
Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
AddrN+6n+4:
Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+6n+5:
Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
where
Lx_Py_Bz
=
line X, pixel Y, bit Z;
Line 0
=
ﬁrst (top) cursor’s line;
Pixel 0
=
ﬁrst (left) cursor’s pixel
Bit 1, Bit 0
=
most and least signiﬁcant bits of the cursor’s color deﬁned as
00 = transparent
01 = Color 1
10 = Color 2
11 = Color 3
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
43
2.14 Color Palette Assignment
The Z90T366 features a total of 16 color palettes, 8 of which are ﬁxed and 8 of
which are programmable. Palettes are selected by setting R7(3)<3:0>. Fixed
palettes are deﬁned in Table 15.
Table 15 Fixed Palette Color Assignment
(Color0 is Black; Color7 is White)
Color1
Color2
Color3
Color4
Color5
Color6
Palette Description
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
0
Digital RGB
00
00
11
00
11
00
00
11
11
11
00
00
11
00
11
11
11
00
1
Analog RGB
00
00
11
00
11
00
00
11
11
11
00
00
11
00
11
11
11
00
2
Greyscale_1
01
01
01
10
10
10
11
11
11
00
00
00
01
01
01
10
10
10
3
Greyscale_2
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
11
11
11
4
RGB_Cyan_2Grey
00
00
11
00
11
00
00
11
11
11
00
00
01
01
01
10
10
10
5
RGB_Magenta_2Grey 00
00
11
00
11
00
01
01
01
11
00
00
11
00
11
10
10
10
6
RGB_Yellow_2Grey
00
00
11
00
11
00
01
01
01
11
00
00
10
10
10
11
11
00
7
StarSight
00
11
11
10
11
10
10
10
10
11
01
01
11
11
10
11
11
00
Programmable palettes (8–15) are mapped to AR0–AR63 (8 registers per
palette). The register and bit assignments for Palette # 11 are listed in Figure 24.
Programmable palettes are grouped into 2 banks (palettes 8–11 and 12–15).
Palettes in the bank cannot be modiﬁed if another palette from the same bank is
displayed. An interleaving palette bank access must be created if on-the-ﬂy
palette modiﬁcations are required. One palette bank is used to display four colors,
and the other bank is used for updates. See Figure 24.
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
7 N/A
6
5 R
4
3
G
2
1
B
0
Color0
Color1
Color2
Color3
Color4
Color5
Color6
Color7
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
Figure 24 Programmable Palette Control at AR Register
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
44
2.15 Other Functions
Video and Sound Attribute Control
Basic receiver functions such as color and volume can be controlled directly by six
6-bit pulse-width modulated ports.
InfraRed Capture Function
The Infrared Remote Control data capture feature uses a capture register to hold
the time value from one transition of IR data to the next.
Software periodically checks and reads the capture status and the value if a new
capture occurs. Subsequent decoding and command passing of the received IR
signal is under software control. Figure 25 illustrates the IR input circuit.
20 Ω
PAD
IR Input
Figure 25 IR Capture Register Input
Loop Filter
The Loop Filter pin conﬁguration is represented in Figure 26.
VCC
VCC
VCC
PD “positive” out
PAD
PD “negative” out
20 Ω
To VCO driver
Figure 26 Loop Filter Pin Conﬁguration
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
45
Hardware Accelerated 4-Bit and 8-Bit Shifts
Hardware-accelerated byte and nibble shifts signiﬁcantly reduce software
overhead. Shifts are created by assigning one particular RAM location (%1FE) a
special meaning. Depending on the R4(1)<e:d> settings, data read from this
address are either unmodiﬁed, rotated 4 bits left, 4 bits right, or byte swapped.
See Table 16.
Table 16 R4(1)<e:d> Settings
R4(1)<e:d>
Function
00
Direct (unmodiﬁed)–POR
01
4-bit left rotate
10
4-bit right rotate
11
Byte swap
Example
LD
LD
AND
OR
LD
LD
LD
LD
LD
OR
LD
LD
SR,#%20
A,EXT4
A, #%9FFF
A, #%4000
EXT4, A
A, #%3ED7
%1FE, A
A, %1FE
A,EXT4
A,#%6000
EXT4, A
A, %1FE
; Select RegBank1
; turn “hardware-supported shift” mode on
;
;
; select “4-bit right rotate”
; load A = 3ED7h
; write A to the RAM
; A = 73EDh
; turn “hardware-supported rotate” mode on
;
; select “byte swap”
; A = D73Eh
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
46
3
Register Groups
Table 17 provides a summary of the registers in external banks.
Table 17 Register Summary
Bank
Bank Sub READ
Address Register
Bank0
7
dir1
9-bit I/O port 1 direction control
6
dir0
16-bit I/O port 0 direction control
5
port1
9-bit I/O port 1
4
port0
16-bit I/O port 0
3
I2C_int
I2C interface register
2
pll_freq
PLL frequency control
1
write control register
Cursor palette gauge Write control register
0
Reserved
Reserved
7
wdt_smr_ctl/Interrupt
SMR and WDT control and interrupt
6
clock_ctl
Clock control (switch VCO/DOT)
5
cap_1s_ctl
Counter timers control
4
ADC_ctl
A/D converter control
3
standard_ctl
Output H/VSYNC/blnk control
2
9-bit counter
1
sclk_freq
Stop/sleep/normal mode
0
clamp_pos
Deﬁnes position of video clamp pulse
7
CGROM offset register
CGROM offset register
6
Shadow Control register
Deﬁnes right and left shadow color
5
pwm_data6
8-bit PWM 6 data
4
pwm_data5
8-bit PWM 5 data
3
pwm_data4
8-bit PWM 4 data
2
pwm_data3
8-bit PWM 3 data
1
pwm_data2
8-bit PWM 2 data
0
pwm_data1
8-bit PWM 1 data
Bank1
Bank2
WRITE
Register
STOP/WDT
Description
Stop and WDT instructions, 9-bit counter
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
47
Table 17 Register Summary (Continued)
Bank
Bank Sub READ
Address Register
Bank3
7
output palette
Output palette
6
palette_color
Display palette color/underline color
5
capture_data
4
osd_control
3
attribute_data
vram_data
Character attribute/video RAM data
2
ch_x1_lo_x3
cg_attribute
Character multiple/character graphics
attribute
1
lo_x2_mid_x3
cg_nxt_prv
Character multiple/next or previous data
0
hi_x2_hi_x3
cg_current
Character multiple/current data
3.1
WRITE
Register
Description
I2C slave addr. Capture register data
On screen display control
Register Description
The register ﬁle in the Z90T366 is organized into four banks that can be selected
by writing to bits 5 and 6 (Register Bank Selector bits) in the Status Register of the
Z90T366 core.
All registers are mapped into an external register space; each bank consists of
8 registers. The Status register is available to read or write at any time. The
appropriate bank of registers must be selected before accessing the register. The
software must keep track of which register bank is accessible at any time. Refer to
Table 18 for register bank assignments.
Table 18 Bank Assignments
Bank
Status Register
Bank Functions
Bank0
xxxx xxxx x00x xxxx b
I/O ports, I2C interface, PLL frequency, cursor
Bank1
xxxx xxxx x01x xxxx b
Control registers
Bank2
xxxx xxxx x10x xxxx b
PWM1–PWM5
Bank3
xxxx xxxx x11x xxxx b
OSD, palette control
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
48
3.2
Bank0 (I/O Ports, I2C Interface, PLL Frequency, Cursor)
Control Registers
Table 19 deﬁnes the bits for Register1, R1(0) Cursor Palette Control Register.
Table 20 deﬁnes the bits for Register2, R2(0) PLL Frequency Data Register.
Table 19 Register1, Bank 0, Cursor Palette
Bit
R/W
Reset
15
14
reserved reserved
x
x
Bit
R/W
Reset
13
12
11
10
9
8
R/W
0
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
Reserved
fe--------------
W Data
Description
Reserved
Cursor Palette --d------------- R
W 1
0
Palette #6 (recommended)
Current palette—POR
PgWritenEn
---c------------ R
W 1
0
Page Write Enable
Page Write Disable—POR
PageWrite
----ba9876543210 R
W xxxx
PageWrite#
Table 20 Register2, Bank 0, PLL Frequency Data Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
reserved
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Note: R = Read W = Write X = Indeterminate
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
49
Reg Field
Bit Position
R W Data Description
M_disable
f--------------- R W
1
0
I2C Master interface disabled
I2C Master interface enabled–POR
S_disable
-e-------------- R W
1
0
I2C Slave interface disabled
I2C Slave interface enabled–POR
I2CM_mux --d------------- R W
1
0
Select I2MSD2, I2MSC2–POR
Select I2MSD1, I2MSC1
I2C_Out_ ---c------------ R W
Resistance
1
0
600Ω output resistance
Normal CMOS port output
resistance–POR
I2C_speed ----b----------- R W
_range
1
0
Low speed range (10 KHz, 50 KHz)
High speed range (100 KHz, 400
KHz)–POR
Reserved
-----a----------
Reserved
P46/
HSYNC2
------9--------- R W
10
HSYNC logic takes input from
HSYNC pin–POR. This bit must
always be set to 0.
P07/
CSYNC
-------8-------- R W
1
0
Composite Sync Output
P07 I/O–POR
PLL_data
--------76543210 R W
D
PLL divider = 256 + D
If the master I2C interface is enabled, the corresponding I/Os, Port11 and Port12
must be assigned as outputs. (The Z90T366 does not have pins to support a
slave interface.)
The VCO, DOT, and SCLK frequency are deﬁned as the following:
FVCO = FDOT = FSCLK = XTAL * (256 + PLLDATA)
Therefore, XTAL = 32.768 KHz
At POR, the PLL frequency data register is preset to 70h, which corresponds to
the VCO frequency of 12.058 MHz.
The PLL_data ﬁeld can be loaded with any value from 00h. This value
corresponds to an SCLK = 256*XTAL up to FFh, which corresponds to an SCLK =
511*XTAL.
Table 21 through Table 25 describe the bits in registers 3 through 7.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
50
Table 21 Register3, BAnk 0, I2C Interface Register
Bit
15
14
13
12
11
10
9
8
R/W
Reset
W
0
W
0
W
0
R/W
0
W
0
R/W
1
R/W
x
R/W
x
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Command
fed-------------
Toggle
---c------------ R
W
D
See Table 9 and Table 10 for a full
description.
1
0
1
0
Slave interface
Master interface–POR condition
Toggle active I2C interface
No effect
1
0
Reset Slave I2C interface if bit <c> =1
Reset Master I2C interface if bit <c> =0
No effect
Slave_mode -----a---------- R
1
0
Slave mode is active (POR condition)
Slave mode is inactive
SlaveBusy
------9--------- R
1
0
Slave I2C interface is busy
Slave I2C interface is idle
MasterBusy -------8-------- R
1
0
Master I2C interface is busy
Master I2C interface is idle
Data
xx
xx
Received data
Data to be sent
W
Reset
----b-----------
W
--------76543210 R W
Data written to R3(0)<cb> requires 4 cycles before being applied. Consecutive
writings to these bits require at least a 6-cycle delay.
The received data is available for reading only when the “busy” bit is reset to a “0.”
When POR, the speed of the I2C interface is set to “Low.”
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
51
Table 22 Register4, Bank 0, Port 0 Data Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
Port_data
fedcba9876543210
R
W
W
Data Description
xxxx
If a port is conﬁgured in Input
mode, enter the input data onto the
port pins.
xxxx
If a port is conﬁgured in Output
mode, then the data is written
directly to the port data.
Table 23 Register5, Bank 0, Port 1 Data Register
Bit
R/W
Reset
15
14
13
12
11
10
9
reserved reserved reserved reserved reserved reserved reserved
x
x
x
x
x
x
x
Bit
R/W
Reset
8
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Reserved
fedcba9---------
Port_data
-------876543210
R
W
Data Description
Reserved
R
xxxx If a port is conﬁgured in Input
mode, enter the input data onto the
port pins.
W
xxxx If a port is conﬁgured in Output
mode, then the data is written
directly to the port data.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
52
Table 24 Register6, Bank 0, Port 0 Direction Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Port_direction
fedcba9876543210
R
W
xxxx
1: Input mode for
corresponding bit
0: Output mode for
corresponding bit
Table 25 Register7, Bank 0, Port 1 Direction Register
Bit
R/W
Reset
15
14
13
12
11
10
9
reserved reserved reserved reserved reserved reserved reserved
x
x
x
x
x
x
x
Bit
R/W
Reset
8
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Reserved
fedcba9---------
Port_direction -------876543210
R
W
Data
Description
Reserved
R
W
xxxx
1: Input mode for
corresponding bit
0: Output mode for
corresponding bit
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
53
3.3
Bank1 (Control Registers)
Table 26 through Table 33 provide bit functions for Bank 1 Control registers.
Table 26 Register0, Bank 1, Clamp Position Register
Bit
15
14
13
12
11
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
7
6
5
4
3
2
1
0
reserved
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
Reset
Bit
R/W
Reset
10
9
8
reserved reserved reserved
0
0
0
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Disable_clamp_1
f--------------- R W
1
0
Disable_clamp_2
-e-------------- R W
1
0
Disable_tip_clamp --d------------- R W
1
0
Counter_input
---c------------ R W
1
0
ARenable
----b----------- R W
Reserved
-----a987-------
Position
---------6543210 R W
1
0
ADC0 Clamp generation is
disabled
ADC0 Clamp generation is
enabled
ADC5 Clamp generation is
disabled
ADC5 Clamp generation is
enabled
ADC0 Tip clamp is disabled–
POR
ADC0 Tip clamp is enabled
Counter takes input from P06–
POR
Counter takes input from
internal HSYNC Separator
AR enabled
AR disabled–POR
Reserved
xx
Position of clamp pulse (from
leading edge of the HFLYBACK)
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
54
At POR the disable_clamp bit is set to 1.
The clamp pulse is generated if Enabled (bit <f>) and the SCLK frequency is
switched back to PVCO. The SVCO/PVCO ﬂag in R6(1) must be reset to 0 before
the current HSYNC, regardless of whether the SVCO is enabled or disabled.
The clamp position is deﬁned by the Position ﬁeld. The width of the clamp pulse
cannot be modiﬁed and is set to 1µs. The value that can be assigned to the
“Position” ﬁeld must be >10h and <7Fh. The time interval between the leading
edge of the H-FLYBACK and the beginning of the clamp pulse can be calculated
from the following equation:
TDELAY
1
= Positio n  --------------- = Position × 82ns
 T SCLK
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
55
Table 27 Register1, Bank 1, Speed Control Register
Bit
15
14
13
12
11
10
9
8
reserved
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
R/W
Reset
W
x
W
x
W
x
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
Reserved
f---------------
Mode selection
-e-------------- R
W Data Description
Reserved
W
1
0
Standard interlace mode (single
scan)
Double scan -POR
H_SHIFT
--dcba98-------- R
W
D
Horizontal delay* POR = 0
1xHSYNC
--------7-------
W
1
0
1xHSYNC connected to Port03
1xHSYNC is 2xHSYNC/2-POR
Skip_HSYNC
---------6------
W
1
0
Skip next HSYNC
Do not skip next HSYNC
Frame_start
----------5-----
W
1
0
Field start initializaiton
No effect
OSD_black
-----------4---
R
W
1
0
Next output line is OSD
Next output line is black
Line_buffer_mode ------------3--- R
W
1
0
Interlaced(OSD/black)
Progressive (OSD/OSD)-POR
2x_RGB
-------------2-- R
W
1
0
Double RGB output
Normal RGB output-POR
Fast_enable
--------------1- R
W
1
0
PVCO/SVCO enabled
PVCO/SVCO disabled–POR
Fast_slow
---------------0 R
W
1
0
SCLK is 12.058 MHz
SCLK is 32.768 KHz–POR
Note: * 1 step = 4 pixels
When a POR, SMR, or WDT reset occurs, both the Fast_enable and Fast/Slow
are reset to 0. This event corresponds to an SCLK frequency of 32.768 KHz.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
56
To switch from a 32.768 KHz SCLK to 12 MHz, use the following procedure:
1.
Be sure the registerer bank is set to Bank 1 with the following settings.
CTL_BANK
2.
EQU
%0020
LD
SR, #CTL_BANK
Set the H_Position ﬁeld R6(1)<3:0> to a nonzero value.
HSYNCH_DELAY_MIN EQU
LD
3.
CLK_CONTROL, #HSYNCH_DELAY_MIN
Enable the primary and secondary VCOs by setting by Fast_enable bit
R1(1)<1> to 1.
VCO_ENABLE
4.
%0001
EQU
%0002
LD
SCLK_FREQ, #VCO_ENABLE
Wait one second for the 12 MHz PLL to stabilize (about 33,000 clock cycles
at 32.768 KHz). The delay depends on the external Pll ﬁlter and can vary
signiﬁcantly.
LD A, #11000
VCO_DELAY:
SUB A, #1
JP NZ, VCO_DELAY
5.
Switch the SCLK to a fast clock by setting Fast/Slow bit R(1)<0> to 1.
VCO_ENABLE
FAST_CLK
EQU
EQU
%0002
%0001
LD
SCLK_FREQ,#(VCO_ENABLE|FAST_CLK)
The following code is the complete code to switch from 32.768 KHz clock to 12
MHz clock:
CTL_BAN
EQU
%0020
VCO_ENABLE
EQU
%0002
FAST_CLK
EQU
%0001
HSYNCH_DELAY_MIN EQU
%0001
;
; Set register bank to Bank 1
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
57
;
LD
CLK_CONTROL, #HSYNCH_DELAY_MIN
;
; Change the system clock rate from 32 KHz up to 12 MHz
; before switching over
; 11000 * 3 * 32µSec ~= 1 second
;
LD
A, #11000
VCO_DELAY:
SUB
A, #1
JP
NZ, VCO_DELAY
LD
SCLK_FREQ, #(VCO_ENABLE | FAST_CLK)
;
To switch from the 12 MHz SCLK to 32.768 KHz, use the following procedure:
1.
Switch the SCLK to a 32.768 KHz clock (set Fast/Slow bit R1(1)<0> to 0).
2.
Wait for more than R2(0)<7:0> + 256 clock cycles (approximately 32 µS) for
the SCLK to be switched.
3.
Set the HSYNC_DELAY ﬁeld R6(1)<3:0> to 0FH.
4.
Disable the primary and secondary VCOs (set the Fast_enable bit R1(1)<1>
to 0).
If R1(1)<3> is set to “1” (Interlaced OSD/Black), the interleaving of OSD and Black
can be controlled by writing “1” or “0” into R1(1)<4>; this must be done once every
VSYNC.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
58
Table 28 Register2, Bank1, WDT/STOP (write only) and
9-bit Counter (read only) Control Register
Bit
15
14
13
12
11
10
9
8
R/W
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
7
6
5
4
3
2
1
0
R/W
Reset
R
x
W
0
W
0
reserved reserved reserved reserved reserved
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data
Description
Counter_value
fedcba987-------
R
Reserved
---------65432--
WDT_instr
--------------1-
W
1
0
WDT enable, WDT reset
No effect
STOP_instr
---------------0
W
1
0
Stop
No effect
Counter on Port06 value
Reserved
When a POR, SMR or a WDT reset occurs, the WDT is disabled. The WDT can
be reenabled only after the PVCO and SVCO are enabled, and the part is
switched into a Fast mode (SCLK = 12 MHz).
When switching the part into a SLOW mode (SCLK = 32.768 KHz), the WDT
halts. To return to Fast mode, the WDT must be initialized again.
Table 29 Register3, Bank 1, Standard Control Register
Bit
15
14
13
12
11
10
9
8
R/W
Reset
W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
x
x
x
0
0
R/W
Reset
Note: R = Read W = Write X = Indeterminate
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
59
Reg Field
Bit Position
R W Data Description
Counter_ reset
f---------------
W
1
0
Reset Counter on Port06
No effect
Counter_ON/OFF
-e-------------- R W
1
0
Counter on Port06 is ON
Counter is OFF–POR condition
Mask_HVSYNC
--d------------- R W
1
0
Disable HVSYNC output
HVSYNC IN/OUT–POR condition
Char_size_16_18/20 ---c------------ R W
1
0
16x20 character matrix
16x16 or 16x18 character matrix–
POR
Bank0_sel
----ba---------- R W 00
01
10
11
RAM Bank 00–POR
RAM Bank 01
RAM Bank 02
Reserved
RGBC/Port1
------9--------- R W
1
0
SCLK, R1, R0, G1, G0, B1, B0
P16,P08,P10,P13,P18,P15,P14
I2C_HI/LO_speed
-------8-------- R W
1
0
HI speed (400/50 KHz)
LO speed (100/10 KHz)–POR
CGROM bank
--------7------- R W
1
Bank1 is selected (starts
@1000h)
Bank0 is selected (starts
@0000h)
0
SOVL/Port0F
---------6------ R W
1
0
Semi-transparency
P0f output
OSD_on/off
----------5----- R W
1
0
OSD is enabled
OSD is disabled–POR
RGB_polarity
-----------4----
R W
1
0
Negative
Positive
Positive/Negative
------------3---
R W
1
0
Negative HVSYNC in output mode
Positive HVSYNC in output mode
SYNC/OVL
-------------2--
R W
1
0
HVOVL outputs
HVSYNC outputs
25/30_Hz and
HV_polarity
--------------10
R W
Internal mode only (TV Standard)
10
00
11
01
50 Hz/625 lines support
60 Hz/525 lines support–POR
External mode only (HV Polarity)
Positive
Negative
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
60
Two bits deﬁne the polarity of the HVSYNC signals. Bit <3> deﬁnes the polarity of
the signals when they are conﬁgured as outputs (it does not affect internal HV –
SYNC signals). Bit <1> deﬁnes the polarity of the external HV –SYNC signals
which affect the device synchronization.
Note: 1. The composite SYNC is active in internal mode only.
2.
When using the internally-generated COMPOSITE SYNC
signal, be sure the SCLK is set to 12.09 MHz (R2(0)<7:0> =
71h). This action helps ensure the best HSYNC frequency
approximation.
Table 30 Register 4, Bank 1, ADC Control Register
Bit
R/W
Reset
15
14
13
12
11
10
9
8
reserved
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R
x
R
x
R
x
R
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Reserved
f---------------
HW_shift
-ed------------- R W
00
01
10
11
Direct (unmodiﬁed)–POR
4-bit shift left
4-bit shift right
Byte swap
HSYNC_edge* ---c------------ R W
1
0
HSYNC is leading edge active
HSYNC is trailing edge active–POR
ADC_ref
1
All ADCs use AVCC and AGND as
reference voltage
All ADCs use 2.0V and 1.5V as
reference voltage–POR
----b----------- R W
Reserved
0
ADC_select
-----a---------- R W
1
0
ADC4, ADC5 select
ADC0, ADC1, ADC2, ADC3 select–
POR condition
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
61
Reg Field
Bit Position
R W Data Description
ADCdataPacking
------9--------- R W
Reserved
-------8--------
ADCspeed
--------76------ R W
00
01
10
11
Single conversion–POR condition
SCLK/4
SCLK/6
SCLK/8
ADCsource
----------54---- R W
00
01
10
11
ADC0 (CVI)/ADC4 (P04)–POR
ADC1 (P17)/ADC5
ADC2 (P00)
ADC3 (P05)
ADCdata
------------3210 R
1
0
ADC data packing is on
ADC data packing is off—POR
Reserved
ADC data
Note: *If HSYNC is Leading Edge Active (R4(1)<c> = 1),the actual interrupt is delayed from the
leading edge of HSYNC by 72 cycles (~6µS @12 MHz).
ADC0 has a signal range from 1.5 to 2.0 V. This ﬁeld is always connected to the
Composite Video Input pin and can be clamped to a Ref– voltage (1.5V).
ADC1, ADC2, ADC3, and ADC4 have a signal range from 0 to 5.0 V.
ADC5 features a signal range from 1.5 to 2.0 V. For this ﬁeld, the input signal can
be clamped to a Ref+ voltage (2.0V).
To use the I/O pin as an ADC input, the corresponding port must be set up as an
input (refer to R4(0) and R6(0)).
Table 31 Register5, Bank 1, Timer Control Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
10
9
8
R/W
x
R/W
x
2
1
0
R/W
x
R/W
x
R/W
x
reserved reserved
0
0
Note: R = Read W = Write X = Indeterminate
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
62
Reg Field
Bit Position
R
CAPint_r
f---------------
R
W
W
CAPint_f
-e--------------
R
W
Tout_1s
--d-------------
R
W
Tout_CAP
---c------------
R
W
Data Description
1
0
Rising edge is captured
No rising edge is captured
1
0
Reset ﬂag
No effect
1
0
Falling edge is captured
No falling edge is captured
1
0
Reset ﬂag
No effect
1
0
Timeout of 1s timer
No timeout of 1s timer
1
0
Reset ﬂag
No effect
1
0
Timeout of Capture timer
No timeout of Capture timer
1
0
Reset ﬂag
No effect
Reserved
----ba----------
Reserved
Speed_1s
------98--------
R
W
00
01
10
11
1s
250 ms
62.5 ms
15.625 ms
Port09/
CAP_int*
--------7-------
R
W
1
0
int2 source is Port09
int2 source is Capture timer
CAP_halt*
---------6------
R
W
1
0
Capture timer is halted
Capture timer is running
CAP_edge* ----------54----
R
W
00
01
10
11
No Capture
Capture on rising edge only
Capture on falling edge only
Capture on both edges
CAP_glitch* ------------32--
R
W
00
01
10
11
Glitch ﬁlter is disabled
<8TSCLK is ﬁltered out
<32TSCLK is ﬁltered out
<128TSCLK is ﬁltered out
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
63
Reg Field
Bit Position
CAP_speed --------------10
*
R
W
R
W
Data Description
00
01
10
11
SCLK/4
SCLK/8
SCLK/16
SCLK/32
*Resetting a Capture Timer flag does not modify Capture Counter or Capture register data. When the
glitch filter is enabled, the duration of the pulse is decreased by the CAP_glitch value.
Table 32 Register6, Bank 1, Clock Switch Control Register
Bit
R/W
Reset
15
13
12
11
10
9
8
reserved reserved reserved reserved reserved reserved reserved reserved
0
0
0
0
0
0
0
0
Bit
R/W
Reset
14
7
6
reserved reserved
0
0
5
4
3
2
1
0
R/W
0
R/W
1
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Reserved
fedcba9876------
SVCO/PVCO ----------5-----
No_Switch
-----------4----
R
W
Data Description
Reserved
R
R
1
0
SCLK = SVCO (ﬂag)
SCLK = PVCO (ﬂag) POR
W
1
0
Switch SCLK to PVCO
No effect
W
1
SCLK = PVCO, no clock
switching—POR
Clock switching is enabled
0
H_Position
------------3210
R
W
D
Deﬁnes delay of HSYNC interrupt
by 4X SCLK cycles
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
64
H_Position
The H_position ﬁeld must be set to “F”. The actual horizontal position adjustment
is controlled by R1(1)<c:7>.
No_Switch
The No_switch bit determines if the system clock is permanently set to the
Primary VCO (PVCO) or allowed to switch between PVCO and the Secondary
VCO (SVCO). This bit is set to 1 (NO clock switching) at power up reset.
Caution:
After the system has been switched to fast (12 MHz) clock
both signals feeding into this switch MUST be PVCO
BEFORE the switch setting is changed. Otherwise a short
system clock can result which causes the processor to run
at a higher frequency than speciﬁed. The instruction
fetched from memory, at the location with the out-of-spec
frequency, can be corrupted!
To ensure safe clocks, the following practices are recommended:
1.
Set the No_switch to the required setting before switching from the 32.768
KHz to the fast (12 MHz) clock and leave it there permanently.
2.
Use the following procedure when changing from Switching VCO to
permanent PVCO while running from the fast clock:
3.
-
Simultaneously set the H_position delay to 0x0, while leaving the
No_switch enabled (0), and the SVCO/PVCO left as (0).
-
Wait a minimum of 80 clock cycles to ﬂush any HSYNC out of the system.
-
Simultaneously Switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch enabled (0), and the H_position delay at
0x0.
-
Wait 3 system clock cycles to be sure that the clock has had time to
switch to PVCO.
-
Switch No_switch to No clock switch (write 1 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.
Use the following procedure when changing from permanent PVCO to
Switching VCO while running from the fast clock.
-
Simultaneously set the H_position delay to 0x0, while leaving the
No_switch disabled (1), and the SVCO/PVCO setting as don’t care (0).
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
65
-
Wait a minimum of 80 clock cycles to ﬂush residual H-sync out of the
system.
-
Simultaneously switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch disabled (1), and the H_position delay at
0x0.
-
Wait 3 system clock cycles to be sure that the clock has had time to
switch to PVCO.
-
Switch No_switch to Clock switching is Enabled (write 0 into R6(1)<6>).
The H_position can be set to none-zero at this time as well.
SVCO/PVCO
The SVCO/PVCO bit when read back determines the current setting of the
system clock. Writing a 1 to this bit switches the system clock from its current
setting to PVCO. This switch has a glitch ﬁlter that removes random voltage
spikes. It must be changed back to PVCO. The Z90T366 switches to the SVCO
automatically when it receives an H-sync interrupt. This mechanism exists to
synchronize the system clock exactly with the H-sync trailing edge. The result is a
sharp start of the OSD, jitter free.
An example of a typical SVCO/PVCO switching follows:
1.
System clock is set to PVCO.
2.
H-sync interrupt occurs. (The system clock has automatically been set to the
SVCO). OSD code is executed inside of the H-sync Interrupt Service
Routine (ISR).
3.
Before leaving the ISR, the user switches the clock back to PVCO.
The clamp pulse (deﬁned in R0(1)) is generated only if the SVCO/PVCO switch is
set to PVCO before receiving an HSYNC. The software provides the correct switch
setting before every HSYNC.
Table 33 lists the interrupt/WDT for the WST/SMR control register.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
66
Table 33 Register7, Bank 1, Interrupts/WDT/SMR Control Register
Bit
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
7
6
5
4
3
2
1
0
R/W
Reset
R
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Int_priority
fed------------- R
W
x
See Table 34.
Int_mask
---cba---------- R
W
1xx
0xx
x1x
x0x
xx1
xx0
int2 is enabled
int2 is disabled
int1 is enabled
int1 is disabled
int0 is enabled
int0 is disabled
WDTspeed
------98-------- R
W
00
01
10
11
1.83 ms
7.68 ms
31.12 ms
124.8 ms
SMRﬂag
--------7------- R
0
1
No Stop-Mode Recovery–POR
Stop-Mode Recovery
SMR
polarity
---------6------ R
W
0
1
OR of all SMR sources
NAND of all SMR sources
SMRsource ----------543210 R
W
xx
Bit which corresponds to a “1” in xx
binary representation is active
p09
p14
p13
p12
p11
p10
smr5
smr4
smr3
smr2
smr1
smr0
----------5---------------4---------------3---------------2---------------1---------------0
Data Description
The ﬁnal result of the Stop-Mode Recovery (SMR) is RESET. Ports selected for
SMR must be assigned as inputs, while the other SMR ports must be assigned as
outputs exhibiting an inactive value. If any SMR source is active, and the Stop
Mode is executed, the part resets immediately.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
67
All core interrupts are set to interrupt0 >interrupt1 > interrupt2. These priorities
cannot be changed and are embedded into the core. However, Z90T366
architecture provides ﬂexibility to change the priority of the interrupts by switching
the interrupt sources between interrupt inputs of the Z90T366 core. The
correspondence between HSYNC, VSYNC and 1s/CAP interrupts sources, and int0,
int1, and int2 interrupts inputs of the Z90T366 are listed in Table 34.
Table 34 Interrupt Priority
HSYNC Is
Switched To:
Int_Priority
Field
3.4
VSYNC Is
Switched To:
1s/CAP Is
Switched To:
000
int0
int1
int2
001
int0
int2
int1
010
int1
int0
int2
011
int2
int0
int1
100
int1
int2
int0
101
int2
int1
int0
Bank2 (PWM Registers)
Table 35 lists the bits for the PWM registers.
Table 35 Register0–Register5, Bank 2, PWM 1–6 Registers
Bit
R/W
15
14
13
12
11
10
9
8
reserved reserved reserved reserved reserved reserved reserved reserved
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Reserved
fedcba98--------
PWM_data
--------76543210
R
W
Data
Description
Reserved
R
W
xx
8-bit PWM data
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
68
All of the PWMs feature push-pull. Outputs from all PWMs are staged by one
PVCO clock. The repetition frequency of the PWM output signals can be
calculated from the following equation:
F PVCO
12MHz
F PWM = ----------- = ---------- = 6kHz
8 – 256
2048
When reset, PWM_data registers are not initialized; however, PWM output is set
to 0. Because the PWM is clocked with PVCO, it is better to initialize the
PWM_data before enabling PVCO.
Table 36 lists the bits for the shadow control register.
Table 37 lists the bits for the CGROM offset register.
Table 36 Register6, Bank 2, Shadow Control Register
Bit
R/W
15
14
reserved reserved
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
reserved reserved reserved reserved reserved reserved reserved reserved
Reset
x
x
x
x
x
x
x
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data
Description
Reserved
fe--------------
Lshadow-Color
--dcb-----------
R
W
xx
Left shadow color-POR = 0
Rshadow-Color
-----a98--------
R
W
xx
Right shadow color-POR =
0
Reserved
--------76543210
Reserved
Reserved
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
69
Table 37 Register7, Bank 2, CGROM Offset Register
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W
R/W
Reset
Note: R = Read W = Write X = Indeterminate
3.5
Reg Field
Bit Position
R
W
Data
Description
CGoffset
fedcba9876543210
R
W
xxxx
CGROM offset, POR=0
Bank3 (On Screen Display [OSD] registers)
Table 38 lists the R0(3)- R2(3) character multiplier registers (Read operation).
Table 39 lists the R0(3)–R1(3) Shift Registers (Write operation).
Table 40 lists the R2(3) Attributes Register (Write operation).
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
70
Table 38 Register0–Register2, Bank 3, Read Operation, Character Multiple
Registers
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Name
CGROM Data
Reg Add
Description
cgrom_x2_hi
ffeeddccbbaa9988 R0(3)
cgrom_x3_hi
fffeeedddcccbbba
cgrom_x2_lo
7766554433221100 R1(3)
cgrom_x3_mid
aa99988877766655
cgrom_x1
fedcba9876543210 R2(3)
Single size character R4(3)<6> = 0
cgrom_x3_lo
5444333222111000
Low word of triple size character
R4(3)<6> = 1
High word of double size character
R4(3)<6> = 0
High word of triple size character
R4(3)<6> = 1
Low word of double size character
R4(3)<6> = 0
Middle word of triple size character
R4(3)<6> = 1
Table 39 Register0–Register1, Bank 3, Write Operation, Shift Registers
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Name
CGROM Data
Reg Address Description
current_reg
fedcba9876543210 R0(3)
current line shift register
next/previous_reg
fedcba9876543210 R1(3)
next/previous line shift register
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
71
Registers R1(3) and R0(3) must be loaded with video data one time every 16
cycles. To support smoothing, register R1(3) must be updated every 16 cycles.
The current line register is loaded ﬁrst, followed by next/previous register during
the next cycle. The next/previous register is loaded only if smoothing/fringing
attributes are activated for the current character. If neither register is loaded, the
space character is displayed. There is no difference between loading 0000h into
either register or not loading at all.
Table 40 Register2, Bank 3, Attributes Register, Write Operation
Bit
R/W
Reset
15
14
13
12
11
10
9
8
reserved
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Reserved
f---------------
Background color
-edc------------
Data
Description
Reserved
000
001
010
011
100
101
110
111
Foreground color NOT ----ba9--------Palette Mode
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
Same as Background mode
Palette selection
Palette Mode
----ba----------
00
01
10
11
Palette0
Palette1
Palette2
Palette3
2nd_underline
Palette Mode
------9---------
1
0
Second Underline is active
Second Underline is NOT active
1st_underline
-------8--------
1
0
First Underline is active
First Underline is NOT active
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
72
Reg Field
Bit Position
Shift_video
--------7-------
Data
1
0
Description
Video signal is delayed by 8
pixels
Standard character positioning
Semi-Transparent
---------6------
1
0
Semi-Transparent background
Background color deﬁned by
“background color” ﬁeld
Blinking
----------5-----
1
0
Blinking character
Not blinking character
Italic
-----------4----
1
0
Italic character
Not italic character
Color_delay
------------32--
00
Character color changes
instantly
Color changes with 4 pixels
delay
Color changes with 8 pixels
delay
Color changes with 12 pixels
delay
01
10
11
Shadowing
Note:
--------------10
00
01
10
11
No shadowing
Left shadow
Right shadow
Both shadows
If both the background and foreground colors of a character are
set to be the same, the character’s background is displayed as
transparent.
The attributes register must be loaded 8 cycles after the current line register R0(3)
is loaded. Loading the attributes register enables the OSD logic during the next 16
cycles. If the attributes register is not loaded, there is no active OSD, even if the
current line register R0(3) is loaded. See Table 41.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
73
Table 41 Register3, Bank 3, Read Operation, Attributes Register
Bit
R/W
Reset
15
14
13
12
11
10
9
8
reserved
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Same as R2(3)
Data
Description
Read operation
The data read from the attribute register is a combination of attribute ﬁelds from
the most recently displayed character and control character codes loaded into the
attribute_data register. Character codes are fetched from Video RAM and must be
loaded into the attribute_data register R3(3). Bit <f> of the attribute_data register
(during a read) indicates whether the most recent character was a control or
displayed character. The data read from the attribute_data register must be
directly loaded into attribute register R2(3). Refer to Table 42.
Table 42 Register3, Bank 3, Write Operation, Attribute Data Register
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data
Description
VRAM_data
fedcba9876543210
xxxx
Character code fetched from VRAM
Loading VRAM data into an attribute_data register initializes a CGROM access
cycle. Four clock cycles after the LD instruction, the Z90T366 halts for three clock
cycles to fetch the data from CGROM and latch it into a CGROM data capture
register. After the CGROM data is latched, core operations are resumed. When a
control character code is loaded into the attribute_data register, the CGROM data
from address 0000 hex is fetched. Therefore, ZiLOG recommends placing a
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
74
space character at location 0000 hex in CGROM. Refer to Table 43 through Table
46 for the various VRAM data formats loaded in R3(3).
Table 43 Register 3, Bank 3, Display Character Format for Attribute Data Register,
OSD Mode Write Operation
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Control bit
f---------------
Data Description
0
Display character
Background color* -edc------------
000
001
010
011
100
101
110
111
Foreground color ------ba9------(Not Palette mode)
D
Same as Background_color
Foreground palette --------ba-----(Palette mode)
00
01
10
11
Palette 0 (deﬁned in R6(3)<8–6>
Palette 1 (deﬁned in R6(3)<b–9>
Palette 2 (deﬁned in R6(3)<5–3>
Palette 3 (deﬁned in R6(3)<2–0>
Second underline -------9--------(Palette mode)
1
0
Second underline attribute is active
Second underline attribute is inactive
Attribute8
1
Selected attribute (R7(3),<76>) is
active
Selected attribute (R7(3),<76>) is
inactive
-------8--------
0
Character code
--------76543210
D
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
Deﬁnes the character in CGROM
Note: *If both the background and foreground colors of a character are set to be the same, the
character’s background is displayed as transparent.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
75
Table 44 Register 3, Bank 3, Control Character Format for Attribute Data Register,
OSD Mode Write Operation
Bit
R/W
Reset
15
R/W
x
Bit
R/W
Reset
14
13
12
11
10
9
8
reserved reserved reserved reserved reserved reserved reserved
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
1
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
Control bit
f---------------
Reserved
-edcba98--------
Shift_video
--------7-------
1
0
Video signal is delayed by 8 pixels
Standard character positioning
Transparent
---------6------
1
0
Transparent background
Background color deﬁned by “background
color” ﬁeld
Blinking
----------5-----
1
0
Blinking character
Not blinking character
Italic
-----------4----
1
0
Italic character
Not italic character
Color_delay
------------32--
00
01
10
11
Character color changes instantly
Color changes with 4 pixels delay
Color changes with 8 pixels delay
Color changes with 12 pixels delay
Shadowing
--------------10
00
01
10
11
No shadowing
Left shadow
Right shadow
Both shadows
1
Control character
Reserved
Smoothing is supported for double size (x2) and triple size (x3) characters only.
At reset, the background color in OSD mode is black. Foreground color,
background color, blinking and italic attributes are delayed by 3/4 character. The
smoothing attribute is enabled.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
76
Table 45 Register 3, Bank 3, Display Character Format for Attribute Data Register,
Write Operation CCD Mode
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Control bit
7-------
Character code
-6543210
Data
0
Description
Display character
Deﬁnes the character in CGROM.
Table 46 Register 3, Bank 3, Control Character Format for Attribute Data Register,
CCD Mode, Write Operation
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data
Description
Control bit
7-------
1
Control character
Transparent
-6------
1
0
Transparent background
Background color deﬁned by “background
color” ﬁeld
Blinking
--5-----
1
0
Blinking character
Not blinking character
Italic
---4----
1
0
Italic character
Not italic character
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
77
Reg Field
Bit Position
Data
Description
Foreground color
----321-
000
001
010
011
100
101
110
111
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
First underline
-------0
1
0
Underline attribute is active
Underline attribute is inactive
In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD
characters must be mapped into a 16-bit VRAM data ﬁeld. The hardware supports
compressed character placement in VRAM. Each word in VRAM is represented
by HIGH byte and LOW byte. A currently active byte is selected by R4(3)<c>. The
format and data representation for both bytes is the same.
There are two possible character formats deﬁned: a “display” character and a
“control” character. The code stored in “display” character format deﬁnes a
character code. The “control” character deﬁnes up to seven attributes of the next
character and is presented on screen as a space character.
Combining display and control characters generates of a CCD OSD according to
FCC speciﬁcation. Refer to Table 47.
Table 47 Register4, Bank 3, OSD Control Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W Data Description
Underline
fe--------------
R
W
1x
0x
x1
x0
Second underline is active
Second underline is inactive
First underline is active
First underline is inactive
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
78
Reg Field
Bit Position
R
W Data Description
OSD/CCD
--d-------------
R
W
1
0
OSD mode
CCD mode
CCD_top/btm ---c------------
R
W
1
0
The upper byte in VRAM is used
The lower byte in VRAM is used
Italic_shift
----ba98--------
R
W
x
Deﬁnes delay of the character
Blink_off/on
--------7-------
R
W
0
1
Blinking character is displayed
Blinking character is NOT
displayed (hidden)
MPX_bus
----------65----
R
W
00
01
10
11
x1 character size
x2 character size
x3 character size
Reserved
CGROM
scan_line
-----------43210
R
W
Deﬁnes CGROM addressing
The Underline ﬁeld must be set by ﬁrmware when scan lines that contain
underline information are displayed. The underline bits are ANDed with the
second and ﬁrst underline active ﬁelds of data loaded into attribute register R2(3),
causing the screen character to be underlined.
The Italic shift ﬁeld deﬁnes a delay of video data. It is used to generate italic
characters. The ﬁrmware decrements by 1 (the value of the Italic_shift ﬁeld) for
each consecutive line. The video signal is delayed only for characters that have
the R2(3)<4> (“italic”) bit set to 1.
Table 48 lists the bits for the capture register.
Table 48 Register5, Bank 3, Capture Register, Read Operation
Bit
15
14
13
12
11
10
9
8
R/W
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R
x
R/W
Reset
Note: R = Read W = Write X = Indeterminate
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
79
Reg Field Bit Position
R
Cap_data
R
fedcba9876543210
I2C_saddr --------7654321-
W
Data
Description
16-bit captured data
I2C Slave interface address
W
In Read mode, R5(3) returns the 16-bit captured data from the IRIN pin.
In Write mode, the 7-bit I2C slave interface address must be put in bit 7-1.
Table 49 lists the bits for the palette control register.
Table 49 Register6, Bank 3, Palette Control Register
Bit
R/W
Reset
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data
Description
Palette
f---------------
R
W
1
0
Underline
color
-edc------------
R
W
000
001
010
011
100
101
110
111
Palette1
----ba9---------
R
W
Same as Underline color
Palette0
-------876------
R
W
Same as Underline color
Palette3
----------543---
R
W
Same as Underline color
Palette2
-------------210
R
W
Same as Underline color
Palette mode is active
Palette mode is INACTIVE
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
At POR the palette control register is reset to 0.
Table 50 lists the bits for the output palette control register.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
80
Table 50 Register7, Bank 3, Output Palette Control Register
Bit
R/W
Reset
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
BLANK_delay
fedc------------ R W
D
VBlank and SVBLANK delay
value—%00–POR condition
Background_on/off ----b----------- R W
1
0
Master background is on
Master background is off–POR
condition
Background_color -----a98-------- R W
D
Deﬁnes the color of the Master
background (same as the
palette)
AttrSelect
--------76------ R W
00
01
10
11
1st underline—POR
Semi-transparency
Blinking
CGROM bank select
Smoothing
----------5----- R W
0
1
Smoothing logic disabled—POR
Smoothing logic enabled
Cursor Write
Enable
-----------4---- R
W
0
1
Palette #
------------3210 R W
Return “0”
Cursor parameters write
disabled—POR
Cursor parameters write enabled
Palette number
At POR the Output palette register is set to 0 for digital output.
Table 15 is the look-up table for the color palettes.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
81
4
Instruction Set
The processor instruction set consists of 30 basic instructions. It has been
optimized for high code density and reduced execution time. Single-cycle
instruction execution is possible on most instructions.
The format for Op Codes and addressing modes is provided in the following
tables but is normally not required. The assembler removes the burden of hand
constructing the instruction format. by translating the mnemonics. System
designers can access the instruction format when debugging.
4.1
Instruction Summary
The DSP instruction set can be broken down into the following types of
instructions:
•
•
•
•
•
•
•
Accumulator Modiﬁcation
Arithmetic
Bit Manipulation
Load
Logical
Program Control
Rotate and Shift
Instruction format mnemonics are in Table 51. Table 52 through Table 58 list other
instructions.
Table 51 Instruction Format Mnemonics
Mnemonic
Description
A
Address
am
Accumulator Modiﬁcation
b
RAM Bank
cc
Condition Code
const exp
Constant Expression
d
Destination Address
dest
Destination Value
fm
Flag Modiﬁcation
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
82
Table 51 Instruction Format Mnemonics (Continued)
Mnemonic
Description
op
Op Code
rp
Register Pointer
s
Source Address
src
Source Value
Table 52 Accumulator Modiﬁcation Instructions
Mnemonic
Operands
Instruction
ABS
<cc>, A
Absolute Value
CP
A, <src>
Comparison
DEC
<cc>, A
Decrement
INC
<cc>, A
Increment
NEG
<cc>, A
Negate
Table 53 Arithmetic Instructions
Mnemonic
Operands
Instruction
ADD
A, <src>
Add
CP
A, <src>
Compare
SUB
A, <src>
Subtract
Table 54 Bit Manipulation Instructions
Mnemonic
Operands
Instruction
CCF
None
Clear Carry Flag
CIEF
None
Clear Interrupt Enable Flag
COPF
None
Clear Overﬂow Protection Flag
SCF
None
Set Carry Flag
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
83
Table 54 Bit Manipulation Instructions
Mnemonic
Operands
Instruction
SIEF
None
Set Interrupt Enable Flag
SOPF
None
Set Overﬂow Protection Flag
Table 55
Load Instructions
Mnemonic
Operands
Instruction
LD
<dest>, <src>
Load
POP
<dest>
Pop
PUSH
<src>
Push
Table 56 Logical Instructions
Mnemonic
Operands
Instruction
AND
A, <src>
Logical AND
OR
A, <src>
Logical OR
XOR
A, <src>
Logical Exclusive OR
Table 57 Program Control Instructions
Mnemonic
Operands
Instruction
CALL
A
Call Procedure
JP
A
Jump
RET
None
Return
Table 58 Rotate and Shift Instructions
Mnemonic
Operands
Instruction
RL
<cc>, A
Rotate Left
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
84
Table 58 Rotate and Shift Instructions
4.2
Mnemonic
Operands
Instruction
RR
<cc>, A
Rotate Right
SLL
<cc>, A
Shift Left Logical
SRA
<cc>, A
Shift Right Arithmetic
Instruction Operands
To access the operands for the DSP, use the Register Pointers, Data Pointers,
Hardware Registers, Direct Addressing, Immediate Data and Memory. There are
nine distinct types of instruction operands. Table 59 and Table 60 describe these
instructions.
Table 59 Instruction Operand Summary
Symbolic Name
Syntax
Description
<pregs>
Pn:b
Register Pointer
<dregs>
Dn:b
Data Pointer
<hwregs>
X, Y, PC, SR,
EXTn, A, BUS
Hardware Registers
<accind>
@A
Accumulator Indirect
<direct>
<const exp>
Direct Address Expression
<limm>
#<const exp>
Long (16-Bit) Immediate
<simm>
#<const exp>
Short (8-Bit) Immediate Value
<regind>
@Pn:b
@Pn:b+
@Pn:b+Loop
@Pn:b-Loop
Indirect Addressing of RAM
<memind>
@Dn:b
@Dn:b
@@Pn:b
@@Pn:b+
@@Pn:b+Loop
@@Pn:b-Loop
Indirect Addressing of ROM
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
85
Table 60 Instruction Mnemonics/Operands
#
Instruction
Mnemonic/Operand Representation
1
LD
P2:0, #%F2
LD
<pregs>, <simm>
2
LD
A, @P2:0
LD
<hwreg>, <regind>
3
LD
X, @A
LD
<hwreg>, <accind>
4
LD
Y, #%3CF5
LD
<hwreg>, <limm>
5
SUB
A, @@P2:0
SUB
A, <memind>
6
OR
A, @D2:0
OR
A, <memind>
7
ADD
A, %F2
ADD
A, <direct>
8
PUSH
D1:1
PUSH
<dregs>
<pregs> The register pointer mode is used for loading the pointer with the
appropriate RAM address. This address references the RAM location that stores
the requested data. The pointer can also be used to store 8-bit data when used as
a temporary register. The pointers are connected to the lower 8 bits of the D-bus.
Instruction 1 loads Pointer 2, RAM Bank0 with the value F2h.
<regind> The register indirect mode is used for indirect access to RAM. As
noted in Instruction 2, the register indirect address method is used to get the
operand to multiply it with the accumulator.
<dregs> The data-pointer mode is used as an indirect addressing method
similar to @P2:0. The data pointers access the lower 16 bits of each RAM bank.
Instruction 7 uses indirect addressing to PUSH information onto the stack.
<memind> Pointer or data registers can be used to access program memory.
Both are commonly used to reference program memory. Instructions 5 and 6
display this addressing method. Either pointer is automatically incremented to
assist in transferring sequential data.
<accind> Another method of indirect addressing is using the accumulator to
store the address. Instruction 2 describes how to use this method.
<direct> The absolute RAM address is used in the direct mode. A range
between 0 and 511 (000h to 1FFh) is allowed. The accumulator is used in
conjunction with this method as a source or destination operand. Instruction 7
displays the accumulator as the destination.
<limm> This instruction indicates a long immediate load. A 16-bit word can be
copied directly from the operand into the speciﬁed register or memory.
Instruction 3 uses this method.
<simm> This instruction can only be used for immediate transfer of 8-bit data in
the operand to the speciﬁed RAM pointer.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
86
4.3
Instruction Format
The instruction format that speciﬁes to the processor the action to be taken
consists of the Op Code, destination, source, and other special bits. The
assembler makes this operation transparent by providing mnemonics.
Occasionally, the instruction format and development code can assist in
debugging. Examples to clarify the various instruction formats and explain how
speciﬁc bit patterns are developed and evaluated are provided below.
Most instructions require one 16-bit word containing the information necessary for
the processor to execute the instruction correctly. This process requires one clock
cycle for execution. Immediate addressing, immediate operands, JUMP and CALL
instructions require two 16-bit words (two clock cycles). Each instruction type has
a unique Op Code and format to differentiate various instructions. Different
operations also have unique formats.
The variables a, op, b, d, s, cc, am, fm, rp are used in the instruction
format to depict bits determined by the active instruction.
ADDITION and INC Formats
The Op Code and format for an instruction differ to allow the processor to
differentiate between the instructions. For example, the ADDITION instruction
requires that two operands be deﬁned in the instruction.
ADD A, <regind>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
1
0
0
0
0
S
S
S
S
Op Code
RAM
Bank
Condition Code
Modiﬁcation Code
The INC (increment) instruction requires that a condition and modiﬁcation code
be speciﬁed.
INC A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
1
0
Op Code
Condition Code
Modiﬁcation Code
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
87
INC and SLL Formats
The INC and SLL instructions have the same Op Code with an accumulator
modiﬁcation format. The least signiﬁcant four bits, the modiﬁcation code,
determine the type of operation the accumulator performs.
INC A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
Op Code
Condition Code
Modiﬁcation Code
SLL A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
Op Code
4.4
Condition Code
Modiﬁcation Code
Instruction Bit Codes
The values in a series of bits in a register form patterns called bit codes. Types
of bit codes include the following:
•
•
•
•
•
Condition Codes
Accumulator Modiﬁcation Code
Flag Modiﬁcation Codes
Source/Destination Field Designators
Register Pointer/Data Pointer
The following tables list the options available and their corresponding instructions.
Condition Codes
Table 61 lists the condition codes that are used in accumulator modiﬁcation,
CALL, and JUMP instructions.
Table 61 Condition Code Bits
Bit Code
Mnemonic
Code Value
00000
F
Condition
Code Value
Condition
Code
False
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
88
Table 61 Condition Code Bits (Continued)
Bit Code
Mnemonic
Code Value
Condition
Code Value
Condition
Code
Unused
00001
00010
NU0
UI0 is set to 0
Not User Zero
00011
NU1
UI1 is set to 0
Not User One
00100
NC
C is set to 0
No Carry
00101
NZ
Z is set to 0
Not Zero (Not Equal)
00110
NOV
OV is set to 0
No Overﬂow
00111
PL
N is set to 0
Plus (Not Negative)
Unused
01xxx
10000
T
True
Unused
10001
10010
U0
UI0 is set to 1
User Zero
10011
U1
UI1 is set to 1
User One
10100
C
C is set to 1
Carry
10101
Z
Z is set to 1
Zero (Equal)
10110
OV
OV is set to 1
Overﬂow
10111
MI
N is set to 1
Minus (Negative)
Unused
11xxx
Accumulator Modiﬁcation Codes
Accumulator modiﬁcation codes determine the type of modiﬁcation made to the
value in the accumulator. See Table 62. Condition codes are also used with
CALL, and JUMP instructions.
Table 62 Accumulator Modiﬁcation Bits
Bit Code
Mnemonic
Operation
0000
RR
Rotate Right
0001
RL
Rotate Left
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
89
Table 62 Accumulator Modiﬁcation Bits
Bit Code
Mnemonic
Operation
0010
SR
Shift Right
0011
SL
Shift Left
0100
INC
Increment
0101
DEC
Decrement
0110
NEG
Negate
0111
ABS
Absolute
Flag Modiﬁcation Codes
Flag modiﬁcations initialize or set/reset bits to accommodate interrupts, overﬂows,
and carrys. See Table 63.
Table 63
Flag Modiﬁcation Bits
Bit Code
Mnemonic
Operation
Flag
Value
xx10
CCF
Clear Carry
C
0
xx11
SCF
Set Carry
C
1
x1x0
CIEF
Clear Interrupt Enable
IE
0
x1x1
SIEF
Set Interrupt Enable
IE
1
1xx0
COPF
Clear Overﬂow Protection
OP
0
1xx1
SOPF
Set Overﬂow Protection
OP
1
Source/Destination Field Designators
Register pointers and data pointers provide convenient access to data. The
pointers are a source or destination ﬁeld in instructions. Speciﬁc bit codes are
listed in Table 64. The register pointer offers optional incrementing or
decrementing. This option is speciﬁed by the following instruction:
LD A, @P2:1+
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
90
Table 64 Register Pointer/ Data Pointer Bits
Bit Code
Mnemonic
00xx
NOP
01xx
+1
10xx
-1/loop
11xx
+1/loop
xx00
P0:0 or P0:1
xx01
P1:0 or P1:1
xx10
P2:0 or P2:1
0011
D0:0 or D0:1
0111
D1:0 or D1:1
1011
D2:0 or D2:1
1111
D3:0 or D3:1
Data pointers are automatically incremented when accessing program memory
(for example, LD A, @D0:0) and do not require an incrementing option. Code in
xx11 format is designated for a data pointer when source or destination format is
used.
Additional source or destination designators include the other hardware registers
provided by the processor. To determine if a data pointer, register pointer or a
register is used as a source or destination is discussed in the next section.
Table 65 lists the bit code for mnemonic register names.
Table 65 Register Bits
Bit Code
Mnemonic
0000
Bus
0001
X
0010
Y
0011
A
0100
SR
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
91
Table 65 Register Bits (Continued)
4.5
Bit Code
Mnemonic
0101
STACK
0110
PC
0111
Reserved
1000
EXT0
1001
EXTI
1010
EXT2
1011
EXT3
1100
EXT4
1101
EXT5
1110
EXT6
1111
EXT7
Instruction Format Examples
Refer to the following examples indicating how bit codes are used in an instruction
format.
Instruction Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
b
d
d
d
d
s
s
s
s
Op Code
RAM
bank
Destination
source
Accumulator Modiﬁcation Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
cc
cc
cc
cc
cc
am
am
am
am
Op Code
Condition Code
ACC Modiﬁcation
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
92
Notes:
1.
The Variables a, op, b, d, s, cc, am, fm, rp are used in the
instruction format to depict bits determined by the instruction.
2.
The General Instruction Format requires an Op Code, RAM bank bit,
destination and source addresses. For example, LD A, @P2:1+
Load Instruction Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
0
Op Code
RAM
Bank
Destination
Source
The Op Code (0000001) provides a unique signature for the LD command. The
processor uses this signature to determine the instruction format. The RAM bank
bit is high (equal to 1) because of the instruction deﬁnition b=1 (Pn:b). The
destination bit code is 0011 which corresponds to the accumulator. The source
0110 corresponds to the +1 option and P2:0 or P2:1. The RAM bank bit
indicates that the processor loaded the accumulator with the operand designated
by Pointer 2 Bank1 (P2:1).
Source and destination ﬁelds can be accessed from the register pointers, data
pointers, or registers. The Op Code speciﬁes the type of source and destination.
An Op Code of 0000101 speciﬁes that the source is an indirect address to
program memory (@@P0.0 or @D0:0) and the destination is a register.
Instruction Format Listing
Instruction formats and applicable instructions are listed in Table 66 through Table
72.
Notes:
1.
Several instructions provide various addressing modes to obtain operands;
therefore, the same instruction can have several different formats depending
on the addressing mode.
2.
The variables a, op, b, d, s, ce, am, fm, rp are used in the
instruction format to depict bits determined by the speciﬁc instruction used.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
93
General Instruction Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
b
d
d
d
d
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Table 66 General Instruction Format
Mnemonic
Operands
Bit Code
Hex
ADD
A, @P0:0
1000001 0 0000 0000
8200
AND
A, D1:1
1100110 1 0000 0111
AB07
CP
A,X
0110000 0 0000 0001
6001
LD
A,P
0000000 0 0011 0111
0037
POP
X
0000000 0 0001 0101
0015
PUSH
D0:0
0000001 0 0101 0011
0253
0000000 0 0110 0101
0065
RET
SUB
A,@D1:1
0010101 1 0000 0111
2B07
XOR
A,P2:0
1111001 0 0000 0010
F202
Accumulator Modiﬁcation Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
cc
cc
cc
cc
cc
am
am
am
am
Op Code
Condition Code
ACC Modiﬁcation
Table 67 Accumulator Modiﬁcation Format
Mnemonic
Operands
Bit Code
Hex
Representation
ABS
Z, A
1001000 10101 0111
9157
DEC
A
1001000 00000 0101
9005
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
94
Table 67 Accumulator Modiﬁcation Format
Mnemonic
Operands
Bit Code
Hex
Representation
INC
NZ, A
1001000 00101 0100
9054
NEG
A
1001000 00000 0110
9006
RR
NU0, A
1001000 00010 0000
9020
RL
PL, A
1001000 00111 0001
9071
SLL
C, A
1001000 10100 0011
9143
SRA
U1, A
1001000 10011 0010
9132
Flag Modiﬁcation Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
cc
cc
cc
cc
cc
fm
fm
fm
fm
Op Code
Condition Code
Flag Modiﬁcation
Table 68 Flag Modiﬁcation Format
Mnemonic
Bit Code
Hex Representation
CCF
1001010 00000 0010
9402
CIEF
1001010 00000 0100
9404
COPF
1001010 00000 1000
9408
SCF
1001010 00000 0011
9403
SIEF
1001010 00000 0101
9405
SOPF
1001010 00000 1001
9409
Direct Internal Addressing Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
a
a
a
a
a
a
a
a
a
Op Code
9-Bit Internal Address
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
95
Table 69 Direct Internal Addressing Format
Mnemonic
Operands
Bit Code
Hex
Representation
ADD
A, %FF
1000011 011111111
86FF
AND
A, 255
1010011 011111111
A6FF
CP
A, 255
0110011 011111111
66FF
0000111 000010010
0E12
LD
Short Immediate Addressing Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
rp
rp
rp
a
a
a
a
a
a
a
a
Op Code
Register
Pointer
8-Bit Immediate Address/Data
Table 70 Short Immediate Addressing Format
Mnemonic
Operands
Bit Code
Hex
Representation
LD
P1:1, #%FA
00011 101 11111010
1DFA
Long Immediate Addressing Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
b
d
d
d
d
s
s
s
s
Op Code
RAM
Bank
Destination
Source
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
16-Bit Address/Data
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
96
Table 71 Long Immediate Addressing Format
Mnemonic
Operands
Hex Representation
ADD
A, #%1234
8800 1234
AND
A, #% 26A4
A800 26A4
LD
X, #%6FFC
0810 6FFC
PUSH
#%C32C
0850 C32C
SUB
A, #%2444
2800 2444
XOR
A,#%AFC2
E800 AFC2
JUMP and CALL Instruction Formats
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
cc
cc
cc
cc
cc
s
s
s
s
Op Code
Condition Code
Not Used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
16-Bit Address
Table 72 Jump and Call Instruction Formats
Mnemonic
Operands
Hex Representation
CALL
END
4800 0004
JP
U1, END
4D30 0004
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
97
4.6
Instruction Timing
The DSP can be executed with single cycle instructions using independent data
memory and program memory buses in the system architecture and pipeline
instructions. This method allows the instruction fetch and execution cycles to
overlap. Figure 27 illustrates the execution sequence. The ﬁrst instruction takes
two clock cycles to execute; subsequent executions occur in a single cycle. All
instruction fetch cycles have the same machine timing regardless of whether
external or internal memory is used. Because the DSP contains a two-level
pipeline, the JUMP and CALL instructions do not disrupt the execution process.
In two-word instructions, the second word is fetched while the ﬁrst word is
executing. Because the processor knows that the instruction is a JUMP or CALL,
the second word is transferred to the program counter and the correct address is
fetched into the pipeline. There is no disruption or pipeline ﬂushing. The pipeline
ﬂow is affected when the program counter is the destination for a load. Because
the load (LD) instruction is a single word instruction, the next instruction is fetched
during load execution. To compensate for the instruction in the pipeline, that
instruction is executed as a NOP.
Fetch
the first
instruction
Execute the
first instruction
Fetch
the second
instruction
Execute the
second instruction
Figure 27 Pipeline Execution
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
98
4.7
Instruction Op Codes
Table 73 summarizes essential information about the instruction set.
Table 73 Instruction Op Codes
Inst
Description
Op Code Synopsis
Operands
ABS
Absolute Value
1001000 ABS[<cc>,] <src>
<cc>,A
1
1
ABS NC, A
1001000
A
1
1
ABS A
1001001 ADD<dest>, <src>
A,<pregs>
1
1
ADD A, P0:0
1000001
A,<dregs>
1
1
ADD A, D0:0
1000100
A,<limm>
2
2
ADD A, #%1234
1000101
A,<memind>
1
3
ADD A,
@@P0:0
1000011
A,<direct>
1
1
ADD A, %F2
1000001
A<regind>
1
1
ADD A, @P1:1
1000000
A,<hwregs>
1
1
ADD A, X
1011001 AND <dest>, <src>
A,<pregs>
1
1
AND A, P2:0
1010001
A,<dregs>
1
1
AND A, D0:1
1010100
A,<limm>
2
2
AND A, #%1234
1010101
A,<memind>
1
3
AND A, @@P1:0
1010001
A,<direct>
1
1
AND A, %2C
1010001
A,<regind>
1
1
AND A,
@P1:2+LOOP
1010000
A,<hwregs>
1
1
AND A, EXT3
2
2
CALL sub1
<direct>
2
2
CALL Z, sub2
ADD
AND
CALL
Addition
Bitwise AND
Subroutine Call
0010100 CALL <cc>, <address> <cc>,<direct>
0010100
Words Cycles Examples
CCF
Clear Carry Flag 1001010 CCF
None
1
1
CCF
CIEF
Clear Carry Flag 1001010 CIEF
None
1
1
CIEF
None
1
1
COPF
COPF Clear OP Flag
1001010 COPF
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Table 73 Instruction Op Codes (Continued)
Inst
Description
CP
Comparison
DEC
INC
JP
Decrement
Increment
Jump
Op Code Synopsis
Operands
Words Cycles Examples
CP<src1>,<src2>
0111001
A, <pregs>
1
1
CP A, P0:0
0110001
A, <dregs>
1
1
CP A, D3:1
0110101
A, <memind>
1
3
CP A, @@P0:0
0110011
A, <direct>
1
1
CP A, %FF
0110001
A, <regind>
1
1
CP A, @P2:1+
0110000
A, <hwregs>
1
1
CP A, STACK
0110100
A, <Iimm>
2
2
CP A, #%FFCF
1001000 DEC [<cc>,] <dest>
<cc>, A
1
1
DEC NZ, A
1001000
A
1
1
DEC A
1001000 INC [<cc>,] <dest>
<cc>, A
1
1
INC PL, A
1001000
A
1
1
INC A
0100110 JP [<cc>,] <address>
<cc>, <direct>
2
2
JP NIE, Label
0100110
<direct>
2
2
JP Label
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Table 73 Instruction Op Codes (Continued)
Inst
Description
Op Code Synopsis
LD
Load Destination 0000000 LD <dest>,<src>
with Source
Operands
Words Cycles Examples
A, <hwregs>
1
1
LD A, X
0000001
A, <dregs>
1
1
LD A, D0:0
0001001
A, <pregs>
1
1
LD A, P0:1
0000001
A, <regind>
1
1
LD A, @P1:1
0000101
A, <memind>
1
3
LD A, @D0:0
0000011
A, <direct>
1
1
LD A, 124
0000111
<direct>, A
1
1
LD 124, A
0000100
<dregs>,
<hwregs>
1
1
LD D0:0, EXT7
0001100
<pregs>,
<simm>
1
1
LD P1:1, #%FA
0001010
<pregs>,
<hwregs>
1
1
LD P1:1, EXT1
0000110
<regind>,
<limm>
1
1
LD @P1:1,
#%1234
0000010
<regind>,
<hwregs>
1
1
LD @PM+, X
0001001
<hwregs>,
<pregs>
1
1
LD Y, P0:0
0000001
<hwregs>,
<dregs>
1
1
LD SR, D0:0
0000100
<hwregs>,
<limm>
2
2
LD PC, #%1234
0100101
<hwregs>,
<accind>
1
3
LD X, @A
0000101
<hwregs>,
<dregs>
1
3
LD Y, D0:0
0000001
<hwregs>,
<regind>
1
1
LD A,
@P0:0-LOOP
0000000
<hwregs>,
<hwregs>
1
1
LD X, EXT6
When <dest> is <hwregs>, <dest> cannot be P.
When<dest> is <hwregs> and <src> is <hwregs>,
<dest> cannot be EXTn if <src> is EXTn, <dest>
cannot be X if <src> is X, <dest> cannot be SR if
<src> is SR.
When <src> is <accind> <dest> cannot be A.
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Table 73 Instruction Op Codes (Continued)
Inst
Description
Op Code Synopsis
Operands
Words Cycles Examples
NEG
Negate
1001000 NEG <cc>, A
<cc>, A
1
1
NEG NZ,A
1001000
A
1
1
NEG A
NOP
No Operation
0000000 NOP
None
1
1
NOP
OR
Bitwise OR
1101001 OR <dest>, <src>
A, <pregs>
1
1
OR A, P0:1
1100001
A, <dregs>
1
1
OR A, D0:1
1100100
A, <limm>
2
2
OR A,#%202
1100101
A, <memind>
1
3
OR
A, @@P2:1+
1100011
A, <direct>
1
1
OR A, %2C
1100001
A, <regind>
1
1
OR A,
@P1:0-LOOP
1100000
A, <hwregs>
1
1
OR A, EXT6
<pregs>
1
1
POP P0:0
0000100
<dregs>
1
1
POP D0:1
0000010
<regind>
1
1
POP @P0:0
0000000
A
1
1
POP A
0001001 PUSH <src>, <pregs> <pregs>
1
1
PUSH P0:0
0000001
<dregs>
1
1
PUSH D0:1
0000001
<regind>
1
1
PUSH @P0:0
0000000
<hwregs>
1
1
PUSH BU.S
0000100
<limm>
2
2
PUSH #%2345
0100101
<accind>
1
3
PUSH @A
0000101
<memind>
1
3
PUSH @@P0:0
POP
Pop a Value from 0001010 POP <dest>
the Stack
PUSH Push a Value
onto the Stack
RET
Return from
Subroutine
0000000 RET
None
1
2
RET
RL
Rotate Left
1001000 RL <cc>, A
<cc>, A
1
1
RL NZ, A
1001000
A
1
1
RL A
1001000 RR <cc>, A
<cc>, A
1
1
RR C, A
1001000
A
1
1
RR A
RR
Rotate Right
SCF
Set C Flag
1001010 SCF
None
1
1
SCF
SIEF
Set IE Flag
1001010 SIEF
None
1
1
SIEF
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Table 73 Instruction Op Codes (Continued)
Inst
Description
Op Code Synopsis
SLL
Shift Left Logical 1001000 SLL
Operands
Words Cycles Examples
[<cc>,] A
1
1
SLL NZ, A
1001000
A
1
1
SLL A
SOPF
Set OP Flag
1001010 SOPF
None
1
1
SOPF
SRA
Shift Right
1001000 SRA <cc>, A
<cc>, A
1
1
SRA NZ, A
Arithmetic
1001000
A
1
1
SRA A
Subtract
0011001 SUB <dest>,
A, <pregs>
1
1
SUB A, P1:1
A, <dregs>
1
1
SUB A, D0:1
0010100
A, <limm>
2
2
SUB A, #%2C2C
0010101
A, <memind>
1
3
SUB A, @D0:1
0010011
A, <direct>
1
1
SUB A, %15
0010001
A, <regind>
1
1
SUB A,
@P2:0-LOOP
0010000
A, <hwregs>
1
1
SUB A, STACK
1111001
A, <pregs>
1
1
XOR A, P2:0
1110001
A, <dregs>
1
1
XOR A, D0:1
1110100
A, <limm>
2
2
XOR A, #%3933
1110001
A, <memind>
1
3
XOR A, @P2:1+
1110011
A, <direct>
1
1
XOR A, %2F
1110001
A, <regind>
1
1
XOR A, @P2:0
1110000
A, <hwregs>
1
1
XOR A, BUS
SUB
0010011
XOR
Bitwise Exclusive
OR
<src>
XOR <dest>, <src>
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Instruction Descriptions
The DSP instruction set consists of 30 basic instructions, optimized for high-code
density and reduced execution time. Single-cycle instruction execution is possible
because of the Z90T366 pipeline and system architecture. Table 74 contains a
description for each instruction.
Table 74 Instruction Descriptions
Mnemonic
Mnemonic Expansion
Instruction Operands Lists the types of addressing methods for a speciﬁc
instruction (ABS A or ABS <cc>, A).
Instruction Format
Displays instruction format for register indirect addressing.
Operation
Displays operation sequence.
Affected Flags
Lists ﬂags affected by operation.
Description
Describes the instruction operation.
Examples
A simple example displays the instruction operation and
how registers are affected. The example includes
initialization, instruction and result. It also includes the
number of cycles and instruction length.
Each Assembly Instruction includes an example for each
addressing mode available for the speciﬁc instruction.
The mnemonics listed in Table 75 are used in the instruction format.
Table 75 Instruction Format Mnemonics
Mnemonic
Description
Mnemonic
Description
A
Address
dest
Destination Value
am
Accumulator Modiﬁcation
fm
Flag Modiﬁcation
b
RAM Bank
op
Op Code
cc
Condition Code
rp
Register Pointer
const exp
Constant Expression
s
Source Address
d
Destination Address
src
Source Value
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ABS
Absolute Value
ABS
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
1
1
1
Op Code
Condition Code
ACC Modiﬁcation
Syntax
ABS <cc>, A
ABS A
Operation
If ACC < 0 then -(ACC) -> ACC
Flags: N:
Set if the accumulator has 800000h (see below).
Description
If the contents of the accumulator are determined to be less then 0 (a negative
number), the absolute value of the accumulator is calculated (accumulator
replaced by its two's complement value). Using the condition code provides an
additional method to evaluate a status ﬂag before the absolute value of the
accumulator is calculated.
Note: If the accumulator contains 800000h, the ABS A instruction
stores the value of the two's complement at address 800000h
and sets the Overﬂow and Negative status bits. There is no
overﬂow protection.
Example 1
ABS A
Initialization:
Accumulator contains FFEB00h
SR contains 0000h
Instruction:
ABS A
Result:
Accumulator contains 001500h
SR contains 1000h
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This example uses one word of memory and executes in one machine cycle.
Because the value in the accumulator is less than zero, the two's complement is
performed and the result is placed in the accumulator ABS(FFEBh)=001500h.
The carry bit is set.
Example 2
ABS <cc>, A
Initialization:
Accumulator contains 456400h
Instruction:
ABS MI, A
Result:
Accumulator contains 456400h
This example uses one word of memory and executes in one machine cycle. The
condition code (negative bit) is not set because the accumulator value is positive;
therefore, the instruction is not executed.
<A> =
456400h
ABS MI, A
<A> =
456400h
Example:
<A> =
C56400h
ABS MI, A
<A> =
3AC900h
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ADD
Addition
ADD
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
ADD
A,
<regind>
ADD
A,
<memind>
ADD
A,
<limm>
ADD
A,
<hwregs>
ADD
A,
<direct>
ADD
A,
<pregs>
ADD
A,
<dregs>
Operation
ACC + <source> -> ACC
Flags: C
N:
Z:
OV:
Set if carry from the most signiﬁcant bit is found.
Set if result in the accumulator is negative.
Set if result is 0.
Set if addition exceeds upper (FFFFFh)
or lower (800000h) limit of the accumulator.
Description
The addressed data memory operand is added to the accumulator. The result is
loaded into the accumulator.
Note: The lower eight bits of the accumulator are unchanged while
the add instruction is executed.
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Example 1
ADD A, <regind>
Initialization:
Accumulator contains 123456h
P0:0 contains 4Dh
RAM Bank1: 4Dh contains 8746h
Instruction:
ADD A, @P0:0
Result:
A contains 997A56h
@P0:0 contains 746h
This example uses one word of memory and executes in one machine cycle. The
pointer P0:0 contains the RAM register location (4Dh). The contents of RAM
register 4Dh are added to the accumulator to obtain the sum (874600h +
123456h = 997A56h). The sum is contained in the accumulator and the pointer
is left unchanged. The direct addressing equivalent is ADD A, %4D or ADD A,
77 (4Dh = 77 decimal).
Example 2
ADD A, <memind>
Initialization:
Accumulator contains 123400h
P0:0 contains 21h
RAM Bank0: 21h contains 247Ah
ROM Address: 247Ah contains 0C12h
Instruction:
ADD A, @@P0:0
Result:
A contains lE4600h
P0:0 contains 21h
RAM Bank0: 21h contains 247Bh
This example uses one word of memory and executes in three machine cycles.
The pointer P0:0 contains the RAM register location (21h). The contents of this
register have a ROM address. This address refers to the ROM data placed in the
speciﬁed accumulator by an AND instruction 123400h + 0C1200h = 1E4600h.
When memory indirect addressing is used, the ROM address is automatically
incremented. to provide a convenient method of accessing sequential data. Using
ADD A, @@P0:0+ performs the same operation and also increments the P0:0
content to 22h.
Example 3
ADD A, <limm>
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Initialization:
Accumulator contains 123400h
Instruction:
ADD A, #%0C12
Result:
A contains lE4600h
This example uses two words of memory and executes in two machine cycles.
The immediate operand 0C12h is added to the accumulator to obtain the sum
123400h + 0C1200h = 1E4600h.
Example 4
ADD A,<hwregs>
Initialization:
Accumulator contains 23400Hh
Register X contains 0C12h
Instruction:
ADD A, X
Result:
A contains 1E4600h
This example uses one word of memory and executes in one machine cycle. The
contents of register X are added to the accumulator to obtain the sum. 123400h
+ 0C1200h = 1E4600h. All hardware registers can transfer from <hwregs>.
Example 5
ADD A,<direct>
Initialization:
Accumulator contains 123400h
RAM Bank0: F3h contains 0C12h
Instruction:
ADD A,%F3
Result:
A contains 1E4600h
This example uses one word of memory and executes in one machine cycle.
Register F3h is added to the accumulator to obtain the sum. 123400h +
0C1200h = 1E4600h. An equivalent instruction is ADD A, 243 (F3h = 243
decimal).
Example 6
ADD A, <pregs>
Initialization:
Accumulator contains 123400h
P0:0 contains 56h
Instruction:
ADD A, P0:0
Result:
Accumulator contains 128A00h
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This example uses one word of memory and executes in one machine cycle. The
contents of the pointer register P0:0 is added to the accumulator. 123400h +
005600h = 128A00h. The Pointer Register is connected to the lower 8 bits of
the D-bus. The D-bus is connected to the upper 16-bits of the P-bus. This causes
the pointer register operand to become 005600h before being added to the
accumulator.
Example 7
ADD A,<dregs>
Initialization:
Accumulator contains 123400h
D0: 1 contains 8746h
Instruction:
ADD
Result:
A contains 997A00h
D0: 1 contains 8746h
A,D0:1
This example uses one word of memory and executes in one machine cycle. The
contents of the data pointer D0:1 are added to the accumulator. The sum is
contained in the accumulator and the pointer is left unchanged. The data pointer
contains 8746h.
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AND
BITWISE AND
AND
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
1
1
0
0
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
AND A, <regind>
AND A, <memind>
AND A, <limm>
AND A, <hwregs>
AND A, <direct>
AND A, <pregs>
AND A, <dregs>
AND A, <simm>
Operation
<accumulator>. AND.<source> —> <accumulator>
Flags: N:
Z:
Set if accumulator result is less than 0.
Set if accumulator result is 0.
Description
Data is stored in the speciﬁed accumulator by an AND instruction. The lower eight
bits of the accumulator are cleared when this instruction is executed.
Example 1
AND A, <regind>
Initialization:
Accumulator contains 123456h
P0A contains 45h
RAM Bank1: 45h contains 8746h
Instruction:
AND A, @P0:1
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Result:
Accumulator contains 020400h
This example uses one word of memory and executes in one machine cycle. The
data in RAM Bank1, referenced by RAM pointer 0, is stored in the speciﬁed
accumulator using an AND instruction 123456h.AND.874600h = 020400h.
Example 2
AND A, <memind>
Initialization:
Accumulator contains 123400h
P0:0 contains45h
RAM Bank0: 45h contains 047Ah
ROM Address: 047Ah contains 8746h
Instruction:
AND A, @@P0:0
Result:
A contains 020400h
P0:0 contains 45h
RAM Bank0: 45h contains 247Bh
This example uses one word of memory and executes in three machine cycles.
The pointer P0:0 contains the RAM register location (45h). The contents of this
register has a ROM address. This address refers to the ROM data that is placed
in the speciﬁed accumulator by an AND instruction 123400h.AND.874600h =
020400h. With memory-indirect addressing, the ROM address is automatically
incremented. This provides a convenient method to access sequential data. Using
AND A, @@P0:0+ performs the same operation and also increments the P0:0
content to 46h.
Example 3
AND A, <limm>
Initialization:
Accumulator contains 362400h
Instruction:
AND A, #%1234
Result:
Accumulator contains 122400h
This example uses two words of memory and executes in two machine cycles.
The immediate operand 1234h and an accumulator address are processed with
an AND instruction to produce the result, 362400h.AND.123400h = 122400h.
Example 4
AND A, <simm>
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Initialization:
Accumulator contains 123456h
Instruction:
AND A, #%1F
Result:
Accumulator contains 001400h
This example uses one word of memory and executes in one machine cycle. The
data in the immediate ﬁeld and the contents of the accumulator are processed
with an AND instruction. 123456h.AND.001F00h = 001400h.
Example 5
AND A, <hwregs>
Initialization:
Accumulator contains 123400h
Register X contains OC12h
Instruction:
AND A, X
Result:
A contains 001000h
This example uses one word of memory and executes in one machine cycle. Use
an AND instruction to send the contents of Register X to the accumulator to obtain
the result 123400h.AND.0C1200h = 001000h. All hardware registers can
transfer from <hwregs>.
Example 6
AND A, <direct>
Initialization:
Accumulator contains 123400h
RAM Bank0: F3h contains 0C12h
Instruction:
AND A, %F3
Result:
A contains 001000h
This example uses one word of memory and executes in one machine cycle. Use
an AND instruction to send Register F3h to the accumulator to obtain the result
123400h AND OC1200h = 001000h. An equivalent instruction is AND A, 243
(F3h = 243 decimal).
Example 7
AND A, <pregs>
Initialization:
Accumulator contains 123400h
P0:0 contains 56h
Instruction:
AND A, P0:0
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Result:
Accumulator contains 001400h
This example uses one word of memory and executes in one machine cycle. Use
an AND instruction to send the contents of the pointer register P0:0 to the
accumulator 123400h.AND.005600h = 001400h. The Pointer Register is
connected to the lower 8 bits of the D-bus. The D-bus is connected to the upper
16 bits of the P-bus. This action changes the pointer register operand to 005600h
before being added to the accumulator.
Example 8
AND A, <dregs>
Initialization:
Accumulator contains 123400h
D0:1 contains 2645h
Instruction:
AND A, D0:1
Result:
Accumulator contains 020400h
This example uses one word of memory and executes in one machine cycle. The
data register, D0:1, references the operand 2645h. Use an AND instruction to
send this data register to the accumulator to produce the result
123400h.AND.2645h = 020400h.
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CALL
SUBROUTINE CALL
CALL
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
b
cc
cc
cc
cc
s
s
s
s
Op Code
Condition Code
Not Used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
16-Bit Address
Syntax
CALL <cc>,<direct>
CALL <direct>
Operation
PC + 2 —> STACK
16-Bit Address —> PC
Flags: None
Description
The current Program Counter (PC) register content is incremented by two and
placed on the stack. The address of the speciﬁed label in the CALL instruction is
then placed in the PC register. The jump is made to the appropriate subroutine via
the PC. The condition code option is used if CALL is executed.
Example 1
CALL <direct>
Initialization:
PC contains 1FFBh
FFT2 subroutine address contains F234h
Stack Level 0 contains 0025h
Instruction:
CALL FFT2
Result:
PC contains F234h
Stack Level 0 contains 1FFDh
Stack Level 1 contains 0025h
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This example uses two words of memory and executes in two machine cycles.
The call to the subroutine FFT2 places PC+2 (1 FFDh) on the stack. All
information currently on the stack is pushed up the stack. The subroutine address
is then placed in the PC register. The processor executes the next instruction
addressed by the PC, the FFT2 subroutine.
Example 2
CALL <cc>, <direct>
Initialization:
PC contains 1FFBh
FFT2 subroutine address contains F234h
Stack Level 0 contains 0025h
UO (User Zero Bit) contains 1
Instruction:
CALL UO, FFT2
Result:
PC= F234h
Stack Level 0= 1FFDh
Stack Level 1= 0025h
This example uses two words of memory and executes in two machine cycles.
The condition code UO is tested by the processor before executing the CALL
instruction. Because the UO bit is enabled, the CALL routine is executed exactly
like the example above. The condition code UO is input to the processor that
determines if subroutine FFT2 is used. Another CALL instruction can determine if
another subroutine, FFT1, is used.
Example 3
CALL <direct>
Initialization:
PC contains 1FFBh
FFT2 subroutine address contains F234h
Stack Level 0 contains 0025h
Instruction:
CALL FFT2
Result:
PC containsF234h
Stack Level 0 contains 1FFDh
Stack Level 1 contains 0025h
This example uses two words of memory and executes in two machine cycles.
The call to the subroutine FFT2 places PC+2 (1 FFDh) on the stack. All
information currently on the stack is pushed up the stack. The subroutine address
is then placed in the PC register. The processor executes the next instruction
addressed by the PC, the FFT2 subroutine.
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CCF
CLEAR CARRY FLAG
CCF
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
Op Code
Condition Code
Flag Modiﬁcation
Syntax
CCF
Operation
Zero —> Carry Bit
Flags: C:
Set to 0.
Description
The Clear Carry Flag instruction resets the carry ﬂag with a 0.
Example
CCF
Initialization:
SR contains 3000h
Instruction:
CCF
Result:
SR contains 2000h
C contains 0
This example uses one word of memory and executes in one machine cycle.
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CIEF
CLEAR INTERRUPT ENABLE FLAG
CIEF
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
Op Code
Condition Code
Flag Modiﬁcation
Syntax
CIEF
Operation
Zero —> IE bit
Flags: IE:
Set to 0.
Description
The Clear Interrupt Enable Flag instruction sets the IE ﬂag to 0.
Example
CIEF
Initialization:
SR contains 3080h
Instruction:
CIEF
Result:
SR contains 3000h
IE contains 0
This example uses one word of memory and executes in one machine cycle.
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COPF CLEAR
OVERFLOW PROTECTION FLAG
COPCLEAR
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
Op Code
Condition Code
Flag Modiﬁcation
Syntax
COPF
Operation
Zero —> OP bit
Flags: P:
Set to 0.
The Clear Overﬂow Protection Flag instruction resets the OP ﬂag to 0.
Example
COPF
Initialization:
SR contains 0100h
Instruction:
COPF
Result:
SR contains 0000h
OP contains 0
This example uses one word of memory and executes in one machine cycle.
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CP
COMPARISON
CP
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
CP
A, <regind>
CP
A, <memind>
CP
A, <limm>
CP
A, <hwregs>
CP
A, <direct>
CP
A, <pregs>
CP
A, <dregs>
CP
A, <simm>
Operation
A - <source> —> set appropriate status bits
Flags: C:
Z:
OV:
N:
Set if carry is required for operation.
Set if operands are equal.
Set if operation exceeds the low (800000h) or high
limit (7FFFFFh) of accumulator.
Set if result is negative.
Description
The contents of the register speciﬁed in the instruction are compared to the
contents of the accumulator in 16-bit mode. The register speciﬁed is subtracted
from the accumulator and the appropriate ﬂags are set. Because the registers are
16-bit, a comparison with the 24-bit accumulator requires that the lower eight bits
of the accumulator be ﬁlled with zeros for accurate comparisons. The instruction
does not affect the contents of the accumulator except when the overﬂow
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protection bit is set and an overﬂow occurs after the compare is executed. The
accumulator updates with the appropriate low (800000h) or high (7FFFFFh) limit.
Example 1
CP A, <regind>
Initialization:
A contains 7A2500h
P2:1 contains A4h
RAM Bank1: A4h contains 5463h
Instruction:
CP A, @P2:1
Result:
A contains 7A2500h
SR contains 1000h
This example uses one word of memory and executes in one machine cycle. The
operand referenced by P2:1 is subtracted from the accumulator. 7A2500h 546300h = 25C200h. Because the comparison does not yield a 0, Bit 0 is not
set. The content of the P2:1 register is appended with eight additional 0 bits. For
consistent comparisons, the accumulator must contain zeros in the lower eight
bits.
The accumulator is unaffected by the operation.
Example 2
CP A, <memind>
Initialization:
A contains 7A2500h
P2:1 contains A4h
RAM Bank1: A4h contains 5463h
ROM Address: 5463h contains OC12h
Instruction:
CP A, @@P2:1
Result:
A contains 7A2500h
P2:1 contains A4h
RAM Bank1: A4h contains 5464h
SR contains 1000h
This example uses one word of memory and executes in three machine
cycles.The pointer P2:1 contains the RAM register location (A4h). The contents
of this register have a ROM address. This address refers to the ROM data
compared to the accumulator 7A2500h - OC1200h = 6E1300h. Because the
comparison does not yield a 0, Bit 0 is not set. With memory indirect addressing,
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the ROM address is automatically incremented. Using CP A,@@P2:1 + performs
the same operation and also increments P2:1 content to A5h.
Example 3
CP A, <limm>
Initialization:
A contains 7A2500h
Instruction:
CP A, #%7A25
Result:
A contains 7A2500h
SR contains 3000h
This example uses two words of memory and executes in two machine cycles.
The immediate operand is compared to the accumulator. Because they are equal,
the Zero Flag is set.
Example 4
CP A, <hwregs>
Initialization:
A contains 7A2500h
SR contains 0000h
BUS contains 7A25h
Instruction:
CP A, BUS
Result:
A contains 7A2500h
SR contains 3000h
This example uses one word of memory and executes in one machine cycle. The
<hwreg> operand is subtracted from the accumulator. Because the two operands
are equal, the zero-status bit is set high. <hwregs> can be compared from all
hardware registers.
Example 5
CP A, <direct>
Initialization:
Accumulator contains 7A2500h
RAM Bank0 F3h contains 5463h
Instruction:
CP A, %F3
Result:
A contains 7A2500h
SR contains 1000h
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This example uses one word of memory and executes in one machine cycle.
Register F3h is compared to the accumulator. 7A2500h - 546300h =
25C200h. An equivalent instruction is CP A,243 (173h = 243 decimal).
Example 6
CP A, <pregs>
Initialization:
Accumulator contains 123400h
P0:0 contains 56h
Instruction:
CP A, P0:0
Result:
Accumulator contains 123400h
SR contains 1000h
This example uses one word of memory and executes in one machine cycle. The
contents of the pointer register P0:0 are compared to the accumulator. 123400h
- 005600h = 11DE00h The Pointer Register is connected to the lower 8 bits of
the D-bus. The D-bus is connected to the upper 16 bits of the P-bus. This action
changes the pointer register operand to 005600h before being compared to the
accumulator.
Example 7
CP A, <dregs>
Initialization:
A contains 7A2500h
D2:1 contains 5463h
Instruction:
CP A, D2:1
Result
A contains 7A2500h
SR contains 1000h
This example uses one word of memory and executes in one machine cycle. The
contents of the data pointer D2:1 are compared to the accumulator. 7A2500h 546300h = 25C200h.
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DEC
DECREMENT
DEC
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
1
0
1
Op Code
Condition Code
ACC Modiﬁcation
Syntax
DEC A
DEC <cc>, A
Operation
ACC - 1 —> ACC
Flags: C:
Z:
N:
OV:
Set if carry is required for operation
Set if result is 0.
Set if decrement results in a value less then 0.
Set if upper (7FFFFFh) or lower (800000h) limits
are exceeded.
Description
The accumulator decrements by 1. A condition code can be used to test for a
speciﬁc condition before decrementing.
Example 1
DEC A
Initialization:
A contains 7A2500h
Instruction:
DEC A
Result:
A contains 7A24FFh
This example uses one word of memory and executes in one machine cycle. The
value in the accumulator decrements by 1.
Example 2
DEC <cc>, A
Initialization:
A contains 7A2500h
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Instruction:
DEC MI, A
Result:
A contains 7A2500h
This example uses one word of memory and executes in one machine cycle.
Because the accumulator is not negative, the decrement instruction is not
executed.
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INC
INCREMENT
INC
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
1
0
0
Op Code
Condition Code
ACC Modiﬁcation
Syntax
INC <cc>, A
INC A
Operation
ACC + 1 —> ACC
Flags: C:
Z:
N:
OV:
Set if carry is required for operation.
Set if result is 0.
Set if results in a value less then 0.
Set if upper (7FFFFFh) or lower (800000h) limits
are exceeded.
Description
The Increment instruction adds one to the accumulator. A condition code can be
used to test for a speciﬁc condition for an increment to occur.
Example 1
INC <cc>, A
Initialization:
A contains 7A2500h
Instruction:
INC MI, A
Result:
A contains 7A2500h
This example uses one word of memory and executes in one machine cycle.
Because the accumulator is not negative, the increment instruction is not
executed.
Example 2
INC A
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Initialization:
A contains 7A2500h
Instruction:
INC A
Result:
A contains 7A2501h
This example uses one word of memory and executes in one machine cycle. The
value in the accumulator is incremented by 1.
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JP
JUMP
JP
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
cc
cc
cc
cc
cc
0
0
0
0
Op Code
Condition Code
Not Used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
16-Bit Address
Syntax
JP
<cc>,
JP
<direct>
<direct>
Operation
16-Bit address —> PC
Flags: None
Description
The instruction places the address of the referenced ROM location in the Program
Counter (PC). Because the processor obtains its next instruction address from the
PC, the processor jumps to the appropriate location. A condition code can be used
to test for a speciﬁc condition for a JUMP to occur.
Example 1
JP <cc>, <direct>
Initialization:
Routine 1 address contains 1455h
PC contains 1343h
User 0 input contains 1
Instruction:
JP NUO, Routine 1
Result:
PC contains 1343h
This example uses two words of memory and executes in two machine cycles.
Because the User 0 input is set high, the condition code is not met. Therefore,
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the JUMP instruction does not execute. The User 0 input is used to control the
ﬂow of the software.
Example 2
JP <direct>
Initialization:
Routine 1 address contains 1455h
PC contains 1343h
Instruction:
JP Routine 1
Result:
PC contains 1455h
This example uses two words of memory and executes in two machine cycles.
The value in the program counter is replaced by the Routine 1 address (1455h).
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LD
LOAD
LD
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
b
0
0
1
1
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
LD
A,
<pregs>
LD
<direct>,
A
LD
<hwregs>,
<dregs>
LD
A,
<dregs>
LD
<dregs>,
<hwregs>
LD
<hwregs>,
<limm>
LD
A,
<memind>
LD
<pregs>,
<simm>
LD
<hwregs>,
<accind>
LD
A,
<direct>
LD
<pregs>,
<hwreg>
LD
<hwregs>,
<memind>
LD
A,
<regind>
LD
<regind>,
<limm>
LD
<hwregs>,
<regind>
LD
A,
<hwregs>
LD
<hwregs>,
< pregs>
LD
<hwregs>,
<hwregs>
Operation
<source> —> <destination>
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Flags: None
Description
The LOAD command provides the ability to transfer data to several different
locations in the processor including hardware registers, accumulator, stack,
pointers and memory. All transfers across the various internal buses are
transparent to the user.
Notes:
1.
A load using the X or Y register provides an automatic multiply operation.
This means the operand can be obtained from any register location.
2.
The P register is a read-only register, therefore the destination of the load
cannot be the P register.
3.
LD EXTN, EXTN is not allowed.
4.
A LOAD instruction to the accumulator clears the lower 8 bits of the 24-bit
accumulator.
Example 1
LD A, <regind>
Initialization:
A contains 7A2500h
P2:1 contains A4h
RAM Bank1: A4h contains 5463h
Instruction:
LD A, @P2:1
Result:
A contains 546300h
This example uses one word of memory and executes in one machine cycle.
Indirect addressing through the pointer registers provides access to RAM data.
The data in RAM Bank 1, register A4 is transferred to the accumulator. The
contents of the P2:1 register are appended with eight additional 0 bits. This is
added to verify a correct arithmetic comparison.
Example 2
LD A, <memind>
Initialization:
Accumulator contains 123400h
P0:0 contains 21h
RAM Bank0: 21h contains 247Ah
ROM Address: 247Ah equals OC1 2h
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Instruction:
LD A, @@P0:0
Result:
A contains OC1 200h
P0:0 contains 21h
RAM Bank0: 21h contains 247Bh
This example uses one word of memory and executes in three machine cycles.
The pointer P0:0 contains the RAM register location (21h). The contents of this
register have a ROM address. This address refers to the ROM data that loads to
the accumulator. When memory indirect addressing is used, the ROM address is
automatically incremented. Using LD A, @@P0:0+ has the same result, also
incrementing the P0:0 content to 22h.
Example 3
LD A, <limm>
Initialization:
Accumulator contains 123400h
Instruction:
LD A, #%2474
Result:
A contains 247400h
This example uses two words of memory and executes in two machine cycles.
The immediate operand 2474h loads to the accumulator.
Example 4
LD A, <hwregs>
Initialization:
Accumulator contains 123400h
Register X contains OC12h
Instruction:
LD A, X
Result:
A contains OC1200h
This example uses one word of memory and executes in one machine cycle. The
contents of Register X are loaded to the accumulator. All hardware registers can
transfer from <hwregs>.
Example 5
LD A, <direct>
Initialization:
Accumulator contains 123400h
RAM Bank0 F3h contains OC12h
Instruction:
LD A, %F3
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Result:
A contains OC1200h
This example uses one word of memory and executes in one machine cycle.
Register F3h is loaded to the accumulator. An equivalent instruction is LD A,243
(F3h = 243 decimal).
Example 6
LD A, <dregs>
Initialization:
Accumulator contains123400h
D0: 1 contains 8746h
Instruction:
LD A, D0:1
Result:
A contains 874600h
D0: 1 contains 8746h
This example uses one word of memory and executes in one machine cycle. The
contents of the data pointer D0:1 load to the accumulator.
Example 7
LD A, <pregs>
Initialization:
Accumulator contains 123400h
P0:0 contains 56h
Instruction:
LD A, P0:0
Result:
Accumulator contains 005600h
This example uses one word of memory and executes in one machine cycle. The
contents of the pointer register P0:0 are loaded to the accumulator. The Pointer
Register is connected to the lower 8 bits of the D-bus. The D-bus is connected to
the upper 16 bits of the P-bus. This operation causes the pointer register operand
to become 005600h before being loaded into the accumulator.
Example 8
LD <direct>, A
Initialization:
Accumulator contains 123400h
RAM Bank0: 3Ch contains 5678h
Instruction:
LD %3C, A
Result:
Accumulator contains 123400h
RAM Bank0: 3Ch contains 1234h
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This example uses one word of memory and executes in one machine cycle. The
current value in the accumulator is loaded to the register addressed by the
instruction (3Ch). An equivalent instruction is LD 60, A. (3Ch = 60 decimal).
Example 9
LD <pregs>, <simm>
Initialization:
P2:0 contains 2Fh
RAM Bank0: 3Fh contains 254645h
Instruction:
LD P2:0, #%3F
Result:
P2:0 contains 3Fh
RAM Bank0: 3Fh contains 254645h
This example uses one word of memory and executes in one machine cycle. The
immediate data (3Fh) is loaded into the pointer register P2:0. This action
provides a convenient method for initializing pointer registers.
Example 10
LD <pregs>, <hwregs>
Initialization:
P0: 1 contains 2Fh
Y contains 2376h
Instruction:
LD P0:1, Y
Result:
P0: 1 contains 76h
Y contains 2376h
This example uses one word of memory and executes in one machine cycle. The
lower 8-bits of the Y register are transferred to the pointer register P0:1. All
hardware registers can transfer from <hwregs>.
Example 11
LD <regind>, <limm>
Initialization:
P0:1 contains 2Fh
RAM Bank0: 2Fh contains 2376h
Instruction:
LD @P0:1, #%35B8
Result:
P0:1 contains 2Fh
RAM Bank1: 2Fh contains 35B8h
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This example uses two words of memory and executes in two machine cycles.
The immediate operand 35B8h is transferred to the Register 2Fh of RAM Bank1.
Example 12
LD <hwregs>, <pregs>
Initialization:
P2:0 contains 2Fh
X Register contains 8B87h
Instruction:
LD X,P2:0
Result:
P2:0 contains 2Fh
X Register contains 002Fh
This example uses one word of memory and executes in one machine cycle. The
contents of the P2:0 pointer (2Fh) are loaded into the X register. Transfer to
<hwreg> is possible to all hardware registers except the read-only P register.
Example 13
LD <hwregs>, <dregs>
Initialization:
D2:0 contains 3C87h
Accumulator contains 8BB722h
Instruction:
LD A,D2:0
Result:
D2:0 contains 3C87h
Accumulator contains 3C8700h
This example uses one word of memory and executes in one machine cycle. The
contents of the D2:0 pointer (3C87h) are loaded into the accumulator. Transfer to
<hwregs> is possible to all hardware registers except the read-only P register.
Example 14
LD <hwregs>, <limm>
Initialization:
Stack0 contains 8B2Fh
Stack1 contains 0000h
Instruction:
LD Stack, #%35B8
Result:
Stack0 contains 35B8h
Stack1 contains 8B2Fh
This example uses two words of memory and executes in two machine cycles.
The immediate data is pushed onto the stack as previous stack data is pushed up
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the stack. Transfer to <hwregs> is possible to all hardware registers except the
read-only P register.
Example 15
LD <hwregs>, <accind>
Initialization:
EXT7 Register contains 8B87h
Accumulator contains 77B6h
ROM 77B6h contains 387Dh
Instruction:
LD EXT7, @A
Result:
EXT7 Register contains 387Dh
Accumulator contains 77B6h
This example uses one word of memory and executes in one machine cycle. The
contents of the ROM Register 77B6h (387Dh) are loaded into External Register
7. Transfer to <hwregs> is possible to all hardware registers except the read-only
P register and the accumulator register.
Example 16
LD <hwregs>, <memind>
Initialization:
Y Register contains 1234h
P0:0 contains 21h
RAM Bank0: 21h contains 247Ah
ROM Address: 247Ah contains 0C12h
Instruction:
LID Y, @@P0:0
Result:
Y Register contains 0C12h
P0:0 contains 21h
RAM Bank0: 21h contains 247Bh
This example uses one word of memory and executes in three machine cycles.
The pointer P0:0 contains the RAM register location (21h). The contents of this
register have a ROM address that refers to the ROM data that loads to the Y
register. Transfer to <hwregs> is possible to all hardware registers except the
read-only P register. When memory indirect addressing is used the ROM address
is automatically incremented. Using LD A,@@P0:0+ performs the same
operation and also increments the P0:0 content to 22h.
Example 17
LD <hwregs>, <regind>
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Initialization:
X Register contains 7A25h
P21 contains A4h
RAM Bank1: A4h contains 5463h
Instruction:
LD X, @P2:1
Result:
X Register contains 5463h
This example uses one word of memory and executes in one machine cycle.
Indirect addressing through the pointer registers provides access to RAM data.
The data in RAM bank 1, register A4 is transferred to the X register. Transfer to
<hwreg> is possible to all hardware registers except the read-only P register.
Example 18
LD <hwregs>, <hwregs>
Initialization:
X Register contains 7A25h
EXT5 Register contains 789Ah
Instruction:
LD X, EXT5
Result:
X Register contains 789Ah
EXT5 Register contains 789Ah
This example uses one word of memory and executes in one machine cycle. The
EXT5 Register contents are transferred to the X register. Transfer to <hwregs> is
possible to all hardware registers except the read-only P register.
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NEG
NEGATE
NEG
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
1
1
0
Op Code
Condition Code
ACC Modiﬁcation
Syntax
NEG A
NEG <cc>, A
Operation
-ACC —> ACC
Flags: N
Set if result is a negative number.
Two special cases are:
1.
If ACC contains 000000 after execution, then N and 0V are cleared, and Z
and C are set
2.
If ACC contains 800000 after execution, then N and 0V are set; and Z and
C are cleared.
The accumulator is replaced with a negative of the current value. To achieve
this state, the two's complement is performed.
Example 1
NEG A
Initialization:
A contains 003654h
Instruction:
NEG A
Result:
A contains FFC9ACh
This example uses one word of memory and executes in one machine cycle.
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Z90T366 ROM and Z90T361 OTP
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138
Example 2
NEG <cc>, A
Initialization:
A contains 000111h
Carry bit contains 1
Instruction:
NEG C, A
Result:
A contains FFFEEFh
This example uses one word of memory and executes in one machine cycle.
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Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
139
NOP
NO OPERATION
NOP
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Syntax
NOP
Operation
PC+ 1—> PC
Flags:
None
Description
The NOP instruction causes the processor to continue operation for one cycle
without affecting previous registers and I/0.
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140
OR
BITWISE OR
OR
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
OR A, <regind>
OR A, <memind>
OR A, <limm>
OR A, <hwregs>
OR A, <direct>
OR A, <pregs>
OR A, <dregs>
OR A, <simm>
Operation
ACC .OR. source —> ACC
Flags: N
Z
Set If result in accumulator is negative.
Set If result is 0.
Description
The accumulator performs an OR instruction on the contents of the speciﬁed
register. The upper 16 bits of the accumulator are used. The result is placed in the
accumulator. The OR instruction is frequently used to compare speciﬁc bits to
assist in program control.
The lower eight bits of the accumulator are unchanged after
execution of the OR instruction.
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Example 1
OR A, <regind>
Initialization:
Accumulator contains 3264A0h
P0:0 contains E2h
RAM Bank0: E2h contains 1126h
Instruction:
OR A, @P0:0
Result:
A contains 336600h
This example uses one word of memory and executes in one machine cycle. Use
an OR instruction to reference the operand P0:0 with the upper 16 bits of the
accumulator. The result is stored in the accumulator. 3264A0h OR. 1126A0h =
3366A0h.
Example 2
OR A,<memind>
Initialization:
A contains 3264A0h
P2:1 contains A4h
RAM Bank 1: A4h contains 5463h
ROM Address: 5463h contains 1126h
Instruction:
OR A, @@P2:1
Result
A contains 3366A0h
P2:1 contains A4h
RAM Bank0: A4h contains 5464h
SR contains 0000h
This example uses one word of memory and executes in three machine cycles.
The pointer P2:1 contains the RAM register location (A4h). The contents of this
register have a ROM address. This address refers to the ROM data that is
compared to the accumulator. 3264A0h.OR.112600h = 3366A0h. With
memory indirect addressing, the ROM address is automatically incremented.
Using ORA,@@P0:0+ performs the same operation and also increments the P0:0
content to A5h.
Example 3
OR A, <limm>
Initialization:
A contains 3264A0h
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Instruction:
OR A, #%1126
Result:
A contains 3366A0h
SR contains 0000h
This example uses two words of memory and executes in two machine cycles.
The accumulator performs an OR instruction on the immediate data.
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POP
POP VALUE FROM STACK
POP
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
b
d
d
d
d
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
POP <pregs>
POP <dregs>
POP <regind>
POP <hwregs>
Operation
STACK 0 —> <destination>
Stack n —> Stack N-1
Flags: None
Description
The current value of the stack is copied to the speciﬁed register. Because the
stack is a last-in, ﬁrst-out (LIFO) hard-wired architecture, the copy and shift of
data remaining in the stack are all performed in a single cycle.
The POP instruction provides the ability to control information sent to the stack,
making it possible to expand the stack using software.
Example 1
POP <pregs>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
P0:0 contains 24h
Instruction:
POP P0:0
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Result
Stack 0 contains 0426h
P0:0 contains 06h
This example uses one word of memory and executes in one machine cycle. The
destination of Stack 0 (item on top of stack) is P0:0. The 8-LSBs of the data in
stack 0 are loaded into P0:0. At transfer, Stack 1 is automatically moved to
Stack 0.
Example 2
POP <dregs>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
D0:0 contains 7676h
Instruction:
POP D0:0
Result:
Stack 0 contains 0426h
D0:0 contains 0C06h
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by D0:0. When
transferred, Stack 1 is automatically moved to Stack 0.
Example 3
POP <regind>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
P0:0 contains 24h
RAM Bank0: 24h contains 42A4h
Instruction:
POP @P0:0
Result
Stack 0 contains 0426h
RAM Bank0: 24h contains 0C06h
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by P0:0. 24h is the
register location in RAM Bank0 to which the stack item is transferred. At transfer,
Stack 1 is automatically moved to Stack 0.
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Example 4
POP <hwregs>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
X Register contains 089Ch
Instruction:
POP X
Result:
Stack 0 contains 0426h
X Register contains 0C06h
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by the X Register. At
transfer, Stack 1 is automatically moved to Stack 0. Transfer to <hwregs> is
possible to all hardware registers except the read-only P register.
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PUSH
PUSH VALUE ONTO STACK
PUSH
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
PUSH <pregs>
PUSH <dregs>
PUSH <memind>
PUSH <accind>
PUSH <regind>
PUSH <hwregs>
PUSH <direct>
PUSH <limm>
Operation
<source> —> Stack
Stack n —> Stack n+ 1
Flags: None
Description
The contents of the speciﬁed register are placed on the stack. Because the stack
is a last-in, ﬁrst-out (LIFO) hard-wired architecture, the placement and shifting of
current stack data is performed in a single cycle.
The PUSH instruction provides the ability to control information sent to the stack,
making it possible to expand the stack through software.
Example 1
PUSH <pregs>
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Z90T366 ROM and Z90T361 OTP
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Initialization:
Stack 0 contains 0C06h
P1:1 contains A4h
Instruction:
PUSH P1:1
Result
Stack 1 contains 0C06h
Stack 0 contains 00A4h
This example uses one word of memory and executes in one machine cycle. The
pointer P1:1 contains the 8-bit value A4h. The
16-bit value, 00A4h, is pushed onto the stack. At transfer, Stack 0 is automatically
moved to Stack 1.
Example 2
PUSH <dregs>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
D1:1 contains 42A4h
Instruction:
PUSH D1:1
Result
Stack 1 contains 0C06h
Stack 0 contains 42A4h
This example uses one word of memory and executes in one machine cycle. The
pointer D1:1 is pushed onto the stack. At transfer, Stack 0 is automatically moved
to Stack 1.
Example 3
PUSH <memind>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
RAM Bank0: 24h contains 42A4h
P1:1 contains A4h
RAM Bank1: A4h contains 5463h
ROM Address 5463h contains 1126h
Instruction:
PUSH @@P1:1
Result:
Stack 1 contains 0C06h
Stack 0 contains 1126h
RAM Bank1: A4h contains 5464h
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This example uses one word of memory and executes in three machine cycles.
When memory indirect addressing is used, the ROM address is automatically
incremented. Using OR A,@@P0:0+ performs the same operation and also
increments the P0:0 content to A5h.
Example 4
PUSH <accind>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
Accumulator contains 42A4h
ROM address 42A4h contains 4C45h
Instruction:
PUSH @A
Result
Stack 1 contains 0C06h
Stack 0 contains 4C45h
This example uses one word of memory and executes in one machine cycle.
Indirect addressing with the accumulator points to the ROM memory (42A4h) The
data in this location is pushed onto the stack. At transfer, Stack 0 is automatically
moved to Stack 1.
Example 5
PUSH <regind>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
P1:1 contains A4h
RAM Bank1: A4h contains 42A4h
Instruction:
PUSH @P1:1
Result:
Stack 1 contains 0C06h
Stack 0 contains 42A4h
RAM Bank1: A4h contains 42A4h
This example uses one word of memory and executes in one machine cycle. The
pointer P1:1 contains the RAM register location (A4h). The data at this location is
pushed onto the stack. At transfer, Stack 0 is automatically moved to Stack 1.
Example 6
PUSH <hwregs>
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Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
X Register contains 42A4h
Instruction:
PUSH X
Result:
Stack 1 contains 0C06h
Stack 0 contains 42A4h
This example uses one word of memory and executes in one machine cycle. The
data in the X register is pushed onto the stack. At transfer, Stack 0 is
automatically moved to Stack 1. Transfer from <hwregs> is possible from all
hardware registers.
Example 7
PUSH <direct>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
RAM Bank0: 24h contains 42A4h
Instruction:
PUSH %24
Result:
Stack 1 contains 0C06h
Stack 0 contains 42A4h
This example uses one word of memory and executes in one machine cycle. The
instruction (24h) provides the direct register address. The value contained in this
register is pushed onto the stack (42A4h). At transfer, Stack 0 is automatically
moved to Stack 1.
Example 8
PUSH <limm>
Initialization:
Stack 1 contains 0426h
Stack 0 contains 0C06h
Instruction:
PUSH #%5757
Result:
Stack 1 contains 0C06h
Stack 0 contains 5757h
This example uses two words of memory and executes in two machine cycles.
The immediate operand 5757h is pushed onto the stack. At transfer, Stack 0 is
automatically moved to Stack 1.
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RET
RETURN FROM SUBROUTINE
RET
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
Op Code
RAM
Bank
Destination
Source
Syntax
RET
Operation
Stack 0 —> PC
Stack n —> Stack n-1
Flags: None
Description
The current stack information is popped from the stack and placed in the Program
Counter (PC) register. The jump is made from the subroutine via the PC.
Example
RET
Initialization:
Stack 1 contains 0624
Stack 0 contains 0401
PC contains 06DF
Instruction:
RET
Result:
Stack 0 contains 0624
PC contains 0401h
This example uses one word of memory and executes in one machine cycle.
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RL
ROTATE LEFT
RL
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
1
1
1
Op Code
Condition Code
ACC Modiﬁcation
Syntax
RL A
RL <cc>,A
Operation
C <= 23 ------------ < ---------- 8 <= C
Flags: N
Z
C
Set if result of accumulator is negative
Set if result is zero.
Set if MSB is set before rotate.
Description
The upper 16 bits of the accumulator are rotated left through the carry bit. The
lower 8 bits remain unchanged while the resultant LSB, bit 0, is placed with the
value 0 (see the accumulator section).
Example 1
RL A
Initialization:
A contains 226A84h
Carry bit contains 1
Instruction:
RL A
Result:
A contains 44D584h
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The
upper 16 bits (226Ah) are shifted left through the carry bit to produce 44D5h. The
lower 8 bits (84h) remain unchanged.
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Example 2
RL <cc>, A
Initialization:
A contains 226A84h
Carry bit contains 0, Z=0
Instruction:
RL Z, A
Result:
A contains 226A84h
This example uses one word of memory and executes in one machine cycle. The
condition code 0 is not set; therefore, the instruction is not executed.
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RR
ROTATE RIGHT
RR
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
0
0
0
Op Code
Condition Code
ACC Modiﬁcation
Syntax
RR A
RR <cc>, A
Operation
C =>23 ---- > 8 = => 7 - -> -- 0 —> discarded
Flags: N
Z
C
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before rotate.
Description
The upper 16 bits of ACC are rotated right through the carry bit. The MSB of the
lower 8 bits also obtains the data shifted from the LSB of upper 16 bits. The lower
8 bits are shifted right with the LSB being discarded.
Example 1
RR A
Initialization:
A contains 226A84h
Carry bit contains 0
Instruction:
RR A
Result:
A contains 113542h
This example uses one word of memory and executes in one machine cycle. The
upper 16 bits (226Ah) are shifted right through the carry bit to produce 1135h.
The lower 8 bits (84h) are shifted right to provide 42h.
Example 2
RR <cc>, A
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Z90T366 ROM and Z90T361 OTP
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Initialization:
A contains 226A84h
Carry bit contains 0, Z=0
Instruction:
RR Z, A
Result:
A contains 226A84h
This example uses one word of memory and executes in one machine cycle. The
condition code 0 is not set; therefore, the instruction is not executed.
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SCF
SET CARRY FLAG
SCF
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
op
op
op
op
op
op
op
cc
cc
cc
cc
cc
fm
fm
fm
fm
Op Code
Condition Code
Flag Modiﬁcation
Syntax
SCF
Operation
1 —> Carry Bit
Flags: C
Set to 1.
Description
The Set Carry Flag instruction places a one in the carry bit (bit 12 of the Status
Register).
Example
SCF
Initialization:
SR contains 2000h
Instruction:
SCF
Result:
SR contains 3000h
C contains 1
This example uses one word of memory and executes in one machine cycle.
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SIEF
SET INTERRUPT ENABLE FLAG
SIEF
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
cc
cc
cc
cc
cc
0
1
0
1
Op Code
Condition Code
Flag Modiﬁcation
Syntax
SIEF
Operation
1 —> IE bit
Flags: None
Description
The instruction places a 1 in bit 7 of the status register and is used to enable
interrupts.
Example
SIEF
Initialization:
SR contains 3000h
Instruction:
SIEF
Result:
SR contains 3080h
IE contains 1
This example uses one word of memory and executes in one machine cycle.
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SLL
SHIFT LEFT LOGICAL
SLL
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
0
1
1
Op Code
Condition Code
ACC Modiﬁcation
Syntax
SLL A
SLL <cc>, A
Operation
discarded <— C <= 23 - - - - < - - - -0 <= 0
Flags: N
Z
C
Set if result of accumulator is negative
(bit 23 set to 1).
Set if result is 0.
Set if MSB is set before shift.
Description
All 24 bits of the accumulator are shifted left through the carry bit. The MSB, bit
23, passes through the carry bit before being discarded. The LSB, bit 0, is ﬁlled
with a zero. Subsequent shifts cause additional zeroes to be shifted in.
Example 1
SLL A
Initialization:
A contains 226A84h
Carry bit contains 0
Instruction:
SLL A
Result:
A contains 226A84h
This example uses one word of memory and executes in one machine cycle. All
24 bits of the accumulator are shifted left through the carry bit, producing the
result 44D508h.
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Example 2
SLL <cc>, A
Initialization:
A contains 226A84h
Carry bit contains 0
Instruction:
SLL MI, A
Result:
A contains 226A84h
This example uses one word of memory and executes in one machine cycle. The
condition code N is not set, and the instruction is not executed.
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SOPF
SET OVERFLOW PROTECTION FLAG
SOPF
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
Op Code
Condition Code
Flag Modiﬁcation
Syntax
SOPF
Operation
1 —> OP bit
Flags: None
Description
The Set Overﬂow Protection Flag instruction places a one in bit 8 of the status
register. If an ALU operation exceeds the limits of the processor, the overﬂow
protection sets the overﬂow ﬂag (OV) and holds the limit value in the accumulator.
Example
SOPF
Initialization:
SR contains 0000h
Instruction:
SOPF
Result:
SR contains 0100h
OP contains 1
This example uses one word of memory and executes in one machine cycle.
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SRA
SHIFT RIGHT ARITHMETIC
SRA
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
cc
cc
cc
cc
cc
0
0
0
0
Op Code
Condition Code
ACC Modiﬁcation
Syntax
SRA A
SRA
<cc>, A
Operation
23 => 23 --- > ---- 0 => discarded
Flags: N
Z
C
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before the shift.
Description
All 24 bits of the accumulator are shifted right with sign extension through the
carry bit. The MSB, bit 23, is replicated in vacated bits. The LSB, bit 0, is passed
through the carry before it is discarded.
Example 1
SRA A
Initialization:
A contains 226A84h
Carry bit contains 0
Instruction:
SRA A
Result:
A contains 113542h
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. All
24 bits of the accumulator are shifted right. The MSB, bit 23, is copied into bit 22.
The LSB, bit 0, is discarded.
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Example 2
SRA
<cc>, A
Initialization:
A contains 226A84h
Carry bit contains 0, N=0
Instruction:
SRA A
Result:
A contains 113542h
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The
condition code is set; therefore, the instruction is executed. The initialization of the
accumulator sets the PL (NN) condition code.
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SUB
SUBTRACT
SUB
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
SUB A, <regind>
SUB A, <memind>
SUB A, <limm>
SUB A, <hwregs>
SUB A, <direct>
SUB A, <pregs>
SUB A, <dregs>
SUB A, <simm>
Operation
ACC – (Source) —> ACC
Flags: C
N
Z
OV
Set if a carry from the most signiﬁcant bit is
performed.
Set if the result in the accumulator is negative.
Set if the result is 0.
Set if the addition exceeds the upper (7FFFFFh)
or lower (800000h) limit of the accumulator.
Description
The addressed data memory operand is subtracted from the accumulator. The
result is loaded into the accumulator.
The lower eight bits of the accumulator are cleared by the execution of the
subtract instruction.
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Example 1
SUB A, <regind>
Initialization:
Accumulator contains 874600h
P0: 1 contains 45h
RAM Bank1: 45h contains 1234h
Instruction:
SUB A, @P0:1
Result:
A contains 751200h
@P0:1 contains 1234h
This example uses one word of memory and executes in one machine cycle. The
contents of the register pointed by P0:1 are subtracted from the accumulator. The
difference is contained in the accumulator and the pointer is left unchanged. The
register pointer contains 45h. Because the pointer references RAM Bank1, the
absolute register is 145h (325). Therefore, the contents of register 145h are
subtracted from the accumulator. 874600h - 123400h = 751200h. The direct
addressing equivalent is SUB A,%145 or SUB A,325.
Example 2
SUB A, <memind>
Initialization:
Accumulator contains 874600h
P0:0 contains 21h
RAM Bank0: 21h contains 247Ah
ROM Address: 247Ahcontains 1234H
Instruction:
SUB A, @@P0:0
Result:
A contains 751200h
P0:0 contains 22h
RAM Bank0: 21 h contains 247Bh
This example uses one word of memory and executes in three machine cycles.
The pointer is used for memory indirect addressing. The pointer contains the
address of the RAM (address 247Ah). The RAM contains the address of the
requested ROM data (data 247Ah). This operand is subtracted from the
accumulator. 874600h - 123400h = 751200h.
Example 3
SUB A, <limm>
Initialization:
Accumulator contains 874600h
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Instruction:
SUB A, #%1234
Result:
Accumulator contains 751200h
This example uses two words of memory and executes in two machine cycles.
The immediate operand 8746h is subtracted from the accumulator. 874600h 123400h = 751200h.
Example 4
SUB A, <hwregs>
Initialization:
Accumulator contains 874600h
Register X contains 1234h
Instruction:
SUB A, X
Result:
A contains 751200h
This example uses one word of memory and executes in one machine cycle. The
contents of Register X are subtracted from the accumulator. 874600h 123400h = 751200h. Transfer from <hwregs> is possible from all hardware
registers.
Example 5
SUB A, <direct>
Initialization:
Accumulator contains 874600h
RAM Bank0: F3h contains 1234h
Instruction:
SUB A, %F3
Result:
A contains 751200h
This example uses one word of memory and executes in one machine cycle. The
contents of register F3h are subtracted from the accumulator. 874600h 123400h = 751200h. An equivalent instruction is SUB A, 243 (F3h = 243
decimal).
Example 6
SUB A, <dregs>
Initialization:
Accumulator contains 874600h
D0: 1 contains 1234h
Instruction:
SUB A, D0:1
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Result:
A contains 751200h
D0:1 contains 1234h
This example uses one word of memory and executes in one machine cycle. The
contents of the data pointer D0:1 are subtracted from the accumulator. The
difference is contained in the accumulator and the pointer is left unchanged.
Example 7
SUB A, <pregs>
Initialization:
Accumulator contains 874600h
P0:0 contains 56h
Instruction:
SUB A, P0:0
Result:
Accumulator contains 86F000h
This example uses one word of memory and executes in one machine cycle. The
contents of pointer register P0:0 are subtracted from the accumulator. 874600h
- 005600h = 86F000h. The Pointer Register is connected to the lower 8 bits
of the D-bus. The D-bus is connected to the upper 16 bits of the P-bus. This
causes the pointer register operand to become 005600h before it is subtracted
from the accumulator.
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XOR
BITWISE EXCLUSIVE OR
XOR
Instruction Word
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
1
b
0
0
0
0
s
s
s
s
Op Code
RAM
Bank
Destination
Source
Syntax
XOR A, <regind>
XOR A, <memind>
XOR A, <limm>
XOR A, <hwregs>
XOR A, <direct>
XOR A, <pregs>
XOR A, <dregs>
XOR A, <simm>
Operation
A.XOR.<operand> —> A
Flags: C
N
Z
OV
Set if carry from the most signiﬁcant bit is
performed.
Set if result in the accumulator is negative.
Set if result is 0.
Set if operation exceeds upper (7FFFFFh) or lower
(800000h) limit of accumulator.
Description
With the accumulator, perform an XOR instruction on the addressed data memory
operand. The result loads into the accumulator.
The lower eight bits of the accumulator are cleared by the XOR instruction.
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Example 1
XOR A, <regind>
Initialization:
Accumulator contains 005600h
P0:0 contains 00h
RAM Bank0: 00h contains 1234h
Instruction:
XOR A, @P0:0
Result:
A contains 126200h
This example uses one word of memory and executes in one machine cycle. The
pointer is used for memory indirect addressing. The pointer contains the address
of the RAM (address 00h). Location 00h has operand 1234h. With the
accumulator, 005600h, perform an XOR instruction to obtain the result 126200h.
Example 2
XOR A, <memind>
Initialization:
A contains 3264A0h
P2:1 contains A4h
RAM Bank1: A4h contains 5463h
ROM Address: 5463h contains 1126h
Instruction:
XOR A, @@P2:1
Result
A contains 2342A0h
P2:1 contains A41h
RAM Bank1: A4h contains 5464h
SR contains 0000h
This example uses one word of memory and executes in three machine cycles.
The pointer P2:1 contains the RAM register location(A4h). The contents of this
register have a ROM address. This address refers to the ROM data compared to
the accumulator. 3264A0h.XOR.112600h = 2342A0h. When indirect memory
addressing is used, the ROM address is automatically incremented. Using XOR
A, @@P2:1+ performs the same operation and also increments the P21 content
to A5h.
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Example 3
XOR A, <limm>
Initialization:
A contains 3264A0h
Instruction:
XOR A, #%1126
Result:
A contains 2342A0h
SR contains 0000h
This example uses two words of memory and executes in two machine cycles.
Perform an XOR instruction on the immediate data.
Example 4
XOR A, <hwreg>
Initialization:
A contains 3264A0h
SR contains 0000h
BUS contains 1126h
Instruction:
XOR A, BUS
Result:
A contains 2342A0h
SR contains
This example uses one word of memory and executes in one machine cycle. With
the accumulator, perform an XOR instruction on the <hwreg> operand.
Example 5
XOR A, <direct>
Initialization:
Accumulator contains 3264A0h
RAM Bank0: F3h contains 1126h
Instruction:
XOR A, %F3
Result:
A contains 2342A0h
SR contains 0000h
This example uses one word of memory and executes in one machine cycle.
Register F3h is compared to the accumulator. 3264A0h.XOR.112600h =
2342A0h. An equivalent instruction is XOR A, 243 (F3h = 243 decimal).
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169
5
System Design Considerations
The Z90T366 provides the ability to
•
•
•
•
•
decode closed-caption transmissions
display characters on the screen
manipulate analog and digital control circuits
monitor keypad button and infrared signals directly
generate OSD if the Z90T366 receives vertical and horizontal
synchronization signals
In a typical system, normal transmission is received and demodulated. The
signals received from the color decoder and deﬂection unit control the CRT
display. To display characters generated by the Z90T366 requires a video
multiplexor which enables the CRT display’s RGB signals and synchronization to
be controlled by the video outputs from the processor. When the controller has to
display a character on the screen, the multiplexor is switched, and the processor’s
video signals appear on the display.
The band-limited, A/C-coupled composite video signal is clamped internally to the
negative reference voltage (REF–) during the back porch interval. It is then
passed to the analog-to-digital converter through a 6:1 multiplexor. The digital
signal is then decoded to extract the closed-caption text embedded in the video
signal. The characters received are generated as video signals and are then
passed to the display.
When a detectable composite video signal is received, the SYNC separator
extracts the horizontal and vertical synchronization signals and passes them to
the deﬂection module of the television. The FLYBACK signals from the deﬂection
coils are fed back to the Z90T366. The controller uses these signals to align its
video signals with those of the normal display. If the composite video signal is not
present, video synchronization is provided by the controller. In this case, the
SYNC signal pins are set to be outputs. The pins then feed to the deﬂection unit
which controls the display. The SYNC generators can be conﬁgured to provide
either HSYNC and VSYNC, or H-FLYBACK and V-FLYBACK.
Analog functions such as volume and color controls can be controlled by pulse
width modulated outputs from the Z90T366. Additional digital controls like channel
ﬁne tuning are controlled via the serial I2C bus.
An infrared remote control receiver can be directly decoded through the capture
register, and keypad input can be scanned by directly controlling I/O pins as
keyscan ports.
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The processor clock is available by referencing an internal phase locked loop to
an external 32.768 KHz crystal oscillator. The oscillator minimizes EMI emissions
from the clock circuitry. The internal system clock frequency can be selected as
12.058 MHz in normal operation or 32.768 KHz in low power consumption SLEEP
mode (usually used if there is a general system power failure). The Z90T366’s
STOP mode suspends processor clocking for a power-down.
Program, display, and character graphics memory are on the chip, eliminating the
requirement for external memory components. Characters can be displayed as
two or three times normal size. Smoothing and fringing circuits enhance display
appearance.
Figure 28 diagrams a typical application of the Z90T366 Television Controller as
an embedded controller in a television.
L
FM Audio
Audio
R
RGB
Color
Decoder
Unit
Tuning
Control
CRT
H & V Deflection
Deflection
SYNC/
Flyback
RGB
Amplifiers
SYNC/
Flyback
Composite
Video
Television
Tuner, IF
RGB
MUX
OSD
OVL
Control
eZVision
Z90T366 Television Controller
Front Panel
Keypad
I2C Bus
IR
Detector
Figure 28 System Block Diagram
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171
6
Electrical Characteristics
Table 76 Absolute Maximum and Minimum Ratings
Sym
Parameter
VCC
Power supply voltage
VID
Min
Max
Units
Conditions
0
7
V
Input voltage
–0.3
VCC+0.3
V
Digital inputs
VIA
Input voltage
–0.3
VCC+0.3
V
Analog inputs (A/D0–A/D4)
VO
Output voltage
–0.3
VCC+0.3
V
All push-pull digital outputs
VO
Output voltage
–0.3
VCC+0.3
V
PWM outputs
IOH
Output current high
–10
mA
one pin
IOH
Output current high
–100
mA
all pins
IOL
Output current low
20
mA
one pin
IOL
Output current low
200
mA
all pins
0
70
oC
–65
150
oC
TA
Operating temperature
TS
Storage temperature
Table 77 DC Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Power supply voltage
4.75
5.00
5.25
V
VIL
Input voltage low
0
0.4
0.2 VCC
V
VIH
Input voltage high
0.7VCC
3.6
VCC
V
VIHR
Input voltage High on
Reset pin
0.75
VCC
4.2
VCC
V
VPU
Maximum pull-up
voltage
VCC
V
For PWM
VOL
Output voltage low
0.4
V
@ IOL = 1 mA
VOH
Output voltage high
VCC–
0.4
4.75
V
@ IOH = –0.75 mA
IOL
Output current low
7.2
12
mA
@ VOL = 0.4v
IOL1
Output current low
12
20
mA
@ VOL = 0.8v
0.16
Conditions
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172
Table 77 DC Characteristics (Continued)
Symbol
Parameter
Min
Typ
IOH
Output current high
4.0
7.0
mA
@ VOH = VCC–0.4
IOH1
Output current high
16
20
mA
@ VOH = 2.4v
VXL
Input voltage XTAL1
low
VXH
Input voltage XTAL1
high
0.6
VCC
IIR
Reset input current
25
90
150
µA
VRL = 0V
IIL
Input leakage
–3.0
0.01
3.0
µA
@ 0V and VCC
ICC
Supply current
60
100
mA
All ports are inputs, RGB is in
digital mode
ICC
Supply current
30
50
mA
All ports are inputs, RGB is in
analog mode
ICC1
Supply current
5
10
mA
Sleep mode @ 32.768 KHz
ICC2
Supply current
50
100
µA
Stop mode all PWM outputs
are @ VIN = 0V
6.1
Max
Units
0.3 VCC
V
Conditions
External clock generator
driven
V
DC Peripherals
Table 78 R, G, and B Analog Output
Output Voltage (30 KΩ Load)
Settling Time
@ VCC = 4.75V
@ VCC = 5.00V
@ VCC = 5.25V
data = 00
0.00V–0.65V
0.00V–0.70V
0.00V–0.75V
data = 01
1.70V–0.20V
1.80V–0.20V
1.90V–0.20V
data = 10
2.80V–0.25V
2.90V–0.25V
3.00V–0.25V
data = 11
3.90V–0.30V
4.00V–0.30V
4.10V–0.30V
70% of DC Level, 10pF Load
<50ns
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173
Table 79 ADC0/Small Range*
Sym
Parameter
Min
Typ
Max
UR–
Clamping voltage at ADC0
1.0
1.5
2.0
V
ADC0
Input voltage for level 0
UR––(UR++UR–)/15
UR–
UR–+(UR+–UR–)/15
V
ADC1
Input voltage for level 1
UR–
UR–+(UR+–UR–)/15
UR–+2(UR+–UR–)/15
V
ADC2
Input voltage for level 2
UR–+(UR+–UR–)/15
UR–+2(UR+–UR–)/15
UR–+3(UR+–UR–)/15
V
ADC3
Input voltage for level 3
UR–+2(UR+–UR–)/15
UR–+3(UR+–UR–)/15
UR–+4(UR+–UR–)/15
V
ADC4
Input voltage for level 4
UR–+3(UR+–UR–)/15
UR–+4(UR+–UR–)/15
UR–+5(UR+–UR–)/15
V
ADC5
Input voltage for level 5
UR–+4(UR+–UR–)/15
UR–+5(UR+–UR–)/15
UR–+6(UR+–UR–)/15
V
ADC6
Input voltage for level 6
UR–+5(UR+–UR–)/15
UR–+6(UR+–UR–)/15
UR–+7(UR+–UR–)/15
V
ADC7
Input voltage for level 7
UR–+6(UR+–UR–)/15
UR–+7(UR+–UR–)/15
UR–+8(UR+–UR–)/15
V
ADC8
Input voltage for level 8
UR–+7(UR+–UR–)/15
UR–+8(UR+–UR–)/15
UR–+9(UR+–UR–)/15
V
ADC9
Input voltage for level 9
UR–+8(UR+–UR–)/15
UR–+9(UR+–UR–)/15
UR–+10(UR+–UR–)/15
V
ADCA
Input voltage for level A
UR–+9(UR+–UR–)/15
UR–+10(UR+–UR–)/15 UR–+11(UR+–UR–)/15
V
ADCB
Input voltage for level B
UR–+10(UR+–UR–)/15
UR–+11(UR+–UR–)/15 UR–+12(UR+–UR–)/15
V
ADCC Input voltage for level C
UR–+11(UR+–UR–)/15
UR–+12(UR+–UR–)/15 UR–+13(UR+–UR–)/15
V
ADCD Input voltage for level D
UR–+12(UR+–UR–)/15
UR–+13(UR+–UR–)/15 UR–+14(UR+–UR–)/15
V
ADCE
Input voltage for level E
UR–+13(UR+–UR–)/15
UR–+14(UR+–UR–)/15 UR–+15(UR+–UR–)/15
V
ADCF
Input voltage for level F
UR–+14(UR+–UR–)/15
RIN
Input impedance
1.0
UR+
Units
UR–+16(UR+–UR–)/15
V
MΩ
Note: * The Input voltage level indicated in the table is a switch point from one ADC level to another. To be in the middle of
the level half, LSB ((UR+–UR–)/(15*2)) must be added. The Input voltage must be prorated accordingly if VCC is changed.
1.5–2.0V; TA = 0ºC to 70ºC; VCC = 4.75V to 5.25V
PS005901-1100
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Table 80 ADC1-ADC4/Full range
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
0000
0.000 ± 0.15
0100
1.250 ± 0.15
1000
2.500 ± 0.15
1100
3.750 ± 0.15
0001
0.312 ± 0.15
0101
1.563 ± 0.15
1001
2.813 ± 0.15
1101
4.063 ± 0.15
0010
0.625 ± 0.15
0110
1.875 ± 0.15
1010
3.125 ± 0.15
1110
4.375 ± 0.15
0011
0.934 ± 0.15
0111
2.188 ± 0.15
1011
3.438 ± 0.15
1111
4.688 ± 0.15
Input impedance
> 1.0 MΩ
Note: 0-5.0V; Vcc = 5.0V; Temp=0-70C
6.2
AC Characteristics
Table 81 lists the AC characteristics.
Table 81 AC Characteristics
Sym
Parameter
Min
Typ
Max
Units
TPC
Input clock period
16
32
100
µsec
TRC, TFC
Clock input Rise and Fall
TDPOR
Power on reset delay
TWRES
Power on reset minimum width
TDHS
HSYNC incoming signal width
1
TDVS
VSYNC incoming signal width
TDES
0.8
12
nsec
1.2
sec
5 TPC
µsec
10
15
µsec
1
200
10000
µsec
Time delay between leading edge of
VSYNC and HSYNC in EVEN ﬁeld
–12
0
+12
µsec
TDOS
Time delay between leading edge of
VSYNC and HSYNC in ODD ﬁeld
20
32
44
µsec
TWHVS
HSYNC/VSYNC edge width
0.5
2.0
µsec
Note: *All timing of the I2C bus interface are defined by related specifications of the I2C bus interface.
Note: TA = 0˚C to 70˚C; VCC=4.75V to 5.25V; FOSC=32,768Hz
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6.3
ANALOG RGB
The RGB outputs in analog mode are controlled current sources with an internal
load. These outputs display gamma-corrected, VCC prorated characteristics. See
Table 82, Table 83, and Figure 29.
Table 82 RGB Voltage Speciﬁcation
Parameter
Min
Typical
Max
Units
Supply voltage
4.5
5.0
5.5
V
Full scale voltage
1.8V
1.9V (0.40 * VCC)
2.2V
V
2/3 scale voltage
1.5V
1.6V (0.33 * VCC)
1.815V
V
1/3 scale voltage
1.125V
1.2V (0.25 * VCC)
1.375V
V
Zero scale voltage
—
0.0V (0.00 * VCC)
+0.1 V
V
Note: *Measured with 3.9 kΩ load.
Table 83 RGB Time Speciﬁcation
Parameter
Min
Typical
Max
Units
Output rise time
50
65
ns
Output fall time
50
65
ns
Note: *Measured with 4 kΩ resistor in parallel with 30 pF capacitor load.
Z90T366
R1
R, G, B
R2
R1 + R2 = 3.9K
VOUT = 2 * R2 4.0
Figure 29 Recommended Application Schematics
PS005901-1100
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eZVision 64 KWord Television Controller with OSD
176
7
Packaging
Figure 30 and Table 84 indicate the controlling dimensions.
26
1
E1
27
52
D
Detail A
Q1
A2
A1
L
S
e
B
B1
Controlling dimension in inches
E
Optional end lead config
Detail A
C
eA
Figure 30 52-Pin SDIP Package Dimensions
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
177
Table 84 Controlling Dimensions
Symbol
Millimeter
Min
Max
Inch
Min
Max
A1
0.51
—
0.020
—
A2
3.25
3.94
0.128
0.155
B
0.38
0.53
0.015
0.021
B1
0.89
1.14
0.035
0.045
C
0.23
0.38
0.009
0.015
D
—
47.50
—
1.870
E
15.24
15.75
0.600
0.620
E1
13.72
14.10
0.540
0.555
e
1.778 TYP
0.070 TYP
eA
15.49
16.76
0.610
0.660
L
3.05
3.68
0.120
0.145
Q1
1.52
1.91
0.060
0.075
S
0.64
1.78
0.025
0.070
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
178
8
Ordering Information
Device
Order number
Description
Z90T361 64 KWord OTP
Z90T361PZ016SC
16 MHZ, 64 KWord OTP
Television Controller with OSD
Z90T366 64 KWord ROM
Z90T366PZ016SC Rxxxx*
16 MHZ, 64 KWord Mask ROM
Television Controller with OSD
Emulation Kit
Z9036900ZEM
Emulator/ Programmer
OTP Adapter
Z903xx00100ZDP
OTP programming adapter
Evaluation Board
Z9034600ZCO
OSD Evaluation Board
Note: * xxxx is a unique ROM number assigned to each customer code
ROM Code Submission
ROM Code Submission Instructions
ROM Code can be submitted on ZiLOG’s web site at http://www.zilog.com.
Top Mark Information
Mark Permanency: 3X soak into Alpha 2110 at 63° to 70°C, for 30 seconds
duration each soak. Mechanical brush after each soak.
PS005901-1100
Z90T366 ROM and Z90T361 OTP
eZVision 64 KWord Television Controller with OSD
179
Customer Feedback Form
eZVision Z90T366 Product Speciﬁcation
If there are any problems while operating this product, or any inaccuracies in the
speciﬁcation, please copy and complete this form, then mail or fax it to ZiLOG.
Suggestions welcome!
Customer Information
Name
Country
Company
Phone
Address
Fax
City/State/Zip
E-Mail
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: [email protected]
Problem Description or Suggestion
Provide a complete description of the problem or suggestion. For speciﬁc
problems, include all steps leading up to the occurrence of the problem. Attach
additional pages as necessary.
PS005901-1100

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