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Z90356 ROM and Z90351 OTP
64 KWord Television Controller with OSD
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The Z90356 and Z90351 are the ROM and OTP versions of a Television Controller with
On-Screen Display (OSD) that contains 64 KWords of program memory and 1K words of
RAM.
•
The Z90351 is the one-time programmable (OTP) controller used to develop code
and prototypes for specific television applications or initial limited production.
Program ROM and Character Generation ROM (CGROM) in the Z90351 are both
programmable.
The Z90351 requires ZiLOG’s Z90369ZEM Emulator with its proprietary ZiLOG
Developmental Studio (ZDS) software for programing. To view code effects, the
emulator uses a ZOSD board that connects directly to a television screen. Refer to
Figure 1.
Z90369 In-Circuit
Emulation Kit
ZOSD Board
Z90359
Z90351
Develop
code on PC
Download Code to
Z90359 ICE chip
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Video Display
Review Code
on TV Display
Program the
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The Z90356 incorporates the ROM code developed by the customer with the
Z90351. Customer code is masked into both program ROM and CGROM.
The Z90356 Television Controller with OSD is based on ZiLOG’s Z89C00 RISC
processor core. The Z89C00 is a second-generation, 16-bit, fractional, two’s complement
CMOS Digital Signal Processor (DSP). Most instructions are accomplished in a single
clock cycle. This processor features a 24-bit Arithmetic Logic Unit (ALU) and a 24-bit
Accumulator. The processor also contains a six-level stack and three vectored interrupts.
0QVG The Z89C00 multiplier is disabled in the Z90356 controller.
The Z90356 contains 64 KWords of program ROM and 1 KWord of on-chip data RAM.
Program ROM space can hold an unlimited number of characters with a 16x16, 16x18,
and 16x20 programmable matrix in relocated Character Generation ROM (CGROM),
which is only restricted by the available ROM. In addition, the Z90356 contains four
external register banks with eight registers each. Additional Control Registers (AR) are
available to control new peripheral blocks like palette banks and memory management.
An internal 24-MHz/2 system clock has a Phase Lock Loop (PLL) driven by an external
32.768-KHz crystal.
A six-channel, 4-bit Analog to Digital Converter (ADC) supports the following:
•
Analog front panel control
•
Audio level input
•
Vertical Blanking Interval (VBI) data capture
Six Pulse Width Modulator (PWM) outputs allow low-cost digital-to-analog conversion
(DAC). The PWMs have 8-bit resolution to control video and audio attributes.
A Master/Slave I2C (Inter Integrated Circuit) bus interface provides serial system
interconnect to common peripheral functions.
Twenty-five programmable I/O pins provide flexibility for other digital input/output
functions.
An IR (InfraRed) remote capture register facilitates reliable remote data capture.
On-chip Horizontal Synchronization (HSYNC) and Vertical Synchronization (VSYNC)
circuits generate a video time base (typically used for VCR and set-top applications) in the
absence of an available video signal.
Micro-programmable OSD generation logic provides flexibility to tailor OSD features and
functions. In addition to normal OSD functions, Closed Caption is supported in
accordance with FCC Report and Order on GEN Docket No. 91-1, dated April 12, 1991.
Expanded Data Service (XDS) capability is supported as well.
The Z90356 is packaged in a 52-pin SDIP package.
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Figure 2 is a block diagram of the internal structure of the chip. Figure 3 illustrates the pin
locations, and Table 1 describes the function of each pin.
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The Z89C00 core is a high-performance DSP that has a modified Harvard-type
architecture with separate program and data memories. The design has been optimized for
processing power and silicon space.
The Z89C00 used in the Z90356 device has been modified. The multiplier is disabled and
is not accessible. However, the X and Y registers in the multiplier are still available and
can be used as general-purpose registers. Refer to ZiLOG’s Z89C00 documentation.
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The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit
Accumulator. The other input is connected to the 24-bit P-Bus; the upper 16 bits are
connected to the 16-bit D-Bus.
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Several instructions are executed in one machine cycle. Long immediate instructions and
Jump or Call instructions are executed in two machine cycles. When the program memory
is referenced in internal RAM indirect mode, it requires three machine cycles. An
additional machine cycle is required if the PC is selected as the destination of a data
transfer instruction. This only occurs with a register indirect branch instruction.
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A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses
or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction returns
the contents of the stack to the PC.
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The Z90356 has 11 physical internal registers and four banks of eight external registers. In
addition, it has nine virtual registers. The 11 internal registers are defined in Table 2, and
the status register is defined in Table 3.
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X and Y are 16-bit general purpose registers.
A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data
is transferred into this register, it goes into the 16 MSBs and the least significant eight bits
are set to zero. Only the upper 16 bits are transferred to the destination register when the
Accumulator is selected as a source register in transfer instruction.
SR is the Status Register that contains the ALU status and the control bits listed in
Table 3. The status register is always read in its entirety. S15-S12 are set/reset by the
hardware and can only be read through software. They are set or reset by the ALU after an
operation.
S8-S0 can be written by software. S8, if 0 (reset), allows the hardware to overflow. If S8 is
set, the hardware clamps at maximum positive or negative values instead of overflowing.
S7 enables interrupts. S6–S5 are used for “short form direct” addresses, which are
described below. The definitions of S2-S0 are listed in Table 4.
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Pn:b are the pointer registers for accessing data RAM.
(n= 0, 1, 2 refer to the pointer number)
(b = 0, 1 refers to RAM bank 0 or 1).
They can be read from or written to directly and can point directly to locations in data
RAM or indirectly to Program Memory.
PC is the Program Counter. When this register is assigned as a destination register, one
NOP machine cycle is automatically added to adjust the pipeline timing.
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The Z90356 module is capable of accessing eight external registers directly using only the
three external register address signals that are normally available. Two user bits (Status
register S6-S5) are combined with the register address signals to provide the ability to
address four banks of eight registers each. The registers most critical for speed are located
together in Bank 3. In this specification, all external registers are referred to as:
RX(Y)<Z>
where:
X is a register number within a register bank;
Y is a bank number; and
Z is a bit field number
An external register bank can be selected by setting bits 6 and 5 in the status register to
define the bank, then specifying the address of the register on the external register address
bus.
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External registers reside on the chip and are used to control the operation of all the
peripheral modules in the device. By reading or writing to the fields in the external
registers, the user can interact with the peripheral devices on the chip.
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BUS is a read-only register that, when accessed, returns the contents of the D-Bus. It is
a virtual register. (Physical RAM does not exist on the chip.)
Dn:b These eight data pointers refer to possible locations in RAM that can be used as
pointers to locations in program memory. The programmer decides which location to
choose two bits from in the status register and which two bits in the operand. This means
only the lower 16 possible locations in RAM can be specified. At any one time there are
eight usable pointers, four per bank, and the four pointers are in consecutive locations in
RAM.
For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refers to
locations 4/5/6/7 in RAM bank 0.
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Data RAM, so they can be used as a limited method for writing to RAM.
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Additional Control Registers (AR) control new peripheral blocks like palette banks and
memory management. To activate ARs, R0(1)<b> must be set to “1.” ARs can be disabled
by setting R0(1)<b> = 0, (POR) for software backward compatibility or if access to RAM
location 1FFh is required.
The 128 eight-bit control registers (referred as AR or ARx<y:z>) use RAM-mapped I/O
access. Location 1FFh in RAM is used to address up to 128 byte-width ARs. The AR
number and written data are encoded into the data field as illustrated in Figure 4.
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When writing to address 1FFh, the Data Write Bit (DWB) and AR number are latched,
depending on whether the DWB data field is either written to the selected port (latched) or
discarded (not latched). The AR number and corresponding data are read after reading
from the previously latched DWB address 1FFh.
To write to the AR, the data must be written to address 1FFh; DWB must be set to “1,” the
port number must be specified in bits 8–14, and actual data must be specified in bits 0–7.
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0QVG The DWB and port number are latched for further reading if necessary.
To read from the AR, the address must be previously latched by writing it to address 1FFh
with DWB set to “0.” Bits 0–7 have no meaning. Because the bits are not going to be
written in this mode, only the port number is latched.
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A, #%1E00; latch AR30, data is not written
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A, %1FF; read from AR30-%1EXX, where XX is current content
At least one cycle delay (NOP) is required between two consecutive accesses to the AR. If
access is performed by a two-cycle instruction, no delay is necessary.
External memory must exhibit access times of less than 60 ns. Table 5 lists the additional
control registers.
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The addresses in RAM can be specified in one of three ways. Refer to Figure 5.
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The Z90356 has 64K words of Read Only Memory (ROM) and 1K words of Random
Access Memory (RAM).
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The 64K words mask ROM is designed to provide storage for both program memory
(PROGROM) and character set graphic pixel arrays (CGROM). The address boundary
between these applications is dependent on the storage required for character graphics.
The program ROM section can, in theory, be accessed anywhere in the addressable ROM
space; however, because CGROM usually starts at location 0000h, program ROM resides
in the higher address locations. The maximum available ROM space for program memory
depends on the ROM reserved for CGROM (for an application) and the ROM size of the
device selected.
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CGROM can be placed anywhere in the 64K ROM address space by setting the CGROM
address offset register R7(2). This offset is added to the character address before accessing
ROM. By modifying the CGROM offset, several fonts can be accessed (limited by ROM
size only). When reset, R7(2) =0 (no offset) for backward compatibility with existing
software. Refer to Figure 6.
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The 1K words RAM is organized in four banks of 256 words consisting of 16 bits each.
Bankl.0 is always accessible. Bank0.0 is mapped to other bank(s); only one gauge from 0.X
is active through bit selection. See Figure 7.
256
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The processor is able to operate from several clock sources:
•
Primary Phase Lock Loop VCO source (PVCO)
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Secondary Phase Lock Loop (SVCO)
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32.768-kHz oscillator clock (OSC)
In addition, the processor clock can be halted temporarily to select the clock source or
access ROM without disrupting normal operation of the processor.
An external crystal controls the internal 32.768-kHz oscillator. The crystal is used as the
clock reference for the internal Phase Locked Loop (PLL). The PLL provides the internal
PVCO clock for processor operation. SCLK is generated internally by dividing the
frequency of an appropriate oscillator (PVCO) by 2. The frequency of the SCLK after
POR is 12.058 MHz.
The SCLK signal can be sent to the Port16 output pin under software control by setting bit
9 in register R3(1). The SVCO must be used as the system clock when the OSD is
generated.
The clock switch control register R6(1) defines the source of the SCLK for the Z90356
core. The block diagram in Figure 8 represents the clock switch circuit.
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The 32-KHz oscillator circuit in Figure 9 is suggested for proper clock operation.
32.768 KHz
22 pF
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Z90356
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Reset conditions including addresses and registers are listed in Table 6.
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There are two low-power operating modes for Z90356: SLEEP mode and STOP mode.
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In SLEEP mode, the controller uses the 32.768-KHz clock for the SCLK to reduce power
consumption.
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In STOP mode, the processor is suspended, and the power consumption is minimized.
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User control can be monitored either through the keypad scanning port or the 16-bit
remote control capture register.
Two input/output port blocks are available for general-purpose digital I/O application.
Each port bit can be programmed to be either an input or output port. To conserve the
device pin count, some port pins are mapped to provide I/O to the ADC converter block
and I2C interface block.
The 25 configurable I/O pins are general-purpose pins for functions such as serial data
I/O, LED control, key scanning, power control and monitoring, and I2C serial data
communications.
Port 0 and 1 directions are defined in R6(0) and R7(0), respectively. R4(0) and
R5(0) are data registers for both Ports 0 and 1. Figure 10, Figure 11, and Figure 12
indicate I/O configuration and sharing with other functional units.
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The Z90356 has three external interrupt signals. There are four interrupt sources as
follows:
•
Horizontal sync (HSYNC)
•
Vertical sync (VSYNC)
•
Capture timer
•
External event (Port09).
All interrupts are vectored. The capture timer and Port09 are multiplexed to the same
interrupt.
Interrupt priorities are programmable. Each interrupt can be masked by setting fields in
the external registers.
When the Z90356 receives an interrupt request from one of the interrupt sources, it
executes the interrupt service routine directly for that source.
External register R7(1) controls interrupts.
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The watch-dog timer resets the CPU when it times out.
External register R7(1) controls the watch-dog timer.
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A clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. External
register R5(1) controls the real time clock.
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A capture timer measures time between edges of the IR signal. This timer can be
programmed to measure timing from rising-to-rising, falling-to-rising, rising-to-falling, or
falling-to-falling edges.
The IR capture timer is controlled by External register R5(1). Figure 13 is a block
diagram of the IR capture register structure.
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This function employs a 4-bit resolution, flash A-to-D converter. The six-to-one analog
input multiplexor and conversion start circuits are controlled by the user program. The
4-bit conversion result is available to be read by the CPU at the end of each conversion.
One input channel (ADC0) is dedicated for quantizing VBI (vertical blank interval) data
for subsequent digital signal processing. Another channel, ADC5, is typically used for
VSYNC separation from the composite TV signal. These channels (ADC0 and ADC5)
feature a special video clamp circuit that provides DC restoration of the composite video
input signal. Typical VBI applications include Line 21 Closed Caption, Electronic Data
Services, and StarSight Telecast. The range of ADC0 and ADC5 is from 1.5 to 2.0 V.
The four remaining channels of ADC (ADC1, ADC2, ADC3, and ADC4) are general purpose. They are typically used for tuner automatic frequency control and analog key entry.
The range of ADC1–ADC4 is from 0 to 5.0 V.
The 4-bit ADC in the Z90356 features six multiplexed inputs.
The allowed range of the input signals is different for different ADC inputs according to
Table 7.
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Reference voltages that have been generated internally define the maximum range of the
input signal for the ADC.
Nominal values are as follows:
Ref+ = 2.0 V
Ref– = 1.5 V @ VCC = 5.0 V
For other VCC values, the reference voltages must be prorated as follows:
Ref+ = 0.4 * VCC
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Ref– = 0.3 * VCC
The maximum sampling rate of the ADC converter is 3 MHz. It takes 4 SCLK cycles for
valid output data from the ADC to become available. This is especially important if the
application uses the single-shot mode.
The ADC exhibits monotonous conversion characteristics with a nonlinearity of less than
0.5 LSB. ADC0. The ADC has a range of 0.5V (from 1.5V to 2.0V) and is directly
multiplexed to the input of the ADC. The remaining ADC inputs (ranging from 0V to 5V)
use AGND and AVCC voltage as a reference.
Figure 14 is a block diagram of the ADC inner structure, and Figure 15 illustrates ADC
input circuits.
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Up to four 4-bit ADC data samples can be packed into one 16-bit word without software
overhead. If R4(1)<9> = 1, every reading of R4(1) returns the result, where the High 12
bits are the three previous ADC samples and the Low 4 bits are the current one, as
illustrated in Figure 15.
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NOPs between ADC accesses are omitted.
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A,EXT4; turn “ADC data packing” mode on
A, #%0200;
EXT4, A;
A, EXT4; read first ADC sample, A = %0005
A, EXT4; read second ADC sample, A = %005E
A, EXT4; read third ADC sample, A = %05E7
A, EXT4; read forth ADC sample, A= %5E74
A, EXT4; read fifth ADC sample, first sample is thrown away, A = %E741
The ADC is controlled by the external register R4(1).
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Pulse Width Modulation is used in conjunction with external low-pass filters to perform
digital-to-analog conversion. Six PWMs (8-bit resolution each) generate signals for the
control of video and sound attributes. In case of a chassis employing a frequency synthesis
tuner, these PWMs can also control video or sound attributes.
Each PWM circuit features a data register whose contents are set under program control.
The data in the register determines the ratio of PWM High to PWM Low time. PWM data
registers are not initialized when reset. In order to eliminate a potential glitch on a PWM
output, it is recommended to initialize PWM data registers before enabling the VCOs.
External registers R0(2) to R5(2) are data registers for PWM1 to PWM6 accordingly.
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There are two hardware modules that support standard I2C bus protocol according to the
I2C bus specification published by Phillips in 1992, entitled I2C Peripherals for
Microcontrollers Data Handbook.
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The first module, the Master, can be configured for fast (400 kHz) or slow (100 kHz) bit
rates and can be used in applications with a single master.
The second module, the Slave, supports a 7-bit addressing format with both fast and slow
bit rates.
The Z90356 adds two additional nonstandard bit rates (50 kHz and 10 kHz) and an additional
multiplexed master port that is controlled by the I2CM_mux control bit.
Table 8 lists the bit rates for the Master I2C Bus.
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are available for all inputs of the I2C bus interface. These filters exhibit a time constant
equal to 3TSCLK = 250 ns.
If the Master or Slave I2C interface is enabled, corresponding I/Os (Port01 and Port02 for
the slave, Port11 and Port12 for the master) must be assigned as outputs.
Master and Slave modules cannot be used simultaneously because of the shared I2C data
register (see the register R3(0) data field). The software activates I2C modules by writing
appropriate commands into the control register. To control the I2C bus interface, the
control register R3(0) toggle bit <c> must point to an appropriate interface (Master or
Slave).
M_disable or S_disable bits allow either the Master or Slave I 2C interface to be disabled
so as not to interfere with any activity associated with the Port pins. At Power-on Reset
(POR), both I2C interfaces are enabled. To use the I2C interface, the corresponding Port
pin (multiplexed with the I2C Data and Clock) must be configured as an output, while
M_disable or S_disable bits must be reset to 0.
External register R3(0) controls the I2C. Table 9 lists the Master I2C bus interface
commands. Table 10 lists the Slave I2C bus interface commands. Figure 16 and Figure 17
are flow charts of the Master and Slave modes.
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0QVG If a “Stop” condition is detected at any point, the hardware resets the “Slave” bit
(R3(0)<a>) and releases the I2C bus.
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The Z90356 provides sophisticated on-screen display features. On-Screen Display has the
following two modes:
•
OSD
Used to generate TV control OSD
•
CCD
Used to display Closed Caption information
OSD mode provides access to the full set of control attributes including latched and
unlatched attributes. Unlatched attributes can be modified on a character-by-character
basis. Control characters change latched attributes.
Any 256-character set can be displayed with many display attributes, including
underlining, italics, blinking, eight foreground and background colors, character position
offset delay, and background transparency. A 16-bit display character represents
foreground color, background color, and underline attributes, which can be modified
character by character. In addition, the Z90351 supports eight fixed plus eight
programmable color palettes out of 64 colors, independent left and right shadows with
color control. Shadows are available on transparent and nontransparent backgrounds.
Semitransparency is supported on a character-by-character basis. A character’s pixel array
is stored as 16, 18, or 20 words in Character Generation ROM (CGROM).
Additional hardware provides the capability to display characters at two and three times
normal size. The smoothing logic contained in the on-screen display improves the
appearance of two and three times normal size characters. Shadows can be activated to
improve the visibility of characters by adding a border (one pixel wide) on each side.
The Z90351 provides RGB signals and video blank signal. RGB outputs are available in
two modes: digital and analog. In digital mode, the output RGB signals correspond to a
primary colors palette. Analog mode supports 16 different palettes, which can be chosen
under software control. In analog mode, each RGB output is generated by a 2-bit digitalto-analog converter. The user can switch the 2-bit digital inputs of the digital-to-analog
converter to Port pins (P10, P13, P14, P15, P18 and P08) under software control by setting
a bit in the control register.
Video synchronization is normally obtained from H_FLYBACK and V_FLYBACK but
can be generated by the Z90356 and driven to the external deflection unit using the
bidirectional SYNC ports when external video synchronization signals are not present.
OSD is completely software controlled. Hardware supports the optimum generation of the
character-based OS; however, the CPU can bypass it and generate pixels and attributes
directly. The block diagram in Figure 18 illustrates the OSD data flow.
Figure 19 and Figure 20 indicate the V1, V2, V3, and Blank output circuits.
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Closed-caption text can be decoded directly from the composite video signal using the
processor’s digital signal processing capabilities and displayed on the screen. The
character representation in this mode provides simple attribute control by inserting control
characters. Each word of video RAM specifies two displayed characters.
The 4-bit flash A/D converter, with proper clamping, provides the ability to receive the
composite video signal directly and process the closed-caption text embedded in the
signal. Signal processing can be applied directly to the signal to improve decoder
performance.
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CGROM can be placed anywhere in the 64K ROM address space by setting the CGROM
address offset register R7(2). This offset is added to the CGROM address before accessing
the ROM. By modifying the CGROM offset, several fonts can be accessed (limited only
by ROM size). When reset, R7(2) = 0 (no offset), making the Z90351 backwardcompatible with existing OSD control software.
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The character scan line from CGROM addressed by the character register is fetched and
stored into the CGROM capture register. If a pixel is set to 1, it displays the foreground
color. If a pixel is set to 0, it displays the background color. The scan line can be stretched
by the character multiplier to be two or three times normal character size by duplicating
each bit in the word.
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The character size can be stretched to two or three times its size the size of the scan line.
Hardware fetches data from CGROM and stretches the data to be read from registers
R0(3), R1(3), and R2(3). Figure 21 is a block diagram of the structure of the character
expansion multiplexor, and Table 11 lists bit functions.
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The Z90356 hardware supports the following two different data formats:
•
OSD mode, R4(3)<d> = 1 supports a standard OSD with full set of features.
•
CCD mode, R4(3)<d> = 0 supports reduced features which comply with the
recommendations of the FCC on Closed Caption support.
In CCD mode, the background color of the characters cannot be changed and is always
preset to BLACK.
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In OSD mode, each character occupies a 16-bit word in VRAM. There are two possible
character formats defined: a “display” character and a “control” character. The code stored
in “display” character format defines a character code and up to 7 attributes of the
character.
The “control” character defines latched attributes and is presented on-screen as a space
character. The combination of “display” and “control” characters provides versatile OSD
generation.
Smoothing is supported for double-size (x2) and triple-size (x3) characters only.
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In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD characters
must be mapped into a 16-bit VRAM data field. The hardware supports compressed
placement of characters in VRAM. Each word in VRAM is represented by a High byte
and a Low byte. A currently active byte is selected by R4(3)<c>. The format and data
representation in both bytes is exactly the same.
There are two possible character formats defined: a “display” character and a “control”
character. The code stored in “display” character format defines a character code. The
“control” character defines up to five attributes (foreground color, italic, underline,
blinking, and transparent). It is presented on screen as a space character. The combination
of Display and Control characters provides the basis for a specified range of attributes
defined by FCC specifications for CCD.
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Shadows, if enabled, are active on both transparent and nontransparent backgrounds. Two
bits in the AttributeWR and AttributeRD registers (R2(3)<1:0> and R3(3)<1:0>) control
the type of shadow. Refer to Figure 22.
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The smoothing attribute has been moved to R7(3)<5>.
The bit assignment in the Latched Attribute follows the bit assignment in R2(3).
The left and right shadow colors are independently controlled by R6(2)<d:b> and
R6(2)<a:8>.
0QVG The smoothing control bit R7(3)<5> must be set to a “1” in order to activate
fringing.
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Both semi-transparency (pin name SOVL) and transparency (pin name OVL) attributes
are supported. The semi-transparency mode can be enabled through either latched or
unlatched attributes. Latched attributes remain set until they are reset. Unlatched attributes
remain set for only one character, which means the attribute must be constantly refreshed
on a character-by-character basis.
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To activate semi-transparency output, two bits must be set properly. Port 0F must be in
output mode [R6(0)<f> = 0], and the SOVL/port0F control bit must be in SOVL mode
[R3(1)<6> = 1].
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The latched semi-transparency attribute is controlled by bit [R2(3)<6>].
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The unlatched semi-transparency attribute is controlled by bit [R3(3)<8>]. This bit has
one of four possible assignments depending on how it is set up in [R7(3)<7:6>]. The four
assignments are underline, semi-transparency, blinking, and CGROM bank select.
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1.
The semi-transparency signal (SVBLANK), when active, is only valid with the
background color. With the foreground color, SVBLANK is inactive. Therefore,
characters do NOT take on a semi-transparent appearance (only the background
does). This condition allows characters to be read without interference.
2.
If both the transparency (background and foreground color are equal) and semitransparency are activated, the transparency takes precedence over the semitransparency. The VBLANK signal is High, and the SVBLANK signal is Low.
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Depending on R7(3)<7:6>, bit 8 of the Attribute_Data register, R3(3) (in character mode)
can be assigned to control either “1st underline,” “semi-transparency,” “blinking,” or
“CGROM bank select,” as indicated in Table 12.
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The cursor is a one-line pixel buffer. The cursor buffer is loaded via the DMA on every
line where the cursor is displayed (no software support is required). Horizontal size is
programmable at 16, 32, or 48 pixels wide, and vertical size is programmable from 1 to 63
lines per field. The color depth is 2 bits per pixel, 3 programmable colors and the
transparency. Depending on R1(0)<d>, the cursor’s colors can be selected either from a
current palette (R1(0)<d> = 0) or from Palette #6 (R1(0)<d> = 1). Refer to Table 15. The
cursor image is stored in ROM as a bitmap. The number of cursors is limited by ROM size
only.
The cursor is positioned by initializing cursor parameters in the beginning of every field.
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Initialization occurs by setting the Cursor_Info_Load bit R7(3)<4> to 1, then writing
sequentially to the R3(3) 16-bit parameters (COLOR, HPARAM, VPARAM and CADDR,
respectively).
The cursor buffer is loaded from ROM at the leading edge of HSYNC wherever the
horizontal line requires a cursor. This process halts the CPU for 3/5/7 cycles depending on
the cursor’s horizontal size. The cursor bitmap address pointer (CADDR) is incremented
automatically.
Though the cursor can be displayed anywhere on the screen, limiting the cursor to the
OSD area is best. Outside of the OSD area, the cursor can jitter or become distorted.
The cursor bitmap is organized as pixel data placed sequentially in the ROM. The data
format is described below.
For the interlaced mode, even and odd cursor bitmaps must be defined separately. Proper
selection occurs during the cursor initialization at the beginning of every field. See Figure
23, Table 13, and Table 14.
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EXT3,#(3*64 + 7*8 + 2); load CCOLOR: color3 = 3, color2 = 7, color1 = 2
EXT3,#(2*1024 + 120); load HPARAM: hsize = 2 (32 pixels), hpos = 120
EXT3,#(28*1024 + 55); load VPARAM: vsize = 28, vpos = 55
EXT3,#%6000; load CADDR—cursor bitmap address
EXT7,#%FFEF; disable Cursor_Info_Load, ready for OSD
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L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
L0_P0_B0
AddrN+1:
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+2:
L1_P15_B0, L1_P14_B0, L1_P13_B0, ... , L1_P1_B0,
L1_P0_B0
AddrN+3:
L1_P15_B1, L1_P14_B1, L1_P13_B1, ... , L1_P1_B1,
L1_P0_B1
..................................................
AddrN+2n:
Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+2n+1: Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
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L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+1:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
AddrN+2:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
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L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+4:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+5:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
..................................................
AddrN+4n:
Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
AddrN+4n+1: Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
AddrN+4n+2: Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+4n+3: Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
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AddrN:
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P13_B0, L0_P32_B0
AddrN+1:
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
AddrN+2:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
AddrN+3:
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
AddrN+4:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0,
L0_P0_B0
AddrN+5:
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1,
L0_P0_B1
AddrN+6:
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P33_B0, L0_P32_B0
AddrN+7:
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
..................................................
AddrN+6n:
Ln_P47_B0, Ln_P46_B0, Ln_P45_B0, ... , Ln_P33_B0, Ln_P32_B0
AddrN+6n+1: Ln_P47_B1, Ln_P46_B1, Ln_P45_B1, ... , Ln_P33_B1, Ln_P32_B1
AddrN+6n+2: Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
AddrN+6n+3: Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
AddrN+6n+4: Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0,
Ln_P0_B0
AddrN+6n+5: Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1,
Ln_P0_B1
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The Z90356 features a total of 16 color palettes, 8 of which are fixed and 8 of which are
programmable. Palettes are selected by setting R7(3)<3:0>. Fixed palettes are defined in
Table 15.
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Programmable palettes (8–15) are mapped to AR0–AR63 (8 registers per palette). The
register and bit assignments for Palette # 11 are listed in Figure 24.
Programmable palettes are grouped into 2 banks (palettes 8–11 and 12–15). Palettes in the
bank cannot be modified if another palette from the same bank is displayed. If on-the-fly
palette modifications are required, an interleaving palette bank access must be created.
One palette bank is used to display four colors, and the other bank is used for updates. See
Figure 24.
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Basic receiver functions such as color and volume can be controlled directly by six 6-bit
pulse-width modulated ports.
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The Infrared Remote Control data capture feature uses a capture register to hold the time
value from one transition of IR data to the next.
Software periodically checks and reads the capture status and the value if a new capture
occurs. Subsequent decoding and command passing of the received IR signal is under
software control. Figure 25 illustrates the IR input circuit.
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The Loop Filter pin configuration is represented in Figure 26.
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Hardware-accelerated byte and nibble shifts significantly reduce software overhead. Shifts
are created by assigning one particular RAM location (%1FE) a special meaning.
Depending on the R4(1)<e:d> settings data read from this address is either unmodified,
rotated 4 bits left, 4 bits right, or byte swapped. See Table 16.
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A, %1FE; A = %73ED
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Table 17 provides a summary of the registers in external banks.
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The register file in the Z90356 is organized into four banks that can be selected by writing
to bits 5 and 6 (Register Bank Selector bits) in the Status Register of the Z90356 core.
All registers are mapped into an external register space; each bank consists of 8 registers.
The Status register is available to read or write at any time. The appropriate bank of
registers must be selected before accessing the register. The software must keep track of
which register bank is accessible at any time. Refer to Table 18 for register bank
assignments.
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Table 19 defines the bits for Register1–R1(0) Cursor Palette Control Register. Table 20
defines the bits for Register2–R2(0) PLL Frequency Data Register.
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If the master or slave I2C interface is enabled, the corresponding I/Os (Port01 and Port02
for the slave, Port11 and Port12 for the master) must be assigned as outputs.
The VCO, DOT, and SCLK frequency are defined as the following:
FVCO = FDOT = FSCLK = XTAL * (256 + PLLDATA)
Therefore, XTAL = 32.768 KHz.
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At POR, the PLL frequency data register is preset to %70, which corresponds to the VCO
frequency of 12.058 MHz.
The PLL_data field can be loaded with any value from %00. This value corresponds to an
SCLK = 256*XTAL up to %FF, which corresponds to an SCLK = 511*XTAL.
Table 21 through Table 25 describe the bits in registers 3 through 7.
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Data written to R3(0)<cb> requires 4 cycles before being applied. Consecutive writings to
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The received data is available for reading only when the “busy” bit is reset to a “0.” When
POR, the speed of the I2C interface is set to “Low.”
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At POR the disable_clamp bit is set to 1.
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The clamp pulse is generated if Enabled (bit <f>) and the SCLK frequency are switched
back to PVCO. The SVCO/PVCO flag in R6(1) must be reset to 0 before the current
HSYNC, regardless of whether the SVCO is enabled or disabled.
The clamp position is defined by the Position field. The width of the clamp pulse cannot
be modified and is set to 1us. The value that can be assigned to the “Position” field must
be >%10 and <%7F. The time interval between the leading edge of the H-FLYBACK and
the beginning of the clamp pulse can be calculated from the following equation:
T D E L AY
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When a POR, SMR, or WDT reset occurs, both the Fast_enable and Fast/Slow are reset to
0. This event corresponds to an SCLK frequency of 32.768 kHz.
To switch from a 32.768-kHz SCLK to 12 MHz, use the following procedure:
1.
Set the H_Position field R6(1)<3:0> to a nonzero value.
2.
Enable the primary and secondary VCOs (set the Fast_enable bit R1(1)<1> to “1”).
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4.
Switch the SCLK to a fast clock (set Fast/Slow bit R1(1)<0> to 1).
5.
Simultaneously set the H_Position field R6(1)<3:0> to 0FH and the No_Switch
field R6(1)<4> to 1 (no clock switch).
To switch from the 12-MHz SCLK to 32.768 kHz, use the following procedure:
1.
Switch the SCLK to a 32.768-kHz clock (set Fast/Slow bit R1(1)<0> to 0).
2.
Wait for more than R2(0)<7:0> + 256 clock cycles (approximately 32 mS) for the
SCLK to be switched.
3.
Set the HSYNC_DELAY field R6(1)<3:0> to 0FH.
4.
Disable the primary and secondary VCOs (set the Fast_enable bit R1(1)<1> to 0).
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When a POR, SMR or a WDT reset occurs, the WDT is disabled. The WDT can be
reenabled only after the PVCO and SVCO are enabled, and the part is switched into a Fast
mode (SCLK = 12 MHz).
When switching the part into a SLOW mode (SCLK = 32.768 kHz), the WDT halts. To
return to Fast mode, the WDT must be initialized again.
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Two bits define the polarity of the HVSYNC signals. Bit <3> defines polarity of the
signals when they are configured as outputs (it does not affect the internal HV–SYNC
signals). Bit <1> defines the polarity of the external HV–SYNC signals, affecting the
synchronization of the device.
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1.
The composite SYNC is active in internal mode only.
2.
When using the internally-generated COMPOSITE SYNC signal, be sure the SCLK
is set to 12.09 MHz (R2(0)<7:0> = %71). This action helps ensure the best HSYNC
frequency approximation.
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ADC0 has a signal range from 1.5 to 2.0 V. This field is always connected to the
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ADC1, ADC2, ADC3, and ADC4 have a signal range from 0 to 5.0 V.
ADC5 features a signal range from 1.5 to 2.0 V. For this field, the input signal can be
clamped to a Ref+ voltage (2.0V).
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(refer to R4(0) and R6(0)).
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The H_position field defines the delay between when the Z90356 receives an H-sync and
when the H-sync interrupt is executed. Because the On-Screen Display is controlled by
software this delay allows fine tuning for On-Screen Display centering. At Power On
Reset (POR) this value is in an unknown state. If this value is set to 0x0, neither the
HSYNC interrupt nor clock switching can execute. To receive an H SYNC interrupt, valid
delay values are between 0x1 and 0xF. Valid delay values produce a delay according to
the following equation:
11 + 4 * (H_position - 1)
For example, an H_position setting of 0xF produces a delay of 67 system clock cycles
after the trailing edge of HSYNC.
11 + 4 * (15 - 1) = 67
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The No_switch bit determines if the system clock is permanently set to the Primary VCO
(PVCO) or allowed to switch between PVCO and the Secondary VCO (SVCO). This bit is
set to 1 (NO clock switching) at power up reset.
Caution: After the system has been switched to fast (12 MHz) clock both signals feeding
into this switch MUST be PVCO BEFORE the switch setting is changed. Otherwise a
short system clock can result which causes the processor to run at a higher frequency than
specified. The instruction fetched from memory, at the location with the out-of-spec
frequency, can be corrupted!
To ensure safe clocks, the following practices are recommended:
1.
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the fast (12 MHz) clock and leave it there permanently.
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2.
3.
Use the following procedure when changing from Switching VCO to permanent
PVCO while running from the fast clock:
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
enabled (0), and the SVCO/PVCO left as (0).
Wait a minimum of 80 clock cycles to flush any H-sync out of the system.
Simultaneously Switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch enabled (0), and the H_position delay at 0x0.
Wait for 3 system clock cycles to be sure that the clock has had time to switch
to PVCO.
Switch No_switch to No clock switch (write 1 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.
Use the following procedure when changing from permanent PVCO to Switching
VCO while running from the fast clock.
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
disabled (1), and the SVCO/PVCO setting as don’t care (0).
Wait a minimum of 80 clock cycles to flush residual H-sync out of the system.
Simultaneously switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>), while
leaving the No_switch disabled (1), and the H_position delay at 0x0.
Wait 3 system clock cycles to be sure that the clock has had time to switch to
PVCO.
Switch No_switch to Clock switching is Enabled (write 0 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.
69&239&2
The SVCO/PVCO bit when read back determines the current setting of the system clock.
Writing a 1 to this bit switches the system clock from its current setting to PVCO. This
switch has a glitch filter that removes random voltage spikes. It must be changed back to
PVCO. The Z90356 switches to the SVCO automatically when it receives an H-sync
interrupt. This mechanism exists to synchronize the system clock exactly with the H-sync
trailing edge. The result is a sharp start of the OSD, jitter free.
An example of a typical SVCO/PVCO switching follows:
1.
System clock is set to PVCO.
2.
H-sync interrupt occurs. (The system clock has automatically been set to the
SVCO). OSD code is executed inside of the H-sync Interrupt Service Routine (ISR).
3.
Before leaving the ISR, the user switches the clock back to PVCO.
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The clamp pulse (defined in R0(1)) is generated only if the SVCO/PVCO switch is set to
PVCO before receiving an HSYNC. The software provides the correct switch setting before
every HSYNC.
Table 33 lists the interrupt/WDT for the WST/SMR control register.
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the part resets immediately.
All core interrupts are set to int0 > int1 > int2. These priorities cannot be changed and are
embedded into the core. However, Z90356 architecture provides flexibility to change the
priority of the interrupts by switching the interrupt sources between interrupt inputs of the
Z90356 core. The correspondence between HSYNC, VSYNC and 1s/CAP interrupts
sources, and int0, int1, and int2 interrupts inputs of the Z90356 are listed in Table 34.
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Table 36 lists the bits for the shadow control register.
Table 37 lists the bits for the CGROM offset register.
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Table 38 lists the R0(3)- R2(3) character multiplier registers (Read operation).
Table 39 lists the R0(3)–R1(3) Shift Registers (Write operation).
Table 40 lists the R2(3) Attributes Register (Write operation).
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Registers R1(3) and R0(3) must be loaded with video data once every 16 cycles. To
support smoothing, register R1(3) must be updated every 16 cycles. The current line
register is loaded first, followed by next/previous register during the next cycle. The next/
previous register is loaded only if smoothing/fringing attributes are activated for the
current character. If neither register is loaded, the space character is displayed. There is no
difference between loading 0000h into either register or not loading at all.
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same, the character’s background is displayed as transparent.
The attributes register must be loaded 8 cycles after the current line register R0(3) is
loaded. Loading the attributes register enables the OSD logic during the next 16 cycles. If
the attributes register is not loaded, there is no active OSD, even if the current line register
R0(3) is loaded. See Table 41.
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recently displayed character and control character codes loaded into the attribute_data
register. Character codes are fetched from Video RAM and must be loaded into the
attribute_data register R3(3). Bit <f> of the attribute_data register (during a read) indicates
whether the most recent character was a control or displayed character. The data read from
the attribute_data register must be directly loaded into attribute register R2(3). Refer to
Table 42.
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Four clock cycles after the LD instruction, the Z90356 halts for three clock cycles to fetch
the data from CGROM and latch it into a CGROM data capture register. After the
CGROM data is latched, core operations are resumed. When a control character code is
loaded into the attribute_data register, the CGROM data from address 0000 hex is
fetched. Therefore, ZiLOG recommends placing a space character at location 0000 hex in
CGROM. Refer to Table 43 through Table 46 for the various VRAM data formats loaded
in R3(3).
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At reset, the background color in OSD mode is black. Foreground color, background
color, blinking and italic attributes are delayed by 3/4 character. The smoothing attribute is
enabled.
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must be mapped into a 16-bit VRAM data field. The hardware supports compressed
character placement in VRAM. Each word in VRAM is represented by HIGH byte and
LOW byte. A currently active byte is selected by R4(3)<c>. The format and data
representation for both bytes is the same.
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character. The code stored in “display” character format defines a character code. The
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specification. Refer to Table 47.
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underline active fields of data loaded into attribute register R2(3), causing the screen
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The Italic shift field defines a delay of video data. It is used to generate italic characters.
The firmware decrements by 1 (the value of the Italic_shift field) for each consecutive
line. The video signal is delayed only for characters that have the R2(3)<4> (“italic”) bit
set to 1.
Table 48 lists the bits for the capture register.
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In Write mode, the 7-bit I2C slave interface address must be put in bit 7-1.
Table 49 lists the bits for the palette control register.
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Table 50 lists the bits for the output palette control register.
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At POR the Output palette register is set to 0 for digital output.
Table 15 is the look-up table for the color palettes.
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The processor instruction set consists of 30 basic instructions. It is optimized for high code
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instructions.
The format for Op Codes and addressing modes is provided in the following tables but is
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instruction format. by translating the mnemonics. System designers can access the
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of instruction operands. Table 59 and Table 60 list instructions.
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RTGIU The register pointer mode is used for loading the pointer with the appropriate
RAM address. This address references the RAM location that stores the requested data.
The pointer can also be used to store 8-bit data when used as a temporary register. The
pointers are connected to the lower 8 bits of the D-bus. Instruction 1 loads Pointer 2,
RAM Bank0 with the value F2H.
TGIKPF The register indirect mode is used for indirect access to RAM. As noted in
Instruction 2, the register indirect address method is used to get the operand to multiply it
with the accumulator.
FTGIU The data-pointer mode is used as an indirect addressing method similar to
@P2:0. The data pointers access the lower 16 bits of each RAM bank. Instruction 8 uses
indirect addressing to PUSH information onto the stack.
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commonly used to reference program memory. Instructions 5 and 6 display this addressing
method. Either pointer is automatically incremented to assist in transferring sequential
data.
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address. Instruction 3 describes how to use this method.
FKTGEV The absolute RAM address is used in the direct mode. A range between 0 and
511 (000H to 1FFH) is allowed. The accumulator is used in conjunction with this
method as a source or destination operand. Instruction 7 displays the accumulator as the
destination.
NKOO This instruction indicates a long immediate load. A 16-bit word can be copied
directly from the operand into the specified register or memory. Instruction 4 uses this
method.
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8-bit data in the operand to the specified RAM pointer.
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transparent by providing mnemonics. Occasionally, the instruction format and
development code can assist in debugging. Examples to clarify the various instruction
formats and explain how specific bit patterns are developed and evaluated are provided
below.
Most instructions require one 16-bit word containing the information necessary for the
processor to execute the instruction correctly. This process requires one clock cycle for
execution. Immediate addressing, immediate operands, JUMP and CALL instructions
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require two 16-bit words (two clock cycles). Each instruction type has a unique Op Code
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formats.
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format to depict bits determined by the active instruction.
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source or destination field in instructions. Specific bit codes are listed in Table 64. The
register pointer offers optional incrementing or decrementing. This option is specified by
the following instruction:
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Data pointers are automatically incremented when accessing program memory (for
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format is designated for a data pointer when source or destination format is used.
Additional source or destination designators include the other hardware registers provided
by the processor. To determine if a data pointer, register pointer or a register is used as a
source or destination is discussed in the next section.
Table 65 lists the bit codes for mnemonic resister names.
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code is 0011 which corresponds to the accumulator. The source 0110 corresponds to the
+1 option and P2:0 or P2:1. The RAM bank bit indicates that the processor loaded the
accumulator with the operand designated by Pointer 2 Bank1 (P2:1).
Source and destination fields can be accessed from the register pointers, data pointers, or
registers. The Op Code specifies the type of source and destination. An Op Code of
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addressing mode.
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instruction format to depict bits determined by the specific instruction used.
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The DSP can be executed with single cycle instruction using the independent data memory
and program memory buses offered by the modified Harvard architecture and pipeline
instruction. This method provides overlapping of instruction fetch and execution cycles.
Figure 27 illustrates the execution sequence. The first instruction takes two clock cycles to
execute; subsequent executions occur in a single cycle. All instruction fetch cycles have
the same machine timing regardless of whether external or internal memory is used.
Because the DSP contains a two-level pipeline, the JUMP and CALL instructions do not
disrupt the execution process
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In two-byte instructions, the second byte is being fetched while the first byte is executing.
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transferred to the program counter and the correct address is fetched into the pipeline.
There is no disruption or pipeline flushing. The pipeline flow is affected when the program
counter is the destination for a load. Because the load (LD) instruction is a single word
instruction, the next instruction is fetched during load execution. To compensate for the
instruction in the pipeline, that instruction is executed as a NOP.
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The DSP instruction set consists of 30 basic instructions, optimized for high-code density
and reduced execution time. Single-cycle instruction execution is possible because of the
pipeline and other architectural features. Table 74 contains a description for each
instruction.
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0QVG Each Assembly Instruction includes an example for each addressing mode
available for the specific instruction.
The mnemonics listed in Table 75 are used in the instruction format.
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Flags: N:
Set if the accumulator has 800000H (see below).
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If the contents of the accumulator are determined to be less then 0 (a negative number),
the absolute value of the accumulator is calculated (accumulator replaced by its two’s
complement value). Using the condition code provides an additional method to evaluate a
status flag before the absolute value of the accumulator is calculated.
0QVG If the accumulator contains 800000H, the ABS A instruction stores the value of
the two’s complement at address 800000H and sets the Overflow and Negative
status bits. There is no overflow protection.
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ABS A
Initialization:
Accumulator contains FFEB00H
SR contains 0000H
Instruction:
ABS A
Result:
Accumulator contains 001500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. Because the
value in the accumulator is less then zero, the two’s complement is performed and the
result is placed in the accumulator ABS(FFEBH)=001500H. The carry bit is set.
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ABS <cc>, A
Initialization:
Accumulator contains 456400H
Instruction:
ABS MI, A
Result:
Accumulator contains 456400H
This example uses one word of memory and executes in one machine cycle. The condition
code (negative bit) is not set because the accumulator value is positive; therefore, the
instruction is not executed.
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N:
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Set if carry from the most significant bit is found.
Set if result in the accumulator is negative.
Set if result is 0.
Set if addition exceeds upper (FFFFFH)
or lower (800000H) limit of the accumulator.
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The addressed data memory operand is added to the accumulator. The result is loaded into
the accumulator.
0QVG The lower eight bits of the accumulator are unchanged while the add instruction is
executed.
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ADD A, <regind>
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Initialization:
Accumulator contains 123456H
P0:0 contains 4DH
RAM Bank1: 4DH contains 8746H
Instruction:
ADD A, @P0:0
Result:
A contains 997A56H
@P0:0 contains 746H
This example uses one word of memory and executes in one machine cycle. The pointer
P0:0 contains the RAM register location (4DH). The contents of RAM register 4DH are
added to the accumulator to obtain the sum (874600H + 123456H = 997A56H). The
sum is contained in the accumulator and the pointer is left unchanged. The direct
addressing equivalent is ADD A, %4D or ADD A, 77 (4DH = 77 decimal).
([DPSOH
ADD A, <memind>
Initialization:
Accumulator contains 123400H
P0:0 contains 21H
RAM Bank0: 21H contains 247AH
ROM Address: 247AHcontains 0C12H
Instruction:
ADD A, @@P0:0
Result:
A contains lE4600H
P0:0 contains 21H
RAM Bank0: 21H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0 contains the RAM register location (21H). The contents of this register have a
ROM address. This address refers to the ROM data placed in the specified accumulator by
an AND instruction 123400H + 0C1200H = 1E4600H. When memory indirect
addressing is used, the ROM address is automatically incremented. to provide a
convenient method of accessing sequential data. Using ADD A, @@P0:0+ performs the
same operation and also increments the P0:0 content to 22H.
([DPSOH
ADD A, <limm>
Initialization:
Accumulator contains 123400H
Instruction:
ADD A, #%0C12
Result:
A contains lE4600H
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This example uses two words of memory and executes in two machine cycles. The
immediate operand 0C12H is added to the accumulator to obtain the sum 123400H +
0C1200H = 1E4600H.
([DPSOH
ADD A,<hwregs>
Initialization:
Accumulator contains 23400H
Register X contains 0C12H
Instruction:
ADD A, X
Result:
A contains 1E4600H
This example uses one word of memory and executes in one machine cycle. The contents
of register X are added to the accumulator to obtain the sum. 123400H + 0C1200H =
1E4600H. All hardware registers can transfer from <hwregs>.
([DPSOH
ADD A,<direct>
Initialization:
Accumulator contains 123400H
RAM Bank0: F3H contains 0C12H
Instruction:
ADD A,%F3
Result:
A contains 1E4600H
This example uses one word of memory and executes in one machine cycle. Register F3H
is added to the accumulator to obtain the sum. 123400H + 0C1200H = 1E4600H.
An equivalent instruction is ADD A, 243 (F3H = 243 decimal).
([DPSOH
ADD A, <pregs>
Initialization:
Accumulator contains 123400H
P0:0 contains 56H
Instruction:
ADD A, P0:0
Result:
Accumulator contains 128A00H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0 is added to the accumulator. 123400H + 005600H =
128A00H. The Pointer Register is connected to the lower 8 bits of the D-bus. The D-bus
is connected to the upper 16-bits of the P-bus. This causes the pointer register operand to
become 005600H before being added to the accumulator.
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ADD A,<dregs>
Initialization:
Accumulator contains 123400H
D0: 1 contains 8746H
Instruction:
ADDA,D0:1
Result:
A contains 997A00H
D0: 1 contains 8746H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1 are added to the accumulator. The sum is contained in the
accumulator and the pointer is left unchanged. The data pointer contains 8746H.
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AND A, <regind>
AND A, <memind>
AND A, <limm>
AND A, <hwregs>
AND A, <direct>
AND A, <pregs>
AND A, <dregs>
AND A, <simm>
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Flags: N:
Z:
Set if accumulator result is less than 0.
Set if accumulator result is 0.
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Data is stored in the specified accumulator by an AND instruction. The lower eight bits of
the accumulator are cleared when this instruction is executed.
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AND A, <regind>
Initialization:
Accumulator contains 123456H
P0A contains 45H
RAM Bank1: 45H contains 8746H
Instruction:
AND A, @P0:1
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Result:
Accumulator contains 020400H
This example uses one word of memory and executes in one machine cycle. The data in
RAM Bank1, referenced by RAM pointer 0, is stored in the specified accumulator using
an AND instruction 123456H.AND.874600H = 020400H.
([DPSOH
AND A, <memind>
Initialization:
Accumulator contains 123400H
P0:0 contains45H
RAM Bank0: 45H contains 047AH
ROM Address: 047AH contains 8746H
Instruction:
AND A, @@P0:0
Result:
A contains 020400H
P0:0 contains 45H
RAM Bank0: 45H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0 contains the RAM register location (45H). The contents of this register has a ROM
address. This address refers to the ROM data that is placed in the specified accumulator by
an AND instruction 123400H.AND.874600H = 020400H. With memory-indirect
addressing, the ROM address is automatically incremented. This provides a convenient
method to access sequential data. Using AND A, @@P0:0+ performs the same operation
and also increments the P0:0 content to 46H.
([DPSOH
AND A, <limm>
Initialization:
Accumulator contains 362400H
Instruction:
AND A, #%1234
Result:
Accumulator contains 122400H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 1234H and an accumulator address are processed with an AND
instruction to produce the result, 362400H.AND.123400H = 122400H.
([DPSOH
AND A, <simm>
Initialization:
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Instruction:
AND A, #%1F
Result:
Accumulator contains 001400H
This example uses one word of memory and executes in one machine cycle. The data in
the immediate field and the contents of the accumulator are processed with an AND
instruction. 123456H.AND.001F00H = 001400H.
([DPSOH
AND A, <hwregs>
Initialization:
Accumulator contains 123400H
Register X contains OC12H
Instruction:
AND A, X
Result:
A contains 001000H
This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send the contents of Register X to the accumulator to obtain the result
123400H.AND.0C1200H = 001000H. All hardware registers can transfer from
<hwregs>.
([DPSOH
AND A, <direct>
Initialization:
Accumulator contains 123400H
RAM Bank0: F3H contains 0C12H
Instruction:
AND A, %F3
Result:
A contains 001000H
This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send Register F3H to the accumulator to obtain the result 123400H AND
OC1200H = 001000H. An equivalent instruction is AND A, 243 (F3H = 243
decimal).
([DPSOH
AND A, <pregs>
Initialization:
Accumulator contains 123400H
P0:0 contains 56H
Instruction:
AND A, P0:0
Result:
Accumulator contains 001400H
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This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send the contents of the pointer register P0:0 to the accumulator
123400H.AND.005600H = 001400H. The Pointer Register is connected to the
lower 8 bits of the D-bus. The D-bus is connected to the upper 16 bits of the P-bus. This
action changes the pointer register operand to 005600H before being added to the
accumulator.
([DPSOH
AND A, <dregs>
Initialization:
Accumulator contains 123400H
D0:1 contains 2645H
Instruction:
AND A, 00:0
Result:
Accumulator contains 020400H
This example uses one word of memory and executes in one machine cycle. The data
register, D0:0, references the operand 2645H. Use an AND instruction to send this data
register to the accumulator to produce the result 123400H.AND.2645H = 020400H.
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CALL <cc>,<direct>
CALL <direct>
2SHUDWLRQ
PC + 2 —> STACK
16-Bit Address —> PC
Flags: None
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The current Program Counter (PC) register content is incremented by two and placed on
the stack. The address of the specified label in the CALL instruction is then placed in the
PC register. The jump is made to the appropriate subroutine via the PC. The condition
code option is used if CALL is executed.
([DPSOH
CALL <direct>
Cycles: 2
Words: 2
Initialization:
PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
Instruction:
CALL FFT2
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Result:
PC contains F234H
Stack Level 0 contains 1FFDH
Stack Level 1 contains 0025H
This example uses two words of memory and executes in two machine cycles. The call to
the subroutine FFT2 places PC+2 (1 FFDH) on the stack. All information currently on
the stack is pushed up the stack. The subroutine address is then placed in the PC register.
The processor executes the next instruction addressed by the PC, the FFT2 subroutine.
([DPSOH
CALL <cc>, <direct>
Initialization:
PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
UO (User Zero Bit) contains 1
Instruction:
CALL UO, FFT2
Result:
PC
= F234H
Stack Level 0= 1FFDH
Stack Level 1= 0025H
This example uses two words of memory and executes in two machine cycles. The
condition code UO is tested by the processor before executing the CALL instruction.
Because the UO bit is enabled, the CALL routine is executed exactly like the example
above. The condition code UO is input to the processor that determines if subroutine FFT2
is used. Another CALL instruction can determine if another subroutine, FFT1, is used.
([DPSOH
CALL <direct>
Initialization:
PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
Instruction:
CALL FFT2
Result:
PC containsF234H
Stack Level 0 contains 1FFDH
Stack Level 1 contains 0025H
This example uses two words of memory and executes in two machine cycles. The call to
the subroutine FFT2 places PC+2 (1 FFDH) on the stack. All information currently on
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the stack is pushed up the stack. The subroutine address is then placed in the PC register.
The processor executes the next instruction addressed by the PC, the FFT2 subroutine.
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Zero —> Carry Bit
Flags: C:
Set to 0.
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The Clear Carry Flag instruction resets the carry flag with a 0.
([DPSOH
CCF
Initialization:
SR contains 3000H
Instruction:
CCF
Result:
SR contains 2000H
C contains 0
This example uses one word of memory and executes in one machine cycle.
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Zero —> IE bit
Flags: IE:
Set to 0.
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The Clear Interrupt Enable Flag instruction sets the IE flag to 0.
([DPSOH
CIEF
Initialization:
SR contains 3080H
Instruction:
CIEF
Result:
SR contains 3000H
IE contains 0
This example uses one word of memory and executes in one machine cycle.
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Zero —> OP bit
Flags: P:
Set to 0.
The Clear Overflow Protection Flag instruction resets the OP flag to 0.
([DPSOH
COPF
Initialization:
SR contains 0100H
Instruction:
COPF
Result:
SR contains 0000H
OP contains 0
This example uses one word of memory and executes in one machine cycle.
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CP
A,
<regind>
CP
A,
<memind>
CP
A,
<limm>
CP
A,
<hwregs>
CP
A,
<direct>
CP
A,
<pregs>
CP
A,
<dregs>
CP
A,
<simm>
2SHUDWLRQ
A - <source> —> set appropriate status bits
Flags: C:
Z:
OV:
N:
Set if carry is required for operation.
Set if operands are equal.
Set if operation exceeds the low (800000H) or high
limit (7FFFFFH) of accumulator.
Set if result is negative.
'HVFULSWLRQ
The contents of the register specified in the instruction are compared to the contents of the
accumulator in 16-bit mode. The register specified is subtracted from the accumulator and
the appropriate flags are set. Because the registers are 16-bit, a comparison with the 24-bit
accumulator requires that the lower eight bits of the accumulator be filled with zeros for
accurate comparisons. The instruction does not affect the contents of the accumulator
except when the overflow protection bit is set and an overflow occurs after the compare is
executed. The accumulator updates with the appropriate low (800000H) or high
(7FFFFFH) limit.
3679&
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([DPSOH
CP A, <regind>
Initialization:
A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
Instruction:
CP A, @P2:1
Result:
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The operand
referenced by P2:1 is subtracted from the accumulator. 7A2500H - 546300H =
25C200H. Because the comparison does not yield a 0, Bit 0 is not set. The content of the
P2:1 register is appended with eight additional 0 bits. For consistent comparisons, the
accumulator must contain zeros in the lower eight bits.
0QVG The accumulator is unaffected by the operation.
([DPSOH
CP A, <memind>
Initialization:
A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
ROM Address: 5463H contains OC12H
Instruction:
CP A, @@P2:1
Result:
A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5464H
SR contains 1000H
This example uses one word of memory and executes in three machine cycles.The pointer
P2:1 contains the RAM register location (A4H). The contents of this register have a
ROM address. This address refers to the ROM data compared to the accumulator
7A2500H - OC1200H = 6E1300H. Because the comparison does not yield a 0, Bit 0
is not set. With memory indirect addressing, the ROM address is automatically
incremented. Using CP A,@@P2:1 + performs the same operation and also increments
P2:1 content to A5H.
([DPSOH
CP A, <limm>
3679&
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Initialization:
A contains 7A2500H
Instruction:
CP A, #%7A25
Result:
A contains 7A2500H
SR contains 3000H
This example uses two words of memory and executes in two machine cycles. The
immediate operand is compared to the accumulator. Because they are equal, the Zero Flag
is set.
([DPSOH
CP A, <hwregs>
Initialization:
A contains 7A2500H
SR contains 0000H
BUS contains 7A25H
Instruction:
CP A, BUS
Result:
A contains 7A2500H
SR contains 3000H
This example uses one word of memory and executes in one machine cycle. The
<hwreg> operand is subtracted from the accumulator. Because the two operands are
equal, the zero-status bit is set High. <hwregs> can be compared from all hardware
registers.
([DPSOH
CP A, <direct>
Initialization:
Accumulator contains 7A2500H
RAM Bank0 F3H contains 5463H
Instruction:
CP A, %F3
Result:
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. Register F3H
is compared to the accumulator. 7A2500H - 546300H = 25C200H. An equivalent
instruction is CP A,243 (173H = 243 decimal).
([DPSOH
CP A, <pregs>
3679&
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Initialization:
Accumulator contains 123400H
P0:0 contains 56H
Instruction:
CP A, P0:0
Result:
Accumulator contains 123400H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0 are compared to the accumulator. 123400H - 005600H
= 11DE00H The Pointer Register is connected to the lower 8 bits of the D-bus. The
D-bus is connected to the upper 16 bits of the P-bus. This action changes the pointer
register operand to 005600H before being compared to the accumulator.
([DPSOH
CP A, <dregs>
Initialization:
A contains 7A2500H
D2:1 contains 5463H
Instruction:
CP A, D2:1
Result
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D2:1 are compared to the accumulator. 7A2500H - 546300H =
25C200H.
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DEC A
DEC <cc>, A
2SHUDWLRQ
ACC - 1 —> ACC
Flags: C:
Z:
N:
OV:
Set if carry is required for operation
Set if result is 0.
Set if decrement results in a value less then 0.
Set if upper (7FFFFFH) or lower (800000H) limits
are exceeded.
'HVFULSWLRQ
The accumulator decrements by 1. A condition code can be used to test for a specific
condition before decrementing.
([DPSOH
DEC A
Initialization:
A contains 7A2500H
Instruction:
DEC A
Result:
A contains 7A24FFH
This example uses one word of memory and executes in one machine cycle. The value in
the accumulator decrements by 1.
([DPSOH
DEC <cc>, A
Initialization:
3679&
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Instruction:
DEC MI, A
Result:
A contains 7A2500H
This example uses one word of memory and executes in one machine cycle. Because the
accumulator is not negative, the decrement instruction is not executed.
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INC A
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ACC + 1 —> ACC
Flags: C:
Z:
N:
OV:
Set if carry is required for operation.
Set if result is 0.
Set if results in a value less then 0.
Set if upper (7FFFFFH) or lower (800000H) limits
are exceeded.
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The Increment instruction adds one to the accumulator. A condition code can be used to
test for a specific condition for an increment to occur.
([DPSOH
INC <cc>, A
Initialization:
A contains 7A2500H
Instruction:
INC MI, A
Result:
A contains 7A2500H
This example uses one word of memory and executes in one machine cycle. Because the
accumulator is not negative, the increment instruction is not executed.
([DPSOH
INC A
Initialization:
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Instruction:
INC A
Result:
A contains 7A2501H
This example uses one word of memory and executes in one machine cycle. The value in
the accumulator is incremented by 1.
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JP
<cc>,
JP
<direct>
<direct>
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16-Bit address —> PC
Flags: None
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The instruction places the address of the referenced ROM location in the Program Counter
(PC). Because the processor obtains its next instruction address from the PC, the processor
jumps to the appropriate location. A condition code can be used to test for a specific
condition for a JUMP to occur.
([DPSOH
JP <cc>, <direct>
Initialization:
Routine 1 address contains 1455H
PC contains 1343H
User 0 input contains 1
Instruction:
JP NUO, Routine 1
Result:
PC contains 1343H
This example uses two words of memory and executes in two machine cycles. Because the
User 0 input is set High, the condition code is not met. Therefore, the JUMP instruction
does not execute. The User 0 input is used to control the flow of the software.
3679&
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([DPSOH
JP <direct>
Initialization:
Routine 1 address contains 1455H
PC contains 1343H
Instruction:
JP Routine 1
Result:
PC contains 1455H
This example uses two words of memory and executes in two machine cycles. The value
in the program counter is replaced by the Routine 1 address (1455H).
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LD
A,
<pregs>
LD
<direct>,
A
LD
<hwregs>,
<dregs>
LD
A,
<dregs>
LD
<dregs>,
<hwregs>
LD
<hwregs>,
<limm>
LD
A,
<memind>
LD
<pregs>,
<simm>
LD
<hwregs>,
<accind>
LD
A,
<direct>
LD
<pregs>,
<hwreg>
LD
<hwregs>,
<memind>
LD
A,
<regind>
LD
<regind>,
<limm>
LD
<hwregs>,
<regind>
LD
A,
<hwregs>
LD
<hwregs>,
< pregs>
LD
<hwregs>,
<hwregs>
2SHUDWLRQ
<source> —> <destination>
Flags: None
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'HVFULSWLRQ
The LOAD command provides the ability to transfer data to several different locations in
the processor including hardware registers, accumulator, stack, pointers and memory. All
transfers across the various internal buses are transparent to the user.
0QVGU
1.
A load using the X or Y register provides an automatic multiply operation. This
means the operand can be obtained from any register location.
2.
The P register is a read-only register, therefore the destination of the load cannot be
the P register.
3.
LD EXTN, EXTN is not allowed.
4.
A LOAD instruction to the accumulator clears the lower 8 bits of the 24-bit
accumulator.
([DPSOH
LD A, <regind>
Initialization:
A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
Instruction:
LD A, @P2:1
Result:
A contains 546300H
This example uses one word of memory and executes in one machine cycle. Indirect
addressing through the pointer registers provides access to RAM data. The data in RAM
Bank 1, register A4 is transferred to the accumulator. The contents of the P2:1 register
are appended with eight additional 0 bits. This is added to verify a correct arithmetic
comparison.
([DPSOH
LD A, <memind>
Initialization:
Accumulator contains 123400H
P0:0 contains 21H
RAM Bank0: 21H contains 247AH
ROM Address: 247AHequals OC1 2H
Instruction:
LD A, @@P0:0
3679&
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Result:
A contains OC1 200H
P0:0 contains 21H
RAM Bank0: 21H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0 contains the RAM register location (21H). The contents of this register have a
ROM address. This address refers to the ROM data that loads to the accumulator. When
memory indirect addressing is used, the ROM address is automatically incremented.
Using LD A, @@P0:0+ has the same result, also incrementing the P0:0 content to
22H.
([DPSOH
LD A, <limm>
Initialization:
Accumulator contains 123400H
Instruction:
LD A, #%2474
Result:
A contains 247400H
Cycles: 2
Words: 2
This example uses two words of memory and executes in two machine cycles. The
immediate operand 2474H loads to the accumulator.
([DPSOH
LD A, <hwregs>
Initialization:
Accumulator contains 123400H
Register X contains OC12H
Instruction:
LD A, X
Result:
A contains OC1200H
This example uses one word of memory and executes in one machine cycle. The contents
of Register X are loaded to the accumulator. All hardware registers can transfer from
<hwregs>.
([DPSOH
LD A, <direct>
Initialization:
Accumulator contains 123400H
RAM Bank0 F3H contains OC12H
Instruction:
LD A, %F3
Result:
A contains OC1200H
3679&
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This example uses one word of memory and executes in one machine cycle. Register F3H
is loaded to the accumulator. An equivalent instruction is LD A,243 (F3H = 243
decimal).
([DPSOH
LD A, <dregs>
Initialization:
Accumulator contains123400H
D0: 1 contains 8746H
Instruction:
LD A, D0:1
Result:
A contains 874600H
D0: 1 contains 8746H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1 load to the accumulator.
([DPSOH
LD A, <pregs>
Initialization:
Accumulator contains 123400H
P0:0 contains 56H
Instruction:
LD A, P0:0
Result:
Accumulator contains 005600H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0 are loaded to the accumulator. The Pointer Register is
connected to the lower 8 bits of the D-bus. The D-bus is connected to the upper 16 bits of
the P-bus. This operation causes the pointer register operand to become 005600H before
being loaded into the accumulator.
([DPSOH
LD <direct>, A
Initialization:
Accumulator contains 123400H
RAM Bank0: 3CH contains 5678H
Instruction:
LD %3C, A
Result:
Accumulator contains 123400H
RAM Bank0: 3CH contains 1234H
This example uses one word of memory and executes in one machine cycle. The current
value in the accumulator is loaded to the register addressed by the instruction (3CH). An
equivalent instruction is LD 60, A. (3CH = 60 decimal).
3679&
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([DPSOH
LD <pregs>, <simm>
Initialization:
P2:0 contains 2FH
RAM Bank0: 3FH contains 254645H
Instruction:
LD P2:0, #%3F
Result:
P2:0 contains 3FH
RAM Bank0: 3FH contains 254645H
This example uses one word of memory and executes in one machine cycle. The
immediate data (3FH) is loaded into the pointer register P2:0. This action provides a
convenient method for initializing pointer registers.
([DPSOH
LD <pregs>, <hwregs>
Initialization:
P0: 1 contains 2FH
Y contains 2376H
Instruction:
LD P0:1, Y
Result:
P0: 1 contains 76H
Y contains 2376H
This example uses one word of memory and executes in one machine cycle. The lower
8-bits of the Y register are transferred to the pointer register P0:1. All hardware registers
can transfer from <hwregs>.
([DPSOH
LD <regind>, <limm>
Initialization:
P0:1 contains 2FH
RAM Bank0: 2FH contains 2376H
Instruction:
LD @P0:1, #%35B8
Result:
P0:1 contains 2FH
RAM Bank1: 2FH contains 35B8H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 35B8H is transferred to the Register 2FH of RAM Bank1.
([DPSOH
LD <hwregs>, <pregs>
3679&
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Initialization:
P2:0 contains 2FH
X Register contains 8B87H
Instruction:
LD X,P2:0
Result:
P2:0 contains 2FH
X Register contains 002FH
This example uses one word of memory and executes in one machine cycle. The contents
of the P2:0 pointer (2FH) are loaded into the X register. Transfer to <hwreg> is possible
to all hardware registers except the read-only P register.
([DPSOH
LD <hwregs>, <dregs>
Initialization:
D2:0 contains 3C87H
Accumulator contains 8BB722H
Instruction:
LD A,D2:0
Result:
D2:0 contains 3C87H
Accumulator contains 3C8700H
This example uses one word of memory and executes in one machine cycle. The contents
of the D2:0 pointer (3C87H) are loaded into the accumulator. Transfer to <hwregs> is
possible to all hardware registers except the read-only P register.
([DPSOH
LD <hwregs>, <limm>
Initialization:
Stack0 contains 8B2FH
Stack1 contains 0000H
Instruction:
LD Stack, #%35B8
Result:
Stack0 contains 35B8H
Stack1 contains 8B2FH
This example uses two words of memory and executes in two machine cycles. The
immediate data is pushed onto the stack as previous stack data is pushed up the stack.
Transfer to <hwregs> is possible to all hardware registers except the read-only P
register.
([DPSOH
LD <hwregs>, <accind>
3679&
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Initialization:
EXT7 Register contains 8B87H
Accumulator contains 77B6H
ROM 77B6H contains 387DH
Instruction:
LD EXT7, @A
Result:
EXT7 Register contains 387DH
Accumulator contains 77B6H
This example uses one word of memory and executes in one machine cycle. The contents
of the ROM Register 77B6H (387DH) are loaded into External Register 7. Transfer to
<hwregs> is possible to all hardware registers except the read-only P register and the
accumulator register.
([DPSOH
LD <hwregs>, <memind>
Initialization:
Y Register contains 1234H
P0:0 contains 21H
RAM Bank0: 21H contains 247AH
ROM Address: 247AH contains 0C12H
Instruction:
LID Y, @@P0:0
Result:
Y Register contains 0C12H
P0:0 contains 21H
RAM Bank0: 21H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0 contains the RAM register location (21H). The contents of this register have a
ROM address that refers to the ROM data that loads to the Y register. Transfer to
<hwregs> is possible to all hardware registers except the read-only P register. When
memory indirect addressing is used the ROM address is automatically incremented. Using
LD A,@@P0:0+ performs the same operation and also increments the P0:0 content to
22H.
([DPSOH
LD <hwregs>, <regind>
Initialization:
X Register contains 7A25H
P21 contains A4H
RAM Bank1: A4H contains 5463H
Instruction:
LD X, @P2:1
3679&
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Result:
X Register contains 5463H
This example uses one word of memory and executes in one machine cycle. Indirect
addressing through the pointer registers provides access to RAM data. The data in RAM
bank 1, register A4 is transferred to the X register. Transfer to <hwreg> is possible to all
hardware registers except the read-only P register.
([DPSOH
LD <hwregs>, <hwregs>
Initialization:
X Register contains 7A25H
EXT5 Register contains 789AH
Instruction:
LD X, EXT5
Result:
X Register contains 789AH
EXT5 Register contains 789AH
This example uses one word of memory and executes in one machine cycle. The EXT5
Register contents are transferred to the X register. Transfer to <hwregs> is possible to all
hardware registers except the read-only P register.
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6\QWD[
NEG A
NEG <cc>, A
2SHUDWLRQ
-ACC —> ACC
Flags: N
Set if result is a negative number.
Two special cases are:
1.
If ACC contains 000000 after execution, then N and 0V are cleared, and Z and C
are set
2.
If ACC contains 800000 after execution, then N and 0V are set; and Z and C are
cleared.
The accumulator is replaced with a negative of the current value. To achieve this
state, the two’s complement is performed.
([DPSOH
NEG A
Initialization:
A contains 003654H
Instruction:
NEG A
Result:
A contains FFC9ACH
This example uses one word of memory and executes in one machine cycle.
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([DPSOH
NEG <cc>, A
Initialization:
A contains 000111H
Carry bit contains 1
Instruction:
NEG C, A
Result:
A contains FFFEEFH
This example uses one word of memory and executes in one machine cycle.
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1223(5$7,21
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6\QWD[
NOP
2SHUDWLRQ
PC+ 1—> PC
Flags:
None
'HVFULSWLRQ
The NOP instruction causes the processor to continue operation for one cycle without
affecting previous registers and I/0.
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OR A, <regind>
OR A, <memind>
OR A, <limm>
OR A, <hwregs>
OR A, <direct>
OR A, <pregs>
OR A, <dregs>
OR A, <simm>
2SHUDWLRQ
ACC .OR. source —> ACC
Flags: N
Z
Set If result in accumulator is negative.
Set If result is 0.
'HVFULSWLRQ
The accumulator performs an OR instruction on the contents of the specified register. The
upper 16 bits of the accumulator are used. The result is placed in the accumulator. The OR
instruction is frequently used to compare specific bits to assist in program control.
0QVG The lower eight bits of the accumulator are unchanged after execution of the OR
instruction.
([DPSOH
OR A, <regind>
3679&
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Initialization:
Accumulator contains 3264A0H
P0:0 contains E2H
RAM Bank0: E2H contains 1126H
Instruction:
OR A, @P0:0
Result:
A contains 336600H
This example uses one word of memory and executes in one machine cycle. Use an OR
instruction to reference the operand P0:0 with the upper 16 bits of the accumulator. The
result is stored in the accumulator. 3264A0H OR. 1126A0H = 3366A0H.
([DPSOH
OR A,<memind>
Initialization:
A contains 3264A0H
P2:11 contains A4H
RAM Bank 1: A4H contains 5463H
ROM Address: 5463H contains 1126H
Instruction:
OR A, @@P2:1
Result
A contains 3366A0H
P2:1 contains A4H
RAM Bank0: A4H contains 5464H
SR contains 0000H
This example uses one word of memory and executes in three machine cycles. The pointer
P2:1 contains the RAM register location (A4H). The contents of this register have a
ROM address. This address refers to the ROM data that is compared to the accumulator.
3264A0H.OR.112600H = 3366A0H. With memory indirect addressing, the ROM
address is automatically incremented. Using ORA,@@P0:0+ performs the same operation
and also increments the P0:0 content to A5H.
([DPSOH
OR A, <limm>
Initialization:
A contains 3264A0H
Instruction:
OR A, #%1126
Result:
A contains 3366A0H
SR contains 0000H
This example uses two words of memory and executes in two machine cycles. The
accumulator performs an OR instruction on the immediate data.
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323
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RS
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6\QWD[
POP <pregs>
POP <dregs>
POP <regind>
POP <hwregs>
2SHUDWLRQ
STACK 0 —> <destination>
Stack n —> Stack N-1
Flags: None
'HVFULSWLRQ
The current value of the stack is copied to the specified register. Because the stack is a
last-in, first-out (LIFO) hard-wired architecture, the copy and shift of data remaining in
the stack are all performed in a single cycle.
The POP instruction provides the ability to control information sent to the stack, making it
possible to expand the stack using software.
([DPSOH
POP <pregs>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
P0:0 contains 24H
Instruction:
POP P0:0
Result
Stack 0 contains 0426H
P0:0 contains 06H
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This example uses one word of memory and executes in one machine cycle. The
destination of Stack 0 (item on top of stack) is P0:0. The 8-LSBs of the data in
stack 0 are loaded into P0:0. At transfer, Stack 1 is automatically moved to Stack
0.
([DPSOH
POP <dregs>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
D0:0 contains 7676H
Instruction:
POP D0:0
Result:
Stack 0 contains 0426H
D0:0 contains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by D0:0. When transferred,
Stack 1 is automatically moved to Stack 0.
([DPSOH
POP <regind>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
P0:0 contains 24H
RAM Bank0: 24H contains 42A4H
Instruction:
POP @P0:0
Result
Stack 0 contains 0426H
RAM Bank0: 24H contains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by P0:0. 24H is the register
location in RAM Bank0 to which the stack item is transferred. At transfer, Stack 1 is
automatically moved to Stack 0.
([DPSOH
POP <hwregs>
3679&
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Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
X Register contains 089CH
Instruction:
POP X
Result:
Stack 0 contains 0426H
X Register contains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by the X Register. At transfer,
Stack 1 is automatically moved to Stack 0. Transfer to <hwregs> is possible to all
hardware registers except the read-only P register.
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386+
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6\QWD[
PUSH <pregs>
PUSH <dregs>
PUSH <memind>
PUSH <accind>
PUSH <regind>
PUSH <hwregs>
PUSH <direct>
PUSH <limm>
2SHUDWLRQ
<source> —> Stack
Stack n —> Stack n+ 1
Flags: None
'HVFULSWLRQ
The contents of the specified register are placed on the stack. Because the stack is a last-in,
first-out (LIFO) hard-wired architecture, the placement and shifting of current stack data
is performed in a single cycle.
The PUSH instruction provides the ability to control information sent to the stack, making
it possible to expand the stack through software.
([DPSOH
PUSH <pregs>
3679&
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Initialization:
Stack 0 contains 0C06H
P1:1 contains A4H
Instruction:
PUSH P1:1
Result
Stack 1 contains 0C06H
Stack 0 contains 00A4H
This example uses one word of memory and executes in one machine cycle. The pointer
P1:1 contains the 8-bit value A4H. The 16-bit value, 00A4H, is pushed onto the stack. At
transfer, Stack 0 is automatically moved to Stack 1.
([DPSOH
PUSH <dregs>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
D1:1 contains 42A4H
Instruction:
PUSH D1:1
Result
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The pointer
D1:1 is pushed onto the stack. At transfer, Stack 0 is automatically moved to Stack 1.
([DPSOH
PUSH <memind>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
RAM Bank0: 24H contains 42A4H
P1:1 contains A4H
RAM Bank1: A4H contains 5463H
ROM Address 5463H contains 1126H
Instruction:
PUSH @@P1:1
Result:
Stack 1 contains 0C06H
Stack 0 contains 1126H
RAM Bank1: A4H contains 5464H
This example uses one word of memory and executes in three machine cycles. When
memory indirect addressing is used, the ROM address is automatically incremented.
3679&
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Using OR A,@@P0:0+ performs the same operation and also increments the P0:0
content to A5H.
([DPSOH
PUSH <accind>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
Accumulator contains 42A4H
ROM address 42A4H contains 4C45H
Instruction:
PUSH @A
Result
Stack 1 contains 0C06H
Stack 0 contains 4C45H
This example uses one word of memory and executes in one machine cycle. Indirect
addressing with the accumulator points to the ROM memory (42A4H) The data in this
location is pushed onto the stack. At transfer, Stack 0 is automatically moved to Stack 1.
([DPSOH
PUSH <regind>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
P1:1 contains A4H
RAM Bank1: A4H contains 42A4H
Instruction:
PUSH @P1:1
Result:
Stack 1 contains 0C06H
Stack 0 contains 42A4H
RAM Bank1: A4H contains 42A4H
This example uses one word of memory and executes in one machine cycle. The pointer
P1:1 contains the RAM register location (A4H). The data at this location is pushed onto
the stack. At transfer, Stack 0 is automatically moved to Stack 1.
([DPSOH
PUSH <hwregs>
Initialization:
3679&
Stack 1 contains 0426H
Stack 0 contains 0C06H
X Register contains 42A4H
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Instruction:
PUSH X
Result:
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The data in
the X register is pushed onto the stack. At transfer, Stack 0 is automatically moved to
Stack 1. Transfer from <hwregs> is possible from all hardware registers.
([DPSOH
PUSH <direct>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
RAM Bank0: 24H contains 42A4H
Instruction:
PUSH %24
Result:
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The
instruction (24H) provides the direct register address. The value contained in this register
is pushed onto the stack (42A4H). At transfer, Stack 0 is automatically moved to Stack 1.
([DPSOH
PUSH <limm>
Initialization:
Stack 1 contains 0426H
Stack 0 contains 0C06H
Instruction:
PUSH #%5757
Result:
Stack 1 contains 0C06H
Stack 0 contains 5757H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 5757H is pushed onto the stack. At transfer, Stack 0 is automatically
moved to Stack 1.
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5(7
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RET
2SHUDWLRQ
Stack 0 —> PC
Stack n —> Stack n-1
Flags: None
'HVFULSWLRQ
The current stack information is popped from the stack and placed in the Program Counter
(PC) register. The jump is made from the subroutine via the PC.
([DPSOH
RET
Initialization:
Stack 1 contains 0624
Stack 0 contains 0401
PC contains 06DF
Instruction:
RET
Result:
Stack 0 contains 0624
PC contains 0401H
This example uses one word of memory and executes in one machine cycle.
3679&
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6\QWD[
RL A
RL <cc>,A
2SHUDWLRQ
C <= 23 ------------ < ---------- 8 <= C
Flags: N
Z
C
Set if result of accumulator is negative
Set if result is zero.
Set if MSB is set before rotate.
'HVFULSWLRQ
The upper 16 bits of the accumulator are rotated left through the carry bit. The lower 8 bits
remain unchanged while the resultant LSB, bit 0, is placed with the value 0 (see the
accumulator section).
([DPSOH
RL A
Initialization:
A contains 226A84H
Carry bit contains 1
Instruction:
RL A
Result:
A contains 44D584H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The upper 16
bits (226AH) are shifted left through the carry bit to produce 44D5H. The lower 8 bits
(84H) remain unchanged.
3679&
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([DPSOH
RL <cc>, A
Initialization:
A contains 226A84H
Carry bit contains 0, Z=0
Instruction:
RL Z, A
Result:
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code 0 is not set; therefore, the instruction is not executed.
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55
527$7(5,*+7
55
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FF
FF
FF
FF
FF
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$&&0RGLILFDWLRQ
6\QWD[
RR A
RR <cc>, A
2SHUDWLRQ
C =>23 ---- > 8 = => 7 - -> -- 0 —> discarded
Flags: N
Z
C
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before rotate.
'HVFULSWLRQ
The upper 16 bits of ACC are rotated right through the carry bit. The MSB of the lower 8
bits also obtains the data shifted from the LSB of upper 16 bits. The lower 8 bits are
shifted right with the LSB being discarded.
([DPSOH
RR A
Initialization:
A contains 226A84H
Carry bit contains 0
Instruction:
RR A
Result:
A contains 113542H
This example uses one word of memory and executes in one machine cycle. The upper 16
bits (226AH) are shifted right through the carry bit to produce 1135H. The lower 8 bits
(84H) are shifted right to provide 42H.
([DPSOH
RR <cc>, A
3679&
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Initialization:
A contains 226A84H
Carry bit contains 0, Z=0
Instruction:
RR Z, A
Result:
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code 0 is not set; therefore, the instruction is not executed.
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RS
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6\QWD[
SCF
2SHUDWLRQ
1 —> Carry Bit
Flags: C
Set to 1.
'HVFULSWLRQ
The Set Carry Flag instruction places a one in the carry bit (bit 12 of the Status Register).
([DPSOH
SCF
Initialization:
SR contains 2000H
Instruction:
SCF
Result:
SR contains 3000H
C contains 1
This example uses one word of memory and executes in one machine cycle.
3679&
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6,()
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FF
FF
FF
FF
FF
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6\QWD[
SIEF
2SHUDWLRQ
1 —> IE bit
Flags: None
'HVFULSWLRQ
The instruction places a 1 in bit 7 of the status register and is used to enable interrupts.
([DPSOH
SIEF
Initialization:
SR contains 3000H
Instruction:
SIEF
Result:
SR contains 3080H
IE contains 1
This example uses one word of memory and executes in one machine cycle.
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6+,)7/()7/2*,&$/
6//
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FF
FF
FF
FF
FF
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6\QWD[
SLL A
SLL <cc>, A
2SHUDWLRQ
discarded <— C <= 23 - - - - < - - - -0 <= 0
Flags: N
Z
C
Set if result of accumulator is negative
(bit 23 set to 1).
Set if result is 0.
Set if MSB is set before shift.
'HVFULSWLRQ
All 24 bits of the accumulator are shifted left through the carry bit. The MSB, bit 23,
passes through the carry bit before being discarded. The LSB, bit 0, is filled with a zero.
Subsequent shifts cause additional zeroes to be shifted in.
([DPSOH
SLL A
Initialization:
A contains 226A84H
Carry bit contains 0
Instruction:
SLL A
Result:
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. All 24 bits of
the accumulator are shifted left through the carry bit, producing the result 44D508H.
([DPSOH
SLL <cc>, A
3679&
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Initialization:
A contains 226A84H
Carry bit contains 0
Instruction:
SLL MI, A
Result:
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code N is not set, and the instruction is not executed.
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6\QWD[
SOPF
2SHUDWLRQ
1 —> OP bit
Flags: None
'HVFULSWLRQ
The Set Overflow Protection Flag instruction places a one in bit 8 of the status register. If
an ALU operation exceeds the limits of the processor, the overflow protection sets the
overflow flag (OV) and holds the limit value in the accumulator.
([DPSOH
SOPF
Initialization:
SR contains 0000H
Instruction:
SOPF
Result:
SR contains 0100H
OP contains 1
This example uses one word of memory and executes in one machine cycle.
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65$
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FF
FF
FF
FF
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$&&0RGLILFDWLRQ
6\QWD[
SRA A
SRA
<cc>, A
2SHUDWLRQ
23 => 23 --- > ---- 0 => discarded
Flags: N
Z
C
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before the shift.
'HVFULSWLRQ
All 24 bits of the accumulator are shifted right with sign extension through the carry bit.
The MSB, bit 23, is replicated in vacated bits. The LSB, bit 0, is passed through the carry
before it is discarded.
([DPSOH
SRA A
Initialization:
A contains 226A84H
Carry bit contains 0
Instruction:
SRA A
Result:
A contains 113542H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. All 24 bits of
the accumulator are shifted right. The MSB, bit 23, is copied into bit 22. The LSB, bit 0,
is discarded.
3679&
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([DPSOH
SRA
<cc>, A
Initialization:
A contains 226A84H
Carry bit contains 0, N=0
Instruction:
SRA A
Result:
A contains 113542H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The condition
code is set; therefore, the instruction is executed. The initialization of the accumulator sets
the PL (NN) condition code.
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68%75$&7
68%
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SUB A, <regind>
SUB A, <memind>
SUB A, <limm>
SUB A, <hwregs>
SUB A, <direct>
SUB A, <pregs>
SUB A, <dregs>
SUB A, <simm>
2SHUDWLRQ
ACC – (Source) —> ACC
Flags: C
N
Z
OV
Set if a carry from the most significant bit is
performed.
Set if the result in the accumulator is negative.
Set if the result is 0.
Set if the addition exceeds the upper (7FFFFFH)
or lower (800000H) limit of the accumulator.
'HVFULSWLRQ
The addressed data memory operand is subtracted from the accumulator. The result is
loaded into the accumulator.
The lower eight bits of the accumulator are cleared by the execution of the subtract
instruction.
([DPSOH
SUB A, <regind>
3679&
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Initialization:
Accumulator contains 874600H
P0: 1 contains 45H
RAM Bank1: 45H contains 1234H
Instruction:
SUB A, @P0:1
Result:
A contains 751200H
@P0:1 contains 1234H
This example uses one word of memory and executes in one machine cycle. The contents
of the register pointed by P0:1 are subtracted from the accumulator. The difference is
contained in the accumulator and the pointer is left unchanged. The register pointer
contains 45H. Because the pointer references RAM Bank1, the absolute register is 145H
(325). Therefore, the contents of register 145H are subtracted from the accumulator.
874600H - 123400H = 751200H. The direct addressing equivalent is SUB
A,%145 or SUB A,325.
([DPSOH
SUB A, <memind>
Initialization:
Accumulator contains 874600H
P0:0 contains 21H
RAM Bank0: 21H contains 247AH
ROM Address: 247AHcontains 1234H
Instruction:
SUB A, @@P0:0+
Result:
A contains 751200H
P0:0 contains 22H
RAM Bank0: 21 H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
is used for memory indirect addressing. The pointer contains the address of the RAM
(address 247AH). The RAM contains the address of the requested ROM data (data
247AH). This operand is subtracted from the accumulator. 874600H - 123400H =
751200H.
([DPSOH
SUB A, <limm>
Initialization:
Accumulator contains 874600H
Instruction:
SUB A, #%1234
Result:
Accumulator contains 751200H
3679&
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This example uses two words of memory and executes in two machine cycles. The
immediate operand 8746H is subtracted from the accumulator. 874600H - 123400H
= 751200H.
([DPSOH
SUB A, <hwregs>
Initialization:
Accumulator contains 874600H
Register X contains 1234H
Instruction:
SUB A, X
Result:
A contains 751200H
This example uses one word of memory and executes in one machine cycle. The contents
of Register X are subtracted from the accumulator. 874600H - 123400H =
751200H. Transfer from <hwregs> is possible from all hardware registers.
([DPSOH
SUB A, <direct>
Initialization:
Accumulator contains 874600H
RAM Bank0: F3H contains 1234H
Instruction:
SUB A, %F3
Result:
A contains 751200H
This example uses one word of memory and executes in one machine cycle. The contents
of register F3H are subtracted from the accumulator. 874600H - 123400H =
751200H. An equivalent instruction is SUB A, 243 (F3H = 243 decimal).
([DPSOH
SUB A, <dregs>
Initialization:
Accumulator contains 874600H
D0: 1 contains 1234H
Instruction:
SUB A, D0:1
Result:
A contains 751200H
D0:1 contains 1234H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1 are subtracted from the accumulator. The difference is contained
in the accumulator and the pointer is left unchanged.
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SUB A, <pregs>
Initialization:
Accumulator contains 874600H
P0:0 contains 56H
Instruction:
SUB A, P0:0
Result:
Accumulator contains 86F000H
This example uses one word of memory and executes in one machine cycle. The contents
of pointer register P0:0 are subtracted from the accumulator. 874600H - 005600H =
86F000H. The Pointer Register is connected to the lower 8 bits of the D-bus. The D-bus
is connected to the upper 16 bits of the P-bus. This causes the pointer register operand to
become 005600H before it is subtracted from the accumulator.
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XOR A, <regind>
XOR A, <memind>
XOR A, <limm>
XOR A, <hwregs>
XOR A, <direct>
XOR A, <pregs>
XOR A, <dregs>
XOR A, <simm>
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Flags: C
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Set if carry from the most significant bit is
performed.
Set if result in the accumulator is negative.
Set if result is 0.
Set if operation exceeds upper (7FFFFFH) or lower
(800000H) limit of accumulator.
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With the accumulator, perform an XOR instruction on the addressed data memory operand.
The result loads into the accumulator.
The lower eight bits of the accumulator are cleared by the XOR instruction.
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XOR A, <regind>
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Initialization:
Accumulator contains 005600H
P0:0 contains 00H
RAM Bank0: 00H contains 1234H
Instruction:
XOR A, @P0:0
Result:
A contains 126200H
This example uses one word of memory and executes in one machine cycle. The pointer is
used for memory indirect addressing. The pointer contains the address of the RAM
(address 00H). Location 00H has operand 1234H. With the accumulator, 005600H,
perform an XOR instruction to obtain the result 126200H.
([DPSOH
XOR A, <memind>
Initialization:
A contains 3264A0H
P21 contains A4H
RAM Bank1: A4H contains 5463H
ROM Address: 5463H contains 1126H
Instruction:
XOR A, @@P2:1
Result
A contains 2342A0H
P2:1 contains A41H
RAM Bank1: A4H contains 5464H
SR contains 0000H
This example uses one word of memory and executes in three machine cycles. The pointer
P2:1 contains the RAM register location(A4H). The contents of this register have a ROM
address. This address refers to the ROM data compared to the accumulator.
3264A0H.XOR.112600H = 2342A0H. When indirect memory addressing is used,
the ROM address is automatically incremented. Using XOR A, @@P2:1+ performs the
same operation and also increments the P21 content to A5H.
([DPSOH
XOR A, <limm>
Initialization:
A contains 3264A0H
Instruction:
XOR A, #%1126
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Result:
A contains 2342A0H
SR contains 0000H
This example uses two words of memory and executes in two machine cycles. Perform an
XOR instruction on the immediate data.
([DPSOH
XOR A, <hwreg>
Initialization:
A contains 3264A0H
SR contains 0000H
BUS contains 1126H
Instruction:
XOR A, BUS
Result:
A contains 2342A0H
SR contains
This example uses one word of memory and executes in one machine cycle. With the
accumulator, perform an XOR instruction on the <hwreg> operand.
([DPSOH
XOR A, <direct>
Initialization:
Accumulator contains 3264A0H
RAM Bank0: F3H contains 1126H
Instruction:
XOR A, %F3
Result:
A contains 2342A0H
SR contains 0000H
This example uses one word of memory and executes in one machine cycle. Register F3H
is compared to the accumulator. 3264A0H.XOR.112600H = 2342A0H. An
equivalent instruction is XOR A, 243 (F3H = 243 decimal).
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The RGB outputs in analog mode are controlled current sources with an internal load.
These outputs display gamma-corrected, VCC prorated characteristics. See Table 82,
Table 83, and Figure 28.
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The Z90356 provides the ability to
•
decode closed-caption transmissions
•
display characters on the screen
•
manipulate analog and digital control circuits
•
monitor keypad and infrared signals directly
•
generate OSD if the Z90356 receives vertical and horizontal synchronization signals
In a typical system, normal transmission is received and demodulated. The signals
received from the color decoder and deflection unit control the CRT display. To display
characters generated by the Z90356 requires a video multiplexor which enables the CRT
display’s RGB signals and synchronization to be controlled by the video outputs from the
processor. When the controller has to display a character on the screen, the multiplexor is
switched, and the processor’s video signals appear on the display.
The band-limited, A/C-coupled composite video signal is clamped internally to the
negative reference voltage (REF–) during the back porch interval. It is then passed to the
analog-to-digital converter through a 6:1 multiplexor. The digital signal is then decoded to
extract the closed-caption text embedded in the video signal. The characters received are
generated as video signals and are then passed to the display.
When a detectable composite video signal is received, the SYNC separator extracts the
horizontal and vertical synchronization signals and passes them to the deflection module
of the television. The FLYBACK signals from the deflection coils are fed back to the
Z90356. The controller uses these signals to align its video signals with those of the
normal display. If the composite video signal is not present, video synchronization is
provided by the controller. In this case, the SYNC signal pins are set to be outputs. The
pins then feed to the deflection unit which controls the display. The SYNC generators can
be configured to provide either HSYNC and VSYNC, or H-FLYBACK and V-FLYBACK.
Analog functions such as volume and color controls can be controlled by pulse width
modulated outputs from the Z90356. Additional digital controls like channel fine tuning
are controlled via the serial I2C bus.
An infrared remote control receiver can be directly decoded through the capture register,
and keypad input can be scanned by directly controlling I/O pins as keyscan ports.
The processor clock is available by referencing an internal phase locked loop to an
external 32.768 KHz crystal oscillator. The oscillator minimizes EMI emissions from the
clock circuitry. The internal system clock frequency can be selected as 12.058 MHz in
normal operation or 32.768 KHz in low power consumption SLEEP mode (usually used if
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there is a general system power failure). The Z90356’s STOP mode suspends processor
clocking for a power-down.
Program, display, and character graphics memory are on the chip, eliminating the
requirement for external memory components. Characters can be displayed as two or three
times normal size. Smoothing and fringing circuits enhance display appearance.
Figure 29 diagrams a typical application of the Z90356 Television Controller as an
embedded controller in a television.
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Figure 30 and Table 84 indicate the controlling dimensions.
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If there are any problems while operating this product, or any inaccuracies in the specification,
please copy and complete this form, then mail or fax it to ZiLOG. Suggestions welcome!
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System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: [email protected]
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