Revised October 2000 74F538 1-of-8 Decoder with 3-STATE Outputs General Description Features The 74F538 decoder/demultiplexer accepts three Address (A0–A2) input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of 32 decoding with four packages, or for data demultiplexing to 1-of-8 or 1-of-16 destinations. ■ Output polarity control ■ Data demultiplexing capability ■ Multiple enables for expansion ■ 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F538SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F538SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F538PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009551 www.fairchildsemi.com 74F538 1-of-8 Decoder with 3-STATE Outputs April 1988 74F538 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL A0–A2 Address Inputs 1.0/1.0 20 µA/−0.6 mA E1 , E2 Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA E3 , E4 Enable Inputs (Active HIGH) 1.0/1.0 20 µA/−0.6 mA P Polarity Control Input 1.0/1.0 20 µA/−0.6 mA OE1, OE2 Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA O0–O7 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Truth Table Inputs Function Outputs OE1 OE2 E1 E2 E3 E4 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 High H X X X X X X X X Z Z Z Z Z Z Z Z Impedance X H X X X X X X X Z Z Z Z Z Z Z Z L Disable L L H X X X X X X L L X H X X X X X L L X X L X X X X X O7 Outputs Equal P Input L L X X X L X X Active HIGH L L L L H H L L L H L L L L L L Output L L L L H H L L H L H L L L L L L (P = L) L L L L H H L H L L L H L L L L L L L L L H H L H H L L L H L L L L L L L L H H H L L L L L L H L L L L L L L H H H L H L L L L L H L L L L L L H H H H L L L L L L L H L L L L L H H H H H L L L L L L L H Active LOW L L L L H H L L L L H H H H H H H Output L L L L H H L L H H L H H H H H H (P = H) L L L L H H L H L H H L H H H H H L L L L H H L H H H H H L H H H H L L L L H H H L L H H H H L H H H L L L L H H H L H H H H H H L H H L L L L H H H H L H H H H H H L H L L L L H H H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance www.fairchildsemi.com 2 74F538 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F538 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150 °C Ambient Temperature under Bias −55°C to +125 °C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150 °C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH VOL 2.0 Units VIH IIN = −18 mA 10% VCC 2.5 IOH = −1 mA 10% VCC 2.4 IOH = −3 mA 5% VCC 2.7 5% VCC 2.7 Output LOW Input HIGH Current IBVI Input HIGH Current V 10% VCC Output HIGH Leakage Current Input Leakage Test Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCH Power Supply Current ICCL ICCZ IOH = −1 mA 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Min IOH = −3 mA Breakdown Test IOD Recognized as a LOW Signal Min Output HIGH IIH VID Conditions Recognized as a HIGH Signal Voltage Voltage ICEX VCC V IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 31 45 mA Max VO = HIGH Power Supply Current 37 56 mA Max VO = LOW Power Supply Current 37 56 mA Max VO = HIGH Z www.fairchildsemi.com −60 4 74F538 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max 6.0 11.0 16.0 6.0 17.0 tPLH Propagation Delay tPHL An to On 4.0 7.5 11.0 4.0 12.0 tPLH Propagation Delay 5.0 8.5 15.0 5.0 16.0 tPHL E1 or E2 to On 4.0 6.5 9.0 4.0 10.0 17.0 tPLH Propagation Delay 6.0 11.0 16.0 6.0 tPHL E3 or E4 to On 5.0 10.0 14.0 5.0 15.0 tPLH Propagation Delay 6.0 11.5 18.0 6.0 20.0 tPHL P to On 6.0 11.0 16.0 6.0 17.0 tPZH Output Enable Time 3.0 5.5 10.0 3.0 11.0 tPZL OE1 or OE2 to On 5.0 9.0 13.0 5.0 14.0 tPHZ Output Disable Time 2.0 4.0 6.0 2.0 7.0 tPLZ OE1 or OE2 to On 3.0 5.0 8.0 3.0 9.0 5 Units ns ns ns www.fairchildsemi.com 74F538 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B www.fairchildsemi.com 6 74F538 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74F538 1-of-8 Decoder with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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