® ADS ADS1286 128 ADS 6 128 6 12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● The ADS1286 is a 12-bit, 20kHz analog-to-digital converter with a differential input and sample and hold amplifier and consumes only 250µA of supply current. The ADS1286 offers an SPI and SSI compatible serial interface for communications over a two or three wire interface. The combination of a serial two wire interface and micropower consumption makes the ADS1286 ideal for remote applications and for those requiring isolation. The ADS1286 is available in a 8-pin plastic mini DIP and a 8-lead SOIC. SERIAL INTERFACE GUARANTEED NO MISSING CODES 20kHz SAMPLING RATE LOW SUPPLY CURRENT: 250µA APPLICATIONS ● ● ● ● REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION TRANSDUCER INTERFACE BATTERY OPERATED SYSTEMS Control SAR VREF DOUT +In Serial Interface CDAC –In S/H Amp Comparator DCLOCK CS/SHDN International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © SBAS053 1996 Burr-Brown Corporation PDS-1335B Printed in U.S.A. October, 1998 SPECIFICATIONS At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified. ADS1286, ADS1286A PARAMETER CONDITIONS MIN +In – (–In) +In –In 0 –0.2 –0.2 ANALOG INPUT Full-Scale Input Range Absolute Input Voltage ADS1286K, ADS1286B ADS1286C, ADS1286L MAX MIN MAX MIN VREF VCC +0.2 +0.2 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ TYP Capacitance Leakage Current ✻ ✻ 25 ±1 SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Differential Linearity Offset Error Gain Error Noise Power Supply Rejection ±2 ±1.0 ±3 ±8 VIN = VIN = VIN = VIN = SINAD Spurious Free Dynamic Range REFERENCE INPUT REF Input Range Input Resistance 5.0Vp-p 5.0Vp-p 5.0Vp-p 5.0Vp-p at at at at ✻ ✻ ✻ ✻ ✻ ✻ 1.25 DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format ✻ TEMPERATURE RANGE Specified Performance ADS1286, K, L ADS1286A, B, C ✻ ✻ –85 –83 72 90 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ dB dB dB dB VCC+0.05V ✻ 2.5 20 20 3 0.0 3 0.0 5 200 250 0 –40 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ +VCC 0.8 +VCC 0.4 +4.50 ±1 ±0.75 ✻ ✻ Bits Bits LSB LSB LSB LSB µVrms dB ✻ ✻ ✻ ✻ ✻ 5.25 400 500 3 ✻ ✻ ✻ ✻ ✻ +70 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V MΩ MΩ µA µA µA ✻ ✻ ✻ ✻ V V V V ✻ ✻ ✻ ✻ V µA µA µA ✻ ✻ °C °C ✻ ✻ ✻ ✻ ✻ ✻ Straight Binary POWER SUPPLY REQUIREMENTS Power Supply Voltage VCC Quiescent Current, VANA tCYC ≥ 640µS, fCLK ≤ 25kHz tCYC = 90µS, fCLK = 200kHz Power Down CS = VCC V V V pF µA 500 CMOS IIH = +5µA IIL = +5µA IOH = 250µA IOL = 250µA ✻ ✻ ✻ Clk Cycles Clk Cycles kHz 2.5 5000 5000 0.01 2.4 2.4 CS = VCC CS = GND, fCLK = 0Hz CS = VCC tCYC ≥ 640µs, fCLK ≤ 25kHz tCYC = 80µs, fCLK = 200kHz Current Drain ±0.5 ±0.25 ✻ ✻ ✻ ✻ ✻ ±0.75 ✻ ✻ ✻ 1kHz 5kHz 1kHz 1kHz UNITS ✻ 12 1.5 DYNAMIC CHARACTERISTICS Total Harmonic Distortion MAX ✻ ✻ ±1 ±0.5 0.75 ±2 50 82 TYP ✻ ✻ ✻ 12 12 SAMPLING DYNAMICS Conversion Time Acquisition Time Small Signal Bandwidth TYP ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ Specifications same as grade to the left. TIMING CHARACTERISTICS fCLK = 200kHz, TA = TMIN to TMAX. SYMBOL PARAMETER CONDITIONS MIN tSMPL tSMPL (MAX) tCONV tdDO tdis ten thDO tf tr tCSD tSUCS Analog Input Sample Time Maximum Sampling Frequency Conversion Time Delay TIme, DCLOCK↓ to DOUT Data Valid Delay TIme, CS↑ to DOUT Hi-Z Delay TIme, DCLOCK↓ to DOUT Enable Output Data Remains Valid After DCLOCK↓ DOUT Fall Time DOUT Rise Time Delay Time, CS↓ to DCLOCK↓ Delay Time, CS↓ to DCLOCK↑ See Operating Sequence ADS1286 See Operating Sequence See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits See Operating Sequence See Operating Sequence 1.5 ® ADS1286 2 15 30 TYP 12 85 25 50 30 70 60 MAX UNITS 2.0 20 Clk Cycles kHz Clk Cycles ns ns ns ns ns ns ns ns 150 50 100 100 100 0 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VCC ..................................................................................................... +6V Analog Input ....................................................... –0.3V to (+VCC + 300mV) Logic Input ......................................................... –0.3V to (+VCC + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. NOTE: (1) Stresses above these ratings may permanently damage the device. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION VREF 1 +In 2 8 +VCC 7 DCLOCK ADS1286 –In 3 6 DOUT GND 4 5 CS/SHDN 8-Pin Mini PDIP 8-Lead SOIC PIN ASSIGNMENTS PIN NAME 1 VREF DESCRIPTION 2 +In Non Inverting Input. 3 –In Inverting Input. Connect to ground or remote ground sense point. Reference Input. 4 GND 5 CS/SHDN Ground. 6 DOUT 7 DCLOCK 8 +VCC Chip Select when low, Shutdown Mode when high. The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges. Data Clock synchronizes the serial data transfer and determines conversion speed. Power Supply. PACKAGE/ORDERING INFORMATION PRODUCT ADS1286P ADS1286PK ADS1286PL ADS1286U ADS1286UK ADS1286UL ADS1286PA ADS1286PB ADS1286PC ADS1286UA ADS1286UB ADS1286UC INTEGRAL LINEARITY TEMPERATURE RANGE PACKAGE PACKAGE DRAWING NUMBER(1) ±2 ±2 ±1 ±2 ±2 ±1 ±2 ±2 ±1 ±2 ±2 ±1 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Plastic DIP Plastic DIP Plastic DIP SOIC SOIC SOIC Plastic DIP Plastic DIP Plastic DIP SOIC SOIC SOIC 006 006 006 182 182 182 006 006 006 182 182 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS1286 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs CODE 3.0 Differential Linearity Error (LSB) 11.75 11.5 11.25 11 10.75 10.5 10.25 2.0 1.0 0 –1.0 –2.0 –3.0 10 0.1 1 Reference Voltage (V) 10 0 100 100 90 90 Spurious Free Dynamic Range and Signal-to-Noise Ratio (dB) Signal-to-(Noise + Distortion) (dB) 2048 Code 4095 SPURIOUS FREE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO vs FREQUENCY SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY 80 70 60 50 40 30 20 Spurious Free Dynamic Range 80 70 60 Signal-to-Noise Ratio 50 40 30 20 10 10 0 0 0.1 1 Frequency (kHz) 0.1 10 SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL 1 Frequency (kHz) 10 TOTAL HARMONIC DISTORTION vs FREQUENCY 80 0 70 –10 Total Harmonic Distortion (dB) Signal-to-(Noise + Distortion) (dB) Effective Number of Bits (rms) 12 60 50 40 30 20 10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 –40 –35 –30 –25 –20 –15 Input Level (dB) –10 –5 0.1 0 1 Frequency (kHz) 10 ® 5 ADS1286 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. 4096 POINT FFT PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 10 0 Peak-to-Peak Noise (LSB) 9 Magnitude (dB) –25 –50 –75 –100 8 7 6 5 4 3 2 1 –125 0 0 2 4 0.1 6 1 Reference Voltage (V) Frequency (kHz) POWER SUPPLY REJECTION vs RIPPLE FREQUENCY 10 CHANGE GAIN vs TEMPERATURE 0 0.15 VRIPPLE = 20mV –20 0.1 Delta from 25°C (LSB) Power Supply Rejection (dB) –10 –30 –40 –50 –60 –70 0.05 0 –0.05 –0.1 –80 –0.15 –90 1 10 100 1000 Ripple Frequency (kHz) –55 10000 –25 0 25 70 85 Temperature (°C) POWER DOWN SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 3 400 2.5 350 Supply Current (µA) Supply Current (µA) –40 2 1.5 1 0.5 300 fSAMPLE = 12.5kHz 250 200 fSAMPLE = 1.6kHz 150 0 100 –55 –40 –25 0 25 70 85 –55 Temperature (°C) –25 0 25 Temperature (°C) ® ADS1286 –40 6 70 85 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified. DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE INTEGRAL LINEARITY ERROR vs CODE Digital Input Threshold Voltage (V) 3 2.0 1.0 0 –1.0 –2.0 –3.0 2.5 2 1.5 1 0.5 0 0 2048 Code 4095 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 Supply Voltage (V) INPUT LEAKAGE CURRENT vs TEMPERATURE 10 Leakage Current (nA) Integral Linearity Error (LSB) 3.0 1 0.1 0.01 –55 –40 –25 0 25 70 85 Temperature (°C) ® 7 ADS1286 TIMING DIAGRAMS AND TEST CIRCUITS 1.4V 3kΩ DOUT VOH DOUT VOL Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times tr, and tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VIL VCC tdDO DOUT VOH DOUT tdis Waveform 2, ten 3kΩ tdis Waveform 1 100pF CLOAD VOL thDO Load Circuit for tdis and tden Voltage Waveforms for DOUT Delay Times, tdDO VIH CS/SHDN DOUT Waveform 1(1) CS/SHDN 90% DCLOCK 10% DOUT 1 2 tdis DOUT Waveform 2(2) ten Voltage Waveforms for tdis NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Voltage Waveforms for ten ® ADS1286 VOL 8 B11 tCYC CS/SHDN POWER DOWN tSUCS DCLOCK tCSD DOUT HI-Z NULL BIT B11 B10 B9 (MSB) tSMPL NULL BIT HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0(1) tCONV B11 B10 B9 B8 tDATA Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output LSB-First data then followed with zeroes indefinitely. tCYC CS/SHDN tSUCS POWER DOWN DCLOCK tCSD DOUT HI-Z tSMPL NULL BIT B11 B10 B9 (MSB) HI-Z B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 (2) tCONV tDATA Note: (2) After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output zeroes indefinitely. tDATA: During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes. FIGURE 1. ADS1286 Operating Sequence. SERIAL INTERFACE leaving the DCLOCK running to clock out the LSB first data or zeroes. If the CS input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. The ADS1286 communicates with microprocessors and other external digital systems via a synchronous 3-wire serial interface. DCLOCK synchronizes the data transfer with each bit being transmitted on the falling DCLOCK edge and captured on the rising DCLOCK edge in the receiving system. A falling CS initiates data transfer as shown in Figure 1. After CS falls, the second DCLOCK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line. Bringing CS high resets the ADS1286 for the next data exchange. Supply Current (µA) 1000 MICROPOWER OPERATION With typical operating currents of 250µA and automatic shutdown between conversions, the ADS1286 achieves extremely low power consumption over a wide range of sample rates (see Figure 2). The auto-shutdown allows the supply current to drop with sample rate. 100 10 1 0.1k SHUTDOWN The ADS1286 is equipped with automatic shutdown features. The device draws power when the CS pin is LOW and shuts down completely when the pin is HIGH. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion TA = 25°C VCC = 5V VREF = 5V fCLK = 16 • fSAMPLE 1k 10k 100k Sample Rate (kHz) FIGURE 2. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate. ® 9 ADS1286 REDUCED REFERENCE OPERATION MINIMIZING POWER DISSIPATION In systems that have significant time between conversions, the lowest power drain will occur with the minimum CS LOW time. Bringing CS LOW, transferring data as quickly as possible, and then bringing it back HIGH will result in the lowest current drain. This minimizes the amount of time the device draws power. After a conversion the A/D automatically shuts down even if CS is held LOW. If the clock is left running to clock out LSB-data or zero, the logic will draw a small amount of current (see Figure 3). The effective resolution of the ADS1286 can be increased by reducing the input span of the converter. The ADS1286 exhibits good linearity and gain over a wide range of reference voltages (see Typical Performance Curves “ Change in Linearity vs Reference Voltage” and “Change in Gain vs Reference Voltage”). However, care must be taken when operating at low values of VREF because of the reduced LSB size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 6.00 TA = 25°C VCC = +5V VREF = +5V fCLK = 16 • fSAMPLE Supply Current (µA) 5.00 4.00 1. Offset 2. Noise OFFSET WITH REDUCED VREF CS = LOW (GND) 3.00 The offset of the ADS1286 has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Curve “Change in Offset vs Reference Voltage” shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.1 LSB with a 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the negative input of the ADS1286. 2.00 1.00 CS HIGH (VCC) 0.00 0.1 1 10 100 Sample Rate (kHz) FIGURE 3. Shutdown Current with CS HIGH is Lower than with CS LOW. RC INPUT FILTERING It is possible to filter the inputs with an RC network as shown in Figure 4. For large values of CFILTER (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 20pF x VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 64µs, the input current equals 1.56µA at VIN = 5V. In this case, a filter resistor of 75Ω will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. RFILTER NOISE WITH REDUCED VREF The total input referred noise of the ADS1286 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the 200µV noise is only 0.15LSB peak-to-peak. In this case, the ADS1286 noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 2.5V reference this same 200µV noise is 0.3LSB peak-to-peak. If the reference is further reduced to 1V, the 200µV noise becomes equal to 0.8LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. IDC VIN CFILTER ADS1286 FIGURE 4. RC Input Filtering. ® ADS1286 10 +5V +5V +5V R8 46kΩ D1 R1 150kΩ TC1 R9 1kΩ OPA237 C2 0.1µF R3 500kΩ R2 59kΩ 0.4V R7 10Ω R6 1MΩ C1 10µF VREF MUX 0.2V ADS1286 DOUT A0 CS/SHDN A1 Thermocouple TC3 R4 1kΩ C4 10µF ISO Thermal Block R10 1kΩ DCLOCK C3 0.1µF TC2 0.3V U2 U1 R5 500Ω U3 C5 0.1µF R11 1kΩ 0.1V R12 1kΩ µP 3-Wire Interface U4 FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286. +VCC REF200 (100µA) 0.1µF VREF 1 8 DCLOCK 2 ADS1286 RTD DOUT µP CS/SHDN 3 4 FIGURE 6. ADS1286 with RTD Sensor. ® 11 ADS1286 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. 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