LTC1286/LTC1298 Micropower Sampling 12-Bit A/D Converters In S0-8 Packages DESCRIPTION U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC1286/LTC1298 are micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 250µA of supply current when converting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 5V to 9V supplies. These 12-bit, switched-capacitor, successive approximation ADCs include sample-and-holds. The LTC1286 has a single differential analog input. The LTC1298 offers a software selectable 2-channel MUX. 12-Bit Resolution 8-Pin SOIC Plastic Package Low Cost Low Supply Current: 250µA Typ. Auto Shutdown to 1nA Typ. Guaranteed ±3/4LSB Max DNL Single Supply 5V to 9V Operation On-Chip Sample-and-Hold 60µs Conversion Time Sampling Rates: 12.5 ksps (LTC1286) 11.1 ksps (LTC1298) I/O Compatible with SPI, Microwire, etc. Differential Inputs (LTC1286) 2-Channel MUX (LTC1298) 3V Versions Available: LTC1285/LTC1288 On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. These circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. U APPLICATIONS ■ ■ ■ ■ ■ ■ Battery-Operated Systems Remote Data Acquisition Battery Monitoring Handheld Terminal Interface Temperature Measurement Isolated Data Acquisition U TYPICAL APPLICATIONS N 25µW, S0-8 Package, 12-Bit ADC Samples at 200Hz and Runs Off a 5V Supply MPU (e.g., 8051) 1 ANALOG INPUT 0V TO 5V RANGE 2 3 4 VREF +IN –IN GND VCC LTC1286 CLK DOUT CS/SHDN 8 P1.4 7 P1.3 6 5 TA = 25°C VCC = VREF = 5V fCLK = 200kHz 5V SUPPLY CURRENT (µA) 4.7µF Supply Current vs Sample Rate 1000 100 10 P1.2 SERIAL DATA LINK LTC1286/98 • TA01 1 0.1k 1k 10k SAMPLE FREQUENCY (Hz) 100k LTC1286/98 • TA02 1 LTC1286/LTC1298 W W W ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Supply Voltage (VCC) to GND ................................... 12V Voltage Analog and Reference ................ –0.3V to VCC + 0.3V Digital Inputs......................................... –0.3V to 12V Digital Output ............................. –0.3V to VCC + 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1286C/LTC1298C............................. 0°C to 70°C LTC1286I/LTC1298I ........................... –40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C U W U PACKAGE/ORDER INFORMATION TOP VIEW VREF 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 CS/SHDN TOP VIEW ORDER PART NUMBER LTC1286CN8 LTC1286IN8 VREF 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 CS/SHDN ORDER PART NUMBER LTC1286CS8 LTC1286IS8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SOIC N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 150°C, θJA = 130°C/W TOP VIEW CS/SHDN 1 8 VCC (VREF) CH0 2 7 CLK CH1 3 6 DOUT GND 4 5 DIN 1286C 1286I TJMAX = 150°C, θJA = 175°C/W ORDER PART NUMBER TOP VIEW LTC1298CN8 LTC1298IN8 CS/SHDN 1 8 VCC (VREF) CH0 2 7 CLK CH1 3 6 DOUT GND 4 5 DIN ORDER PART NUMBER LTC1298CS8 LTC1298IS8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SOIC N8 PACKAGE 8-LEAD PLASTIC DIP 1298C 1298I TJMAX = 150°C, θJA = 175°C/W TJMAX = 150°C, θJA = 130°C/W Consult factory for military grade parts. U U U U WW RECOM ENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN VCC Supply Voltage (Note 3) LTC1286 LTC1298 4.5 4.5 9.0 5.5 V V fCLK Clock Frequency VCC = 5V (Note 4) 200 kHz tCYC Total Cycle Time LTC1286, fCLK = 200kHz LTC1298, fCLK = 200kHz 80 90 µs µs thDI Hold Time, DIN After CLK↑ VCC = 5V 150 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) LTC1286, VCC = 5V LTC1298, VCC = 5V 2 2 µs µs tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 5V 400 ns tWHCLK CLK High Time VCC = 5V 2 µs tWLCLK CLK Low Time VCC = 5V 2 µs tWHCS CS High Time Between Data Transfer Cycles VCC = 5V 2 µs tWLCS CS Low Time During Data Transfer LTC1286, fCLK = 200kHz LTC1298, fCLK = 200kHz 75 85 µs µs 2 TYP MAX UNITS LTC1286/LTC1298 W U U CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER CONDITIONS Resolution (No Missing Codes) MIN ● LTC1286 TYP MAX 12 (Note 5) LTC1298 TYP MAX MIN 12 UNITS Bits ● ±3/4 ±2 ±3/4 ±2 Differential Linearity Error ● ±1/4 ±3/4 ±1/4 ±3/4 LSB Offset Error ● 3/4 ±3 3/4 ±3 LSB Gain Error ● ±2 ±2 ±8 LSB Integral Linearity Error (Note 6) Analog Input Range (Note 7 and 8) REF Input Range (LTC1286) (Notes 7, 8, and 9) 4.5 ≤ VCC ≤ 5.5V 5.5V < VCC ≤ 9V Analog Input Leakage Current (Note 10) ● ±8 –0.05V to VCC + 0.05V V 1.5V to VCC + 0.05V 1.5V to 5.55V ● V V ±1 U DIGITAL AND DC ELECTRICAL CHARACTERISTICS LSB ±1 µA MAX UNITS (Note 5) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIH High Level Input Current VIN = VCC IIL Low Level Input Current VIN = 0V VOH High Level Output Voltage VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA ● ● VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA ● 0.4 V IOZ Hi-Z Output Leakage CS = High ● ±3 µA ISOURCE Output Source Current VOUT = 0V – 25 mA ISINK Output Sink Current VOUT = VCC 45 mA RREF Reference Input Resistance (LTC1286) CS = VCC CS = GND 5000 55 MΩ kΩ IREF Reference Current (LTC1286) CS = VCC tCYC ≥ 640µs, fCLK ≤ 25kHz tCYC = 80µs, fCLK = 200kHz ● ● ● 0.001 90 90 2.5 140 140 µA µA µA ICC Supply Current W U DYNAMIC ACCURACY MIN TYP 2 V 0.8 V ● 2.5 µA ● – 2.5 µA 4.0 2.4 4.64 4.62 V V CS = VCC ● 0.001 ±3.0 µA LTC1286, tCYC ≥ 640µs, fCLK ≤ 25kHz LTC1286, tCYC = 80µs, fCLK = 200kHz ● ● 200 250 400 500 µA µA LTC1298, tCYC ≥ 720µs, fCLK ≤ 25kHz LTC1298, tCYC = 90µs, fCLK = 200kHz ● ● 290 340 490 640 µA µA TYP MAX UNITS fSMPL = 12.5kHz (LTC1286), fSMPL = 11.1kHz (LTC1298) (Note 5) SYMBOL PARAMETER CONDITIONS S/(N +D) Signal-to-Noise Plus Distortion Ratio 1kHz/7kHz Input Signal MIN 71/68 dB THD Total Harmonic Distortion (Up to 5th Harmonic) 1kHz/7kHz Input Signal – 84/–80 dB SFDR Spurious-Free Dynamic Range 1kHz/7kHz Input Signal 90/86 dB Peak Harmonic or Spurious Noise 1kHz/7kHz Input Signal – 90/–86 dB 3 LTC1286/LTC1298 AC CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS tSMPL Analog Input Sample Time See Operating Sequence MIN TYP MAX 1.5 ● ● UNITS CLK Cycles fSMPL (MAX) Maximum Sampling Frequency LTC1286 LTC1298 12.5 11.1 kHz kHz tCONV Conversion Time See Operating Sequence tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 250 tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 135 300 ns ten Delay Time, CLK↓ to DOUT Enable See Test Circuits ● 75 200 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF tf DOUT Fall Time See Test Circuits ● 20 75 ns tr DOUT Rise Time See Test Circuits ● 20 75 ns CIN Input Capacitance Analog Inputs, On Channel Analog Inputs, Off Channel Digital Input 12 CLK Cycles 600 ns 230 ns 20 5 5 pF pF pF Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 4.5V ≤ VCC ≤ 5.5V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. For 5.5V < VCC ≤ 9V, reference and analog input range cannot exceed 5.55V. If reference and analog input range are greater than 5.55V, the output code will not be guaranteed to be correct. Note 8: The supply voltage range for the LTC1286 is from 4.5V to 9V, but the supply voltage range for the LTC1298 is only from 4.5V to 5.5V. Note 9: Recommended operating conditions Note 10: Channel leakage current is measured after the channel selection. The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: These devices are specified at 5V. For 3V specified devices, see LTC1285 and LTC1288. Note 4: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 120kHz at 85°C, fCLK ≥ 75kHz at 70° and fCLK ≥ 1kHz at 25°C. Note 5: VCC = 5V, VREF = 5V and CLK = 200kHz unless otherwise specified. Note 6: Linearity error is specified between the actual end points of the A/D transfer curve. U W TYPICAL PERFORMANCE CHARACTERISTICS 35 450 400 100 LTC1298 LTC1286 10 TA = 25°C VCC = VREF = 5V fCLK = 200kHz 30 350 LTC1298 fSMPL =11.1kHz 300 LTC1286 fSMPL =12.5kHz 1k 10k SAMPLE RATE (kHz) 100k LT1286/98 G03 4 200 –55 –35 –15 TA = 25°C VCC = VREF = 5V 25 20 15 10 CS = 0 (AFTER CONVERSION) 5 1 250 1 SUPPLY CURRENT (µA) TA = 25°C VCC = VREF = 5V fCLK = 200kHz SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1000 0.1k Shutdown Supply Current vs Clock Rate with CS High and CS Low Supply Current vs Temperature Supply Current vs Sample Rate 0.002 CS = VCC 0 5 25 45 65 85 105 125 TEMPERATURE (°C) LT1286/98 G04 1 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) LT1286/98 G01 LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Reference Current vs Sample Rate (LTC1286) 100 70 60 50 40 30 20 CHANGE IN OFFSET (LSB = 1/4096 VREF) VCC = VREF = 5V fSMPL = 12.5kHz fCLK = 200kHz TA = 25°C 94.5 REFERENCE CURRENT (µA) REFERENCE CURRENT (µA) 80 3 95 TA = 25°C VCC = 5V VREF = 5V fCLK = 200kHz 90 94 93.5 93 92.5 10 92 –55 –35 –15 0 0 2 4 8 6 10 FREQUENCY (kHz) 12 14 -1 1.5 -2 VCC = VREF = 5V fCLK = 200kHz fSMPL = fSMPL (MAX) 65 –0.4 –8 –0.3 –.25 –0.2 –0.15 –6 –5 –4 –3 –2 –0.05 –1 1.5 1 3.5 4 2 2.5 3 REFERENCE VOLTAGE (V) 4.5 0 5 1 1.5 3.5 4 2 2.5 3 REFERENCE VOLTAGE (V) LT1286/98 G10 1 0.5 EFFECTIVE NUMBER OF BITS (ENOBs) DIFFERENTIAL NONLINEARITY ERROR (LBS) 1.5 0.60 0.40 0.20 0.00 –0.20 –0.40 –0.60 –0.80 –1.0 5 LT1286/98 G15 0 2048 CODE 4096 5 Effective Bits and S/(N + D) vs Input Frequency 1.0 0.80 4.5 LT1286/98 G11 Differential Nonlinearity vs Code TA = 25°C VCC = 5V fCLK = 200kHz 5 –7 –0.1 0 4.5 TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz –9 –0.35 85 2 ADC NOISE IN LBSs 3.5 4 2 2.5 3 REFERENCE VOLTAGE (V) –10 Peak-to-Peak ADC Noise vs Reference Voltage 3 4 2 REFERENCE VOLTAGE (V) 1.5 Change In Gain vs Reference Voltage TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz LT1286/98 G09 1 0.5 LT1286/98 G08 CHANGE IN GAIN (LSB) CHANGE IN LINEARITY (LSB) CHANGE IN OFFSET (LSB) -0.5 45 -15 5 25 TEMPERATURE (°C) 1 1 –0.5 –0.45 -35 1.5 Change In Linearity vs Reference Voltage 0 -3 -55 2 LT1286/98 G07 Change in Offset vs Temperature -2.5 TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz 2.5 0 5 25 45 65 85 105 125 TEMPERATURE (°C) LT1286/98 G06 0 Change in Offset vs Reference Voltage Reference Current vs Temperature 12 11 74 68 10 9 62 56 8 50 7 44 6 38 5 4 3 TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz 2 1 0 1 10 100 INPUT FREQUENCY (kHz) 1000 LTC 1286/98 G20 5 LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Spurious Free Dynamic Range vs Frequency 100 0 80 90 80 70 60 50 40 30 20 TA = 25°C VCC = VREF = 5V fSMPL = 12.5kHz 10 0 10k 100k INPUT FREQUENCY (Hz) 1k TA = 25°C VCC = VREF = 5V fIN = 1kHz fSMPL = 12.5kHz 70 60 20 50 40 30 20 30 40 50 60 70 80 10 TA = 25°C VCC = VREF = 5V fSMPL = 12.5kHz 90 100 0 –40 1M 10 ATTENUATION (%) SIGNAL-TO-NOISE PLUS DISTORTION (dB) SPURIOUS FREE DYNAMIC RANGE (dB) Attenuation vs Input Frequency S/(N+D) vs Input Level –30 –20 –10 INPUT LEVEL (dB) 1 0 10k 100k 1M INPUT FREQUENCY (Hz) LTC 1286/98 G27 LTC 1286/98 G26 LT1286/98 G25 4096 Point FFT Plot –60 –80 TA = 25°C VCC = VREF = 5V –20 f1 = 5kHz f2 = 6kHz –40 fSMPL = 12.5kHz –60 –80 –100 –100 –120 –120 –140 0 1 2 4 3 5 FREQUENCY (kHz) 6 TA = 25°C VCC = 5V (VRIPPLE = 20mV) VREF = 5V fCLK = 200kHz FEEDTHROUGH (dB) MAGNITUDE (dB) 0 1 2 4 3 5 FREQUENCY (kHz) LTC 1286/98 G21 S&H ACQUISITION TIME (ns) CLOCK FREQUENCY (kHz) VIN 150 +INPUT –INPUT 100 RSOURCE– 300 TA = 25°C VCC = VREF = 5V 1000 RSOURCE+ VIN +INPUT 0.1 1 SOURCE RESISTANCE (kΩ) 10 LT1286/98 G12 100 0.1 1 10 100 1000 SOURCE RESISTANCE (Ω) 290 280 270 260 –INPUT TA = 25°C VCC = VREF = 5V 10000 Maximum Clock Frequency vs Supply Voltage TA = 25°C VCC = VREF = 5V 200 10 100 1000 RIPPLE FREQUENCY (kHz) LTC 1286/98 G22 10000 250 6 1 7 Sample and Hold Aquisition Time vs Source Resistance 300 0 6 LTC 1286/98 G24 Maximum Clock Frequency vs Source Resistance 50 –50 –100 –140 7 CLOCK FREQUENCY (kHz) MAGNITUDE (dB) –40 0 0 TA = 25°C VCC = VREF = 5V fIN = 5kHz fCLK = 200kHz fSMPL = 12.5kHz –20 Power Supply Feedthrough vs Ripple Frequency Intermodulation Distortion 0 10M 10000 250 5 6 7 8 9 SUPPLY VOLTAGE (V) LT1286/98 G16 LT1286/98 G13 LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage Minimum Clock Frequency for 0.1 LSB Error vs Temperature 200 1000 150 100 50 0 –55 –35 TA = 25°C 100 LEAKAGE CURRENT (nA) DIGITAL LOGIC THRESHOLD VOLTAGE (V) 3 VCC = VREF = 5V CLOCK FREQUENCY (kHz) Input Channel Leakage Current vs Temperature 2 5 25 45 TEMPERATURE (°C) 65 85 10 ON CHANNEL 1 OFF CHANNEL 0.1 1 –15 VCC = 5V VREF = 5V 3 4 5 6 7 SUPPLY VOLTAGE (V) LT1286/98 • G14 8 9 0.01 – 60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) LTC 1286/98 G17 1196/98 G19 U U U PIN FUNCTIONS LTC1286 LTC1298 VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter. IN + (Pin 2): Positive Analog Input. CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1298. A logic high on this input disables and powers down the LTC1298. IN – (Pin 3): Negative Analog Input. CH0 (Pin 2): Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CH1 (Pin 3): Analog Input. CS/SHDN (Pin 5): Chip Select Input. A logic low on this input enables the LTC1286. A logic high on this input disables and powers down the LTC1286. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer and determines conversion speed. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer and determines conversion speed. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. VCC /VREF (Pin 8): Power Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. 7 LTC1286/LTC1298 W BLOCK DIAGRAM CS/SHDN CLK (DIN) VCC (VCC/V REF) BIAS AND SHUTDOWN CIRCUIT IN + (CH0) CSAMPLE SERIAL PORT DOUT – IN – (CH1) + SAR MICROPOWER COMPARATOR CAPACITIVE DAC VREF GND PIN NAMES IN PARENTHESES REFER TO THE LTC1298 TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 1.4V DOUT VOH DOUT 3k VOL TEST POINT tr 100pF tf LTC1286/98 • TC02 LTC1286/98 • TC01 Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and ten TEST POINT CLK VIL tdDO 3k VCC tdis WAVEFORM 2, ten DOUT DOUT VOH 100pF tdis WAVEFORM 1 VOL LTC1286/98 • TC04 LTC1286/98 • TC03 8 LTC1286/LTC1298 TEST CIRCUITS Voltage Waveforms for tdis VIH CS Voltage Waveforms for ten LTC1286 DOUT WAVEFORM 1 (SEE NOTE 1) CS 90% 1 CLK 2 tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10% B11 DOUT NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. VOL ten LTC1286/98 • TC06 LTC1286/98 • TC05 Voltage Waveforms for ten LTC1298 CS START DIN 1 CLK 2 3 4 B11 DOUT VOL ten LTC1286/98 • TC07 U W U U APPLICATION INFORMATION OVERVIEW while the LTC1298 operates from a 4.5V to 5.5V supply. The LTC1286 and LTC1298 are micropower, 12-bit, successive approximation sampling A/D converters. The LTC1286 typically draws 250µA of supply current when sampling at 12.5kHz while the LTC1298 nominally consumes 350µA of supply current when sampling at 11.1 kHz. The extra 100µA of supply current on the LTC1298 comes from the reference input which is intentionally tied to the supply. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs automatically power down when not performing conversions, drawing only leakage current. They are packaged in 8-pin SO and DIP packages. The LTC1286 operates on a single supply from 4.5V to 9V, Both the LTC1286 and the LTC1298 contain a 12-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). Although they share the same basic design, the LTC1286 and LTC1298 differ in some respects. The LTC1286 has a differential input and has an external reference input pin. It can measure signals floating on a DC common-mode voltage and can operate with reduced spans to 1V. Reducing the spans allows it to achieve 244µV resolution. The LTC1298 has a two-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. The reference input is tied to the supply pin. 9 LTC1286/LTC1298 U W U U APPLICATION INFORMATION SERIAL INTERFACE The 2-channel LTC1298 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. The single channel LTC1286 uses a 3-wire interface (see Operating Sequence in Figures 1 and 2). Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1286 does not require a configuration input word and has no DIN pin. A falling CS initiates data transfer as shown in the LTC1286 operating sequence. After CS falls the second CLK pulse enables DOUT. After one null bit the A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1286 for the next data exchange. The LTC1298 first receives input data and then transmits back the A/D conversion result (half duplex). Because of the half duplex operation, DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls the LTC1298 looks for a start bit. After the start bit is received, the 3-bit input word is shifted into the DIN input which configures the LTC1298 and starts the conversion. After one null bit, the result of the conversion is output on the DOUT line. At the end of the data exchange CS should be brought high. This resets the LTC1298 in preparation for the next data exchange. tCYC CS POWER DOWN tsuCS CLK DOUT HI-Z NULL BIT B11 B10 B9 B8 (MSB) tSMPL B7 B6 B5 B4 B3 B2 B1 tCONV NULL BIT B11 B10 HI-Z B0* B9 B8 tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS tsuCS POWER DOWN CLK DOUT HI-Z NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z (MSB) tSMPL tDATA tCONV *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES. Figure 1. LTC1286 Operating Sequence 10 LTC1286/98 • F01 LTC1286/LTC1298 U W U U APPLICATION INFORMATION CS DIN 1 DIN 2 DOUT 1 DOUT 2 SHIFT MUX ADDRESS IN 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT LTC1096/98 • AI01 MSB-First Data (MSBF = 0) tCYC CS tsuCS POWER DOWN CLK ODD/ SIGN START DIN DON'T CARE MSBF NULL HI-Z BIT SGL/ DIFF DOUT B11 B10 B9 (MSB) tSMPL B8 B6 B7 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z tDATA tCONV MSB-First Data (MSBF = 1) tCYC CS POWER DOWN tsuCS CLK ODD/ SIGN START DIN DON'T CARE SGL/ DIFF DOUT MSBF NULL BIT B11 B10 B9 HI-Z tSMPL (MSB) B8 B7 B6 tCONV B5 B4 B3 B2 B1 HI-Z B0* tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES. LTC1286/98 • F02 Figure 2. LTC1298 Operating Sequence Example: Differential Inputs (CH+, CH–) 11 LTC1286/LTC1298 U W U U APPLICATION INFORMATION Input Data Word The LTC1286 requires no DIN word. It is permanently configured to have a single differential input. The conversion result appears on the DOUT line. The data format is MSB first followed by the LSB sequence. This provides easy interface to MSB or LSB first serial ports. For MSB first data the CS signal can be taken high after B0 (see Figure 1). The LTC1298 clocks data into the DIN input on the rising edge of the clock. The input data words are defined as follows: START SGL/ DIFF ODD/ SIGN MSBF Start Bit GND – – LTC1096/8 • AI03 MSB First/LSB First (MSBF) The output data of the LTC1298 is programmed for MSB first or LSB first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB first format. Logical zeros will be filled in indefinitely following the last data bit. When the 1LSB = VREF 4096 VREF CHANNEL # 0 1 + + + – – + VIN 000000000000 VREF–1LSB LTC1298 Channel Selection 000000000001 VREF–2LSB The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and – signs in the selected row of the following tables. In single-ended mode, all input channels are measured with respect to GND. • • • 1LSB Multiplexer (MUX) Address 12 Transfer Curve 0V The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1298 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. DIFFERENTIAL MUX MODE The LTC1286/LTC1298 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures. 111111111110 LTC1096/9 • AI02 SINGLE-ENDED MUX MODE Transfer Curve 111111111111 MUX MSB FIRST/ ADDRESS LSB FIRST MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 MSBF bit is a logical zero, LSB first data will follow the normal MSB first data on the DOUT line. (see Operating Sequence) LTC1286/98 • AI04 Output Code OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5.000V) 11111111111111 11111111111110 • • • 00000000000001 00000000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.99878V 4.99756V • • • 0.00122V 0V LTC1286/98 • AI05 Operation with DIN and DOUT Tied Together The LTC1298 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1298 will take control of the data line and drive it low on the 4th falling CLK edge after the start bit is received (see Figure 3). Therefore the processor port line must be switched to an input before this happens to avoid a conflict. In the Typical Applications section, there is an example of interfacing the LTC1298 with DIN and DOUT tied together to the Intel 8051 MPU. LTC1286/LTC1298 U W U U APPLICATION INFORMATION MSBF BIT LATCHED BY LTC1298 CS 1 2 3 4 START SGL/DIFF ODD/SIGN MSBF CLK DATA (DIN/DOUT) MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1298 B11 B10 • • • LTC1298 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU PROCESSOR MUST RELEASE DATA LINE AFTER 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK LTC1298 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK LTC1286/98 F03 Figure 3. LTC1298 Operation with DIN and DOUT Tied Together ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 250µA and automatic shutdown between conversions, the LTC1286/LTC1298 achieves extremely low power consumption over a wide range of sample rates (see Figure 4). The auto-shutdown allows the supply curve to drop with reduced sample rate. Several things must be taken into account to achieve such a low power consumption. When the CS pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. The status of the DIN and CLK input have no effect on supply current during this time. There is no need to stop DIN and CLK with CS = high; they can continue to run without drawing current. 1000 SUPPLY CURRENT (µA) input becomes high impedance at the end of each conversion leaving the CLK running to clock out the LSB first data or zeroes (see Figures 1 and 2). If the CS is not running railto-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. TA = 25°C VCC = VREF = 5V fCLK = 200kHz 100 LTC1298 LTC1286 10 Minimize CS Low Time 1 0.1k 1k 10k SAMPLE RATE (kHz) 100k LT1286/98 G03 Figure 4. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate. Shutdown The LTC1286/LTC1298 are equipped with automatic shutdown features. They draw power when the CS pin is low and shut down completely when that pin is high. The bias circuit and comparator powers down and the reference In systems that have significant time between conversions, lowest power drain will occur with the minimum CS low time. Bringing CS low, transferring data as quickly as possible, and then bringing it back high will result in the lowest current drain. This minimizes the amount of time the device draws power. After a conversion the ADC automatically shuts down even if CS is held low (see Figures 1 and 2). If the clock is left running to clock out LSB-data or zero, the logic will draw a small current. Figure 5 shows that the typical supply current with CS = ground varies from 1µA at 1kHz to 35µA at 200kHz. When CS = VCC, the logic is gated off and no supply current is drawn regardless of the clock frequency. 13 LTC1286/LTC1298 U W U U APPLICATION INFORMATION Clock Frequency 35 TA = 25°C VCC = VREF = 5V SUPPLY CURRENT (µA) 30 25 20 15 CS = 0 (AFTER CONVERSION) 10 5 1 0.002 The maximum recommended clock frequency is 200kHz for the LTC1286/LTC1298 running off a 5V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of Maximum Clock Rate vs Supply Voltage). If the maximum clock frequency is used, care must be taken to ensure that the device converts correctly. CS = VCC 0 1 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) LT1286/98 G01 Figure 5. Shutdown current with CS high is 1nA typically, regardless of the clock. Shutdown current with CS = ground varies from 1µA at 1kHz to 35µA at 200kHz. DOUT Loading Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the DOUT pin can add more than 50µA to the supply current at a 200kHz clock frequency. An extra 50µA or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C × V × f currents must be evaluated and the troublesome ones minimized. OPERATING ON OTHER THAN 5V SUPPLIES (LTC1286) The LTC1286 operates from 4.5V to 9V supplies and the LTC1298 operates from a 5V supply. To operate the LTC1286 on other than 5V supplies a few things must be kept in mind. Mixed Supplies It is possible to have a microprocessor running off a 5V supply and communicate with the LTC1286 operating on a 9V supply. The requirement to achieve this is that the outputs of CS and CLK from the MPU have to be able to trip the equivalent inputs of the LTC1286 and the output of DOUT from the LTC1286 must be able to toggle the equivalent input of the MPU (see typical curve of Digital Input Logic Threshold vs Supply Voltage). With the LTC1286 operating on a 9V supply, the output of DOUT may go between 0V and 9V. The 9V output may damage the MPU running off a 5V supply. The way to get around this possibility is to have a resistor divider on DOUT (Figure 6) and connect the center point to the MPU input. It should be noted that to get full shutdown, the CS input of the LTC1286 must be driven to the VCC voltage to keep the CS input buffer from drawing current. An alternative is to leave CS low after a conversion, clock data until DOUT outputs zeros, and then stop the clock low. 9V 4.7µF MPU (e.g. 8051) Input Logic Levels 5V The input logic levels of CS, CLK and DIN are made to meet TTL on a 5V supply. When the supply voltage varies, the input logic levels also change. For the LTC1286 to sample and convert correctly, the digital inputs have to be in the proper logical low and high levels relative to the operating supply voltage (see typical curve of Digital Input Logic Threshold vs Supply Voltage). If achieving micropower consumption is desirable, the digital inputs must go rail-torail between supply voltage and ground (see ACHIEVING MICROPOWER PERFORMANCE section). 14 DIFFERENTIAL INPUTS COMMON-MODE RANGE 0V TO 5V VREF VCC +IN CLK –IN DOUT GND CS 5V P1.4 P1.3 50k P1.2 50k LTC1286 LTC1286/98 • F06 Figure 6. Interfacing a 9V Powered LTC1286 to a 5V System LTC1286/LTC1298 U W U U APPLICATION INFORMATION BOARD LAYOUT CONSIDERATIONS SAMPLE-AND-HOLD Grounding and Bypassing Both the LTC1286 and the LTC1298 provide a built-in sample-and-hold (S&H) function to acquire signals. The S&H of the LTC1286 acquires input signals from “+” input relative to “–” input during the tSMPL time (see Figure 1). However, the S&H of the LTC1298 can sample input signals in the single-ended mode or in the differential inputs during the tSMPL time (see Figure 7). The LTC1286/LTC1298 are easy to use if some care is taken. They should be used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 10µF tantalum capacitor with leads as short as possible. If the power supply is clean, the LTC1286/LTC1298 can also operate with smaller 1µF or less surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. Single-Ended Inputs The sample-and-hold of the LTC1298 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. SAMPLE HOLD "+" INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV CLK DIN START SGL/DIFF MSBF DOUT DON'T CARE B11 1ST BIT TEST "–" INPUT MUST SETTLE DURING THIS TIME "+" INPUT "–" INPUT LTC1096/8 • F07 Figure 7. LTC1298 “+” and “–” Input Settling Windows 15 LTC1286/LTC1298 U W U U APPLICATION INFORMATION Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 12 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input this error would be: VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 12/fCLK Where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. In most cases VERROR will not be significant. For a 60Hz signal on the “–” input to generate a 1/4LSB error (305µV) with the converter running at CLK = 200kHz, its peak value would have to be 13.48mV. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1286/ LTC1298 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. sample time can be increased by using a slower CLK frequency. “–” Input Settling At the end of the tSMPL, the input capacitor switches to the “–” input and conversion starts (see Figures 1 and 7). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settles completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– and C2 will improve settling time. If a large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 7). Again, the“+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps, including the LT1006 and LT1413 single supply op amps, can be made to settle well even with the minimum settling windows of 6µs (“+” input) which occur at the maximum clock rate of 200kHz. Source Resistance The analog inputs of the LTC1286/LTC1298 look like a 20pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 8. CIN gets switched between the selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances “+” Input Settling The input capacitor of the LTC1286 is switched onto “+” input during the tSMPL time (see Figure 1) and samples the input signal within that time. However, the input capacitor of the LTC1298 is switched onto “+” input during the sample phase (tSMPL, see Figure 7). The sample phase is 1 1/2 CLK cycles before conversion starts. The voltage on the “+” input must settle completely within tSMPLE for the LTC1286 and the LTC1298 respectively. Minimizing RSOURCE+ and C1 will improve the input settling time. If a large “+” input source resistance must be used, the 16 RSOURCE + “+” INPUT LTC1286/98 VIN + C1 RSOURCE – “–” INPUT RON = 500Ω CIN = 20pF VIN – C2 LTC1286/98 • F08 Figure 8. Analog Input Equivalent Circuit LTC1286/LTC1298 U W U U APPLICATION INFORMATION will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. converter, the reference input should be driven by a reference with low ROUT (ex. LT1004, LT1019 and LT1021) or a voltage source with low ROUT. RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 9. For large values of CF (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 20pF × VIN /tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 64µs, the input current equals 1.56µA at VIN = 5V. In this case, a filter resistor of 75Ω will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. RFILTER IDC “+” VIN CFILTER LTC1286 “–” LTC1286/98 • F09 Figure 9. RC Input Filtering Input Leakage Current Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 240Ω will cause a voltage drop of 240µV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of Input Channel Leakage Current vs Temperature). REFERENCE INPUTS The reference input of the LTC1286 is effectively a 50kΩ resistor from the time CS goes low to the end of the conversion. The reference input becomes a high impedence node at any other time (see Figure 10). Since the voltage on the reference input defines the voltage span of the A/D REF+ 1 LTC1286 ROUT VREF GND 4 LTC1286/98 • F10 Figure 10. Reference Input Equivalent Circuit Reduced Reference Operation The minimum reference voltage of the LTC1298 is limited to 4.5V because the VCC supply and reference are internally tied together. However, the LTC1286 can operate with reference voltages below 1V. The effective resolution of the LTC1286 can be increased by reducing the input span of the converter. The LTC1286 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Change in Linearity vs Reference Voltage and Change in Gain vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise 3. Conversion speed (CLK frequency) Offset with Reduced VREF The offset of the LTC1286 has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.1LSB with a 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 17 LTC1286/LTC1298 U W U U APPLICATION INFORMATION Noise with Reduced VREF The total input referred noise of the LTC1286 can be reduced to approximately 400µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the 400µV noise is only 0.33LSB peak-to-peak. In this case, the LTC1286 noise will contribute virtually no uncertainty to the output code. However, for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 2.5V reference this same 400µV noise is 0.66LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400µV noise becomes equal to 1.65LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. tortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1286 plot. 0 TA = 25°C VCC = VREF = 5V fIN = 5kHz fCLK = 200kHz fSMPL = 12.5kHz –20 MAGNITUDE (dB) 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input of the LTC1286. –40 –60 –80 –100 –120 –140 0 1 2 4 3 5 FREQUENCY (kHz) 6 7 LTC 1286/98 G21 Figure 11. LTC1286 Non-Averaged, 4096 Point FFT Plot Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio (S/N + D) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC’s output. The output is band limited to frequencies above DC and below one half the sampling frequency. Figure 12 shows a typical spectral content with a 12.5kHz sampling rate. Effective Number of Bits Conversion Speed with Reduced VREF With reduced reference voltages, the LSB step size is reduced and the LTC1286 internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of VREF are used. DYNAMIC PERFORMANCE The LTC1286/LTC1298 have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are used to characterize the ADC’s frequency response, dis- 18 The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N+D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 12.5kHz with a 5V supply, the LTC1286 maintains above 11 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in Figure 12, due to increasing second harmonic distortion. The noise floor remains low. LTC1286/LTC1298 U W U U EFFECTIVE NUMBER OF BITS (ENOBs) APPLICATION INFORMATION 12 11 74 68 10 9 62 56 8 50 7 44 6 38 5 4 3 TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz 2 1 0 1 10 100 INPUT FREQUENCY (kHz) 1000 LTC 1286/98 G20 Figure 12. Effective Bits and S/(N + D) vs Input Frequency Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is defined as: THD = 20log If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine waves are equal in magnitudes, the value (in dB) of the 2nd order IMD products can be expressed by the following formula: V22 + V32 + V42 + ... + VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through the Nth harmonics. The typical THD specification in the Dynamic Accuracy table includes the 2nd through 5th harmonics. With a 7kHz input signal, the LTC1286/LTC1298 have typical THD of 80dB with VCC = 5V. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. ( ) amplitude fa ± fb IMD fa ± fb = 20log amplitude at fa ( ) For input frequencies of 5kHz and 6kHz, the IMD of the LTC1286/LTC1298 is 73dB with a 5V supply. Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a fullscale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input. The full-linear bandwidth is the input frequency at which the effective bits rating of the ADC falls to 11 bits. Beyond this frequency, distortion of the sampled input signal increases. The LTC1286/LTC1298 have been designed to optimize input bandwidth, allowing the ADCs to undersample input signals with frequencies above the converters’ Nyquist Frequency. 19 LTC1286/LTC1298 U TYPICAL APPLICATIONS N MICROPROCESSOR INTERFACES The LTC1286/LTC1298 can interface directly without external hardware to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then 3 or 4 of the MPU's parallel port lines can be programmed to form the serial link to the LTC1286/LTC1298. Included here is one serial interface example and one example showing a parallel port programmed to form the serial interface. Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB -first and in 8-bit increments. The DIN word sent to the data register starts with the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. The data is right justified into two memory locations. ANDing the second byte with OFHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. MC68HC11 Code In this example the DIN word configures the input MUX for a single-ended input to be applied to CHO. The conversion result is output MSB-first. 20 Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1286/LTC1298 PART NUMBER TYPE OF INTERFACE Motorola MC6805S2,S3 MC68HC11 MC68HC05 SPI SPI SPI RCA CDP68HC05 SPI Hitachi HD6305 HD63705 HD6301 HD63701 HD6303 HD64180 SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous CSI/O National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family MICROWIRE † MICROWIRE/PLUS† MICROWIRE/PLUS† MICROWIRE/PLUS† Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020 Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port Intel 8051 Bit Manipulation on Parallel Port * Requires external hardware † MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corp. LTC1286/LTC1298 U TYPICAL APPLICATIONS N Timing Diagram for Interface to the MC68HC11 CS CLK DIN START SGL/ DIFF ODD/ SIGN MSBF DON'T CARE DOUT MPU TRANSMIT WORD 0 0 0 0 0 0 0 SGL/ DIFF 1 ODD/ SIGN MSBF ? ? ? ? ? B10 B9 B8 X X X X X B7 X B6 B5 B4 B3 B2 B1 B0 X X X X X X X B2 B1 B0 BYTE 2 BYTE 1 MPU RECEIVED WORD B11 ? ? ? ? ? 0 ? BYTE 3 (DUMMY) B11 B10 B9 B8 B7 B6 BYTE 2 BYTE 1 B5 B3 B4 BYTE 3 LTC1286/98 AI06 Hardware and Software Interface to the MC68HC11 DOUT FROM LTC1298 STORED IN MC68HC11 RAM MSB #62 0 0 0 0 B11 B10 B9 B8 ANALOG INPUTS LSB #63 B7 B6 B5 B4 CH0 BYTE 1 B3 B2 B1 B0 CS D0 CLK SCK LTC1298 DOUT BYTE 2 CH1 DIN MC68HC11 MISO MOSI LTC1286/98 AI07 LABEL MNEMONIC LDAA STAA LDAA STAA LDAA STAA LDAA STAA LDAA LOOP OPERAND #$50 $1028 #$1B $1009 #$01 $50 #$A0 $51 #$00 STAA LDX $52 #$1000 BCLR LDAA STAA LDAA $08,X,#$01 $50 $102A $1029 COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $50 LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $51 LOAD DUMMY DIN WORD INTO ACC A LOAD DUMMY DIN DATA INTO $52 LOAD INDEX REGISTER X WITH $1000 D0 GOES LOW (CS GOES LOW) LOAD DIN INTO ACC A FROM $50 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG LABEL MNEMONIC WAIT1 BPL LDAA STAA WAIT2 LDAA BPL LDAA STAA LDAA STAA WAIT3 LDAA BPL BSET LDAA STAA JMP OPERAND WAIT1 $51 $102A $1029 WAIT2 $102A $62 $52 $102A $1029 WAIT3 $08,X#$01 $102A $63 LOOP COMMENTS CHECK IF TRANSFER IS DONE LOAD DIN INTO ACC A FROM $51 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1291 MSBs INTO ACC A STORE MSBs IN $62 LOAD DUMMY INTO ACC A FROM $52 LOAD DUMMY DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE DO GOES HIGH (CS GOES HIGH) LOAD LTC1291 LSBs IN ACC STORE LSBs IN $63 START NEXT CONVERSION 21 LTC1286/LTC1298 U TYPICAL APPLICATIONS N Interfacing to the Parallel Port of the INTEL 8051 Family LABEL The Intel 8051 has been chosen to demonstrate the interface between the LTC1298 and parallel port microprocessors. Normally the CS, CLK and DIN signals would be generated on 3 port lines and the DOUT signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and DOUT of the LTC1298 tied together as described in the SERIAL INTERFACE section. This saves one wire. LOOP 1 LOOP 2 The 8051 first sends the start bit and MUX address to the LTC1298 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 12-bit A/D result over the same data line. ANALOG INPUTS LTC1298 CS CLK DOUT DIN P1.4 P1.3 P1.2 LOOP 3 8051 MUX ADDRESS LOOP 4 A/D RESULT LTC1286/98 TA01 MNEMONIC OPERAND COMMENTS MOV SETB CLR MOV RLC CLR MOV SETB DJNZ MOV CLR MOV MOV RLC SETB CLR DJNZ MOV CLR MOV MOV RLC SETB CLR DJNZ MOV RRC DJNZ MOV SETB A, #FFH P1.4 P1.4 R4, #04 A P1.3 P1.2, C P1.3 R4, LOOP 1 P1, #04 P1.3 R4, #09 C, P1.2 A P1.3 P1.3 R4, LOOP 2 R2, A A R4, #04 C, P1.2 A P1.3 P1.3 R4, LOOP 3 R4, #04 A R4, LOOP 4 R3, A P1.4 DIN word for LTC1298 Make sure CS is high CS goes low Load counter Rotate DIN bit into Carry SCLK goes low Output DIN bit to LTC1298 SCLK goes high Next bit Bit 2 becomes an input SCLK goes low Load counter Read data bit into Carry Rotate data bit into Acc. SCLK goes high SCLK goes low Next bit Store MSBs in R2 Clear Acc. Load counter Read data bit into Carry Rotate data bit into Acc. SCLK goes high SCLK goes low Next bit Load counter Rotate right into Acc. Next Rotate Store LSBs in R3 CS goes high DOUT FROM 1298 STORED IN 8501 RAM MSB R2 B11 B10 B9 B8 B7 B6 B5 B4 LSB R3 B3 B2 B1 B0 0 0 0 0 MSBF BIT LATCHED INTO LTC1298 CS CLK DATA (DIN/DOUT) START SGL/ DIFF ODD/ SIGN 8051 P1.2 OUTPUTS DATA TO LTC1298 8051 P1.2 RECONFIGURED AS IN INPUT AFTER THE 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK 22 MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1298 SENDS A/D RESULT BACK TO 8051 P1.2 LTC1298 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK LTC1286/98 TA02 LTC1286/LTC1298 U TYPICAL APPLICATIONS N A “Quick Look” Circuit for the LTC1286 Users can get a quick look at the function and timing of the LT1286 by using the following simple circuit (Figure 13). VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground. CS is driven at 1/16 the clock rate by the 74C161 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 14). Note the LSB data is partially clocked out before CS goes high. 4.7µF VREF VIN 5V +IN CLK LTC1286 –IN DOUT CS GND 5V CLR VCC CLK RC A QA B QB 74C161 C QC D QD P T GND LOAD VCC Micropower Battery Voltage Monitor A common problem in battery systems is battery voltage monitoring. This circuit monitors the 10 cell stack of NiCad or NiMH batteries found in laptop computers. It draws only 67µA from the 5V supply at fSMPL = 0.1kHz and 25µA to 55µA from the battery. The 12-bits of resolution of the LTC1286 are positioned over the desired range of 8V to 16V. This is easily accomplished by using the ADC’s differential inputs. Tying the –input to the reference gives an ADC input span of VREF to 2VREF (2.5V to 5V). The resistor divider then scales the input voltage for 8V to 16V. BATTERY MONITOR INPUT 8V TO 16V 5V 0.1µF 200k 39k VCC +IN CS LTC1286 DOUT –IN CLOCK IN 250kHz 91k 1µF CLK VREF GND LT1004-2.5 3Ω TO OSCILLOSCOPE LTC1286/98 F13 Figure 13. “Quick Look” Circuit for the LTC1286 LTC1286/98 F15 Figure 15. Micropower Battery Voltage Monitor NULL BIT MSB (B11) LSB (B0) VERTICAL: 5V/DIV HORIZONTAL: 10µs/DIV LTC1286/98 F14 Figure 14. Scope Trace the LTC1286 “Quick Look” Circuit Showing A/D Output 101010101010 (AAAHEX) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 23 LTC1286/LTC1298 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.300 – 0.320 (7.620 – 8.128) 0.045 – 0.065 (1.143 – 1.651) 0.400 (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 8 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 8.255 +0.635 –0.381 ) 7 6 5 0.065 (1.651) TYP 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 0.250 ± 0.010 (6.350 ± 0.254) 0.020 (0.508) MIN 1 2 4 3 0.018 ± 0.003 (0.457 ± 0.076) S8 Package 8-Lead Plastic SOIC 0.189 – 0.197* (4.801 – 5.004) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 8 7 6 5 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC 0.150 – 0.157* (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 2 3 4 SO8 0294 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 24 Linear Technology Corporation LT/GP 0394 10K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1994