3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® 89#589.ð;245;.ð49#&026#)ODVK#((3520 )HDWXUHV • Organization: 256K×8 or 128K×16 • Sector architecture - One 16K; two 8K; one 32K; and three 64K byte sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 5.0±0.5V power supply for read/write operations • Sector protection • High speed 55/70/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorith - Automatically preprograms/erases chip or specified sectors • 10,000 write/erase cycle endurance • Hardware RESET pin - Resets internal state machine to read mode • Low power consumption - 20 mA typical read current - 30 mA typical program current - 300 µA typical standby current - 1 µA typical standby current (RESET = 0) • JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output • Erase suspend/resume - Supports reading data from a sector not being erased • Low VCC write lock-out below 2.8V /RJLF#EORFN#GLDJUDP 3LQ#DUUDQJHPHQW 48-pin TSOP VSS Input/output buffers Program/erase control Program voltage generator AS29F200 Chip enable Output enable Logic CE OE A-1 STB Timer Data latch Y decoder Y gating X decoder Cell matrix 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC detector STB A0–A16 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 NC RY/BY NC A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC 6HOHFWLRQ#JXLGH 29F200-55 29F200-70 29F200-90 29F200-120 Unit Maximum access time tAA 55 70 90 120 ns Maximum chip enable access time tCE 55 70 90 120 ns Maximum output enable access time tOE 25 30 35 50 ns ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 4 Copyright ©1998 Alliance Semiconductor. All rights reserved. )/$6+ Command register Address latch WE BYTE Erase voltage generator 44-pin SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RESET DQ0–DQ15 AS29F200 VCC Sector protect switches A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC NC A7 A6 A5 A4 A3 A2 A1 RY/BY 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® )XQFWLRQDO#GHVFULSWLRQ The AS29F200 is a 2 megabit, 5 volt only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. For flexible erase and program capability, the 2 megabits of data is divided into 7 sectors: one 16K byte, two 8K byte, one 32K byte, and three 64K bytes. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29F200 is offered in JEDEC standard 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V V CC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29F200 offers access times of 55/70/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable ( WE), and output enable ( OE) controls. Word mode (×16 output) is selected by BYTE = High. The AS29F200 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. Boot sector architecture enables the device to boot from either the top (AS29F200T) or bottom (AS29F200B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically eras es and verifies within 1.6 seconds. Hardware sector protection disables both program and erase operations in all or any combination of the seven sectors. The device provides background erase with Erase Suspend, which puts erase operations on hold to read data from a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29F200 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte/word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes/ words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 5.0V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically resets to the read mode after program/erase operations are completed. )/$6+ The AS29F200 resists accidental erasure or spurious programming signals resulting from power transitions. Control register archi tecture permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program/erase commands disabled when VCC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands. When the device’s hardware RESET pin is driven low, any program/erase operation in progress will be terminated and the internal state machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated onchip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory. The AS29F200 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/words are programmed one at a time using EPROM programming mechanism of hot electron injection. 5 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® )OH[LEOH#VHFWRU#DUFKLWHFWXUH Bottom boot sector architecture (AS29F200B) Top boot sector architecture (AS29F200T) Sector ×8 ×16 Size (Kbytes) ×8 ×16 Size (Kbytes) 0 00000h–03FFFh 00000h–01FFFh 16 00000h–0FFFFh 00000h–07FFFh 64 1 04000h–05FFFh 02000h–02FFFh 8 10000h–1FFFFh 08000h–0FFFFh 64 2 06000h–07FFFh 03000h–03FFFh 8 20000h–2FFFFh 10000h–17FFFh 64 3 08000h–0FFFFh 04000h–07FFFh 32 30000h–37FFFh 18000h–1BFFFh 32 4 10000h–1FFFFh 08000h–0FFFFh 64 38000h–39FFFh 1C000h–1CFFFh 8 5 20000h–2FFFFh 10000h–17FFFh 64 3A000h–3BFFFh 1D000h–1DFFFh 8 6 30000h–3FFFFh 18000h–1FFFFh 64 3C000h–3FFFFh 1E000h–1FFFFh 16 In word mode, there are one 8K word, two 4K word, one 16K word, and three 32K word sectors. Address range is A16–A-1 if BYTE = VIL; address range is A16–A0 if BYTE = VIH. ,'#6HFWRU#DGGUHVV#WDEOH Bottom boot sector address (AS29F200B) Top boot sector address (AS29F200T) Sector A16 A15 A14 A13 A12 A16 A15 A14 A13 A12 0 0 0 0 0 X 0 0 X X X 1 0 0 0 1 0 0 1 X X X 2 0 0 0 1 1 1 0 X X X 3 0 0 1 X X 1 1 0 X X 4 0 1 X X X 1 1 1 0 0 5 1 0 X X X 1 1 1 0 1 6 1 1 X X X 1 1 1 1 X Mode CE OE WE A0 A1 A6 A9 RESET DQ ID read MFR code L L H L L L VID H Code ID read device code L L H H L L VID H Code Read L L H A0 A1 A6 A9 H DOUT Standby H X X X X X X H High Z Output disable L H H X X X X H High Z Write L H L A0 A1 A6 A9 H DIN Enable sector protect L VID Pulse/L L H L VID H X Sector unprotect L VID Pulse/L L H H VID H X Verify sector protect L L H L H L VID H Code Temporary sector unprotect X X X X X X X VID X Hardware Reset X X X X X X X L High Z )/$6+ 2SHUDWLQJ#PRGHV L = Low (<VIL); H = High (>VIH); VID = 12.0 ± 0.5V; X = don’t care; In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL and DQ8–14 is High Z with DQ15 = A-1(X). ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 6 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® 0RGH#GHILQLWLRQV Item Description ID MFR code, device code Selected by A9 = VID(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29F200. Read mode Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Standby Selected with CE = H. Part is powered down, and ICC reduced to <2.0 mA for TTL input levels. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. )/$6+ Output disable Part remains powered up; but outputs disabled with OE pulled high. Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Enable sector protect Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. Sector unprotect Disables sector protection for all sectors using external programming equipment. All sectors must be protected prior to sector unprotection. Verify sector protect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12–16 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Temporary sector unprotect Temporarily disables sector protection for in-system data changes to protected sectors. Apply +12V to RESET to activate sector unprotect mode. During temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +12V from RESET. RESET Resets the write and erase state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted. Deep power down Hold RESET low to enter deep power down mode (<10 µA CMOS). Recovery time to active mode is 1.5 µs. 5($'#FRGHV Mode A16–A12 A6 A1 A0 Code MFR code (Alliance Semiconductor) X L L L 52h ×8 T boot X L L H 51h ×8 B boot X L L H 57h ×16 T boot X L L H 2251h ×16 B boot X L L H 2257h Sector address L H L 01h protected 00h unprotected Device code Sector protection Key: L =Low (<VIL); H = High (>VIH); X =Don’t care; T = top; B = botto 7 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® :ULWH#RSHUDWLRQ#VWDWXV Status DQ7 DQ6 DQ5 DQ3 DQ2 Auto programming (byte/word) DQ7 Toggle 0 0 No toggle Program/erase in auto erase In progress Erase suspend mode 0 † 0 Toggle 0 1 Toggle Read erasing sector 1 No toggle 0 0 Toggle 1 Read non-erasing sector Data Data Data Data Data 1 Program in erase suspend DQ7 Toggle 0 0 Toggle† 0 DQ7 Toggle 1 NA No toggle 1 Auto programming (byte/word) Exceeded time limits RY/BY Program/erase in auto erase Program in erase suspend 0 DQ7 Toggle Toggle 1 1 1 NA Toggle 0 ‡ No toggle 1 ‡ 1 †Toggles with OE or CE only for erasing or erase suspended sector addresses. ‡Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits. DQ8–DQ15 = Don’t care in ×16 mode. &RPPDQG#GHILQLWLRQV Item Description Reset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29F200 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +12V on A9. AS29F200 also contains an ID read command to read the device code with only +5V, since multiplexing +12V on address lines is generally undesirable. Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XX00h to return MFG code. Follow ID read command sequence with a read sequence from address XX01h to return device code. To verify write protect status on sectors, read address XX02h. Sector addresses A16–A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Hardware Reset ','#4407333<0$1#72:233 Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a delay of 1.5 µs for the device to permit read operations. $//,$1&(#6(0,&21'8&725 8 )/$6+ ID Read 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® Item Description Programming the AS29F200 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE (whichever is last); data is latched on the rising edge of CE or WE, (whichever is first). The AS29F200’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word Programming Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), or RY/ BY pin. The AS29F200 returns the equivalent data that was written to it (as opposed to complemented data), to complete the programming operation. The AS29F200 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29F200 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded programming time limits); reading this data after a Read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a reset command returns the device to read mode. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase Chip erase does not require logical 0s written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29F200 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. )/$6+ Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Determine the sector to be erased by addressing any location in the sector. This address is latched on the falling edge of WE; the command, 30H is latched on the rising edge of WE. The sector erase operation begins after a 80 µs time-out. Sector Erase To erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be <80 µs, or the AS29F200 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out resets the AS29F200 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29F200 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29F200 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29F200 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. 9 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® Item Description Erase suspend allows interruption of sector erase operations to perform data reads from a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of time-out period and suspension of erase operation. AS29F200 ignores any commands during erase suspend other than the Reset or Erase Resume commands. Writing erase resume continues erase operations. Addresses are DON’T CARE when writing Erase Suspend or Erase Resume commands. Erase Suspend AS29F200 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command. Check completion of erase suspend by polling RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F200 ignores redundant writes of erase suspend. AS29F200 defaults to erase-suspend-read mode while an erase operation has been suspended. While in erase-suspend-read mode AS29F200 allows reading data from or programming data to any sector not undergoing sector erase. Write the Resume command 30h to continue operation of sector erase. AS29F200 ignores redundant writes of the Resume command. AS29F200 permits multiple suspend/resume operations during sector erase. Sector Protect When attempting to write to a protected sector, DATA polling andToggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors. Ready/Busy RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept program/erase commands when RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. 6WDWXV#RSHUDWLRQV Toggle bit (DQ6) Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for only <1 µs during writes, and <5 µs during erase (if all selected sectors are protected). Exceeding time limit (DQ5) Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming, the entire sector is defective; during sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1. ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 : )/$6+ DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip algorithm (1 after completion of erase agorithm). 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® Sector erase timer (DQ3) Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each sector erase command to verify that the command was accepted. Toggle bit 2 (DQ2) During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. &RPPDQG#IRUPDW Command sequence Reset/Read 2nd bus 1st bus write cycle write cycle Required bus cycles Address Data Address Data 1 ×16 5555h Address Data F0h Address 2AAAh 5555h AAAAh Read Address Read Data ×16 5555h 2AAAh 5555h 01h 2251h (T) 2257h (B) ×8 AAAAh 5555h AAAAh 02h 51h (T) 57h (B) ×16/×8 00h MFR code 52h ×16 XXX02h ×8 XXX04h 01 = protected 00 = unprotected Program Address Program Data AAh 4 5555h 4 ×8 5555h Sector Erase Suspend 1 XXXXh B0h Sector Erase Resume 1 XXXXh 30h Address Data 55h 5555h 10h AAAAh 2AAAh AAh AAAAh 5555h 55h 5555h 5555h 80h AAAAh 2AAAh AAh AAAAh 5555h 55h 5555h 5555h 80h AAAAh 2AAAh AAh AAAAh A0h 55h 5555h 5555h ×8 5555h AAAAh 2AAAh AAh 6 90h 55h 5555h AAAAh ×16 Sector Erase 2AAAh 5555h 6 ×8 55h AAh AAAAh ×16 Chip Erase 55h AAh Data 6th bus write cycle Read Data 5555h ×16 1 2 3 4 5 6 Read Address Data 5th bus write cycle AAAAh 4 Program )/$6+ F0h Address 4th bus read/write cycle ×8 Reset/Read Autoselect ID Read XXXXh 3rd bus write cycle Sector Address 30h Bus operations defined in "Mode definitions," on page 4. Reading data from or programming data to non-erasing sectors allowed in Erase Suspend mode. Address bit A15 = X = Don’t care for all address commands except Program Address and Sector Address. Address bit A16 = X = Don’t care for all address commands except Program Address and Sector Address. System should generate address patterns: ×16 mode - 5555h or 2AAAh to address A0–A14; ×8 mode - AAAAh or 5555h to address A-1–A14. A0 = 0, A1 = 1, A6 = 0 for sector protect verify; sector selected on A16-A12. ; $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® $XWRPDWHG#RQ0FKLS#SURJUDPPLQJ#DOJRULWKP $XWRPDWHG#RQ0FKLS#HUDVH#DOJRULWKP Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA poll device Erase complete Chip erase command sequence ×16 mode (address/command): Sector erase command sequence ×16 mode (address/command): 5555h/AAh 5555h/AAh Programming completed 2AAAh/55h 2AAAh/55h Program command sequence ×16 mode (address/command): 5555h/80h 5555h/80h 5555h/AAh 5555h/AAh 2AAAh/55h 2AAAh/55h 5555h/10h Sector address/30h Verify byte? NO YES 5555h/AAh 2AAAh/55h Program address/program data )/$6+ 5555h/A0h Sector address/30h Optional multiple sector erase commands† Sector address/30h † ','#4407333<0$1#72:233 The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. $//,$1&(#6(0,&21'8&725 < $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® '$7$#SROOLQJ#DOJRULWKP 7RJJOH#ELW#DOJRULWKP Read byte (DQ0–DQ7) Address = VA† Read byte (DQ0–DQ7) Address = don’t care DQ7 = data ? DQ6 = toggle ? YES DONE NO NO DQ5 = 1 ? NO Read byte (DQ0–DQ7) Address = VA Read byte (DQ0–DQ7) Address = don’t care DQ7 = data‡ ? DQ6 = toggle† ? YES† DONE NO DONE YES FAIL )/$6+ DQ5 = 1 ? YES NO† FAIL VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. ‡ DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. 43 DONE YES YES † NO †DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® 7HPSRUDU\#VHFWRU#XQSURWHFW Parameter Symbol All speeds Unit VID rise and fall time tVIDR 500 (min) ns RESET# setup time for temporary sector unprotect tRSP 4 (min) µs 7HPSRUDU\#VHFWRU#XQSURWHFW#ZDYHIRUP# RESET CE Program/erase command sequence tVIDR 10V 0 or 1.8V tVIDR WE tRSP RY/BY '&#HOHFWULFDO#FKDUDFWHULVWLFV 9&&# #813±3189 Symbol Test conditions Min Max Unit Input load current ILI VIN = VSS to VCC, VCC = VCCMAX - ±1 µA A9 Input load current ILIT VCC = VCCMAX, A9 = 12.5V 90 µA ILO VOUT = VSS to VCC, VCC = VCCMAX - ±1 µA IOS VOUT = 0.5V - 200 mA ICC CE = VIL, OE = VIH - 40 mA Active current, program/erase ICC2 CE = VIL, OE = VIH - 60 mA Standby current (TTL compatible) ISB1 CE = OE = VIH, VCC = VCCMAX - 400 µA Deep power down ISB2 RP = 0V - 1 µA Input low voltage VIL -0.5 0.8 V Input high voltage VIH 2.0 VCC + 0.3 V Output low voltage VOL IOL = 5.8mA, VCC = VCC MIN - 0.45 V VOH1 IOH = -2.5 mA, VCC = VCC MIN 2.4 - V VOH2 IOH = -100 µA, VCC = VCC MIN VCC - 0.4 - V Output leakage current Output short circuit current 1 2 Active current, read @ 6MHz 3 Output high level Low VCC lock out voltage VLKO 2.8 4.2 V Input HV select voltage Vh 11.5 12.5 V 1 2 3 )/$6+ Parameter Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.) The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is less than 2 mA/MHz with OE at VIH. ICC active while program or erase operations are in progress. .H\#WR#VZLWFKLQJ#ZDYHIRUPV Rising input ','#4407333<0$1#72:233 Falling input Undefined output/don’t care $//,$1&(#6(0,&21'8&725 44 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® 0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP 20 ns 20 ns 20 ns +0.8V -0.5V -2.0V 0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP VCC+2.0V VCC+0.5V +2.0V 20 ns 20 ns 20 ns $&#SDUDPHWHUV=#UHDG#F\FOH -70 -90 -120 Parameter Min Max Min Max Min Max Min Max Unit tAVAV tRC Read cycle time 55 - 70 - 90 - 120 - ns tAVQV tACC Address to output delay - 55 - 70 - 90 - 120 ns tELQV tCE Chip enable to output - 55 - 70 - 90 - 120 ns tGLQV tOE Output enable to output - 25 - 30 - 35 - 50 ns tEHQZ tDF Chip enable to output High Z - 15 - 20 - 20 - 30 ns tGHQZ tDF Output enable to output High Z - 15 - 20 - 20 - 30 ns tAXQX tOH Output hold time from addresses, first occurrence of CE or OE 0 - 0 - 0 - 0 - ns tELFL/ELFH CE to BYTE transition low/high - 5 - 5 - 5 - 5 ns tPWH RESET high to output delay - 1.5 - 1.5 - 1.5 - 1.5 µs tBDEL BYTE switching to valid data - 55 - 70 - 90 - 120 ns tFLQZ BYTE low to DQ8–DQ15 tri-state 30 - 30 - 35 - 50 - ns tPHQV )/$6+ -55 JEDEC Std Symbol Symbol 5HDG#ZDYHIRUP tRC Addresses stable Addresses tACC CE tDF tOE OE tOEH WE Outputs BYTE tOH tCE High Z Output valid High Z tELFL/ELFH tBDEL tPWH RESET 45 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® $&#SDUDPHWHUV#³#ZULWH#F\FOH :(#FRQWUROOHG -55 -70 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - ns tAVWL tAS Address setup time 0 - 0 - 0 - 0 - ns tWLAX tAH Address hold time 40 - 45 - 45 - 50 - ns tDVWH tDS Data setup time 25 - 30 - 45 - 50 - ns tWHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tOES Output enable setup time 0 - 0 - 0 - 0 - ns Output enable hold time: Read 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: Toggle and DATA polling 10 - 10 - 10 - 10 - ns tREADY RESET pin low to read mode 20 - 20 - 20 - 20 - µs tRP RESET 500 - 500 - 500 - 500 - ns tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - ns tELWL tCS CE setup time 0 - 0 - 0 - 0 - ns tWHEH tCH CE hold time 0 - 0 - 0 - 0 - ns tWLWH tWP Write pulse width 35 - 35 - 45 - 50 - ns tWHWL tWPH Write pulse width high 20 - 20 - 20 - 20 - ns tWHWH1 tWHWH1 Programming pulse time 50 - 50 - 50 - 50 - µs tWHWH2 tWHWH2 Erase pulse time 0.3 - 0.3 - 0.3 - 0.3 - sec :ULWH#ZDYHIRUP :(#FRQWUROOHG 3rd bus cycle tAS 5555h Addresses DATA polling Program address tAH tCH )/$6+ tWC Program address CE tGHWL; tOES OE tWP WE DATA tCS tWHWH1 or 2 tWPH tDH A0h tDS Program data DQ7 DOUT VSS ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 46 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® $&#SDUDPHWHUV³ZULWH#F\FOH#5 &(#FRQWUROOHG -55 -70 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - ns tAVEL tAS Address setup time 0 - 0 - 0 - 0 - ns tELAX tAH Address hold time 40 - 45 - 45 - 50 - ns tDVEH tDS Data setup time 30 - 30 - 45 - 50 - ns tEHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tOES Output enable setup time 0 - 0 - 0 - 0 - ns Output enable hold time: Read 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: Toggle and DATA polling 10 - 10 - 10 - 10 - ns tGHEL tGHEL Read recover time before write 0 - 0 - 0 - 0 - ns tWLEL tWS WE setup time 0 - 0 - 0 - 0 - ns tEHWH tWH WE hold time 0 - 0 - 0 - 0 - ns tELEH tCP CE pulse width 35 - 35 - 45 - 50 - ns tEHEL tCPH CE pulse width high 20 - 20 - 20 - 20 - ns tWHWH1 tWHWH1 Programming pulse time 50 - 50 - 50 - 50 - µs tWHWH2 tWHWH2 Erase pulse time 0.3 - 0.3 - 0.3 - 0.3 - sec :ULWH#ZDYHIRUP#5 &(#FRQWUROOHG DATA polling Addresses 5555h Program address )/$6+ tWC tAS Program address tAH WE tGHEL, tOES OE tWH tCP CE tCPH tWS DATA tWHWH1 or 2 tDH A0h Program data DQ7 DOUT tDS 47 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® (UDVH#ZDYHIRUP ð49#PRGH# tWC Addresses tAS 5555h 2Ah 5555h 5555h 2Ah Sector address tAH CE tGHWL OE tWP tWC WE tWPH tCS 10h for Chip Erase tDH Data AAh 55h 80h AAh 55h 30h tDS 5(6(7#ZDYHIRUP CE RY/BY tRP RESET tREADY )/$6+ 5<2%<#ZDYHIRUP CE Rising edge of last WE signal WE Program/erase operation RY/BY ','#4407333<0$1#72:233 tri-stated open-drain $//,$1&(#6(0,&21'8&725 48 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® '$7$#SROOLQJ#ZDYHIRUP tCH CE tDF tOE OE tOEH WE tCE tOH DQ7 Input DQ7 Output DQ7 High Z Output tWHWH1 or 2 7RJJOH#ELW#ZDYHIRUP CE tOEH WE OE DQ6 )/$6+ tDH tOE (UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH Limits Parameter Min Typical Max Unit Sector erase and verify-1 time (excludes 00h programming prior to erase) - 1.6 - sec Word programming time - 60 - µs Byte program time - 60 - µs Chip programming time - 7.5 - sec Erase/program cycles - - 10,000 cycles 49 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® $&#WHVW#FRQGLWLRQV Test condition Device under Test 100 pF* -170 Output load *including scope and jig capacitance Unit 1 TTL gate Input rise and fall times VSS -200 5 ns 0.0-2.0 V Input timing measurement reference levels 1.0 V Output timing measurement reference levels 1.0 Input pulse levels 5HFRPPHQGHG#RSHUDWLQJ#FRQGLWLRQV Parameter Supply voltage Input voltage Symbol Min Typical Max Unit VCC +4.5 5.0 +5.5 V VSS 0 0 0 V VIH 2.0 - VCC + 0.5 V VIL –0.5 - 0.8 V $EVROXWH#PD[LPXP#UDWLQJV Symbol Min Max Unit Input voltage (Input or DQ pin) VIN –2.0 +7.0 V Input Voltage (A9 pin, OE, RESET) VIN –2.0 +13.0 V Power supply voltage VCC -0.5 +5.5 V Operating temperature TOPR –55 +125 °C Storage temperature (Plastic) TSTG –65 +150 °C Short circuit output current IOUT - 200 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. /DWFKXS#WROHUDQFH# Parameter Min Max Unit Input voltage with respect to VSS on A9, OE, and RESET pin -1.0 +13.0 V Input voltage with respect to VSS on all DQ, address and control pins -1.0 VCC+1.0 V Current -100 +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time. ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 4: )/$6+ Parameter 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® 7623#SLQ#FDSDFLWDQFH Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 µF 62#SLQ#FDSDFLWDQFH Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 µF Temp. (°C) Min Unit 150° 10 years 125° 20 years 'DWD#UHWHQWLRQ Parameter )/$6+ Minimum pattern data retention time 4; $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233 $65<)533 3UHOLPLQDU\#LQIRUPDWLRQ ® 3DFNDJH#GLPHQVLRQV h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin TSOP j g e i f d a a b c d e f g h i j 48-pin TSOP min max (mm) (mm) 1.20 0.25 0.50 0.70 0.1 0.21 18.30 18.50 19.80 20.20 11.90 12.10 0.95 1.05 0.05 0.15 0.50 m n o p q r s t u w 44-pin SO min max (mm) (mm) 28.00 28.40 0.35 0.50 0.10 0.35 2.17 2.45 2.80 1.27 13.10 13.50 15.70 16.30 0.06 1.00 0.10 0.21 0–5° c b w 0–8° u 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 44-pin SO s t 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 r n o m ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 )/$6+ q p 4< 3UHOLPLQDU\#LQIRUPDWLRQ $65<)533 ® 2UGHULQJ#FRGHV Package \ Access Time 55 ns (commercial/industrial) 70 ns (commercial/industrial) 90 ns (commercial/industrial) 120 ns (commercial/industrial) AS29F200B-55TC AS29F200B-55TI AS29F200B-70TC AS29F200B-70TI AS29F200B-90TC AS29F200B-90TI AS29F200B-120TC AS29F200B-120TI AS29F200T-55TC AS29F200T-55TI AS29F200T-70TC AS29F200T-70TI AS29F200T-90TC AS29F200T-90TI AS29F200T-120TC AS29F200T-120TI AS29F200B-55SC AS29F200B-55SI AS29F200B-70SC AS29F200B-70SI AS29F200B-90SC AS29F200B-90SI AS29F200B-120SC AS29F200B-120SI AS29F200T-55SC AS29F200T-55SI AS29F200T-70SC AS29F200T-70SI AS29F200T-90SC AS29F200T-90SI AS29F200T-120SC AS29F200T-120SI TSOP, 12×20 mm, 48-pin SO, 600 mil wide, 44-pin 3DUW#QXPEHULQJ#V\VWHP X Flash EEPROM prefix F = 5V LV = 3V LL = 2.5V 200 Device number X B (bottom) or T (top) boot block –XXX Address access time X Package: C S= SO T= TSOP Temperature range C = Commercial, 0°C to 70 °C I = Industrial, -40°C to 85°C )/$6+ AS29 53 $//,$1&(#6(0,&21'8&725 ','#4407333<0$1#72:233