ETC CD54HCT107F3A

[ /Title
(CD74
HC107
,
CD74
HCT10
7)
/Subject
(Dual
J-K
FlipFlop
with
Reset
Negative-
CD54/74HC107,
CD54/74HCT107
Data sheet acquired from Harris Semiconductor
SCHS139A
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
March 1998 - Revised May 2000
Features
Description
• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
The ’HC107 and ’HCT107 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
• Asynchronous Reset
• Complementary Outputs
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input.
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
This device is functionally identical to the HC/HCT73 but
differs in terminal assignment and in some parametric limits.
• Wide Operating Temperature Range . . . -55oC to 125oC
The HCT logic family is functionally as well as pin compatible
with the standard LS family.
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PACKAGE
CD54HC107F3A
-55 to 125
14 Ld CERDIP
CD74HC107E
-55 to 125
14 Ld PDIP
CD74HC107M
-55 to 125
14 Ld SOIC
CD54HCT107F3A
-55 to 125
14 Ld CERDIP
CD74HCT107E
-55 to 125
14 Ld PDIP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local TI sales office or
customer service for ordering information.
Pinout
CD54HC107, CD54HCT107
(CERDIP)
CD74HC107, CD74HCT107
(PDIP, SOIC)
TOP VIEW
1J 1
14 VCC
1Q 2
13 1R
1Q 3
12 1CP
1K 4
11 2K
2Q 5
10 2R
2Q 6
9 2CP
8 2J
GND 7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2000, Texas Instruments Incorporated
1
CD54/74HC107, CD54/74HCT107
Functional Diagram
1
3
1J
1Q
4
1K
FF 1
2
1Q
12
1CP
13
1R
8
5
2J
11
2K
2Q
FF 2
6
2Q
9
2CP
2R
GND = 7
VCC = 14
10
TRUTH TABLE
INPUTS
R
OUTPUTS
CP
J
K
Q
Q
L
X
X
X
L
H
H
↓
L
L
H
↓
H
L
H
L
H
↓
L
H
L
H
H
↓
H
H
Toggle
H
H
X
X
No Change
No Change
NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↓ = High-to-Low Transition
Logic Diagram
1 (8)
J
4(11)
K
nA
CL R
13 (10)
R
2
3 (5)
Q
K
CL
12 (9)
CP
J
2 (6)
Q
CD54/74HC107, CD54/74HCT107
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54/74HC107, CD54/74HCT107
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-55oC TO 125oC
SYMBOL
VI (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
ICC
VCC or
GND
0
6
-
-
4
-
40
-
80
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Load
VOH
VIH or
VIL
-
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
-4
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
PARAMETER
Quiescent Device
Current
IO (mA) VCC (V)
-40oC TO 85oC
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC
and
GND
4
5.5
-
ICC
VCC or
GND
0
5.5
-
-
4
-
40
-
80
µA
∆ICC
(Note 4)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.3
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER
HC TYPES
CP Pulse Width
R Pulse Width
SYMBOL
TEST
CONDITIONS
tw
-
tw
-
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
4
CD54/74HC107, CD54/74HCT107
Prerequisite For Switching Specifications
PARAMETER
Setup Time, J, K to CP
Hold Time, J, K to CP
Removal Time
CP Frequency
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tSU
-
2
100
-
-
125
-
150
-
ns
tH
-
tREM
-
fMAX
-
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
2
3
-
-
3
-
3
-
ns
4.5
3
-
-
3
-
3
-
ns
6
3
-
-
3
-
3
-
ns
2
60
-
-
75
-
90
-
ns
4.5
12
-
-
15
-
18
-
ns
6
10
-
-
13
-
15
-
ns
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
25
-
20
-
MHz
6
35
-
-
29
-
23
-
MHz
HCT TYPES
CP Pulse Width
R Pulse Width
tw
-
4.5
18
-
-
23
-
27
-
ns
tw
-
4.5
24
-
-
30
-
36
-
ns
Setup Time, J, K to CP
tSU
-
4.5
20
-
-
25
-
30
-
ns
Hold Time, J, K to CP
tH
-
4.5
5
-
-
5
-
5
-
ns
Removal Time
tREM
-
4.5
12
-
-
15
-
18
-
ns
CP Frequency
fMAX
-
4.5
28
-
-
22
-
19
-
MHz
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
HC TYPES
Propagation Delay,
CP to Q
Propagation Delay,
CP to Q
Propagation Delay,
R to Q, Q
Output Transition Time
Input Capacitance
CP Frequency
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
29
-
37
-
43
ns
CL = 50pF
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
29
-
37
-
43
ns
CL = 50pF
2
-
-
155
-
195
-
235
ns
4.5
-
-
31
-
39
-
47
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
40
ns
CL = 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CI
-
-
-
-
10
-
10
-
10
pF
fMAX
CL = 15pF
5
-
60
-
-
-
-
-
MHz
5
CD54/74HC107, CD54/74HCT107
Switching Specifications Input tr, tf = 6ns
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
Power Dissipation Capacitance
(Notes 5, 6)
CPD
-
5
-
31
-
-
-
-
-
pF
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
-
43
-
54
-
65
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
Propagation Delay,
R to Q, Q
tPLH, tPHL
CL = 50pF
4.5
-
-
38
-
48
-
57
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
Output Transition Time
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
-
56
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 5, 6)
CPD
-
5
-
30
-
-
-
-
-
pF
HCT TYPES
Input Capacitance
NOTES:
5. CPD is used to determine the dynamic power consumption, per flip-flop.
6. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tfCL
trCL
CLOCK
tWL + tWH =
90%
10%
I
tWH
tr = 6ns
tf = 6ns
tr = 6ns
VCC
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
GND
tWH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tf = 6ns
90%
50%
10%
1.3V
1.3V
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tPHL
1.3V
0.3V
tWL
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
INPUT
2.7V
0.3V
GND
tWL
I
fCL
3V
CLOCK
50%
50%
tfCL = 6ns
fCL
VCC
50%
10%
tWL + tWH =
trCL = 6ns
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
CD54/74HC107, CD54/74HCT107
Test Circuits and Waveforms
trCL
tfCL
trCL
CLOCK
INPUT
(Continued)
VCC
90%
GND
tH(H)
GND
tH(H)
VCC
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
1.3V
0.3V
tH(L)
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
10%
tfCL
CL
50pF
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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