DS1645Y/AB DS1645Y/AB Partitionable 1024K NV SRAM FEATURES PIN ASSIGNMENT • 10 years minimum data retention in the absence of external power • Data is automatically protected during power loss • Directly replaces 128K x 8 volatile static RAM NC 1 32 VCC A16 2 31 A15 A14 3 30 NC A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 • Write protects selected blocks of memory when programmed • Unlimited write cycles • Low–power CMOS • Read and write access times as fast as 70 ns • Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time • Full +10% VCC operating range (DS1645Y) • Optional +5% VCC operating range (DS1645AB) • Optional 32–PIN ENCAPSULATED PACKAGE 740 MIL EXTENDED industrial temperature range of –40°C to +85°C, designated IND • JEDEC standard 32–pin DIP package • Low Profile Module (LPM) package – Fits into standard 68–pin PLCC surface mountable socket – 250 mil package height – Power Fail Output (PFO) warns system of impending VCC power failure NC A15 A16 PFO VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 34–PIN LOW PROFILE MODULE (LPM) Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 041497 1/12 DS1645Y/AB PIN DESCRIPTION A0 – A16 DQ0 – DQ7 CE WE OE PFO VCC GND NC – – – – – – – – – Address Inputs Data In/Data Out Chip Enable Write Enable Output Enable Power Fail Output (LPM only) Power (+5V) Ground No Connect DESCRIPTION The DS1645 1024K Nonvolatile SRAMs are 1,048,576–bit, fully static, nonvolatile SRAMs organized as 131,072 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out–of–tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. In addition, the device has the ability to unconditionally write protect blocks of memory so that inadvertent write cycles do not corrupt programs and important data. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. DIP–package DS1645 devices can be used in place of existing 128K x 8 SRAMs directly conforming to the popular bytewide 32–pin DIP standard. DS1645 devices in the Low Profile Module package are specifically designed for surface mount applications. DS1645 LPM devices also have an additional pin, a Power Fail Output, that can be used to warn a system of impending VCC power failure. READ MODE The DS1645 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight data 041497 2/12 output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1645 devices execute a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1645AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1645Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvoltile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power–up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1645AB and 4.5 volts for the DS1645Y. DS1645Y/AB FRESHNESS SEAL Each DS1645 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation. PARTITION PROGRAMMING MODE The register controlling the partitioning logic is selected by recognition of a specific binary pattern which is sent on address lines A13 – A16. These address lines are the four upper order address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21st through 24th read cycles will load the partition register. Since there are 16 protectable partitions, the size of each partition is 128K/16 or 8K x 8. Each partition is represented by one of the 16 bits contained in the 21st through 24th read cycles as defined by A13 through A16 and shown in Table 2. A logical 1 in a bit location write protects the corresponding partition. A logical 0 in a bit location disables write protection. For example, if during the pattern match sequence bit 22 on address pin A14 was a 1, this would cause the partition register location for partition 5 to be set to a 1. This in turn would cause the DS1645 devices to internally inhibit WE for all write accesses where A16 A15 A14 A13=0101. Note that while programming the partition register, data which is being accessed from the RAM should be ignored, since the purpose of the 24 read cycles is to program the partition register, not to access data from RAM. 041497 3/12 DS1645Y/AB PATTERN MATCH TO WRITE PARTITION REGISTER Table 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A13 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 X X X X A14 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 X X X X A15 1 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 X X X X A16 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 X X X X FIRST BITS ENTERED LAST BITS ENTERED PARTITION REGISTER MAPPING Table 2 Address Pin Bit number in pattern match sequence Partition Number Address State Affected (A16 A15 A14 A13) A13 BIT 21 PARTITION 0 0000 A14 BIT 21 PARTITION 1 0001 A15 BIT 21 PARTITION 2 0010 A16 BIT 21 PARTITION 3 0011 A13 BIT 22 PARTITION 4 0100 A14 BIT 22 PARTITION 5 0101 A15 BIT 22 PARTITION 6 0110 A16 BIT 22 PARTITION 7 0111 A13 BIT 23 PARTITION 8 1000 A14 BIT 23 PARTITION 9 1001 A15 BIT 23 PARTITION 10 1010 A16 BIT 23 PARTITION 11 1011 A13 BIT 24 PARTITION 12 1100 A14 BIT 24 PARTITION 13 1101 A15 BIT 24 PARTITION 14 1110 A16 BIT 24 PARTITION 15 1111 041497 4/12 DS1645Y/AB ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.5V to +7.0V 0°C to 70°C, –40°C to +85°C for IND parts –40°C to +70°C, –40°C to +85°C for IND parts 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER (tA: See Note 10) SYMBOL MIN TYP MAX UNITS DS1645Y Power Supply Voltage VCC 4.5 5.0 5.5 V DS1645AB Power Supply Voltage VCC 4.75 5.0 5.25 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 +0.8 V ( VCC=5V ± 10% for DS1645Y) (tA: See Note 10) ( VCC=5V ± 5% for DS1645AB) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN MAX UNITS Input Leakage Current IIL –1.0 +1.0 A I/O Leakage Current CE > VIH < VCC IIO –1.0 +1.0 A Output Current @ 2.4V IOH –1.0 mA Output Current @ 0.4V IOL 2.0 mA TYP Standby Current CE = 2.2V ICCS1 5.0 10.0 mA Standby Current CE = VCC - 0.5V ICCS2 3.0 5.0 mA Operating Current ICCO1 85 mA Write Protection Voltage (DS1645Y) VTP 4.25 4.37 4.5 V Write Protection Voltage (DS1645AB) VTP 4.50 4.62 4.75 V NOTES 14 (tA = 25°C) CAPACITANCE PARAMETER NOTES SYMBOL MIN TYP MAX UNITS Input Capacitance CIN 5 10 pF Input/Output Capacitance CI/O 5 10 pF NOTES 041497 5/12 DS1645Y/AB (VCC=5V ± 5% for DS1645AB) (tA: See Note 10) (VCC=5V ± 10% for DS1645Y) AC ELECTRICAL CHARACTERISTICS DS1645Y–70 DS1645AB–70 DS1645Y–85 DS1645AB–85 MIN SYMBOL MIN Read Cycle Time tRC 70 Access Time tACC 70 85 ns OE to Output Valid tOE 35 45 ns CE to Output Valid tCO 70 85 ns OE or CE to Output Valid tCOE Output High Z from Deselection tOD Output Hold from Address Change tOH 5 5 ns Write Cycle Time tWC 70 85 ns Write Pulse Width tWP 55 65 ns Address Setup Time tAW 0 0 ns Write Recovery Time tWR1 tWR2 10 10 10 10 ns ns 12 13 Output High Z from WE tODW ns 5 Output Active from WE tOEW 5 5 ns 5 Data Setup Time tDS 30 35 ns 4 Data Hold Time tDH1 tDH2 5 5 5 5 ns ns 12 13 UNITS NOTES PARAMETER MAX 5 25 30 25 SYMBOL MIN Read Cycle Time tRC 100 Access Time tACC MAX UNITS NOTES ns 5 DS1645Y–100 DS1645AB–100 PARAMETER MAX 85 30 ns 5 ns 5 3 DS1645Y–120 DS1645AB–120 MIN MAX 120 100 ns 120 ns OE to Output Valid tOE 50 60 ns CE to Output Valid tCO 100 120 ns OE or CE to Output Valid tCOE Output High Z from Deselection tOD Output Hold from Address Change tOH 5 5 ns Write Cycle Time tWC 100 120 ns Write Pulse Width tWP 75 90 ns Address Setup Time tAW 0 0 ns Write Recovery Time tWR1 tWR2 10 10 10 10 ns ns 12 13 Output High Z from WE tODW ns 5 Output Active from WE tOEW 5 5 ns 5 Data Setup Time tDS 40 50 ns 4 Data Hold Time tDH1 tDH2 5 5 5 5 ns ns 12 13 041497 6/12 5 5 35 35 35 35 ns 5 ns 5 3 DS1645Y/AB AC ELECTRICAL CHARACTERISTICS (tA: See Note 10) ( VCCI=4.50V to 5.50V)* PARAMETER SYMBOL MIN TYP MAX UNITS Address Setup tAS 0 ns Address Hold tAH 50 ns Read Recovery tRR 10 ns CE Pulse Width tCW 75 ns NOTES *For loading partition register TIMING DIAGRAM: LOADING PARTITION REGISTER VIH A13–A16 VIH BIT 1 BIT 2 BIT 24 tAS tAH tRR tCW CE VIH ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VIL OE VIL VIH WE READ CYCLE tRC ADDRESSES VIH VIL VIH VIL VIH VIL tOH tACC VIH VIH CE tCO VIL tOD VIH OE tOE VIL tCOE tCOE DOUT VIH tOD VOH OUTPUT VOH VOL DATA VALID VOL SEE NOTE 1 041497 7/12 DS1645Y/AB WRITE CYCLE 1 tWC ADDRESSES VIH VIL VIH VIL VIH VIL tAW CE VIL VIL tWP tWR1 WE VIH VIH VIL VIL tOEW tODW HIGH IMPEDANCE DOUT tDS tDH1 VIH VIH DIN DATA IN STABLE VIL VIL SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 tWC ADDRESSES VIH VIH VIH VIL VIL VIL tWP tAW CE tWR2 VIH VIH VIL VIL VIL VIH WE VIL VIL tCOE tODW DOUT tDS tDH2 VIH VIL SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 041497 8/12 VIH DATA IN STABLE DIN VIL DS1645Y/AB POWER–DOWN/POWER–UP CONDITION VCC VTP 3.2V tR tF tREC tPD CE, WE SEE NOTE 11 LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL DATA RETENTION TIME tDR POWER–DOWN/POWER–UP TIMING PARAMETER (tA: See Note 10) SYMBOL MIN tPD VCC slew from VTP to 0V (CE at VIH) VCC slew from 0V to Vtp (CE at VIH) CE, WE at VIH before Power-Down CE, WE at VIH after Power-Up TYP MAX UNITS NOTES 0 s 11 tF 300 s tR 0 s tREC 25 125 ms (tA = 25°C) PARAMETER Expected Data Retention Time SYMBOL MIN tDR 10 TYP MAX UNITS NOTES years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 041497 9/12 DS1645Y/AB 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1645 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C for industrial products (IND), this range is –40°C to +85°C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1, tDH1 are measured from WE going high. 13. tWR2, tDH2 are measured from CE going high. 14. The power fail output signal (PFO) is driven active (VOL=0.4V) when the VCC trip point occurs. While active, the PFO pin can sink 4 mA and will maintain a maximum output voltage of 0.4 volts. When inactive, the voltage output of PFO is 2.4 volts minimum and will source a current of 1 mA. This signal is only present on the LPM package variations. 15. DS1645 modules are recognized by Underwriters Laboratory (U.L.) under file E99151(R). DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open t Cycle = 200 ns All voltages are referenced to ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 – 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION DS1645 TTP– SSS – III Operating Temperature Range blank: 0° to 70° IND: –40° to +85°C Access Speed 70 ns 70: 85 ns 85: 100: 100 ns 120: 120 ns Package Type Blank: 32–pin 600 mil DIP L: 34–pin Low Profile Module VCC Tolerance AB: +5% Y: +10% 041497 10/12 DS1645Y/AB DS1645Y/AB NONVOLATILE SRAM, 32–PIN 740 MIL EXTENDED MODULE PKG 32–PIN DIM MIN MAX A IN. MM 1.680 42.67 1.700 43.18 B IN. MM 0.720 18.29 0.740 18.80 C IN. MM 0.355 9.02 0.375 9.52 D IN. MM 0.080 2.03 0.110 2.79 E IN. MM 0.015 0.38 0.025 0.63 F IN. MM 0.120 3.05 0.160 4.06 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.590 14.99 0.630 16.00 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.021 0.53 1 A C F D K G J E H B 041497 11/12 DS1645Y/AB DS1645Y/AB 34–PIN LOW PROFILE MODULE (LPM) PKG A E F B D C Dallas Semiconductor Low Profile Modules must be inserted into 68–pin PLCC sockets for proper operation. Direct surface–mounting of these products by reflow soldering will destroy internal lithium batteries. For recommended PLCC sockets, contact the Dallas Semiconductor factory. 041497 12/12 INCHES DIM MIN MAX A 0.955 0.980 B 0.840 0.855 C 0.230 0.250 D 0.975 0.995 E 0.047 0.053 F 0.015 0.025