DS1350W

19-5586; Rev 10/10
DS1350W
3.3V 4096k Nonvolatile SRAM
with Battery Monitor
www.maxim-ic.com
FEATURES
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PIN ASSIGNMENT
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Power supply monitor resets processor when
VCC power loss occurs and holds processor in
reset during VCC ramp-up
Battery monitor checks remaining capacity
daily
Read and write access times of 100ns
Unlimited write cycle endurance
Typical standby current 50 µA
Upgrade for 512k x 8 SRAM, EEPROM or
Flash
Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
Optional industrial temperature range of
-40°C to +85°C, designated IND
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
BW
A15
A16
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND VBAT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0-A18
DQ0-DQ7
CE
WE
OE
RST
BW
VCC
GND
NC
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Reset Output
- Battery Warning Output
- Power (+3.3 Volts)
- Ground
- No Connect
DESCRIPTION
The DS1350W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by eight bits. Each NV SRAM has a self-contained lithium energy source
and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a
condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent data corruption. Additionally, the DS1350W has dedicated circuitry
for monitoring the status of VCC and the status of the internal lithium battery. DS1350W devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. The devices can be used in place of 512k x 8
SRAM, EEPROM or Flash components.
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DS1350W
READ MODE
The DS1350W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1350W executes a write cycle whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then
WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1350W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1350W has the ability to monitor the external VCC power supply. When an out-of-tolerance power
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system operation
during power-on transients and to allow tREC to elapse. RST has an open-drain output driver.
BATTERY MONITORING
The DS1350W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1 MΩ test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open-drain output driver.
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DS1350W
FRESHNESS SEAL
Each DS1350W is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
PACKAGES
The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control into a module base
along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap
Module package design allows a DS1350W device to be surface-mounted without subjecting its lithium
backup battery to destructive high-temperature reflow soldering. After a DS1350W module base is reflow
soldered, a DS9034PC is snapped on top of the base to form a complete Nonvolatile SRAM module. The
DS9034PC is keyed to prevent improper attachment. DS1350W module bases and DS9034PC
PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for
further information.
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DS1350W
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
Industrial:
Storage Temperature Range
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
-0.3V to +4.6V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Logic 1
Logic 0
SYMBOL
VCC
VIH
VIL
MIN
3.0
2.2
0.0
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE ≥ VIH ≤ VCC
Output Current @ 2.2V
Output Current @ 0.4V
Standby Current CE = 2.2V
Standby Current
CE = VCC -0.2V
Operating Current
Write Protection Voltage
SYMBOL
IIL
MIN
-1.0
IIO
-1.0
IOH
IOL
ICCS1
-1.0
2.0
ICCS2
ICCO1
VTP
2.8
TYP
3.3
(TA: See Note 10)
MAX
3.6
VCC
0.4
NOTES
(TA: See Note 10) (VCC = 3.3V ± 0.3V)
TYP
MAX
+1.0
UNITS
µA
+1.0
µA
50
250
mA
mA
µA
30
150
µA
2.9
50
3.0
mA
V
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
UNITS
V
V
V
NOTES
14
14
(TA = +25°C)
SYMBOL
CIN
CI/O
MIN
4 of 10
TYP
5
5
MAX
10
10
UNITS
pF
pF
NOTES
DS1350W
(TA: See Note 10) (VCC = 3.3V ± 0.3V)
AC ELECTRICAL CHARACTERISTICS
DS1350W-100
SYMBOL
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z
from Deselection
Output Hold from
Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Z from WE
Output Active from WE
Data Setup Time
Data Hold Time
tRC
tACC
tOE
tCO
tCOE
MIN
MAX
100
100
50
100
5
tOD
35
UNITS
NOTES
ns
ns
ns
ns
ns
5
ns
5
tOH
5
ns
tWC
tWP
tAW
tWR1
tWR2
tODW
tOEW
tDS
tDH1
tDH2
100
75
0
5
20
ns
ns
ns
ns
35
5
40
0
20
READ CYCLE
SEE NOTE 1
5 of 10
ns
ns
ns
ns
3
12
13
5
5
4
12
13
DS1350W
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
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DS1350W
POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
SEE NOTE 14
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DS1350W
POWER-DOWN/POWER-UP TIMING
PARAMETER
VCC Fail Detect to CE and
WE Inactive
VCC slew from VTP to 0V
VCC Fail Detect to RST
Active
VCC slew from 0V to VTP
VCC Valid to CE and WE
Inactive
VCC Valid to End of Write
Protection
VCC Valid to RST Inactive
VCC Valid to BW Valid
SYMBOL
(TA: See Note 10)
MIN
TYP
tPD
tF
UNITS
NOTES
1.5
µs
11
150
µs
tRPD
tR
MAX
15
150
tPU
2
ms
tREC
125
ms
350
1
ms
s
tRPU
tBPU
150
SYMBOL
tBTC
tBTPW
tBW
14
µs
200
BATTERY WARNING TIMING
PARAMETER
Battery Test Cycle
Battery Test Pulse Width
Battery Test to BW Active
µs
14
14
(TA: See Note 10)
MIN
TYP
24
MAX
1
1
UNITS
hr
s
s
NOTES
(TA = +25°C)
PARAMETER
Expected Data
Retention Time
SYMBOL
MIN
tDR
10
TYP
MAX
UNITS
NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1350W has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
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DS1350W
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. RST and BW are open-drain outputs and cannot source current. External pullup resistors should be
connected to these pins for proper operation. Both pins will sink 10 mA.
15. DS1350 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART
DS1350WP-100+
DS1350WP-100IND+
SUPPLY
TOLERANCE
3.3V ± 0.3V
3.3V ± 0.3V
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
34 PCAP*
34 PCAP*
+ Denotes a lead(Pb)-free/RoHS-compliant package.
* DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
LAND
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
PATTERN NO.
34 PCAP
PC2+5
—
21-0246
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DS1350W
REVISION HISTORY
REVISION
DESCRIPTION
DATE
Updated the soldering and storage information in the Absolute
Maximum Ratings section, removed the unused AC timing specs in
the AC Electrical Characteristics table, updated the Ordering
10/10
Information table, replaced the package outline drawing with the
Package Information table
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PAGES
CHANGED
1, 4, 5, 9