ETC DSP56364UM

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Revision 1.1
Published 11/00
DSP56364UM/D
DSP56364
24-Bit Digital Signal Processor
User’s Manual
Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin TX 78735-8598
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
© MOTOROLA INC., 1999, 2000. All rights reserved.
OnCE is a trademark of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function, or design. Motorola does not assume any liability arising out of the application or use
of any product or circuit described herein; neither does it convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Motorola and
Opportunity/Affirmative Action Employer
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Freescale Semiconductor, Inc.
CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Number
Title
Page
Number
Section
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.7
1.8
1 DSP56364 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Audio Prodessor Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
PLL-based Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Data and Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Reserved Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Program ROM Area Reserved for Motorola Use . . . . . . . . . . . . . . . . . . . . 1-10
Bootstrap ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . 1-11
External Memory Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Section
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
2.8
2.9
2.10
2 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Clock and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
External Memory Expansion Port (Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Enhanced Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
MOTOROLA
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Freescale Semiconductor, Inc.
CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Number
Title
Page
Number
Section
3.1
3.1.1
3.1.2
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.5
3.6
3 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
Internal Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
RAM Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
ROM Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . . .3-5
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
External Memory Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Section
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
4.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.9
4.10
4 Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Mode C (MC) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Address Attribute Priority Disable (APD) - Bit 14 . . . . . . . . . . . . . . . . . . . .4-2
Address Tracing Enable (ATE) - Bit 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
PLL and Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
PLL Multiplication Factor (MF0-MF11) - Bits 0-11 . . . . . . . . . . . . . . . . . . .4-8
Crystal Range Bit (XTLR) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
XTAL Disable Bit (XTLD) - Bit 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Clock Output Disable Bit (COD) - Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
PLL Pre-Divider Factor (PD0-PD3) - Bits 20-23. . . . . . . . . . . . . . . . . . . . . .4-9
Device Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Section
5 General Purpose Input/Output Port (GPIO). . . . . . . . . . . . . . . . . . . . . . . .5-1
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2
GPIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2.1
Port B Control Register (PCRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.2.2
Port B GPIO Data Register (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Section
6 Enhanced Serial AUDIO Interface (ESAI) . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2
ESAI Data and Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.2.1
Serial Transmit 0 Data Pin (SDO0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
iv
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CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Number
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.5.1
6.5.2
6.5.3
6.6
6.6.1
6.6.2
6.6.3
Title
Page
Number
Serial Transmit 1 Data Pin (SDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) . . . . . . . . . . . . . . . . . . 6-3
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) . . . . . . . . . . . . . . . . . . 6-4
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) . . . . . . . . . . . . . . . . . . 6-4
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) . . . . . . . . . . . . . . . . . . 6-5
Receiver Serial Clock (SCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Transmitter Serial Clock (SCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Frame Sync for Receiver (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . . 6-8
High Frequency Clock for Receiver (HCKR). . . . . . . . . . . . . . . . . . . . . . . . 6-8
ESAI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
ESAI Transmitter Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . . 6-9
ESAI Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . . 6-26
ESAI Receive Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
ESAI Common Control Register (SAICR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
ESAI Status Register (SAISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
ESAI Receive Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
ESAI Receive Data Registers (RX3, RX2, RX1, RX0) . . . . . . . . . . . . . . . 6-44
ESAI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) . . . . . . 6-44
ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . 6-45
Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . . . . . . . . . . . . . . 6-46
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
ESAI After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
ESAI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
ESAI Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
Operating Modes – Normal, Network, and On-Demand . . . . . . . . . . . . . . 6-50
Serial I/O Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
GPIO - Pins and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
Port C Control Register (PCRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
Port C Direction Register (PRRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
Port C Data register (PDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
ESAI Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Initializing the ESAI Using Individual Reset . . . . . . . . . . . . . . . . . . . . . . . 6-56
Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . 6-56
Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . 6-57
Section
7 Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2
Serial Host Interface Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
MOTOROLA
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CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Number
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
Title
Page
Number
SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Serial Host Interface Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
SHI Input/Output Shift Register (IOSR)—Host Side . . . . . . . . . . . . . . . . . .7-6
SHI Host Transmit Data Register (HTX)—DSP Side . . . . . . . . . . . . . . . . . .7-7
SHI Host Receive Data FIFO (HRX)—DSP Side . . . . . . . . . . . . . . . . . . . . .7-7
SHI Slave Address Register (HSAR)—DSP Side . . . . . . . . . . . . . . . . . . . . .7-8
SHI Clock Control Register (HCKR)—DSP Side . . . . . . . . . . . . . . . . . . . . .7-8
SHI Control/Status Register (HCSR)—DSP Side . . . . . . . . . . . . . . . . . . . .7-12
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
I2C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-21
SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23
I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24
I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27
SHI Operation During DSP Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-29
Appendix
A Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1
DSP56364 Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix
B BDSL File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1
BSDL FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Appendix
C Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.2
Programming Sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8
vi
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List of Figures
Freescale Semiconductor, Inc...
Figure
Number
1-1
2-1
3-1
3-2
3-3
3-4
4-1
4-2
4-3
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
7-1
7-2
7-3
7-4
MOTOROLA
Title
Page
Number
DSP56364 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Memory Maps for MS=0, SC=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Memory Maps for MS=1, SC=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Memory Maps for MS=0, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
Memory Maps for MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Interrupt Priority Register P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Interrupt Priority Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
GPIO Port B Control Register (PCRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
GPIO Port B Direction Register (PRRB) . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
GPIO Port B Data Register (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
ESAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
TCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10
ESAI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . . .6-11
ESAI Frame Sync Generator Functional Block Diagram. . . . . . . . . . . . . .6-13
TCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
Normal and Network Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20
Frame Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23
RCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26
RCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-30
SAICR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35
SAICR SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
SAISR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-38
ESAI Data Path Programming Model ([R/T]SHFD=0) . . . . . . . . . . . . . . .6-42
ESAI Data Path Programming Model ([R/T]SHFD=1) . . . . . . . . . . . . . . .6-43
TSMA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45
TSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45
RSMA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-47
RSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-47
PCRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54
PRRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54
PDRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55
Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
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List of Figures
Figure
Number
7-5
7-6
7-7
7-8
7-9
7-10
7-11
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-10
C-11
C-12
C-13
C-14
C-15
C-16
viii
Page
Number
SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
I2C Start and Stop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Acknowledgment on the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
I2C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .7-21
I2C Bus Protocol For Host Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10
Interrupt Priority Register-Core (IPR-C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11
Interrupt Priority Register- Peripherals (IPR-P) . . . . . . . . . . . . . . . . . . . . . . . . . . C-12
Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
SHI Slave Address (HSAR) and Clock Control Register (HCKR) . . . . . . . . C-14
SHI Host Transmit Data Register (HTX) and Host Receive Data Register (HRX)
(FIFO)C-15
SHI Host Control/Status Register (HCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . C-16
ESAI Transmit Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . . . . . . . . C-17
ESAI Transmit Clock Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . . C-18
ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . C-19
ESAI Receive Clock Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . C-20
ESAI Common Control Register (SAICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-21
ESAI Status Register (SAISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-22
Port B Registers (PCRB, PRRB, PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-23
Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-24
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List of Tables
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Table
Number
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
C-1
C-2
MOTOROLA
Title
Page
Number
DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Clock and PLL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
External Address Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
External Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
Serial Host Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Enhanced Serial Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . .2-10
JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13
GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
Memory Space Configuration Bit Settings for the DSP56364 . . . . . . . . . .3-4
Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
On-chip RAM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
On-chip ROM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
DSP56364 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
JTAG Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . .4-10
DSP56364 BSR Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . . . .6-6
Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
Transmitter High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . .6-14
Transmit Network Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
ESAI Transmit Slot and Word Length Selection . . . . . . . . . . . . . . . . . . .6-21
Receiver High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . .6-27
SCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28
FSR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
HCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
ESAI Receive Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . .6-32
ESAI Receive Slot and Word Length Selection . . . . . . . . . . . . . . . . . . . .6-32
PCRC and PRRC Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54
SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
SHI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
SHI Noise Reduction Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11
SHI Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
HREQ Function In SHI Slave Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
DSP56364 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
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List of Tables
Table
Number
Page
Number
Interrupt Sources Priorities Within an IP . . . . . . . . . . . . . . . . . . . . . . . . . C-7
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C-3
Title
x
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Preface
This manual contains the following sections and appendices.
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SECTION 1—DSP56364 OVERVIEW
–
Provides a brief description of the DSP56364, including a features list and block
diagram. Lists related documentation needed to use this chip and describes the
organization of this manual.
SECTION 2—SIGNAL/CONNECTION DESCRIPTIONS
–
Describes the signals on the DSP56364 pins and how these signals are grouped into
interfaces.
SECTION 3—MEMORY CONFIGURATION
–
Describes the DSP56364 memory spaces, RAM and ROM configuration, memory
configurations and their bit settings, and memory maps.
SECTION 4—CORE CONFIGURATION
–
Describes the registers used to configure the DSP56300 core when programming the
DSP56364, in particular the interrupt vector locations and the operation of the
interrupt priority registers. Explains the operating modes and how they affect the
processor’s program and data memories.
SECTION 5—GENERAL PURPOSE INPUT/OUTPUT (GPIO)
–
Describes the DSP56364 GPIO capability and the programming model for the GPIO
signals (operation, registers, and control).
SECTION 6—ENHANCED SERIAL AUDIO INTERFACE (ESAI)
–
Describes the full-duplex serial port for serial communication with a variety of serial
devices.
SECTION 7—SERIAL HOST INTERFACE (SHI)
–
Describes the serial input/output interface providing a path for communication and
program/coefficient data transfers between the DSP and an external host processor.
The SHI can also communicate with other serial peripheral devices.
APPENDIX A—BOOTSTRAP PROGRAM
–
Lists the bootstrap code used for the DSP56364.
APPENDIX B—BSDL LISTING
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–
Provides the BSDL listing for the DSP56364.
APPENDIX C—PROGRAMMING REFERENCE
–
Lists peripheral addresses, interrupt addresses, and interrupt priorities for the
DSP56364. Contains programming sheets listing the contents of the major DSP56364
registers for programmer reference.
Manual Conventions
Freescale Semiconductor, Inc...
The following conventions are used in this manual:
•
Bits within registers are always listed from most significant bit (MSB) to least significant
bit (LSB).
•
When several related bits are discussed, they are referenced as AA[n:m], where n>m. For
purposes of description, the bits are presented as if they are contiguous within a register.
However, this is not always the case. Refer to the programming model diagrams or to the
programmer’s sheets to see the exact location of bits within a register.
•
When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its
value is 0.
•
The word “assert” means that a high true (active high) signal is pulled high to VCC or that
a low true (active low) signal is pulled low to ground. The word “deassert” means that a
high true signal is pulled low to ground or that a low true signal is pulled high to VCC.
High True/Low True Signal Conventions
Signal/Symbol
Logic State
Signal State
Voltage
PIN1
True
Asserted
Ground2
PIN
False
Deasserted
VCC3
PIN
True
Asserted
VCC
PIN
False
Deasserted
Ground
Note:
1.
2.
3.
•
xii
PIN is a generic term for any pin on the chip.
Ground is an acceptable low voltage level. See the appropriate data sheet for the
range of acceptable low voltage levels (typically a TTL logic low).
VCC is an acceptable high voltage level. See the appropriate data sheet for the
range of acceptable high voltage levels (typically a TTL logic high).
Pins or signals that are asserted low (made active when pulled to ground)
–
In text, have an overbar (e.g., RESET is asserted low).
–
In code examples, have a tilde in front of their names. In example below, line 3 refers
to the SS0 pin (shown as ~SS0).
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•
Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g.,
HA1–HA8).
•
Code examples are displayed in a monospaced font, as shown below:.
Example Sample Code Listing
BFSET
#$0007,X:PCC; Configure:
line
; MISO0, MOSI0, SCK0 for SPI master
line
1
2
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; ~SS0 as PC3 for GPIO
line 3
•
Hex values are indicated with a dollar sign ($) preceding the hex value, as follows:
$FFFFFF is the X memory address for the core interrupt priority register (IPR-C).
•
The word “reset” is used in four different contexts in this manual:
–
the reset signal, written as “RESET,”
–
the reset instruction, written as “RESET,”
–
the reset operating state, written as “Reset,” and
–
the reset function, written as “reset.”
MOTOROLA
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About This Guide
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SECTION
1
DSP56364 OVERVIEW
Freescale Semiconductor, Inc...
1.1
INTRODUCTION
The DSP56364 24-Bit Digital Signal Processor, a new audio digital signal processor based on
the 24-bit DSP56300 architecture, is targeted to applications that require digital audio signal
processing such as sound field processing, acoustic equalization and other digital audio
algorithms.
The DSP56364 supports digital audio applications requiring sound field processing, acoustic
equalization, and other digital audio algorithms. The DSP56364 uses the high performance,
single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal
processors (DSPs) combined with the audio signal processing capability of the Motorola
Symphony™ DSP family, as shown in Figure 1-1. This design provides a two-fold
performance increase over Motorola’s popular Symphony family of DSPs while retaining
code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit
addressing, instruction cache, and direct memory access (DMA).
This document is intended to be used with the following Motorola publications:
• DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD.
• DSP56364 24-Bit Digital Signal Processor Technical Data Sheet, Motorola publication
DSP56364/D.
The DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD provides a description of the components of the DSP56300 modular
chassis which is common to all DSP56300 family processors and includes a detailed
description of the instruction set. This document provides a detailed description of the core
configuration, memory, and peripherals that are specific to the DSP56364. The electrical
specifications, timings and packaging information can be found in the DSP56364 Technical
Data Sheet.
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DSP56364
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1-1
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DSP56364 Overview
Features
12
5
PM_EB
ADDRESS
GENERATION UNIT
0.5K x 24
PROGRAM ROM
8K x 24
BootstrapROM
192x24
PIO_EB
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PERIPHERAL
EXPANSION
AREA
PROGRAM
RAM
YAB
XAB
PAB
DAB
SIX CHANNELS
DMA UNIT
X
MEMORY
RAM
1KX24
YMEMORY
RAM
1.5KX24
YM_EB
SHI
ESAI
GPIO
XM_EB
4
MEMORY
EXPANSION
AREA
ADDRESS
EXTERNAL
ADDRESS BUS
18
SWITCH
24-BIT
DSP56300
CORE
DRAM &SRAM
BUS
INTERFACE
CONTROL
6
DDB
YDB
INTERNAL
DATA BUS
SWITCH
EXTERNAL
DATABUS
SWITCH
XDB
PDB
DATA
8
GDB
POWER
MGMT
PLL
PROGRAM
DECODE
CONT
PROGRAM
INTERRUPT
CONT
CLOCK
GEN
EXTAL
PROGRAM
ADDRESS
GEN
DATA ALU
24X24+56→56-BITMAC
TWO56-BITACCUMULATORS
BARRELSHIFTER
PINIT/NMI
4
24 BITS BUS
MODA/IRQA
MODB/IRQB
MODD/IRQD
RESET
JTAG
OnCE™
Figure 1-1 DSP56364 Block Diagram
1.2
FEATURES
DSP56300 modular chassis
— 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
— Object Code Compatible with the 56K core.
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Features
— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit
arithmetic support.
— Program Control with position independent code support and instruction cache
support.
— Six-channel DMA controller.
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— PLL based clocking with a wide range of frequency multiplications (1 to 4096),
predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces
clock noise.
— Internal address tracing support and OnCE‰ for Hardware/Software debugging.
— JTAG port.
— Very low-power CMOS design, fully static design with operating frequencies down
to DC.
— STOP and WAIT low-power standby modes.
• On-chip Memory Configuration
— 1.5Kx24 Bit Y-Data RAM.
— 1Kx24 Bit X-Data RAM.
— 8Kx24 Bit Program ROM.
— 0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM.
— 0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to
1.25Kx24 Bit of Program RAM.
• Off-chip memory expansion
— External Memory Expansion Port with 8-bit data bus.
— Off-chip expansion up to 2 x 16M x 8-bit word of Data memory when using DRAM.
— Off-chip expansion up to 2 x 256k x 8-bit word of Data memory when using SRAM.
— Simultaneous glueless interface to SRAM and DRAM.
• Peripheral modules
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Audio Prodessor Architecture
— Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or
slave. I2S, Sony, AC97, network and other programmable protocols. Unused pins of
ESAI may be used as GPIO lines.
— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word
receive FIFO, support for 8, 16 and 24-bit words.
— Four dedicated GPIO lines.
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• 100-pin plastic TQFP package.
1.3
AUDIO PRODESSOR ARCHITECTURE
This section defines the DSP56364 audio processor architecture. The audio processor is
composed of the following units:
• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program
Controller, Instruction-Cache Controller, DMA Controller, PLL-based clock oscillator,
Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator
(OnCE). The DSP56300 core is described in the document DSP56300 24-Bit Digital
Signal Processor Family Manual, Motorola publication DSP56300FM/AD.
• Memory modules.
• Peripheral modules. The SHI, ESAI and GPIO peripheral are described in this document.
See Figure 1-1 for the block diagram of the DSP56364.
1.4
CORE DESCRIPTION
The DSP56366 uses the DSP56300 core, a high-performance, single clock cycle per
instruction engine that provides up to twice the performance of Motorola's popular DSP56000
core family while retaining code compatibility with it.
The DSP56300 core provides the following functional blocks:
•
Data arithmetic logic unit (Data ALU)
•
Address generation unit (AGU)
•
Program control unit (PCU)
•
Bus interface unit (BIU)
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DSP56300 Core Functional Blocks
•
DMA controller (with six channels)
•
Instruction cache controller
•
PLL-based clock oscillator
•
OnCE module
•
JTAG TAP
•
Memory
The DSP56300 core family offers a new level of performance in speed and power, provided
by its rich instruction set and low power dissipation, thus enabling a new generation of
wireless, telecommunications, and multimedia products. Significant architectural
enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an
instruction cache, and direct memory access (DMA).
Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and
peripheral features are described in this manual.
1.5
1.5.1
DSP56300 CORE FUNCTIONAL BLOCKS
DATA ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. The components of the Data ALU are as follows:
•
Fully pipelined 24-bit x 24-bit parallel multiplier-accumulator (MAC)
•
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
•
Conditional ALU instructions
•
24-bit or 16-bit arithmetic support under software control
•
Four 24-bit input general purpose registers: X1, X0, Y1, and Y0
•
Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general purpose, 56-bit accumulators (A and B), accumulator shifters
•
Two data bus shifter/limiter circuits
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DSP56300 Core Functional Blocks
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1.5.1.1
Data ALU Registers
The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y
memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit
arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16,
32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The
results of all Data ALU operations are stored in an accumulator.
All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a
new instruction can be initiated in every clock, yielding an effective execution rate of one
instruction per clock cycle. The destination of every arithmetic operation can be used as a
source operand for the immediately following arithmetic operation without a time penalty
(i.e., without a pipeline stall).
1.5.1.2
Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. In the case of arithmetic instructions, the
unit accepts as many as three input operands and outputs one 56-bit result of the following
form- Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between
two’s-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored
as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is
performed if specified.
1.5.2
ADDRESS GENERATION UNIT (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers used to generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has
four sets of register triplets, and each register triplet is composed of an address register, an
offset register, and a modifier register. The two Address ALUs are identical. Each contains a
24-bit full adder (called an offset adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided.
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DSP56300 Core Functional Blocks
The offset adder and the reverse-carry adder are in parallel and share common inputs. The
only difference between them is that the carry propagates in opposite directions. Test logic
determines which of the three summed results of the full adders is output.
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Each Address ALU can update one address register from its respective address register file
during one instruction cycle. The contents of the associated modifier register specifies the
type of arithmetic to be used in the address register update calculation. The modifier value is
decoded in the Address ALU.
1.5.3
PROGRAM CONTROL UNIT (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and
exception processing. The PCU implements a seven-stage pipeline and controls the different
processing states of the DSP56300 core. The PCU consists of the following three hardware
blocks:
•
Program decode controller (PDC)
•
Program address generator (PAG)
•
Program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all
signals necessary for pipeline control. The PAG contains all the hardware needed for program
address generation, system stack, and loop control. The PIC arbitrates among all interrupt
requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQD, and
NMI), and generates the appropriate interrupt vector address.
PCU features include the following:
•
Position independent code support
•
Addressing modes optimized for DSP applications (including immediate offsets)
•
On-chip instruction cache controller
•
On-chip memory-expandable hardware stack
•
Nested hardware DO loops
•
Fast auto-return interrupts
The PCU implements its functions using the following registers:
•
PC—program counter register
•
SR—Status register
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DSP56300 Core Functional Blocks
•
LA—loop address register
•
LC—loop counter register
•
VBA—vector base address register
•
SZ—stack size register
•
SP—stack pointer
•
OMR—operating mode register
•
SC—stack counter register
The PCU also includes a hardware system stack (SS).
1.5.4
INTERNAL BUSES
To provide data exchange between blocks, the following buses are implemented:
•
Peripheral input/output expansion bus (PIO_EB) to peripherals
•
Program memory expansion bus (PM_EB) to program memory
•
X memory expansion bus (XM_EB) to X memory
•
Y memory expansion bus (YM_EB) to Y memory
•
Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and
PCU as well as the memory-mapped registers in the peripherals
•
DMA data bus (DDB) for carrying DMA data between memories and/or peripherals
•
DMA address bus (DAB) for carrying DMA addresses to memories and peripherals
•
Program Data Bus (PDB) for carrying program data throughout the core
•
X memory Data Bus (XDB) for carrying X data throughout the core
•
Y memory Data Bus (YDB) for carrying Y data throughout the core
•
Program address bus (PAB) for carrying program memory addresses throughout the
core
•
X memory address bus (XAB) for carrying X memory addresses throughout the core
•
Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1,
DSP56364 block diagram.
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DSP56300 Core Functional Blocks
1.5.5
DIRECT MEMORY ACCESS (DMA)
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The DMA block has the following features:
•
Six DMA channels supporting internal and external accesses
•
One-, two-, and three-dimensional transfers (including circular buffering)
•
End-of-block-transfer interrupts
•
Triggering from interrupt lines and all peripherals
1.5.6
PLL-BASED CLOCK OSCILLATOR
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator (CLKGEN), which performs low-power division and clock pulse generation.
PLL-based clocking:
•
Allows change of low-power divide factor (DF) without loss of lock
•
Provides output clock with skew elimination
•
Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to
16), and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low
frequency clock input. This feature offers two immediate benefits:
•
A lower frequency clock input reduces the overall electromagnetic interference
generated by a system.
•
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
1.5.7
JTAG TAP AND ONCE MODULE
The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with
testing high-density circuit boards led to developing this standard under the sponsorship of the
Test Technology Committee of IEEE and JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard.
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Data and Program memory
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and
three test data registers. A boundary scan register links all device signals into a single shift
register. The test logic, implemented utilizing static logic design, is independent of the device
system logic.
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The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and
its peripherals so a user can examine registers, memory, or on-chip peripherals. This
facilitates hardware and software development on the DSP56300 core processor. OnCE
module functions are provided through the JTAG TAP signals.
1.6
DATA AND PROGRAM MEMORY
The on-chip memory configuration of the DSP56364 is affected by the state of the MS
(Memory Switch) control bit in the OMR register, and by the SC bit in the Status Register.
Refer to Section 3.
1.6.1
RESERVED MEMORY SPACES
The reserved memory spaces should not be accessed by the user. They are reserved for future
expansion.
1.6.2
PROGRAM ROM AREA RESERVED FOR MOTOROLA USE
The last 128 words ($FF2F80-$FF2FFF) of the Program ROM are reserved for Motorola use.
This memory area is reserved for use as expansion area for the bootstrap ROM as well as for
testing purposes. Customer code should not use this area. The contents of this Program ROM
segment is defined by the Bootstrap ROM source code in Appendix A.
1.6.3
BOOTSTRAP ROM
The 192-word Bootstrap ROM occupies locations $FF0000-$FF00BF. The bootstrap ROM is
factory-programmed to perform the bootstrap operation following hardware reset. The
contents of the Bootstrap ROM are defined by the Bootstrap ROM source code in Appendix
A.
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Data and Program memory
1.6.4
DYNAMIC MEMORY CONFIGURATION SWITCHING
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The internal memory configuration is altered by re-mapping RAM modules from Y data
memory into program memory space and vice-versa. The contents of the switched RAM
modules are preserved.
The memory can be dynamically switched from one configuration to another by changing the
MS bit in OMR. The address ranges that are directly affected by the switch operation are
specified in Table 3-1 The memory switch can be accomplished provided that the affected
address ranges are not being accessed during the instruction cycle in which the switch
operation takes place. Accordingly, the following condition must be observed for trouble-free
dynamic switching:
NOTE
No accesses (including instruction fetches) to or from the
affected address ranges in program and data memories
are allowed during the switch cycle.
NOTE
The switch cycle actually occurs 3 instruction cycles after
the instruction that modifies the MS bit.
Any sequence that complies with the switch condition is valid. For example, if the program
flow executes in the address range that is not affected by the switch, the switch condition can
be met very easily. In this case a switch can be accomplished by just changing the MS bit in
OMR in the regular program flow, assuming no accesses to the affected address ranges of the
data memory occur up to 3 instructions after the instruction that changes the OMR bit. Special
care should be taken in relation to the interrupt vector routines since an interrupt could cause
the DSP to fetch instructions out of sequence and might violate the switch condition.
Special attention should be given when running a memory switch routine using the OnCE™
port. Running the switch routine in Trace mode, for example, can cause the switch to
complete after the MS bit change while the DSP is in Debug mode. As a result, subsequent
instructions might be fetched according to the new memory configuration (after the switch),
and thus might execute improperly.
1.6.5
EXTERNAL MEMORY SUPPORT
The DSP56364 does not support the SSRAM memory type. It does support SRAM and
DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual,
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Internal I/O Memory Map
Motorola publication DSP56300FM/AD. Note that the DSP56364 has only an 8-bit data bus.
This means that no instruction fetches from external memory are possible, and care should be
taken to ensure that no program memory instruction fetch access occurs in the external
memory space. The DMA may be used to automatically pack and unpack 24-bit data into the
8-bit wide external memory, during DMA data transfers.
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Also, care should be taken when accessing external memory to ensure that the necessary
address lines are available. For example, when using glueless SRAM interfacing, it is possible
to directly address 219 memory locations (512K) when using the 18 address lines and the two
programmable address attribute lines. Using DRAM access mode, the full 16M addressing
range may be used.
1.7
INTERNAL I/O MEMORY MAP
The DSP56364 on-chip peripheral modules have their register files programmed to the
addresses in the internal X-I/O memory range (the top 128 locations of the X data memory
space). See Section 3.
1.8
STATUS REGISTER (SR)
Refer to the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD for a description of the Status Register bits.
The Cache Enable bit (Bit 19) in the Status Register must be kept cleared since the DSP56364
does not have an on-chip instruction cache.
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SECTION
2
SIGNAL/CONNECTION DESCRIPTIONS
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2.1
SIGNAL GROUPINGS
The input and output signals of the DSP56364 are organized into functional groups, which are
listed in Table 2-1 and illustrated in Figure 2-1.
The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V.
A special notice for this feature is added to the signal descriptions of those inputs.
Table 2-1 DSP56364 Functional Signal Groupings
Number of Signals
Detailed
Description
Power (VCC)
18
Table 2-2
Ground (GND)
14
Table 2-3
Clock and PLL
3
Table 2-4
18
Table 2-5
Data bus
8
Table 2-6
Bus control
6
Table 2-7
Interrupt and mode control
4
Table 2-8
4
Table 2-12
5
Table 2-9
12
Table 2-10
4
Table 2-11
Functional Group
Address bus
Port A1
General Purpose I/O
Port B2
SHI
Port C3
ESAI
JTAG/OnCE Port
Note:
Note:
Note:
1.
Port A is the external memory interface port, including the external address bus, data bus, and
control signals.
Port B signals are the GPIO signals.
Port C signals are the ESAI port signals multiplexed with the GPIO signals.
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Signal/Connection Descriptions
Signal Groupings
OnCE ON-CHIP EMULATION/
JTAG PORT
PORT A ADDRESS BUS
TDI
TCK
TDO
TMS
A0-A17
VCCA (4)
GNDA (4)
DSP56364
PORT A DATA BUS
D0-D7
VCCD (1)
Port B
GPIO
PB0-PB3
GNDD (1)
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PORT A BUS CONTROL
AA0-AA1/RAS0-RAS1
CAS
RD
WR
TA
VCCC (1)
GNDC (1)
RESERVED (4)
SERIAL AUDIO INTERFACE (ESAI
Port C
INTERRUPT AND
MODE CONTROL
MODA/IRQA
MODB/IRQB
MODD/IRQD
RESET
PLL AND CLOCK
PINIT/NMI
SCKT [PC3]
FST [PC4]
HCKT [PC5]
SCKR [PC0]
FSR [PC1]
HCKR [PC2]
SDO0 [PC11]
SDO1 [PC10]
SDO2/SDI3 [PC9]
SDO3/SDI2 [PC8]
SDO4/SDI1 [PC7]
SDO5/SDI0 [PC6]
VCCSS (3)
GNDS (3)
SERIAL HOST INTERFACE (SHI)
PCAP
VCCP
GNDP
MOSI/HA0
SS/HA2
MISO/SDA
SCK/SCL
EXTAL
HREQ
QUIET POWER
VCCHQ (4)
VCCLQ (4)
GNDQ (4)
Figure 2-1 Signals Identified by Functional Group
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Signal/Connection Descriptions
Power
2.2
POWER
Table 2-2 Power Inputs
Power Name
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VCCP
Description
PLL Power—VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be
provided with an extremely low impedance path to the VCC power rail. There is one VCCP input.
VCCQL (4)
Quiet Core (Low) Power—VCCQL is an isolated power for the internal processing logic. This input must be tied
externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four
VCCQL inputs.
VCCQH (4)
Quiet External (High) Power—VCCQH is a quiet power source for I/O lines. This input must be tied externally to all
other chip power inputs. The user must provide adequate decoupling capacitors. There are four VCCQH inputs.
VCCA (4)
Address Bus Power—VCCA is an isolated power for sections of the address bus
I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external
decoupling capacitors. There are four VCCA inputs.
VCCD (1)
Data Bus Power—VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally
to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCD
inputs.
VCCC (1)
Bus Control Power—VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all
other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCC inputs.
VCCS (3)
SHI and ESAI —VCCS is an isolated power for the SHI and ESAI. This input must be tied externally to all other chip
power inputsL. The user must provide adequate external decoupling capacitors. There are three VCCS inputs.
2.3
GROUND
Table 2-3 Grounds
Ground Name
Description
GNDP
PLL Ground—GNDP is ground-dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to
the chip package. There is one GNDP connection.
GNDQ (4)
Quiet Ground—GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally
to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four
GNDQ connections.
GNDA (4)
Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
There are four GNDA connections.
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Clock and PLL
Table 2-3 Grounds (Continued)
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Ground Name
Description
GNDD (1)
Data Bus Ground—GNDD is an isolated ground for sections of the data bus
I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There is one GNDD connections.
GNDC (1)
Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is
one GNDC connections.
GNDS (3)
SHI and ESAI —GNDS is an isolated ground for the SHI and ESAI. This connection must be tied externally to all other
chip ground connections. The user must provide adequate external decoupling capacitors. There are three GND S
connections.
2.4
CLOCK AND PLL
Table 2-4 Clock and PLL Signals
Signal Name
Signal
Type
State
during
Reset
EXTAL
Input
Input
External Clock Input—An external clock source must be connected to EXTAL in order to
supply the clock to the internal clock generator and PLL.
PCAP
Input
Input
PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect
one capacitor terminal to PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of PINIT/NMI is
written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is
enabled or disabled. After RESET de assertion and during normal instruction processing, the
PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI)
request internally synchronized to internal system clock.
This input is 5 V tolerant.
2.5
Signal Description
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant
port A signals: D0–D7, AA0, AA1, RD, WR, CAS.
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
2.5.1
EXTERNAL ADDRESS BUS
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Table 2-5 External Address Bus Signals
Signal Name
Signal
Type
A0–A17
Output
2.5.2
State
during
Reset
Keeper
active
Signal Description
Address Bus—A0–A17 are active-high outputs that specify the address for external
program and data memory accesses. Otherwise, the signals are kept to their previous values
by internal weak keepers. To minimize power dissipation, A0–A17 do not change state
when external memory spaces are not being accessed.
EXTERNAL DATA BUS
Table 2-6 External Data Bus Signals
Signal Name
Signal Type
State during Reset
Signal Description
D0–D7
Input/Output
Tri-stated
Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide
the bidirectional data bus for external program and data memory accesses.
D0–D7 are tri-stated during hardware reset and when the DSP is in the stop
or wait low-power standby mode.
2.5.3
EXTERNAL BUS CONTROL
Table 2-7 External Bus Control Signals
Signal
Name
Signal
Type
State
during
Reset
AA0–AA1/
RAS0–RAS
1
Output
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these signals can be used as
chip selects or additional address lines. When defined as RAS, these signals can be used as RAS
for DRAM interface. These signals are tri-statable outputs with programmable polarity. These
signals are tri-stated during hardware reset and when the DSP is in the stop or wait low-power
standby mode.
CAS
Output
Tri-stated
Column Address Strobe— CAS is an active-low output used by DRAM to strobe the column
address. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait
low-power standby mode.
RD
Output
Tri-stated
Read Enable—RD is an active-low output that is asserted to read external memory on the data
bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait
low-power standby mode.
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Interrupt and Mode Control
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Table 2-7 External Bus Control Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
WR
Output
Tri-stated
Write Enable— WR is an active-low output that is asserted to write external memory on the data
bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait
low-power standby mode.
TA
Input
Ignored
Input
Transfer Acknowledge—If there is no external bus activity, the TA input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted
by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus
cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus
cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the
internal system clock. The number of wait states is determined by the TA input or by the bus
control register (BCR), whichever is longer. The BCR can be used to set the minimum number of
wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one wait state. A
zero wait state access cannot be extended by TA deassertion, otherwise improper operation may
result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit
in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses, otherwise improper
operation may result.
2.6
Signal Description
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 2-8 Interrupt and Mode Control
Signal Name
Signal
Type
State
during
Reset
MODA/IRQA
Input
Input
2-6
Signal Description
Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low Schmitt-trigger
input, internally synchronized to the internal system clock. MODA/IRQA selects the initial chip
operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input during normal instruction processing. MODA, MODB, and
MODD select one of 8 initial chip operating modes, latched into the OMR when the RESET
signal is deasserted. If IRQA is asserted synchronous to the internal system clock, multiple
processors can be re synchronized using the WAIT instruction and asserting IRQA to exit the wait
state. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the
stop state.
This input is 5 V tolerant.
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Interrupt and Mode Control
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Table 2-8 Interrupt and Mode Control (Continued)
Signal Name
Signal
Type
State
during
Reset
MODB/IRQB
Input
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low Schmitt-trigger
input, internally synchronized to the internal system clock. MODB/IRQB selects the initial chip
operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input during normal instruction processing. MODA, MODB, and
MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is
deasserted. If IRQB is asserted synchronous to the internal system clock, multiple processors can
be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state.
This input is 5 V tolerant.
MODD/IRQD
Input
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low Schmitt-trigger
input, internally synchronized to the internal system clock. MODD/IRQD selects the initial chip
operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input during normal instruction processing. MODA, MODB, and
MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is
deasserted. If IRQD is asserted synchronous to the internal system clock, multiple processors can
be re synchronized using the WAIT instruction and asserting IRQD to exit the wait state.
This input is 5 V tolerant.
RESET
Input
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the
reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly
rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODD
inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be
supplied before deassertionof RESET.
This input is 5 V tolerant.
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Serial Host Interface
2.7
SERIAL HOST INTERFACE
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or
I2C mode.
Table 2-9 Serial Host Interface Signals
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Signal
Name
Signal Type
SCK
Input or
output
SCL
Input or
output
State during
Reset
Tri-stated
Signal Description
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and a
Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a
master, the SCK signal is derived from the internal SHI clock generator. When the SPI is
configured as a slave, the SCK signal is an input, and the clock signal from the external master
synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and
the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted
on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge
polarity is determined by the SPI transfer protocol.
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a
Schmitt-trigger input when configured as a slave and an open-drain output when configured as a
master. SCL should be connected to VCC through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for
an external pull-up in this state.
This input is 5 V tolerant.
MISO
Input or
output
SDA
Input or
open-drain
output
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the master data
input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and
receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master
mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI
Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation.
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when receiving and
an open-drain output when transmitting. SDA should be connected to VCC through a pull-up
resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high
period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is
free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case
of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique
situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a
unique situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for
an external pull-up in this state.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Serial Host Interface
Table 2-9 Serial Host Interface Signals (Continued)
Signal
Name
Signal Type
MOSI
Input or
output
HA0
Input
State during
Reset
Tri-stated
Signal Description
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the master data
output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and
receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This
signal is a Schmitt-trigger input when configured for the SPI Slave mode.
I2C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the I2C
mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device
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address. HA0 is ignored when configured for the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for
an external pull-up in this state.
This input is 5 V tolerant.
SS
Input
Input
SPI Slave Select—This signal is an active low Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for
transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled
high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is
deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance
state.
I2C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I2C
HA2
mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device
address. HA2 is ignored in the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for
an external pull-up in this state.
This input is 5 V tolerant.
HREQ
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when configured for the master
mode but an active low output when configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the
next data word transfer and deasserted at the first clock pulse of the new data word transfer. When
configured for the master mode, HREQ is an input. When asserted by the external slave device, it
will trigger the start of the data word transfer by the master. After finishing the data word transfer,
the master will await the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0
bits in the HCSR are cleared. There is no need for external pull-up in this state.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
2.8
ENHANCED SERIAL AUDIO INTERFACE
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Table 2-10 Enhanced Serial Audio Interface Signals
Signal
Name
Signal Type
State during Reset
Signal Description
HCKR
Input or output
GPIO disconnected
High Frequency Clock for Receiver—When programmed as an input, this signal
provides a high frequency clock source for the ESAI receiver as an alternate to the
DSP core clock. When programmed as an output, this signal can serve as a
high-frequency sample clock (e.g., for external digital to analog converters [DACs])
or as an additional system clock.
PC2
Input, output, or
disconnected
Port C 2—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
HCKT
Input or output
PC5
Input, output, or
disconnected
GPIO disconnected
High Frequency Clock for Transmitter—When programmed as an input, this
signal provides a high frequency clock source for the ESAI transmitter as an
alternate to the DSP core clock. When programmed as an output, this signal can
serve as a high frequency sample clock (e.g., for external DACs) or as an additional
system clock.
Port C 5—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
FSR
Input or output
GPIO disconnected
Frame Sync for Receiver—This is the receiver frame sync input/output signal. In
the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or
output used by all the enabled receivers. In the synchronous mode (SYN=1), it
operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external
buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this pin
will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1
bit will show up at the pin synchronized to the frame sync in normal mode or the slot
in network mode. When configured as the input flag IF1, the data value at the pin
will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PC1
Input, output, or
disconnected
Port C 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Table 2-10 Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during Reset
Signal Description
FST
Input or output
GPIO disconnected
Frame Sync for Transmitter—This is the transmitter frame sync input/output
signal. For synchronous mode, this signal is the frame sync for both transmitters and
receivers. For asynchronous mode, FST is the frame sync for the transmitters only.
The direction is determined by the transmitter frame sync direction (TFSD) bit in
the ESAI transmit clock control register (TCCR).
PC4
Input, output, or
disconnected
Port C 4—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKR
Input or output
GPIO disconnected
Receiver Serial Clock—SCKR provides the receiver serial bit clock for the ESAI.
The SCKR operates as a clock input or output used by all the enabled receivers in
the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode
(SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the
RCKD bit in the RCCR register. When configured as the output flag OF0, this pin
will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0
bit will show up at the pin synchronized to the frame sync in normal mode or the slot
in network mode. When configured as the input flag IF0, the data value at the pin
will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PC0
Input, output, or
disconnected
Port C 0—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKT
PC3
Input or output
Input, output, or
disconnected
GPIO disconnected
Transmitter Serial Clock—This signal provides the serial bit rate clock for the
ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers
in synchronous mode, or by all enabled transmitters in asynchronous mode.
Port C 3—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
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Table 2-10 Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during Reset
SDO5
Output
GPIO disconnected
SDI0
Input
PC6
Input, output, or
disconnected
Signal Description
Serial Data Output 5—When programmed as a transmitter, SDO5 is used to
transmit data from the TX5 serial transmit shift register.
Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive
serial data into the RX0 serial receive shift register.
Port C 6—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO4
Output
SDI1
Input
PC7
Input, output, or
disconnected
GPIO disconnected
Serial Data Output 4—When programmed as a transmitter, SDO4 is used to
transmit data from the TX4 serial transmit shift register.
Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive
serial data into the RX1 serial receive shift register.
Port C 7—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO3
Output
SDI2
Input
PC8
Input, output, or
disconnected
GPIO disconnected
Serial Data Output 3—When programmed as a transmitter, SDO3 is used to
transmit data from the TX3 serial transmit shift register.
Serial Data Input 2—When programmed as a receiver, SDI2 is used to receive
serial data into the RX2 serial receive shift register.
Port C 8—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO2
Output
SDI3
Input
PC9
Input, output, or
disconnected
GPIO disconnected
Serial Data Output 2—When programmed as a transmitter, SDO2 is used to
transmit data from the TX2 serial transmit shift register
Serial Data Input 3—When programmed as a receiver, SDI3 is used to receive
serial data into the RX3 serial receive shift register.
Port C 9—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
JTAG/OnCE Interface
Table 2-10 Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during Reset
Signal Description
SDO1
Output
GPIO disconnected
Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit
shift register.
PC10
Input, output, or
disconnected
Port C 10—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
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This input is 5 V tolerant.
SDO0
Output
GPIO disconnected
PC11
Input, output, or
disconnected
Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial transmit
shift register.
Port C 11—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
2.9
JTAG/OnCE INTERFACE
Table 2-11 JTAG/OnCE Interface
Signal
Name
Signal
Type
State
during
Reset
TCK
Input
Input
Signal Description
Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an
internal pull-up resistor.
This input is 5 V tolerant.
TDI
Input
Input
Test Data Input—TDI is a test data serial input signal used for test instructions and data. TDI is
sampled on the rising edge of TCK and has an internal pull-up resistor.
This input is 5 V tolerant.
TDO
Output
Tri-stated
TMS
Input
Input
Test Data Output—TDO is a test data serial output signal used for test instructions and data. TDO
is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on
the falling edge of TCK.
Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine.
TMS is sampled on the rising edge of TCK and has an internal pull-up resistor.
This input is 5 V tolerant.
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Signal/Connection Descriptions
GPIO Signals
2.10
GPIO SIGNALS
Table 2-12 GPIO Signals
Signal Type
GPIO0GPIO3
Input, output or
disconnected
State during
Reset
disconnected
Signal Description
GPIO0-3- The General Purpose I/O pins are used for control and handshake functions
between the DSP and external circuitry. Each Port B GPIO pin may be individually
programmed as an input, output or disconnected
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Signal
Name
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SECTION
3
MEMORY CONFIGURATION
3.1
MEMORY SPACES
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The DSP56364 provides the following three independent memory spaces:
•
Program
•
X data
•
Y data
Each memory space uses (by default) 18 external address lines for addressing, allowing access
to 256K of external memory when using the SRAM operating mode, and 16 M when using the
DRAM operating mode. Program and data word length is 24 bits, and internal memory uses
24-bit addressing.
The DSP56364 provides a 16-bit compatibility mode that effectively uses 16-bit addressing
for each memory space, allowing access to 64K of memory for each. This mode puts zeros in
the most significant byte of the usual (24-bit) program and data word and ignores the zeroed
byte, thus effectively using 16-bit program and data words. The 16-bit Compatibility mode
allows the DSP56364 to use 56000 object code without change (thus minimizing system cost
for applications that use the smaller address space). See the DSP56300 Family Manual,
Section 6.4, for further information.
3.1.1
PROGRAM MEMORY SPACE
Program memory space consists of the following:
•
Internal program memory, consisting of program RAM, 0.5K by default, and program
ROM, 8K x 24-bit
•
Bootstrap program ROM (192 x 24-bit)
3.1.1.1
Program RAM
On-chip program RAM occupies the lowest 0.5K (default) or 1.25K locations in the program
memory space (depending on the setting of the MS bit). The program RAM default
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Memory Configuration
Memory Spaces
organization is 2 banks of 256 24-bit words (0.5K). The upper 3 banks of Y data RAM can be
configured as program RAM by setting the MS bit.
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3.1.1.2
Program ROM
The program ROM contains customer-supplied code. For further information on supplying
code for a customized DSP56364 program ROM, please contact your Motorola regional sales
office.
The last 128 words ($FF2F80-$FF2FFF) of the program ROM are reserved for Motorola use.
This memory area is reserved for use as expansion area for the bootstrap ROM as well as for
testing purposes. Customer code should not use this area. The contents of this program ROM
segment is defined by the bootstrap ROM source code in Appendix A.
3.1.1.3
Bootstrap ROM
The bootstrap code is accessed at addresses $FF0000 to $FFF0BF (192 words) in program
memory space. The bootstrap ROM is factory-programmed to perform the bootstrap operation
following hardware reset. The bootstrap ROM can not be accessed in 16-bit address
compatibility mode. See Appendix A for a complete listing of the bootstrap code.
3.1.1.4
Reserved Program Memory Locations
Program memory space at locations $FF00C0 to $FF0FFF and $FF3000 to $FFFFFF is
reserved and should not be accessed.
3.1.2
DATA MEMORY SPACES
Data memory space is divided into X data memory and Y data memory to match the natural
partitioning of DSP algorithms. The data memory partitioning allows the DSP56364 to feed
two operands to the Data ALU simultaneously, enabling it to perform a multiply-accumulate
operation in one clock cycle.
X and Y data memory space are similar in structure and functionality, but there are two
differences between them. First, part of Y data RAM may be switched over to program RAM,
while X data RAM is fixed in size. Second, the upper 128 words of each space are reserved
for different uses. The upper 128 words of X data memory are reserved for internal I/O. It is
suggested that the programmer reserve the upper 128 words of Y data memory for external
I/O. (For further information, see Section 3.1.2.1 and Section 3.1.2.3.)
X and Y data memory space each consist of the following:
•
3-2
Internal data RAM memory (X data RAM (1K), and Y data RAM (default size is
1.5K, but 0.75K of Y data RAM can be switched to program RAM)
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Memory Configuration
Memory Spaces
•
(Optionally) Off-chip memory expansion (up to 256K in the 24-bit address mode and
64K in the 16-bit address mode).
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3.1.2.1
X Data Memory Space
The on-chip peripheral registers and some of the DSP56364 core registers occupy the top 128
locations of X data memory ($FFFF80–$FFFFFF in the 24-bit address mode or
$FF80–$FFFF in the 16-bit address mode). This area is called X-I/O space, and it can be
accessed by MOVE and MOVEP instructions and by bit oriented instructions (BCHG, BCLR,
BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For a
listing of the contents of this area, see the programming sheets in Appendix D.
The reserved X memory space from $FF0000 to $FFEFFF should not be accessed.
3.1.2.2
X Data RAM
The on-chip X data RAM consists of 24-bit wide, high-speed, internal static RAM occupying
1K locations in the X memory space. The X data RAM organization is 4 banks of 256 24-bit
words.
3.1.2.3
Y Data Memory Space
The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80–$FFFFFF in the 24-bit address mode or $FF80–$FFFF in the 16-bit
address mode) to take advantage of the move peripheral data (MOVEP) instruction and the bit
oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).
The reserved Y memory space from $FF0000 to $FFEFFF should not be accessed.
3.1.2.4
Y Data RAM
The on-chip Y data RAM consists of 24-bit wide, high-speed, internal static RAM occupying
1.5K (default) or 0.75K locations in the Y memory space. The size of the Y data RAM is
dependent on the setting of the MS bit (default: MS is cleared). The Y data RAM default
organization is 6 banks of 256 24-bit words. Three banks of RAM may be switched to
program RAM by setting the MS bit.
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Memory Configuration
Memory Space Configuration
3.2
MEMORY SPACE CONFIGURATION
Memory space addressing is for 24-bit words by default. The DSP56364 switches to 16-bit
address compatibility mode by setting the 16-bit compatibility (SC) bit in the SR.
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Table 3-1 Memory Space Configuration Bit Settings for the DSP56364
Bit Abbreviation
Bit Name
Bit Location
SC
16-bit Compatibility
SR 13
Cleared = 0 Effect
(Default)
Set = 1 Effect
16 M word address
space (24-bit word)
64 K word address
space (16-bit word)
Accessible external memory in the 24-bit mode is limited to a maximum of 512K when using
the SRAM operating mode and to 16M when using the DRAM operating mode.
Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-8.
3.3
INTERNAL MEMORY CONFIGURATION
The following subsections discuss the internal memory configuration of the DSP56364. The
size and location configurations for RAM and ROM for the DSP56364 are given below.
Table 3-2 Internal Memory Configurations
BIT
SETTINGS
MEMORY SIZES (24-BIT WORDS)
MS
SC
PROG.
RAM
PROG.
ROM
BOOT
ROM
X DATA
RAM
Y DATA
RAM
0
0
0.5K
8K
192
1K
1.5K
1
0
1.25K
8K
192
1K
0.75K
0
1
0.5K
n.a.
n.a.
1K
1.5K
1
1
1.25K
n.a.
n.a.
1K
0.75K
Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-4.
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Memory Configuration
Internal Memory Configuration
3.3.1
RAM LOCATIONS
The actual memory locations for program RAM and Y data RAM in their own memory space
are determined by the MS bit. The memory location of X data RAM is independent of the MS
bit. The addresses of the different RAMs are listed inTable 3-3.
Table 3-3 On-chip RAM Memory Locations
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BIT
SETTINGS
RAM MEMORY LOCATIONS
MS
SC
PROGRAM RAM
X DATA RAM
Y DATA RAM
0
X
$000000-$0001FF
$000000-$0003FF
$000000-$0005FF
1
X
$000000-$0004FF
$000000-$0003FF
$000000-$0002FF
3.3.2
ROM LOCATIONS
The actual memory locations for ROMs in their own memory space are fixed, but when the
SC bit is set (i. e. the chip is in 16-bit mode), the program ROM and the bootstrap ROM are
not accessible. ROM addresses are listed in Table 3-4
Table 3-4 On-chip ROM Memory Locations
BIT
SETTINGS
3.3.3
ROM MEMORY LOCATIONS
MS
SC
PROGRAM ROM
BOOT ROM
X
0
$FF1000-$FF2FFF
$FF0000-$FF00BF
X
1
no access
no access
DYNAMIC MEMORY CONFIGURATION SWITCHING
The internal memory configuration is altered by remapping RAM modules from Y data
memory into program memory space and vice-versa. The contents of the switched RAM
modules are preserved.
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Memory Configuration
Internal Memory Configuration
The memory can be dynamically switched from one configuration to another by changing the
MS bit in OMR. The address ranges that are directly affected by the switch operation are
specified in Table 3-3. The memory switch can be accomplished provided that the affected
address ranges are not being accessed during the instruction cycle in which the switch
operation takes place. For trouble-free dynamic switching, no accesses (including instruction
fetches) to or from the affected address ranges in program and data memories are allowed
during the switch cycle.
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Note:
The switch cycle actually occurs three instruction cycles after the instruction that
modifies the MS bit.
Any sequence that complies with the switch condition is valid. For example, if the program
flow executes in the address range that is not affected by the switch, the switch condition can
be met very easily. In this case a switch can be accomplished by just changing the MS bit in
OMR in the regular program flow, assuming no accesses to the affected address ranges of the
data memory occur up to three instructions after the instruction that changes the OMR bit.
Special care should be taken in relation to the interrupt vector routines since an interrupt could
cause the DSP to fetch instructions out of sequence and might violate the switch condition.
Special attention should be given when running a memory switch routine using the OnCE
port. Running the switch routine in trace mode, for example, can cause the switch to complete
after the MS bit change while the DSP is in debug mode. As a result, subsequent instructions
might be fetched according to the new memory configuration (after the switch), and thus
might execute improperly.
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Memory Configuration
Memory Maps
3.4
MEMORY MAPS
PROGRAM
$FFFFFF
INTERNAL
RESERVED
X DATA
$FFFFFF
$FFFF80
$FF3000
8K INTERNAL
INTERNAL
RESERVED
$FF00C0
$FFFF80
EXTERNAL
$FFF000
EXTERNAL I/O
(128 words)
EXTERNAL
INTERNAL
RESERVED
$FF0000
BOOT ROM
$FF0000
$FFFFFF
INTERNAL I/O
(128 words)
INTERNAL
RESERVED
ROM
$FF1000
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$FFF000
Y DATA
$FF0000
EXTERNAL
EXTERNAL
EXTERNAL
$000600
$000400
$000200
1K INTERNAL
0.5K INTERNAL
RAM
$000000
$000000
1.5K INTERNAL
RAM
$000000
RAM
Figure 3-1 Memory Maps for MS=0, SC=0
PROGRAM
$FFFFFF
X DATA
$FFFFFF
INTERNAL
RESERVED
$FFFF80
$FF3000
$FFF000
8K INTERNAL
INTERNAL
RESERVED
$FF00C0
$FF0000
BOOT ROM
$FF0000
EXTERNAL
$FFFFFF
$FFFF80
$FFF000
INTERNAL
RESERVED
ROM
$FF1000
INTERNAL I/O
(128 words)
Y DATA
EXTERNAL I/O
(128 words)
EXTERNAL
INTERNAL
RESERVED
$FF0000
EXTERNAL
EXTERNAL
EXTERNAL
$000500
$000400
$000300
1K INTERNAL
1.25K INTERNAL
$000000
RAM
$000000
RAM
0.75K INTERNAL
$000000
RAM
Figure 3-2 Memory Maps for MS=1, SC=0
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Memory Configuration
Memory Maps
PROGRAM
$FFFF
X DATA
$FFFF
$FF80
INTERNAL I/O
(128 words)
Y DATA
$FFFF
EXTERNAL I/O
(128 words)
$FF80
EXTERNAL
EXTERNAL
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EXTERNAL
$0600
$0400
$0200
1K INTERNAL
0.5K INTERNAL
$0000
RAM
$0000
RAM
1.5K INTERNAL
RAM
$0000
Figure 3-3 Memory Maps for MS=0, SC=1
PROGRAM
$FFFF
X DATA
$FFFF
$FF80
INTERNAL I/O
(128 words)
Y DATA
$FFFF
$FF80
EXTERNAL I/O
(128 words)
EXTERNAL
EXTERNAL
EXTERNAL
$0500
$0400
$0300
1K INTERNAL
1.25K INTERNAL
$0000
RAM
$0000
RAM
0.75K INTERNAL
$0000
RAM
Figure 3-4 Memory Maps for MS=1, SC=1
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Memory Configuration
External Memory Support
3.5
EXTERNAL MEMORY SUPPORT
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The DSP56364 does not support the SSRAM memory type. It does support SRAM and
DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual,
Motorola publication DSP56300FM/AD. Note that the DSP56364 has only an 8-bit data bus.
This means that no instruction fetches from external memory are possible, and care should be
taken to ensure that no program memory instruction fetch access occurs in the external
memory space. The DMA may be used to automatically pack and unpack 24-bit data into the
8-bit wide external memory, during DMA data transfers.
Also, care should be taken when accessing external memory to ensure that the necessary
address lines are available. For example, when using glueless SRAM interfacing, it is possible
to directly address 219 memory locations (512K) when using the 18 address lines and the two
programmable address attribute lines. Using DRAM access mode, the full 16M addressing
range may be used.
3.6
INTERNAL I/O MEMORY MAP
The DSP56364 on-chip peripheral modules have their register files programmed to the
addresses in the internal X-I/O memory range (the top 128 locations of the X data memory
space) as shown in Appendix C.
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Memory Configuration
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Internal I/O Memory Map
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SECTION
4
CORE CONFIGURATION
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4.1
INTRODUCTION
This chapter contains DSP56300 core configuration information details specific to the
DSP56364. These include the following:
•
Operating modes
•
Bootstrap program
•
Interrupt sources and priorities
•
DMA request sources
•
OMR
•
PLL control register
•
AA control registers
•
JTAG BSR
For more information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual (DSP56300FM/AD).
4.2
OPERATING MODE REGISTER (OMR)
The contents of the Operating Mode Register (OMR) are shown in Figure 4-1. Refer to the
DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD for a description of the OMR bits.
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Core Configuration
Operating Mode Register (OMR)
Figure 4-1 Operating Mode Register (OMR)
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APD
11
10
9
8
7
6
5
4
3
2
1
0
MA
ATE
12
MB
XYS
13
MC
14
MD
15
EBD
16
SD
17
MS
18
CDP1:0
19
COM
TAS
20
EUN
21
EOV
22
WRP
23
EOM
SEN
SCS
ATE
- Address Tracing Enable
MS
- Memory Switch Mode
APD
- Address Priority Disable
SD
- Stop Delay
EBD
- External Bus Disable
MD
- Operating Mode D
MC
- Operating Mode C - Always
set.
SEN
- Stack Extension Enable
WRP
- Extended Stack Wrap Flag
EOV
- Extended Stack Overflow
Flag
EUN
- Extended Stack Underflow
Flag
CDP1
- Core-Dma Priority 1
MB
- Operating Mode B
XYS
- Stack Extension Space Select
CDP0
- Core-Dma Priority 0
MA
- Operating Mode A
TAS
- TA Synchronize Select
- Reserved bit. Read as zero, should be written with zero for future compatibility
4.2.1
MODE C (MC) - BIT 2
The Mode C (MC) bit is set during hardware reset and should be left set in the DSP56364.
4.2.2
ADDRESS ATTRIBUTE PRIORITY DISABLE (APD) - BIT 14
The Address Attribute Priority Disable (APD) bit is used to turn off the address attribute
priority mechanism. When this bit is set, more than one address attribute pin AA/RAS(1:0)
may be simultaneously asserted according to its AAR settings. The APD bit is cleared by
hardware reset.
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Core Configuration
Operating Modes
4.2.3
ADDRESS TRACING ENABLE (ATE) - BIT 15
The Address Tracing Enable (ATE) bit is used to turn on Address Tracing (AT) Mode. When
the AT Mode is enabled, the DSP56300 Core reflects the addresses of internal fetches and
program space moves (MOVEM) to the Address Bus (A0-A17), if the Address Bus is not
needed by the DSP56300 Core for external accesses. The ATE bit is cleared on hardware
reset.
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4.3
OPERATING MODES
The operating modes are as shown in Table 4-1 The operating modes are latched from MODA,
MODB and MODD pins during reset. Each operating mode is briefly described below. The
operation of all bootstrap modes is defined by the Bootstrap ROM source code in Appendix A.
Table 4-1 DSP56364 Operating Modes
MODE
MOD D
MOD B
MOD A
RESET
VECTOR
DESCRIPTION
$4
0
0
0
$FF0000
Jump to PROM starting address
$5
0
0
1
$FF0000
Bootstrap from byte-wide memory
$6
0
1
0
$FF0000
Reserved
$7
0
1
1
$FF0000
Reserved for Burn-in testing
$C
1
0
0
$FF0000
Reserved
$D
1
0
1
$FF0000
Bootstrap from SHI (slave SPI mode)
$E
1
1
0
$FF0000
Bootstrap from SHI (slave I2C mode, clock
freeze enabled)
$F
1
1
1
$FF0000
Bootstrap from SHI (slave I2C mode, clock
freeze disabled)
Mode 4
The DSP starts fetching instructions from the starting address of the
on-chip Program ROM.
Mode 5
The bootstrap program loads instructions through Port A from external
byte-wide memory starting at address P:$D00000. The bootstrap code
expects to read 3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the program words and
then 3 bytes for each program word to be loaded. The number of
words, the starting address and the program words are read least
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Core Configuration
Bootstrap Program
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significant byte first followed by the mid and then by the most
significant byte. The program words will be stored in contiguous PRAM
memory locations starting at the specified starting address. After
reading the program words, program execution starts from the same
address where loading started. The SRAM memory access type is
selected by the values in Address Attribute Register 1 (AAR1), with 31
wait states for each memory access. Address $D00000 is reflected as
address $00000 on Port A pins A0-A17.
Mode 6
Reserved.
Mode 7
Reserved for Burn-In testing.
Mode C
Reserved.
Mode D
In this mode, the internal PRAM is loaded from the Serial Host
Interface (SHI). The SHI operates in the SPI slave mode, with 24-bit
word width.The bootstrap code expects to read a 24-bit word
specifying the number of program words, a 24-bit word specifying the
address to start loading the program words and then a 24-bit word for
each program word to be loaded. The program words will be stored in
contiguous PRAM memory locations starting at the specified starting
address. After reading the program words, program execution starts
from the same address where loading started.
Mode E
Same as mode 5, except the SHI interface operates in the I2C slave
mode with clock freeze enabled.
Mode F
Same as mode 5, except the SHI interface operates in the I2C slave
mode with clock freeze disabled (compatible to DSP56000 family).
4.4
BOOTSTRAP PROGRAM
The bootstrap program is factory-programmed in an internal 192 word by 24-bit bootstrap
ROM located in program memory space at locations $FF0000–$FF00BF. The bootstrap
program can load any program RAM segment from an external byte-wide EPROM or the
SHI. The bootstrap program described here, and listed in Appendix A, is a default, which
may be modified or replaced by the customer.
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Core Configuration
Interrupt Priority Registers
On exiting the Reset state, the DSP56364 does the following:
1. Samples the MODA, MODB, and MODD signal lines
2. Loads their values into bits MA, MB, and MD in the OMR
The contents of the MA, MB, MC, and MD bits determine which bootstrap mode the
DSP56364 enters.
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See Table 4-1 for a tabular description of the mode bit settings for the operating modes.
The bootstrap program options can be invoked at any time by setting the appropriate MA,
MB, and MD bits in the OMR and jumping to the bootstrap program entry point, $FF0000.
The mode selection bits in the OMR can be set directly by software.It is recommended to keep
the MC bit set to 1.
In bootstrap modes 5, D, E, and F, the bootstrap program expects the following data sequence
when downloading the user program through an external port:
1. Three bytes defining the number of (24-bit) program words to be loaded
2. Three bytes defining the (24-bit) start address to which the user program loads in the
DSP56364 program memory
3. The user program (three bytes for each 24-bit program word). The program words will
be stored in contiguous PRAM memory locations starting at the specified starting
address.
The three bytes for each data sequence must be loaded with the least significant byte first.
Once the bootstrap program completes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.5
INTERRUPT PRIORITY REGISTERS
There are two interrupt priority registers in the DSP56364: IPR-C is dedicated for DSP56300
Core interrupt sources and IPR-P is dedicated for DSP56364 peripheral interrupt sources. The
interrupt priority registers are shown in Figure 4-2 and Figure 4-3 The Interrupt Priority Level
bits are defined in Table 4-2. The interrupt vectors are shown in Table C-2 DSP56364
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Core Configuration
Interrupt Priority Registers
Interrupt Vectors on page Appendix C-5 and the interrupt priorities are shown in Table C-3
Interrupt Sources Priorities Within an IP on page Appendix C-7.
Table 4-2 Interrupt Priority Level Bits
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IPL BITS
4-6
INTERRUPTS
ENABLED
INTERRUPT
PRIORITY
LEVEL
XXL1
XXL0
0
0
No
—
0
1
Yes
0
1
0
Yes
1
1
1
Yes
2
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Core Configuration
Interrupt Priority Registers
11
10
9
8
7
6
5
4
3
2
1
0
SHL1
SHL0
ESL1
ESL0
ESAI IPL
SHI IPL
reserved
reserved
reserved
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reserved
22
23
21
20
19
18
17
16
15
14
13
12
reserved
Reserved bit. Read as zero, should be written with zero for future compatibility.
Figure 4-2 Interrupt Priority Register P
11
10
9
IDL2
IDL1
IDL1
8
7
6
5
IBL2
4
IBL1
3
IBL0
2
1
0
IAL2
IAL1
IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
reserved
reserved
IRQD IPL
IRQD mode
22
23
D5L1
D5L0
21
D4L1
20
19
18
17
16
15
14
13
12
D4L0
D3L1
D3L0
D2L1
D2L0
D1L1
D1L0
D0L1
D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
Reserved bit. Read as zero, should be written with zero for future compatibility.
Figure 4-3 Interrupt Priority Register C
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Core Configuration
DMA Request Sources
4.6
DMA REQUEST SOURCES
The DMA Request Source bits (DRS0-DRS4 bits in the DMA Control/Status registers) encode
the source of DMA requests used to trigger the DMA transfers. The DMA request sources may
be the internal peripherals or external devices requesting service through the IRQA, IRQB and
IRQD pins. The DMA Request Sources are shown in Table 4-3.
Table 4-3 DMA Request Sources
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DMA REQUEST SOURCE BITS
DRS4...DRS0
4.7
4.7.1
REQUESTING DEVICE
00000
External (IRQA pin)
00001
External (IRQB pin)
00010
Reserved
00011
External (IRQD pin)
00100
Transfer Done from DMA channel 0
00101
Transfer Done from DMA channel 1
00110
Transfer Done from DMA channel 2
00111
Transfer Done from DMA channel 3
01000
Transfer Done from DMA channel 4
01001
Transfer Done from DMA channel 5
01010
Reserved
01011
ESAI Receive Data (RDF=1)
01100
ESAI Transmit Data (TDE=1)
01101
SHI HTX Empty
01110
SHI FIFO Not Empty
01111
SHI FIFO Full
10000-11111
RESERVED
PLL AND CLOCK GENERATOR
PLL MULTIPLICATION FACTOR (MF0-MF11) - BITS 0-11
The DSP56364 PLL multiplication factor is set to 6 during hardware reset, i.e. the
Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $005.
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Core Configuration
Device Identification (ID) Register
4.7.2
CRYSTAL RANGE BIT (XTLR) - BIT 15
The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The
on-chip crystal oscillator is not used on the DSP56364 since no XTAL pin is available. The
XTLR bit is set to zero during hardware reset in the DSP56364.
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4.7.3
XTAL DISABLE BIT (XTLD) - BIT 16
The XTAL Disable Bit (XTLD) is set to 1 (XTAL disabled) during hardware reset in the
DSP56364.
4.7.4
CLOCK OUTPUT DISABLE BIT (COD) - BIT 19
The Clock Output Disable Bit (COD) is set to 0 during hardware reset. Since no clock output
pin is available in the DSP56364, this bit does not affect the functionality of the clock
generator.
4.7.5
PLL PRE-DIVIDER FACTOR (PD0-PD3) - BITS 20-23
The DSP56364 PLL Pre-Divider factor is set to 1 during hardware reset, i.e. the Pre-Divider
Factor Bits PD0-PD3 in the PLL Control Register (PCTL) are set to $0.
4.8
DEVICE IDENTIFICATION (ID) REGISTER
The Device Identification Register (IDR) is a 24 bit read only factory programmed register
used to identify the different DSP56300 core-based family members. This register specifies
the derivative number and revision number. This information may be used in testing or by
software. Table 4-4 shows the ID register configuration.
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Core Configuration
JTAG Identification (ID) Register
Table 4-4 Identification Register Configuration
23
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4.9
16
15
12
11
0
Reserved
Revision Number
Derivative Number
$00
$0
$364
JTAG IDENTIFICATION (ID) REGISTER
The JTAG Identification (ID) Register is a 32 bit, read only thought JTAG, factory
programmed register used to distinguish the component on a board according to the IEEE
1149.1 standard. Table 4-5 shows the JTAG ID register configuration.
Table 4-5 JTAG Identification Register Configuration
31
4.10
28
27
22
21
12
11
1
0
VERSION
INFORMATION
CUSTOMER PART
NUMBER
SEQUENCE
NUMBER
MANUFACTURER
IDENTITY
1
0000
000110
0001100100
00000001110
1
JTAG BOUNDARY SCAN REGISTER (BSR)
The boundary scan register (BSR) in the DSP56364 JTAG implementation contains bits for
all device signal and clock pins and associated control signals. All bidirectional pins have a
single register bit in the boundary scan register for pin data, and are controlled by an
associated control bit in the boundary scan register. The boundary scan register bit definitions
are described in Table 4-6 The BSDL file may be found in Appendix B.
Table 4-6 DSP56364 BSR Bit Definition
BIT
#
4-10
PIN NAME
PIN TYPE
BSR CELL
TYPE
GPIO3
-
GPIO3
GPIO2
BIT
#
PIN NAME
PIN TYPE
BSR CELL
TYPE
Control
WR
Output3
Data
Input/Output
Data
CAS
-
Control
-
Control
CAS
Output3
Data
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Core Configuration
JTAG Boundary Scan Register (BSR)
Table 4-6 DSP56364 BSR Bit Definition (Continued)
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BIT
#
PIN NAME
PIN TYPE
BSR CELL
TYPE
GPIO2
Input/Output
GPIO1
BIT
#
PIN NAME
PIN TYPE
BSR CELL
TYPE
Data
TA
Input
Data
-
Control
EXTAL
Input
Data
GPIO1
Input/Output
Data
RES
Input
Data
GPIO0
-
Control
PINIT
Input
Data
GPIO0
Input/Output
Data
HREQ
-
Control
D7
Input/Output
Data
HREQ
Input/Output
Data
D6
Input/Output
Data
SCK/SCL
-
Control
D5
Input/Output
Data
SCK/SCL
Input/Output
Data
D4
Input/Output
Data
MISO/SDA
-
Control
D[7:0]
-
Control
MISO/SDA
Input/Output
Data
D3
Input/Output
Data
MOSI/HA0
-
Control
D2
Input/Output
Data
MOSI/HA0
Input/Output
Data
D1
Input/Output
Data
SS
Input
Data
D0
Input/Output
Data
SDO5/SDI0
-
Control
A17
Output3
Data
SDO5/SDI0
Input/Output
Data
A16
Output3
Data
SDO4/SDI1
-
Control
A15
Output3
Data
SDO4/SDI1
Input/Output
Data
A14
Output3
Data
SDO3/SDI2
-
Control
A13
Output3
Data
SDO3/SDI2
Input/Output
Data
A12
Output3
Data
SDO2/SDI3
-
Control
A[17:9]
-
Control
SDO2/SDI3
Input/Output
Data
A11
Output3
Data
SDO1
-
Control
A10
Output3
Data
SDO1
Input/Output
Data
A9
Output3
Data
SDO0
-
Control
A8
Output3
Data
SDO0
Input/Output
Data
A7
Output3
Data
HCKR
-
Control
A[8:0]
-
Control
HCKR
Input/Output
Data
A6
Output3
Data
HCKT
-
Control
A5
Output3
Data
HCKT
Input/Output
Data
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Core Configuration
JTAG Boundary Scan Register (BSR)
Table 4-6 DSP56364 BSR Bit Definition (Continued)
Freescale Semiconductor, Inc...
BIT
#
4-12
PIN NAME
PIN TYPE
BSR CELL
TYPE
A4
Output3
A3
BIT
#
PIN NAME
PIN TYPE
BSR CELL
TYPE
Data
SCKR
-
Control
Output3
Data
SCKR
Input/Output
Data
A2
Output3
Data
SCKT
-
Control
A1
Output3
Data
SCKT
Input/Output
Data
A0
Output3
Data
FSR
-
Control
AA0
-
Control
FSR
Input/Output
Data
AA0
Output3
Data
FST
-
Control
AA1
-
Control
FST
Input/Output
Data
AA1
Output3
Data
MODA
Input
Data
RD,WR
-
Control
MODB
Input
Data
RD
Output3
Data
MODD
Input
Data
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SECTION
5
GENERAL PURPOSE INPUT/OUTPUT
PORT (GPIO)
Freescale Semiconductor, Inc...
5.1
INTRODUCTION
The General Purpose Input/Output (GPIO) pins are used for control and handshake functions
between the DSP and external circuitry. The GPIO port has 4 I/O pins (GPIO0-GPIO3) that
are controlled through a set of memory-mapped registers. Each GPIO pin may be individually
programmed as an output or as an input.
5.2
GPIO PROGRAMMING MODEL
The GPIO port is controlled by three registers: Port B Control register (PCRB), Port B
Direction register (PRRB) and Port B GPIO Data register (PDRB). These registers are shown
in Figure 5-1, Figure 5-2, and Figure 5-3.
Figure 5-1 GPIO Port B Control Register (PCRB)
7
6
5
4
3
2
1
0
PC3
PC2
PC1
PC0
PCRB
X:$FFFFCF
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
Reserved, read as zero, should be written with zero for future compatibility
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General Purpose Input/Output Port (GPIO)
GPIO Programming Model
Figure 5-2 GPIO Port B Direction Register (PRRB)
Freescale Semiconductor, Inc...
7
6
5
4
3
2
1
0
PDC3
PDC2
PDC1
PDC0
PRRB
X:$FFFFCE
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
Reserved, read as zero, should be written with zero for future compatibility
Figure 5-3 GPIO Port B Data Register (PDRB)
7
6
5
4
3
2
1
0
PD3
PD2
PD1
PD0
PDRB
X:$FFFFCD
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
Reserved, read as zero, should be written with zero for future compatibility
5.2.1
PORT B CONTROL REGISTER (PCRB)
The read/write Port B Control Register (PCRB) controls the functionality of the GPIO pins in
conjunction with the Port B Direction Register (PRRB).
5.2.1.1
PCRB Control Bits (PC[3:0]) - Bits 3-0
When a PC[i] bit is cleared, the corresponding GPIO[i] pin is three-stated if PDC[i] is cleared,
or it is an output if PDC[i] is set. When a PC[i] bit is set, the corresponding GPIO[i] pin is an
input if PDC[i] is cleared, or it is an open-drain output if PDC[i] is set. Refer to for a
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General Purpose Input/Output Port (GPIO)
GPIO Programming Model
summary of the GPIO configuration control. Hardware and software reset clear the PC[3:0]
bits.
5.2.1.2
PCRB Reserved Bits - Bits 23-4
These bits are reserved and unused. They read as 0s and should be written with 0s for future
compatibility.
Port B Direction Register (PRRB)
Freescale Semiconductor, Inc...
The read/write Port B Direction Register controls the direction of data transfer for each GPIO
pin.
5.2.1.3
PRRB Direction Bits (PDC[3:0]) - Bits 3-0
When PDC[i] is set, the GPIO port pin[i] is configured as output. When PDC[i] is cleared the
GPIO port pin[i] is configured as input. See . Hardware and software reset clear the PDC[3:0]
bits.
5.2.1.4
PRRB Reserved Bits - Bits 23-4
These bits are reserved and unused. They read as 0s and should be written with 0s for future
compatibility.
Table 5-1 GPIO Pin Configuration
5.2.2
PDC[I]
PC[I]
GPIO PIN[I] FUNCTION
0
0
Three-Stated (Disconnected)
0
1
Input
1
0
Output
1
1
Open-drain output
PORT B GPIO DATA REGISTER (PDRB)
The read/write Port B Data Register (PDRB) is used to read data from or write data to the
GPIO pins.
5.2.2.1
PDRB Data Bits (PD[3:0]) - Bits 3-0
If a GPIO pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect
the value present on this pin. If a GPIO pin [i] is configured as a GPIO output, then the value
written into the corresponding PD[i] bit will be reflected on the pin. The PD[3:0] bits are not
affected by hardware or software reset.
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General Purpose Input/Output Port (GPIO)
GPIO Programming Model
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5.2.2.2
PDRB Reserved Bits - Bits 23-4
These bits are reserved and unused. They read as 0s and should be written with 0s for future
compatibility.
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SECTION
6
ENHANCED SERIAL AUDIO
INTERFACE (ESAI)
Freescale Semiconductor, Inc...
6.1
INTRODUCTION
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial
communication with a variety of serial devices including one or more industry-standard
codecs, other DSPs, microprocessors, and peripherals which implement the Motorola SPI
serial protocol. The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator. It is a superset of the 56300 Family ESSI peripheral and
of the 56000 Family SAI peripheral.
The ESAI block diagram is shown in Figure 6-1. The ESAI is named synchronous because all
serial transfers are synchronized to a clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of operation is used to transfer data at a periodic
rate, one word per period. The network mode is similar in that it is also intended for periodic
transfers; however, it supports up to 32 words (time slots) per period. This mode can be used
to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is
intended for non-periodic transfers of data and to transfer data serially at high speed when the
data becomes available. This mode offers a subset of the SPI protocol.
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Enhanced Serial AUDIO Interface (ESAI)
Introduction
GDB
DDB
TX0
RSMA
SDO0 [PC11]
RSMB
Shift Register
TSMA
TX1
TSMB
SDO1 [PC10]
Freescale Semiconductor, Inc...
Shift Register
RCCR
TX2
RCR
SDO2/SDI3 [PC9]
Shift Register
TCCR
RX3
TCR
TX3
SDO3/SDI2 [PC8]
SAICR
Shift Register
SAISR
RX2
TX4
TSR
SDO4/SDI1 [PC7]
Shift Register
RX1
Clock / Frame Sync
Generators
and
Control Logic
TX5
RCLK
SDO5/SDI0 [PC6]
Shift Register
[PC2] HCKR
[PC1] FSR
[PC0] SCKR
[PC5] HCKT
[PC4] FST
[PC3] SCKT
TCLK
RX0
Figure 6-1 ESAI Block Diagram
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Enhanced Serial AUDIO Interface (ESAI)
ESAI Data and Control Pins
6.2
ESAI DATA AND CONTROL PINS
Freescale Semiconductor, Inc...
Three to twelve pins are required for operation, depending on the operating mode selected and
the number of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by
transmitters 0 and 1 only. The SDO2/SDI3, SDO3/SDI2, SDO4/SDI1, and SDO5/SDI0 pins
are shared by transmitters 2 to 5 with receivers 0 to 3. The actual mode of operation is selected
under software control. All transmitters operate fully synchronized under control of the same
transmitter clock signals. All receivers operate fully synchronized under control of the same
receiver clock signals.
6.2.1
SERIAL TRANSMIT 0 DATA PIN (SDO0)
SDO0 is used for transmitting data from the TX0 serial transmit shift register. SDO0 is an
output when data is being transmitted from the TX0 shift register. In the on-demand mode
with an internally generated bit clock, the SDO0 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO0 may be programmed as a general-purpose I/O pin (PC11) when the ESAI SDO0
function is not being used.
6.2.2
SERIAL TRANSMIT 1 DATA PIN (SDO1)
SDO1 is used for transmitting data from the TX1 serial transmit shift register. SDO1 is an
output when data is being transmitted from the TX1 shift register. In the on-demand mode
with an internally generated bit clock, the SDO1 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO1 may be programmed as a general-purpose I/O pin (PC10) when the ESAI SDO1
function is not being used.
6.2.3
SERIAL TRANSMIT 2/RECEIVE 3 DATA PIN (SDO2/SDI3)
SDO2/SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift
register when programmed as a transmitter pin, or as the SDI3 signal for receiving serial data
to the RX3 serial receive shift register when programmed as a receiver pin. SDO2/SDI3 is an
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Enhanced Serial AUDIO Interface (ESAI)
ESAI Data and Control Pins
input when data is being received by the RX3 shift register. SDO2/SDI3 is an output when
data is being transmitted from the TX2 shift register. In the on-demand mode with an
internally generated bit clock, the SDO2/SDI3 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
Freescale Semiconductor, Inc...
SDO2/SDI3 may be programmed as a general-purpose I/O pin (PC9) when the ESAI SDO2
and SDI3 functions are not being used.
6.2.4
SERIAL TRANSMIT 3/RECEIVE 2 DATA PIN (SDO3/SDI2)
SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit
shift register when programmed as a transmitter pin, or as the SDI2 signal for receiving serial
data to the RX2 serial receive shift register when programmed as a receiver pin. SDO3/SDI2
is an input when data is being received by the RX2 shift register. SDO3/SDI2 is an output
when data is being transmitted from the TX3 shift register. In the on-demand mode with an
internally generated bit clock, the SDO3/SDI2 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO3/SDI2 may be programmed as a general-purpose I/O pin (PC8) when the ESAI SDO3
and SDI2 functions are not being used.
6.2.5
SERIAL TRANSMIT 4/RECEIVE 1 DATA PIN (SDO4/SDI1)
SDO4/SDI1 is used as the SDO4 signal for transmitting data from the TX4 serial transmit
shift register when programmed as transmitter pin, or as the SDI1 signal for receiving serial
data to the RX1 serial receive shift register when programmed as a receiver pin. SDO4/SDI1
is an input when data is being received by the RX1 shift register. SDO4/SDI1 is an output
when data is being transmitted from the TX4 shift register. In the on-demand mode with an
internally generated bit clock, the SDO4/SDI1 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO4/SDI1 may be programmed as a general-purpose I/O pin (PC7) when the ESAI SDO4
and SDI1 functions are not being used.
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ESAI Data and Control Pins
6.2.6
SERIAL TRANSMIT 5/RECEIVE 0 DATA PIN (SDO5/SDI0)
Freescale Semiconductor, Inc...
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit
shift register when programmed as transmitter pin, or as the SDI0 signal for receiving serial
data to the RX0 serial shift register when programmed as a receiver pin. SDO5/SDI0 is an
input when data is being received by the RX0 shift register. SDO5/SDI0 is an output when
data is being transmitted from the TX5 shift register. In the on-demand mode with an
internally generated bit clock, the SDO5/SDI0 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5
and SDI0 functions are not being used
6.2.7
RECEIVER SERIAL CLOCK (SCKR)
SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface. The
direction of this pin is determined by the RCKD bit in the RCCR register.The SCKR operates
as a clock input or output used by all the enabled receivers in the asynchronous mode
(SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in
the RCCR register. When configured as the output flag OF0, this pin reflects the value of the
OF0 bit in the SAICR register, and the data in the OF0 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When this pin is
configured as the input flag IF0, the data value at the pin is stored in the IF0 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in network mode.
SCKR may be programmed as a general-purpose I/O pin (PC0) when the ESAI SCKR
function is not being used.
Note:
Although the external ESAI serial clock can be independent of and asynchronous
to the DSP system clock, the DSP clock frequency must be at least three times the
external ESAI serial clock frequency and each ESAI serial clock phase must
exceed the minimum of 1.5 DSP clock periods.
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ESAI Data and Control Pins
For more information on pin mode and definition, see Table 6-7 and on receiver clock signals
see Table 6-1.
Freescale Semiconductor, Inc...
Table 6-1 Receiver Clock Sources (asynchronous mode only)
RHCKD
RFSD
RCKD
Receiver
Bit Clock
Source
0
0
0
SCKR
0
0
1
HCKR
0
1
0
SCKR
FSR
0
1
1
HCKR
FSR
1
0
0
SCKR
HCKR
1
0
1
INT
HCKR
1
1
0
SCKR
HCKR
FSR
1
1
1
INT
HCKR
FSR
6.2.8
OUTPUTS
SCKR
SCKR
SCKR
SCKR
TRANSMITTER SERIAL CLOCK (SCKT)
SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface.
The direction of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a
clock input or output used by all the enabled transmitters in the asynchronous mode (SYN=0)
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ESAI Data and Control Pins
or by all the enabled transmitters and receivers in the synchronous mode (SYN=1) (see
Table 6-2).
Freescale Semiconductor, Inc...
Table 6-2 Transmitter Clock Sources
THCKD
TFSD
TCKD
Transmitter
Bit Clock Source
0
0
0
SCKT
0
0
1
HCKT
0
1
0
SCKT
FST
0
1
1
HCKT
FST
1
0
0
SCKT
HCKT
1
0
1
INT
HCKT
1
1
0
SCKT
HCKT
FST
1
1
1
INT
HCKT
FST
OUTPUTS
SCKT
SCKT
SCKT
SCKT
SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT
function is not being used.
Note:
6.2.9
Although the external ESAI serial clock can be independent of and asynchronous
to the DSP system clock, the DSP clock frequency must be at least three times the
external ESAI serial clock frequency and each ESAI serial clock phase must
exceed the minimum of 1.5 DSP clock periods.
FRAME SYNC FOR RECEIVER (FSR)
FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface.
The direction of this pin is determined by the RFSD bit in RCR register. In the asynchronous
mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). For
further information on pin mode and definition, see Table 6-8 and on receiver clock signals
see Table 6-1.
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in
the RCCR register. When configured as the output flag OF1, this pin reflects the value of the
OF1 bit in the SAICR register, and the data in the OF1 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When configured as the
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ESAI Data and Control Pins
input flag IF1, the data value at the pin is stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is
not being used.
Freescale Semiconductor, Inc...
6.2.10
FRAME SYNC FOR TRANSMITTER (FST)
FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in
the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0)
(see Table 6-2). The direction of this pin is determined by the TFSD bit in the TCR register.
When configured as an output, this pin is the internally generated frame sync signal. When
configured as an input, this pin receives an external frame sync signal for the transmitters (and
the receivers in synchronous mode).
FST may be programmed as a general-purpose I/O pin (PC4) when the ESAI FST function is
not being used.
6.2.11
HIGH FREQUENCY CLOCK FOR TRANSMITTER (HCKT)
HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI
interface. The direction of this pin is determined by the THCKD bit in the TCCR register. In
the asynchronous mode (SYN=0), the HCKT pin operates as the high frequency clock input or
output used by all enabled transmitters. In the synchronous mode (SYN=1), it operates as the
high frequency clock input or output used by all enabled transmitters and receivers. When
programmed as input this pin is used as an alternative high frequency clock source to the
ESAI transmitter rather than the DSP main clock. When programmed as output it can serve as
a high frequency sample clock (to external DACs for example) or as an additional system
clock. See Table 6-2.
HCKT may be programmed as a general-purpose I/O pin (PC5) when the ESAI HCKT
function is not being used.
6.2.12
HIGH FREQUENCY CLOCK FOR RECEIVER (HCKR)
HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI
interface. The direction of this pin is determined by the RHCKD bit in the RCCR register. In
the asynchronous mode (SYN=0), the HCKR pin operates as the high frequency clock input
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Enhanced Serial AUDIO Interface (ESAI)
ESAI Programming Model
or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as
the serial flag 2 pin. For further information on pin mode and definition, see Table 6-9 and on
receiver clock signals see Table 6-1.
Freescale Semiconductor, Inc...
When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in
the RCCR register. When configured as the output flag OF2, this pin reflects the value of the
OF2 bit in the SAICR register, and the data in the OF2 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When configured as the
input flag IF2, the data value at the pin is stored in the IF2 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR
function is not being used.
6.3
ESAI PROGRAMMING MODEL
The ESAI can be viewed as five control registers, one status register, six transmit data
registers, four receive data registers, two transmit slot mask registers, two receive slot mask
registers and a special-purpose time slot register. The following paragraphs give detailed
descriptions and operations of each bit in the ESAI registers.
The ESAI pins can also function as GPIO pins (Port C), described in Section 6.5, “GPIO Pins and Registers”.
6.3.1
ESAI TRANSMITTER CLOCK CONTROL REGISTER
(TCCR)
The read/write Transmitter Clock Control Register (TCCR) controls the ESAI transmitter
clock generator bit and frame sync rates, the bit clock and high frequency clock sources and
the directions of the HCKT, FST and SCKT signals. (See Figure 6-2). In the synchronous
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ESAI Programming Model
mode (SYN=1), the bit clock defined for the transmitter determines the receiver bit clock as
well. TCCR also controls the number of words per frame for the serial data.
X:$FFFFB6
11
10
9
8
7
6
5
4
3
2
1
0
TDC2
TDC1
TDC0
TPSR
TPM7
TPM6
TPM5
TPM4
TPM3
TPM2
TPM1
TPM0
23
22
21
20
19
18
17
16
15
14
13
12
TCKP
TFP3
TFP2
TFP1
TFP0
TDC4
TDC3
Freescale Semiconductor, Inc...
THCKD TFSD
TCKD THCKP TFSP
Figure 6-2 TCCR Register
Hardware and software reset clear all the bits of the TCCR register.
The TCCR control bits are described in the following paragraphs.
6.3.1.1
TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 0–7
The TPM7–TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter
clock generator. A divide ratio from 1 to 256 (TPM[7:0]=$00 to $FF) may be selected. The bit
clock output is available at the transmit serial bit clock (SCKT) pin of the DSP. The bit clock
output is also available internally for use as the bit clock to shift the transmit and receive shift
registers. The ESAI transmit clock generator functional diagram is shown in Figure 6-3.
6-10
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ESAI Programming Model
RHCKD=1
FOSC
DIVIDE
BY 2
PRESCALE
DIVIDE BY 1
OR
DIVIDE BY 8
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
256
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
RPM0 - RPM7
RFP0 - RFP3
RHCKD=0
RPSR
HCKR
Freescale Semiconductor, Inc...
RHCKD
FLAG0 OUT
(SYNC MODE)
FLAG0 IN
(SYNC MODE)
INTERNAL BIT CLOCK
RSWS4-RSWS0
RX WORD
LENGTH DIVIDER
SYN=1
RX WORD
CLOCK
SYN=0
SCKR
RX SHIFT REGISTER
RCLOCK
SYN=0
TSWS4-TSWS0
SYN=1
RCKD
TCLOCK
INTERNAL BIT CLOCK
SCKT
TX WORD
LENGTH DIVIDER
TX WORD
CLOCK
TCKD
TX SHIFT REGISTER
THCKD
HCKT
TPSR
TPM0 - TPM7
TFP0 - TFP3
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
256
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
THCKD=0
DIVIDE
BY 2
FOSC
PRESCALE
DIVIDE BY 1
OR
DIVIDE BY 8
THCKD=1
Notes:
1. FOSC is the DSP56300 Core internal clock frequency.
Figure 6-3 ESAI Clock Generator Functional Block Diagram
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6.3.1.2
TCCR Transmit Prescaler Range (TPSR) - Bit 8
The TPSR bit controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit clock is
desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed
divide-by-eight prescaler is operational (see Figure 6-3). The maximum internally generated
bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2
x 8 x 256)=Fosc/4096.
Freescale Semiconductor, Inc...
Note:
Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes
synchronization problems when using the internal DSP clock as source (TCKD=1
or THCKD=1).
6.3.1.3
TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13
The TDC4–TDC0 bits control the divide ratio for the programmable frame rate dividers used
to generate the transmitter frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one.
The divide ratio may range from 2 to 32 (TDC[4:0]=00001 to 11111) for network mode. A
divide ratio of one (TDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from
1 to 32 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1
(TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(TFSL=1) must be used in this case.
The ESAI frame sync generator functional diagram is shown in Figure 6-4.
6-12
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RX WORD
CLOCK
RDC0 - RDC4
RFSL
RECEIVER
FRAME RATE
DIVIDER
SYNC
TYPE
INTERNAL RX FRAME CLOCK
RFSD
RFSD=1
SYN=0
SYN=0
RECEIVE
CONTROL
LOGIC
FSR
RECEIVE
FRAME SYNC
RFSD=0
SYN=1
Freescale Semiconductor, Inc...
SYN=1
TDC0 - TDC4
TFSL
FLAG1 IN
(SYNC MODE)
FLAG1OUT
(SYNC MODE)
TFSD
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
TRANSMIT
CONTROL
LOGIC
SYNC
TYPE
INTERNAL TX FRAME CLOCK
FST
TRANSMIT
FRAME SYNC
Figure 6-4 ESAI Frame Sync Generator Functional Block Diagram
6.3.1.4
TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14–17
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the
transmitter serial bit clock when the source of the high frequency clock and the bit clock is the
internal DSP clock. When the HCKT input is being driven from an external high frequency
clock, the TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See
Table 6-3 for the specification of the divide ratio. The ESAI high frequency clock generator
functional diagram is shown in Figure 6-3.
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Freescale Semiconductor, Inc...
Table 6-3 Transmitter High Frequency Clock Divider
TFP3-TFP0
Divide Ratio
$0
1
$1
2
$2
3
$3
4
...
...
$F
16
6.3.1.5
TCCR Transmit Clock Polarity (TCKP) - Bit 18
The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame
sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are
clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the
transmit bit clock. If TCKP is set the falling edge of the transmit clock is used to clock the
data out and frame sync and the rising edge of the transmit clock is used to latch the data and
frame sync in.
6.3.1.6
TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19
The Transmitter Frame Sync Polarity (TFSP) bit determines the polarity of the transmit frame
sync signal. When TFSP is cleared, the frame sync signal polarity is positive (i.e the frame
start is indicated by a high level on the frame sync pin). When TFSP is set, the frame sync
signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync
pin).
6.3.1.7
TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20
The Transmitter High Frequency Clock Polarity (THCKP) bit controls on which bit clock
edge data and frame sync are clocked out and latched in. If THCKP is cleared the data and the
frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the
falling edge of the transmit bit clock. If THCKP is set the falling edge of the transmit clock is
used to clock the data out and frame sync and the rising edge of the transmit clock is used to
latch the data and frame sync in.
6.3.1.8
TCCR Transmit Clock Source Direction (TCKD) - Bit 21
The Transmitter Clock Source Direction (TCKD) bit selects the source of the clock signal
used to clock the transmit shift registers in the asynchronous mode (SYN=0) and the transmit
shift registers and the receive shift registers in the synchronous mode (SYN=1). When TCKD
is set, the internal clock source becomes the bit clock for the transmit shift registers and word
length divider and is the output on the SCKT pin. When TCKD is cleared, the clock source is
external; the internal clock generator is disconnected from the SCKT pin, and an external
clock source may drive this pin. See Table 6-2.
6-14
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6.3.1.9
TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22
TFSD controls the direction of the FST pin. When TFSD is cleared, FST is an input; when
TFSD is set, FST is an output. See Table 6-2.
6.3.1.10
TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23
THCKD controls the direction of the HCKT pin. When THCKD is cleared, HCKT is an input;
when THCKD is set, HCKT is an output. See Table 6-2.
Freescale Semiconductor, Inc...
6.3.2
ESAI TRANSMIT CONTROL REGISTER (TCR)
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section.
Interrupt enable bits for the transmitter section are provided in this control register. Operating
modes are also selected in this register. See Figure 6-5.
11
X:$FFFFB5
10
9
8
7
6
5
4
3
2
1
0
TE5
TE4
TE3
TE2
TE1
TE0
17
16
15
14
13
12
PADC
TFSR
TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
23
22
21
20
19
TLIE
TIE
TEDIE
TEIE
TPR
18
TFSL TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-5 TCR Register
Hardware and software reset clear all the bits in the TCR register.
The TCR bits are described in the following paragraphs.
6.3.2.1
TCR ESAI Transmit 0 Enable (TE0) - Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set
and a frame sync is detected, the transmit #0 portion of the ESAI is enabled for that frame.
When TE0 is cleared, the transmitter #0 is disabled after completing transmission of data
currently in the ESAI transmit shift register. The SDO0 output is tri-stated, and any data
present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; but data is
not transferred to the transmit shift register #0).
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
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In the network mode, the operation of clearing TE0 and setting it again disables the
transmitter #0 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO0 pin remains in the high-impedance
state.The on-demand mode transmit enable sequence can be the same as the normal mode, or
TE0 can be left enabled.
6.3.2.2
TCR ESAI Transmit 1 Enable (TE1) - Bit 1
TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set
and a frame sync is detected, the transmit #1 portion of the ESAI is enabled for that frame.
When TE1 is cleared, the transmitter #1 is disabled after completing transmission of data
currently in the ESAI transmit shift register. The SDO1 output is tri-stated, and any data
present in TX1 is not transmitted (i.e., data can be written to TX1 with TE1 cleared; but data is
not transferred to the transmit shift register #1).
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
In the network mode, the operation of clearing TE1 and setting it again disables the
transmitter #1 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO1 pin remains in the high-impedance state.
The on-demand mode transmit enable sequence can be the same as the normal mode, or TE1
can be left enabled.
6.3.2.3
TCR ESAI Transmit 2 Enable (TE2) - Bit 2
TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set
and a frame sync is detected, the transmit #2 portion of the ESAI is enabled for that frame.
When TE2 is cleared, the transmitter #2 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to TX2 when TE2 is cleared
but the data is not transferred to the transmit shift register #2.
The SDO2/SDI3 pin is the data input pin for RX3 if TE2 is cleared and RE3 in the RCR
register is set. If both RE3 and TE2 are cleared the transmitter and receiver are disabled, and
the pin is tri-stated. Both RE3 and TE2 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
In the network mode, the operation of clearing TE2 and setting it again disables the
transmitter #2 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO2/SDI3 pin remains in the high-impedance
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state. The on-demand mode transmit enable sequence can be the same as the normal mode, or
TE2 can be left enabled.
Freescale Semiconductor, Inc...
6.3.2.4
TCR ESAI Transmit 3 Enable (TE3) - Bit 3
TE3 enables the transfer of data from TX3 to the transmit shift register #3. When TE3 is set
and a frame sync is detected, the transmit #3 portion of the ESAI is enabled for that frame.
When TE3 is cleared, the transmitter #3 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to TX3 when TE3 is cleared
but the data is not transferred to the transmit shift register #3.
The SDO3/SDI2 pin is the data input pin for RX2 if TE3 is cleared and RE2 in the RCR
register is set. If both RE2 and TE3 are cleared the transmitter and receiver are disabled, and
the pin is tri-stated. Both RE2 and TE3 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
In the network mode, the operation of clearing TE3 and setting it again disables the
transmitter #3 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO3/SDI2 pin remains in the high-impedance
state. The on-demand mode transmit enable sequence can be the same as the normal mode, or
TE3 can be left enabled.
6.3.2.5
TCR ESAI Transmit 4 Enable (TE4) - Bit 4
TE4 enables the transfer of data from TX4 to the transmit shift register #4. When TE4 is set
and a frame sync is detected, the transmit #4 portion of the ESAI is enabled for that frame.
When TE4 is cleared, the transmitter #4 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to TX4 when TE4 is cleared
but the data is not transferred to the transmit shift register #4.
The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cleared and RE1 in the RCR
register is set. If both RE1 and TE4 are cleared the transmitter and receiver are disabled, and
the pin is tri-stated. Both RE1 and TE4 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
In the network mode, the operation of clearing TE4 and setting it again disables the
transmitter #4 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO4/SDI1 pin remains in the high-impedance
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state. The on-demand mode transmit enable sequence can be the same as the normal mode, or
TE4 can be left enabled.
Freescale Semiconductor, Inc...
6.3.2.6
TCR ESAI Transmit 5 Enable (TE5) - Bit 5
TE5 enables the transfer of data from TX5 to the transmit shift register #5. When TE5 is set
and a frame sync is detected, the transmit #5 portion of the ESAI is enabled for that frame.
When TE5 is cleared, the transmitter #5 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to TX5 when TE5 is cleared
but the data is not transferred to the transmit shift register #5.
The SDO5/SDI0 pin is the data input pin for RX0 if TE5 is cleared and RE0 in the RCR
register is set. If both RE0 and TE5 are cleared the transmitter and receiver are disabled, and
the pin is tri-stated. Both RE0 and TE5 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
In the network mode, the operation of clearing TE5 and setting it again disables the
transmitter #5 after completing transmission of the current data word until the beginning of
the next frame. During that time period, the SDO5/SDI0 pin remains in the high-impedance
state. The on-demand mode transmit enable sequence can be the same as the normal mode, or
TE5 can be left enabled.
6.3.2.7
TCR Transmit Shift Direction (TSHFD) - Bit 6
The TSHFD bit causes the transmit shift registers to shift data out MSB first when TSHFD
equals zero or LSB first when TSHFD equals one (see Figure 6-13 and Figure 6-14).
6.3.2.8
TCR Transmit Word Alignment Control (TWA) - Bit 7
The Transmitter Word Alignment Control (TWA) bit defines the alignment of the data word
in relation to the slot. This is relevant for the cases where the word length is shorter than the
slot length. If TWA is cleared, the data word is left-aligned in the slot frame during
transmission. If TWA is set, the data word is right-aligned in the slot frame during
transmission.
Since the data word is shorter than the slot length, the data word is extended until achieving
the slot length, according to the following rule:
1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0),
then the last data bit is repeated after the data word has been transmitted. If zero
padding is enabled (PADC=1), zeroes are transmitted after the data word has been
transmitted.
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2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0),
then the first data bit is repeated before the transmission of the data word. If zero
padding is enabled (PADC=1), zeroes are transmitted before the transmission of the
data word.
Freescale Semiconductor, Inc...
6.3.2.9
TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9
The TMOD1 and TMOD0 bits are used to define the network mode of ESAI transmitters
according to Table 6-4. In the normal mode, the frame rate divider determines the word
transfer rate – one word is transferred per frame sync during the frame sync time slot, as
shown in Figure 6-6. In network mode, it is possible to transfer a word for every time slot, as
shown in Figure 6-6. For more details, see Section 6.4, “Operating Modes”.
In order to comply with AC-97 specifications, TSWS4-TSWS0 should be set to 00011 (20-bit
slot, 20-bit word length), TFSL and TFSR should be cleared, and TDC4-TDC0 should be set
to $0C (13 words in frame). If TMOD[1:0]=$11 and the above recommendations are
followed, the first slot and word will be 16 bits long, and the next 12 slots and words will be
20 bits long, as required by the AC97 protocol.
Table 6-4 Transmit Network Mode Selection
TMOD1
TMOD0
TDC4-TDC0
0
0
$0-$1F
0
1
$0
0
1
$1-$1F
1
0
X
1
1
$0C
MOTOROLA
Transmitter Network Mode
Normal Mode
On-Demand Mode
Network Mode
Reserved
AC97
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SLOT 0
SLOT 1
SLOT 0
DATA
RECEIVER INTERRUPT (OR DMA REQUEST)
AND FLAGS SET
SLOT 2
TRANSMITTER INTERRUPTS (OR DMA
REQUEST) AND FLAGS SET
NOTE: Interrupts occur and a word may be transferred at every time slot.
SERIAL DATA
FRAME SYNC
SERIAL
Network Mode
RECEIVER INTERRUPT (OR DMA
REQUEST) AND FLAGS SET
TRANSMITTER INTERRUPT (OR DMA REQUEST)
AND FLAGS SET
NOTE: Interrupts occur and data is transferred once per frame sync.
SERIAL DATA
FRAME SYNC
SERIAL
Normal Mode
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SLOT 1
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Figure 6-6 Normal and Network Operation
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6.3.2.10
TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14
The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data
words being transferred via the ESAI. The word length must be equal to or shorter than the
slot length. The possible combinations are shown in Table 6-5. See also the ESAI data path
programming model in Figure 6-13 and Figure 6-14.
Freescale Semiconductor, Inc...
Table 6-5 ESAI Transmit Slot and Word Length Selection
TSWS4
TSWS3
TSWS2
TSWS1
TSWS0
SLOT LENGTH
WORD LENGTH
0
0
0
0
0
8
8
0
0
1
0
0
12
8
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
12
0
0
0
1
0
16
0
1
1
0
0
0
1
0
0
1
12
0
0
1
1
0
16
0
0
0
1
1
20
1
0
0
0
0
0
1
1
0
1
12
0
1
0
1
0
16
0
0
1
1
1
20
1
1
1
1
0
24
1
1
0
0
0
1
0
1
0
1
12
1
0
0
1
0
16
0
1
1
1
1
20
1
1
1
1
1
24
MOTOROLA
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12
16
20
24
32
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8
8
8
8
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Table 6-5 ESAI Transmit Slot and Word Length Selection (Continued)
TSWS4
TSWS3
TSWS2
TSWS1
TSWS0
0
1
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
SLOT LENGTH
WORD LENGTH
Reserved
6.3.2.11
TCR Transmit Frame Sync Length (TFSL) - Bit 15
The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is
cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is
selected. See Figure 6-7 for examples of frame length selection.
6-22
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WORD LENGTH: TFSL=0, RFSL=0
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA
DATA
DATA
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NOTE: Frame sync occurs while data is valid.
ONE BIT LENGTH: TFSL=1, RFSL=1
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA
DATA
DATA
NOTE: Frame sync occurs for one bit time preceding the data.
MIXED FRAME LENGTH: TFSL=1, RFSL=0
SERIAL CLOCK
RX FRAME SYNC
RX SERIAL DATA
DATA
DATA
DATA
DATA
TX FRAME SYNC
TX SERIAL DATA
MIXED FRAME LENGTH: TFSL=0, RFSL=1
SERIAL CLOCK
RX FRAME SYNC
RX SERIAL DATA
DATA
DATA
DATA
DATA
TX FRAME SYNC
TX SERIAL DATA
Figure 6-7 Frame Length Selection
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6.3.2.12
TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16
TFSR determines the relative timing of the transmit frame sync signal as referred to the serial
data lines, for a word length frame sync only (TFSL=0). When TFSR is cleared the word
length frame sync occurs together with the first bit of the data word of the first slot. When
TFSR is set the word length frame sync starts one serial clock cycle earlier (i.e together with
the last bit of the previous data word).
6.3.2.13
TCR Transmit Zero Padding Control (PADC) - Bit 17
When PADC is cleared, zero padding is disabled. When PADC is set, zero padding is enabled.
PADC, in conjunction with the TWA control bit, determines the way that padding is done for
operating modes where the word length is less than the slot length. See the TWA bit
description in Section 6.3.2.8, “TCR Transmit Word Alignment Control (TWA) - Bit 7” for
more details.
Since the data word is shorter than the slot length, the data word is extended until achieving
the slot length, according to the following rule:
1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0),
then the last data bit is repeated after the data word has been transmitted. If zero
padding is enabled (PADC=1), zeroes are transmitted after the data word has been
transmitted.
2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0),
then the first data bit is repeated before the transmission of the data word. If zero
padding is enabled (PADC=1), zeroes are transmitted before the transmission of the
data word.
6.3.2.14
TCR Reserved Bit - Bits 18
This bit is reserved. It reads as zero, and it should be written with zero for future
compatibility.
6.3.2.15
TCR Transmit Section Personal Reset (TPR) - Bit 19
The TPR control bit is used to put the transmitter section of the ESAI in the personal reset
state. The receiver section is not affected. When TPR is cleared, the transmitter section may
operate normally. When TPR is set, the transmitter section enters the personal reset state
immediately. When in the personal reset state, the status bits are reset to the same state as after
hardware reset. The control bits are not affected by the personal reset state. The transmitter
data pins are tri-stated while in the personal reset state; if a stable logic level is desired, the
transmitter data pins should be defined as GPIO outputs, or external pull-up or pull-down
resistors should be used. The transmitter clock outputs drive zeroes while in the personal reset
state. Note that to leave the personal reset state by clearing TPR, the procedure described in
Section 6.6, “ESAI Initialization Examples” should be followed.
6-24
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6.3.2.16
TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20
When TEIE is set, the DSP is interrupted when both TDE and TUE in the SAISR status
register are set. When TEIE is cleared, this interrupt is disabled. Reading the SAISR status
register followed by writing to all the data registers of the enabled transmitters clears TUE,
thus clearing the pending interrupt.
6.3.2.17
TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21
The TEDIE control bit is used to enable the transmit even slot data interrupts. If TEDIE is set,
the transmit even slot data interrupts are enabled. If TEDIE is cleared, the transmit even slot
data interrupts are disabled. A transmit even slot data interrupt request is generated if TEDIE
is set and the TEDE status flag in the SAISR status register is set. Even time slots are all
even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot in
the frame is marked by the frame sync signal and is considered to be even. Writing data to all
the data registers of the enabled transmitters or to TSR clears the TEDE flag, thus servicing
the interrupt.
Transmit interrupts with exception have higher priority than transmit even slot data interrupts,
therefore if exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit
data with exception interrupt from the interrupt controller.
6.3.2.18
TCR Transmit Interrupt Enable (TIE) - Bit 22
The DSP is interrupted when TIE and the TDE flag in the SAISR status register are set. When
TIE is cleared, this interrupt is disabled. Writing data to all the data registers of the enabled
transmitters or to TSR clears TDE, thus clearing the interrupt.
Transmit interrupts with exception have higher priority than normal transmit data interrupts,
therefore if exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit
data with exception interrupt from the interrupt controller.
6.3.2.19
TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23
TLIE enables an interrupt at the beginning of last slot of a frame in network mode. When
TLIE is set the DSP is interrupted at the start of the last slot in a frame in network mode
regardless of the transmit mask register setting. When TLIE is cleared the transmit last slot
interrupt is disabled. TLIE is disabled when TDC[4:0]=$00000 (on-demand mode). The use
of the transmit last slot interrupt is described in Section 6.4.3, “ESAI Interrupt Requests”.
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6.3.3
ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR)
The read/write Receive Clock Control Register (RCCR) controls the ESAI receiver clock
generator bit and frame sync rates, word length, and number of words per frame for the serial
data. The RCCR control bits are described in the following paragraphs (see Figure 6-8).
11
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X:$FFFFB8
10
9
8
7
6
5
4
3
2
1
0
RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0
23
22
21
20
19
RHCKD RFSD RCKD RHCKP RFSP
18
17
RCKP RFP3
16
15
RFP2
RFP1
14
13
12
RFP0 RDC4 RDC3
Figure 6-8 RCCR Register
Hardware and software reset clear all the bits of the RCCR register.
6.3.3.1
RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver
clock generator. A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit
clock output is available at the receiver serial bit clock (SCKR) pin of the DSP. The bit clock
output is also available internally for use as the bit clock to shift the receive shift registers. The
ESAI receive clock generator functional diagram is shown in Figure 6-3.
6.3.3.2
RCCR Receiver Prescaler Range (RPSR) - Bit 8
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This
bit is used to extend the range of the prescaler for those cases where a slower bit clock is
desired. When RPSR is set, the fixed prescaler is bypassed. When RPSR is cleared, the fixed
divide-by-eight prescaler is operational (see Figure 6-3). The maximum internally generated
bit clock frequency is Fosc/4, the minimum internally generated bit clock frequency is Fosc/(2
x 8 x 256)=Fosc/4096.
Note:
Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes
synchronization problems when using the internal DSP clock as source
(RHCKD=1 or RCKD=1).
6.3.3.3
RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used
to generate the receiver frame clocks.
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In network mode, this ratio may be interpreted as the number of words per frame minus one.
The divide ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A
divide ratio of one (RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from
1 to 32 (RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one
(RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(RFSL=1) must be used in this case.
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The ESAI frame sync generator functional diagram is shown in Figure 6-4.
6.3.3.4
RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the
receiver serial bit clock when the source of the receiver high frequency clock and the bit clock
is the internal DSP clock. When the HCKR input is being driven from an external high
frequency clock, the RFP3-RFP0 bits specify an additional division ration in the clock divider
chain. See Table 6-6 for the specification of the divide ratio. The ESAI high frequency
generator functional diagram is shown in Figure 6-3.
Table 6-6 Receiver High Frequency Clock Divider
RFP3-RFP0
Divide Ratio
$0
1
$1
2
$2
3
$3
4
...
...
$F
16
6.3.3.5
RCCR Receiver Clock Polarity (RCKP) - Bit 18
The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync
are clocked out and latched in. If RCKP is cleared the data and the frame sync are clocked out
on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge
of the receive bit clock. If RCKP is set the falling edge of the receive clock is used to clock the
data and frame sync out and the rising edge of the receive clock is used to latch the frame sync
in.
6.3.3.6
RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19
The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync
signal. When RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is
indicated by a high level on the frame sync pin). When RFSP is set the frame sync signal
polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin).
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6.3.3.7
RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20
The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge
data and frame sync are clocked out and latched in. If RHCKP is cleared the data and the
frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is
latched in on the falling edge of the receive bit clock. If RHCKP is set the falling edge of the
receive clock is used to clock the data and frame sync out and the rising edge of the receive
clock is used to latch the frame sync in.
6.3.3.8
RCCR Receiver Clock Source Direction (RCKD) - Bit 21
The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used
to clock the receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag
direction in the synchronous mode (SYN=1).
In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock
for the receive shift registers and word length divider, and is the output on the SCKR pin. In
the asynchronous mode when RCKD is cleared, the clock source is external; the internal clock
generator is disconnected from the SCKR pin, and an external clock source may drive this pin.
In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If
RCKD is cleared, then the SCKR pin becomes the IF0 input flag. See Table 6-1 and
Table 6-7.
Table 6-7 SCKR Pin Definition Table
Control Bits
SCKR PIN
SYN
RCKD
0
0
SCKR input
0
1
SCKR output
1
0
IF0
1
1
OF0
6.3.3.9
RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
The Receiver Frame Sync Signal Direction (RFSD) bit selects the source of the receiver frame
sync signal when in the asynchronous mode (SYN=0), and the IF1/OF1/Transmitter Buffer
Enable flag direction in the synchronous mode (SYN=1).
In the asynchronous mode when RFSD is set, the internal clock generator becomes the source
of the receiver frame sync, and is the output on the FSR pin. In the asynchronous mode when
RFSD is cleared, the receiver frame sync source is external; the internal clock generator is
disconnected from the FSR pin, and an external clock source may drive this pin.
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In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the
Transmitter Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the
FSR pin becomes the IF1 input flag. See Table 6-1 and Table 6-8.
Table 6-8 FSR Pin Definition Table
Control Bits
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FSR Pin
SYN
TEBE
RFSD
0
X
0
FSR input
0
X
1
FSR output
1
0
0
IF1
1
0
1
OF1
1
1
0
reserved
1
1
1
Transmitter
Buffer
Enable
6.3.3.10
RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver
high frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag
direction in the synchronous mode (SYN=1).
In the asynchronous mode when RHCKD is set, the internal clock generator becomes the
source of the receiver high frequency clock, and is the output on the HCKR pin. In the
asynchronous mode when RHCKD is cleared, the receiver high frequency clock source is
external; the internal clock generator is disconnected from the HCKR pin, and an external
clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If
RHCKD is cleared, then the HCKR pin becomes the IF2 input flag. See Table 6-1 and
Table 6-9.
Table 6-9 HCKR Pin Definition Table
Control Bits
HCKR PIN
MOTOROLA
SYN
RHCKD
0
0
HCKR input
0
1
HCKR output
1
0
IF2
1
1
OF2
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6.3.4
ESAI RECEIVE CONTROL REGISTER (RCR)
The read/write Receive Control Register (RCR) controls the ESAI receiver section. Interrupt
enable bits for the receivers are provided in this control register. The receivers are enabled in
this register (0,1,2 or 3 receivers can be enabled) if the input data pin is not used by a
transmitter. Operating modes are also selected in this register.
11
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10
9
8
7
RSWS1 RSWS0 RMOD1 RMOD0 RWA
23
22
21
20
19
RLIE
RIE
REDIE
REIE
RPR
6
5
4
3
2
1
0
RE3
RE2
RE1
RE0
16
15
14
13
12
RFSR
RFSL
RSHFD
18
17
RSWS4 RSWS3 RSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-9 RCR Register
Hardware and software reset clear all the bits in the RCR register.
The ESAI RCR bits are described in the following paragraphs.
6.3.4.1
RCR ESAI Receiver 0 Enable (RE0) - Bit 0
When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled and samples data at the
SDO5/SDI0 pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1).
When RE0 is cleared, receiver 0 is disabled by inhibiting data transfer into RX0. If this bit is
cleared while receiving a data word, the remainder of the word is shifted in and transferred to
the RX0 data register.
If RE0 is set while some of the other receivers are already in operation, the first data word
received in RX0 will be invalid and must be discarded.
6.3.4.2
RCR ESAI Receiver 1 Enable (RE1) - Bit 1
When RE1 is set and TE4 is cleared, the ESAI receiver 1 is enabled and samples data at the
SDO4/SDI1 pin. TX4 and RX1 should not be enabled at the same time (RE1=1 and TE4=1).
When RE1 is cleared, receiver 1 is disabled by inhibiting data transfer into RX1. If this bit is
cleared while receiving a data word, the remainder of the word is shifted in and transferred to
the RX1 data register.
If RE1 is set while some of the other receivers are already in operation, the first data word
received in RX1 will be invalid and must be discarded.
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6.3.4.3
RCR ESAI Receiver 2 Enable (RE2) - Bit 2
When RE2 is set and TE3 is cleared, the ESAI receiver 2 is enabled and samples data at the
SDO3/SDI2 pin. TX3 and RX2 should not be enabled at the same time (RE2=1 and TE3=1).
When RE2 is cleared, receiver 2 is disabled by inhibiting data transfer into RX2. If this bit is
cleared while receiving a data word, the remainder of the word is shifted in and transferred to
the RX2 data register.
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If RE2 is set while some of the other receivers are already in operation, the first data word
received in RX2 will be invalid and must be discarded.
6.3.4.4
RCR ESAI Receiver 3 Enable (RE3) - Bit 3
When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled and samples data at the
SDO2/SDI3 pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1).
When RE3 is cleared, receiver 3 is disabled by inhibiting data transfer into RX3. If this bit is
cleared while receiving a data word, the remainder of the word is shifted in and transferred to
the RX3 data register.
If RE3 is set while some of the other receivers are already in operation, the first data word
received in RX3 will be invalid and must be discarded.
6.3.4.5
RCR Reserved Bits - Bits 4-5, 17-18
These bits are reserved. They read as zero, and they should be written with zero for future
compatibility.
6.3.4.6
RCR Receiver Shift Direction (RSHFD) - Bit 6
The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is
cleared or LSB first when RSHFD is set (see Figure 6-13 and Figure 6-14).
6.3.4.7
RCR Receiver Word Alignment Control (RWA) - Bit 7
The Receiver Word Alignment Control (RWA) bit defines the alignment of the data word in
relation to the slot. This is relevant for the cases where the word length is shorter than the slot
length. If RWA is cleared, the data word is assumed to be left-aligned in the slot frame. If
RWA is set, the data word is assumed to be right-aligned in the slot frame.
If the data word is shorter than the slot length, the data bits which are not in the data word
field are ignored.
For data word lengths of less than 24 bits, the data word is right-extended with zeroes before
being stored in the receive data registers.
6.3.4.8
RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9
The RMOD1 and RMOD0 bits are used to define the network mode of the ESAI receivers
according to Table 6-10. In the normal mode, the frame rate divider determines the word
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transfer rate – one word is transferred per frame sync during the frame sync time slot, as
shown in Figure 6-6. In network mode, it is possible to transfer a word for every time slot, as
shown in Figure 6-6. For more details, see Section 6.4, “Operating Modes”.
In order to comply with AC-97 specifications, RSWS4-RSWS0 should be set to 00011 (20-bit
slot, 20-bit word), RFSL and RFSR should be cleared, and RDC4-RDC0 should be set to $0C
(13 words in frame).
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Table 6-10 ESAI Receive Network Mode Selection
RMOD1
RMOD0
RDC4-RDC0
Receiver Network Mode
0
0
$0-$1F
Normal Mode
0
1
$0
On-Demand Mode
0
1
$1-$1F
Network Mode
1
0
X
Reserved
1
1
$0C
AC97
6.3.4.9
RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14
The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data
words being received via the ESAI. The word length must be equal to or shorter than the slot
length. The possible combinations are shown in Table 6-11. See also the ESAI data path
programming model in Figure 6-13 and Figure 6-14.
Table 6-11 ESAI Receive Slot and Word Length Selection
6-32
RSWS4
RSWS3
RSWS2
RSWS1
RSWS0
SLOT LENGTH
WORD LENGTH
0
0
0
0
0
8
8
0
0
1
0
0
12
8
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
12
0
0
0
1
0
16
0
1
1
0
0
0
1
0
0
1
12
0
0
1
1
0
16
0
0
0
1
1
20
1
0
0
0
0
0
1
1
0
1
12
0
1
0
1
0
16
0
0
1
1
1
20
1
1
1
1
0
24
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8
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Table 6-11 ESAI Receive Slot and Word Length Selection (Continued)
RSWS4
RSWS3
RSWS2
RSWS1
RSWS0
SLOT LENGTH
WORD LENGTH
1
1
0
0
0
32
8
1
0
1
0
1
12
1
0
0
1
0
16
0
1
1
1
1
20
1
1
1
1
1
24
0
1
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
Reserved
6.3.4.10
RCR Receiver Frame Sync Length (RFSL) - Bit 15
The RFSL bit selects the length of the receive frame sync to be generated or recognized. If
RFSL is cleared, a word-length frame sync is selected. If RFSL is set, a 1-bit clock period
frame sync is selected. See Figure 6-7 for examples of frame length selection.
6.3.4.11
RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16
RFSR determines the relative timing of the receive frame sync signal as referred to the serial
data lines, for a word length frame sync only. When RFSR is cleared the word length frame
sync occurs together with the first bit of the data word of the first slot. When RFSR is set the
word length frame sync starts one serial clock cycle earlier (i.e. together with the last bit of the
previous data word).
6.3.4.12
RCR Receiver Section Personal Reset (RPR) - Bit 19
The RPR control bit is used to put the receiver section of the ESAI in the personal reset state.
The transmitter section is not affected. When RPR is cleared, the receiver section may operate
normally. When RPR is set, the receiver section enters the personal reset state immediately.
When in the personal reset state, the status bits are reset to the same state as after hardware
reset.The control bits are not affected by the personal reset state.The receiver data pins are
disconnected while in the personal reset state. Note that to leave the personal reset state by
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clearing RPR, the procedure described in Section 6.6, “ESAI Initialization Examples” should
be followed.
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6.3.4.13
RCR Receive Exception Interrupt Enable (REIE) - Bit 20
When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status
register are set. When REIE is cleared, this interrupt is disabled. Reading the SAISR status
register followed by reading the enabled receivers data registers clears ROE, thus clearing the
pending interrupt.
6.3.4.14
RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set,
the receive even slot data interrupts are enabled. If REDIE is cleared, the receive even slot
data interrupts are disabled. A receive even slot data interrupt request is generated if REDIE is
set and the REDF status flag in the SAISR status register is set. Even time slots are all
even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot is
marked by the frame sync signal and is considered to be even. Reading all the data registers of
the enabled receivers clears the REDF flag, thus servicing the interrupt.
Receive interrupts with exception have higher priority than receive even slot data interrupts,
therefore if exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive
data with exception interrupt from the interrupt controller.
6.3.4.15
RCR Receive Interrupt Enable (RIE) - Bit 22
The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When
RIE is cleared, this interrupt is disabled. Reading the receive data registers of the enabled
receivers clears RDF, thus clearing the interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts,
therefore if exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive
data with exception interrupt from the interrupt controller.
6.3.4.16
RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
RLIE enables an interrupt after the last slot of a frame ended in network mode only. When
RLIE is set the DSP is interrupted after the last slot in a frame ended regardless of the receive
mask register setting. When RLIE is cleared the receive last slot interrupt is disabled.
Hardware and software reset clear RLIE. RLIE is disabled when RDC[4:0]=00000
(on-demand mode). The use of the receive last slot interrupt is described in Section 6.4.3,
“ESAI Interrupt Requests”.
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6.3.5
ESAI COMMON CONTROL REGISTER (SAICR)
The read/write Common Control Register (SAICR) contains control bits for functions that
affect both the receive and transmit sections of the ESAI. See Figure 6-10.
11
10
9
X:$FFFFB4
Freescale Semiconductor, Inc...
23
22
21
8
7
6
ALC
TEBE
SYN
20
19
18
5
17
4
16
3
15
2
1
0
OF2
OF1
OF0
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-10 SAICR Register
Hardware and software reset clear all the bits in the SAICR register.
6.3.5.1
SAICR Serial Output Flag 0 (OF0) - Bit 0
The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When
the ESAI is in the synchronous clock mode (SYN=1), the SCKR pin is configured as the
ESAI flag 0. If the receiver serial clock direction bit (RCKD) is set, the SCKR pin is the
output flag OF0, and data present in the OF0 bit is written to the OF0 pin at the beginning of
the frame in normal mode or at the beginning of the next time slot in network mode.
6.3.5.2
SAICR Serial Output Flag 1 (OF1) - Bit 1
The Serial Output Flag 1 (OF1) is a data bit used to hold data to be send to the OF1 pin. When
the ESAI is in the synchronous clock mode (SYN=1), the FSR pin is configured as the ESAI
flag 1. If the receiver frame sync direction bit (RFSD) is set and the TEBE bit is cleared, the
FSR pin is the output flag OF1, and data present in the OF1 bit is written to the OF1 pin at the
beginning of the frame in normal mode or at the beginning of the next time slot in network
mode.
6.3.5.3
SAICR Serial Output Flag 2 (OF2) - Bit 2
The Serial Output Flag 2 (OF2) is a data bit used to hold data to be send to the OF2 pin. When
the ESAI is in the synchronous clock mode (SYN=1), the HCKR pin is configured as the
ESAI flag 2. If the receiver high frequency clock direction bit (RHCKD) is set, the HCKR pin
is the output flag OF2, and data present in the OF2 bit is written to the OF2 pin at the
beginning of the frame in normal mode or at the beginning of the next time slot in network
mode.
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ESAI Programming Model
6.3.5.4
SAICR Reserved Bits - Bits 3-5, 9-23
These bits are reserved. They read as zero, and they should be written with zero for future
compatibility.
Freescale Semiconductor, Inc...
6.3.5.5
SAICR Synchronous Mode Selection (SYN) - Bit 6
The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter
sections of the ESAI operate synchronously or asynchronously with respect to each other (see
Figure 6-11). When SYN is cleared, the asynchronous mode is chosen and independent clock
and frame sync signals are used for the transmit and receive sections. When SYN is set, the
synchronous mode is chosen and the transmit and receive sections use common clock and
frame sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter
section clock generator as the source of the clock and frame sync for both sections. Also, the
receiver clock pins SCKR, FSR and HCKR now operate as I/O flags. See Table 6-7, Table 6-8
and Table 6-9 for the effects of SYN on the receiver clock pins.
6.3.5.6
SAICR Transmit External Buffer Enable (TEBE) - Bit 7
The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when
in the synchronous mode. If the ESAI is configured for operation in the synchronous mode
(SYN=1), and TEBE is set while FSR pin is configured as an output (RFSD=1), the FSR pin
functions as the transmitter external buffer enable control, to enable the use of an external
buffers on the transmitter outputs. If TEBE is cleared then the FSR pin functions as the serial
I/O flag 1. See Table 6-8 for a summary of the effects of TEBE on the FSR pin.
6.3.5.7
SAICR Alignment Control (ALC) - Bit 8
The ESAI is designed for 24-bit fractional data, thus shorter data words are left aligned to the
MSB (bit 23). Some applications use 16-bit fractional data. In those cases, shorter data words
may be left aligned to bit 15. The Alignment Control (ALC) bit supports these applications.
If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and
receive shift registers. If ALC is cleared, transmitted and received word are left aligned to bit
23 in the transmit and receive shift registers.
Note:
6-36
While ALC is set, 20-bit and 24-bit words may not be used, and word length
control should specify 8-, 12- or 16-bit words, otherwise results are unpredictable.
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ESAI Programming Model
ASYNCHRONOUS (SYN=0)
TRANSMITTER
SDO
FRAME
SYNC
CLOCK
EXTERNAL TRANSMIT CLOCK
EXTERNAL TRANSMIT FRAME SYNC
SCKT
ESAI BIT
CLOCK
FST
INTERNAL CLOCK
INTERNAL FRAME SYNC
EXTERNAL RECEIVE CLOCK
EXTERNAL RECEIVE FRAME SYNC
Freescale Semiconductor, Inc...
SCKR
FSR
CLOCK
FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN=1)
TRANSMITTER
SDO
FRAME
SYNC
CLOCK
EXTERNAL CLOCK
EXTERNAL FRAME SYNC
SCKT
ESAI BIT
CLOCK
FST
INTERNAL CLOCK
INTERNAL FRAME SYNC
CLOCK
FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver have the same clocks and frame syncs.
Figure 6-11 SAICR SYN Bit Operation
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ESAI Programming Model
6.3.6
ESAI STATUS REGISTER (SAISR)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status
and serial input flags of the ESAI. See Figure 6-12. The status bits are described in the
following paragraphs.
11
Freescale Semiconductor, Inc...
X:$FFFFB3
10
9
RODF REDF
23
22
21
8
7
6
RDF
ROE
RFS
20
19
18
5
17
4
16
TODE TEDE
3
2
1
0
IF2
IF1
IF0
15
14
13
12
TDE
TUE
TFS
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-12 SAISR Register
6.3.6.1
SAISR Serial Input Flag 0 (IF0) - Bit 0
The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control
Register, SYN=1 and RCKD=0, indicating that SCKR is an input flag and the synchronous
mode is selected. Data present on the SCKR pin is latched during reception of the first
received data bit after frame sync is detected. The IF0 bit is updated with this data when the
receiver shift registers are transferred into the receiver data registers. IF0 reads as a zero when
it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF0.
6.3.6.2
SAISR Serial Input Flag 1 (IF1) - Bit 1
The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register,
SYN =1, RFSD=0 and TEBE=0, indicating that FSR is an input flag and the synchronous
mode is selected. Data present on the FSR pin is latched during reception of the first received
data bit after frame sync is detected. The IF1 bit is updated with this data when the receiver
shift registers are transferred into the receiver data registers. IF1 reads as a zero when it is not
enabled. Hardware, software, ESAI individual, and STOP reset clear IF1.
6.3.6.3
SAISR Serial Input Flag 2 (IF2) - Bit 2
The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control
Register, SYN=1 and RHCKD=0, indicating that HCKR is an input flag and the synchronous
mode is selected. Data present on the HCKR pin is latched during reception of the first
received data bit after frame sync is detected. The IF2 bit is updated with this data when the
receive shift registers are transferred into the receiver data registers. IF2 reads as a zero when
it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF2.
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ESAI Programming Model
6.3.6.4
SAISR Reserved Bits - Bits 3-5, 11-12, 18-23
These bits are reserved for future use. They read as zero.
Freescale Semiconductor, Inc...
6.3.6.5
SAISR Receive Frame Sync Flag (RFS) - Bit 6
When set, RFS indicates that a receive frame sync occurred during reception of the words in
the receiver data registers. This indicates that the data words are from the first slot in the
frame. When RFS is clear and a word is received, it indicates (only in the network mode) that
the frame sync did not occur during reception of that word. RFS is cleared by hardware,
software, ESAI individual, or STOP reset. RFS is valid only if at least one of the receivers is
enabled (REx=1).
Note:
In normal mode, RFS always reads as a one when reading data because there is
only one time slot per frame – the “frame sync” time slot.
6.3.6.6
SAISR Receiver Overrun Error Flag (ROE) - Bit 7
The ROE flag is set when the serial receive shift register of an enabled receiver is full and
ready to transfer to its receiver data register (RXx) and the register is already full (RDF=1). If
REIE is set, an ESAI receive data with exception (overrun error) interrupt request is issued
when ROE is set. Hardware, software, ESAI individual, and STOP reset clear ROE. ROE is
also cleared by reading the SAISR with ROE set, followed by reading all the enabled receive
data registers.
6.3.6.7
SAISR Receive Data Register Full (RDF) - Bit 8
RDF is set when the contents of the receive shift register of an enabled receiver is transferred
to the respective receive data register. RDF is cleared when the DSP reads the receive data
register of all enabled receivers or cleared by hardware, software, ESAI individual, or STOP
reset. If RIE is set, an ESAI receive data interrupt request is issued when RDF is set.
6.3.6.8
SAISR Receive Even-Data Register Full (REDF) - Bit 9
When set, REDF indicates that the received data in the receive data registers of the enabled
receivers have arrived during an even time slot when operating in the network mode. Even
time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to
N-1, where N is the number of time slots in the frame. The zero time slot is considered even.
REDF is set when the contents of the receive shift registers are transferred to the receive data
registers. REDF is cleared when the DSP reads all the enabled receive data registers or cleared
by hardware, software, ESAI individual, or STOP resets. If REDIE is set, an ESAI receive
even slot data interrupt request is issued when REDF is set.
6.3.6.9
SAISR Receive Odd-Data Register Full (RODF) - Bit 10
When set, RODF indicates that the received data in the receive data registers of the enabled
receivers have arrived during an odd time slot when operating in the network mode. Odd time
slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1,
where N is the number of time slots in the frame. RODF is set when the contents of the receive
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ESAI Programming Model
Freescale Semiconductor, Inc...
shift registers are transferred to the receive data registers. RODF is cleared when the DSP
reads all the enabled receive data registers or cleared by hardware, software, ESAI individual,
or STOP resets.
6.3.6.10
SAISR Transmit Frame Sync Flag (TFS) - Bit 13
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is
set at the start of the first time slot in the frame and cleared during all other time slots. Data
written to a transmit data register during the time slot when TFS is set is transmitted (in
network mode), if the transmitter is enabled, during the second time slot in the frame. TFS is
useful in network mode to identify the start of a frame. TFS is cleared by hardware, software,
ESAI individual, or STOP reset. TFS is valid only if at least one transmitter is enabled (i.e.
one or more of TE0, TE1, TE2, TE3, TE4 and TE5 are set).
Note:
In normal mode, TFS always reads as a one when transmitting data because there
is only one time slot per frame – the “frame sync” time slot.
6.3.6.11
SAISR Transmit Underrun Error Flag (TUE) - Bit 14
TUE is set when at least one of the enabled serial transmit shift registers is empty (no new
data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs,
the previous data (which is still present in the TX registers that were not written) is
retransmitted. If TEIE is set, an ESAI transmit data with exception (underrun error) interrupt
request is issued when TUE is set. Hardware, software, ESAI individual, and STOP reset clear
TUE. TUE is also cleared by reading the SAISR with TUE set, followed by writing to all the
enabled transmit data registers or to TSR.
6.3.6.12
SAISR Transmit Data Register Empty (TDE) - Bit 15
TDE is set when the contents of the transmit data register of all the enabled transmitters are
transferred to the transmit shift registers; it is also set for a TSR disabled time slot period in
network mode (as if data were being transmitted after the TSR was written). When set, TDE
indicates that data should be written to all the TX registers of the enabled transmitters or to the
time slot register (TSR). TDE is cleared when the DSP writes to all the transmit data registers
of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the
next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TDE is set.
Hardware, software, ESAI individual, and STOP reset clear TDE.
6.3.6.13
SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16
When set, TEDE indicates that the enabled transmitter data registers became empty at the
beginning of an even time slot. Even time slots are all even-numbered slots (0, 2, 4, 6, etc.).
Time slots are numbered from zero to N-1, where N is the number of time slots in the frame.
The zero time slot is considered even. This flag is set when the contents of the transmit data
register of all the enabled transmitters are transferred to the transmit shift registers; it is also
set for a TSR disabled time slot period in network mode (as if data were being transmitted
after the TSR was written). When set, TEDE indicates that data should be written to all the TX
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ESAI Programming Model
Freescale Semiconductor, Inc...
registers of the enabled transmitters or to the time slot register (TSR). TEDE is cleared when
the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP
writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit
data interrupt request is issued when TEDE is set. Hardware, software, ESAI individual, and
STOP reset clear TEDE.
6.3.6.14
SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17
When set, TODE indicates that the enabled transmitter data registers became empty at the
beginning of an odd time slot. Odd time slots are all odd-numbered slots (1, 3, 5, etc.). Time
slots are numbered from zero to N-1, where N is the number of time slots in the frame. This
flag is set when the contents of the transmit data register of all the enabled transmitters are
transferred to the transmit shift registers; it is also set for a TSR disabled time slot period in
network mode (as if data were being transmitted after the TSR was written). When set, TODE
indicates that data should be written to all the TX registers of the enabled transmitters or to the
time slot register (TSR). TODE is cleared when the DSP writes to all the transmit data
registers of the enabled transmitters, or when the DSP writes to the TSR to disable
transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is
issued when TODE is set. Hardware, software, ESAI individual, and STOP reset clear TODE.
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ESAI Programming Model
23
16 15
RECEIVE HIGH BYTE
SERIAL
RECEIVE
SHIFT
REGISTER
8 7
RECEIVE MIDDLE BYTE
7
0
23
16 15
7
0 7
0
8 7
0
RECEIVE MIDDLE BYTE
0
ESAI RECEIVE DATA REGISTER
(READ ONLY)
RECEIVE LOW BYTE
7
RECEIVE HIGH BYTE
0
RECEIVE LOW BYTE
7
0 7
0
24 BIT
20 BIT
Freescale Semiconductor, Inc...
16 BIT
SDI
12 BIT
8 BIT
MSB
RSWS4RSWS0
LSB
8-BIT DATA
0
MSB
0
0
LEAST SIGNIFICANT
ZERO FILL
0
LSB
12-BIT DATA
LSB
MSB
16-BIT DATA
MSB
LSB
20-BIT DATA
MSB
LSB
24-BIT DATA
NOTES:
1. Data is received MSB first if RSHFD=0.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
(a) Receive Registers
23
16 15
TRANSMIT HIGH BYTE
7
TRANSMIT MIDDLE BYTE
0
23
0 7
16 15
7
7
0
0 7
*
MSB
ESAI TRANSMIT
SHIFT REGISTER
TRANSMIT LOW BYTE
0
LSB
8-BIT DATA
ESAI TRANSMIT DATA
REGISTER
(WRITE ONLY)
0
8 7
TRANSMIT MIDDLE BYTE
0
MSB
0
TRANSMIT LOW BYTE
7
TRANSMIT HIGH BYTE
SDO
8 7
*
*
*
* - LEAST SIGNIFICANT
BIT FILL
LSB
12-BIT DATA
LSB
MSB
16-BIT DATA
MSB
LSB
20-BIT DATA
MSB
24-BIT DATA
LSB
NOTES:
1. Data is sent MSB first if TSHFD=0.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
4. Data word is left-aligned (TWA=0,PADC=0).
(b) Transmit Registers
Figure 6-13 ESAI Data Path Programming Model ([R/T]SHFD=0)
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ESAI Programming Model
23
16 15
RECEIVE HIGH BYTE
RECEIVE MIDDLE BYTE
7
0
23
16 15
7
RECEIVE HIGH BYTE
SDI
0
7
ESAI RECEIVE DATA REGISTER
(READ ONLY)
0 7
0
8 7
0
RECEIVE LOW BYTE
0 7
ESAI RECEIVE
SHIFT REGISTER
0
LSB
8-BIT DATA
0
MSB
Freescale Semiconductor, Inc...
0
RECEIVE LOW BYTE
RECEIVE MIDDLE BYTE
7
MSB
8 7
0
0
LEAST SIGNIFICANT
ZERO FILL
0
LSB
12-BIT DATA
LSB
MSB
16-BIT DATA
MSB
LSB
20-BIT DATA
MSB
LSB
24-BIT DATA
NOTES:
1. Data is received LSB first if RSHFD=1.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
(a) Receive Registers
23
16 15
TRANSMIT HIGH BYTE
8 7
TRANSMIT MIDDLE BYTE
TRANSMIT LOW BYTE
7
0
7
0 7
23
16 15
8 7
TRANSMIT HIGH BYTE
7
TRANSMIT MIDDLE BYTE
0
7
0
0
TRANSMIT LOW BYTE
0 7
ESAI TRANSMIT DATA
0 REGISTER
(WRITE ONLY)
ESAI TRANSMIT
SHIFT REGISTER
0
24 BIT
20 BIT
16 BIT
12 BIT
SDO
8 BIT
MSB
LSB
8-BIT DATA
0
MSB
0
0
0
TSWS4TSWS0
LSB
12-BIT DATA
LSB
MSB
16-BIT DATA
MSB
LSB
20-BIT DATA
MSB
LSB
24-BIT DATA
NOTES:
1. Data is sent LSB first if TSHFD=1.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
4. Data word is left aligned (TWA=0,PADC=1).
(b) Transmit Registers
Figure 6-14 ESAI Data Path Programming Model ([R/T]SHFD=1)
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ESAI Programming Model
6.3.7
ESAI RECEIVE SHIFT REGISTERS
Freescale Semiconductor, Inc...
The receive shift registers (see Figure 6-13 and Figure 6-14) receive the incoming data from
the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when
the associated frame sync I/O is asserted. Data is assumed to be received MSB first if
RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI receive data registers
after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot length
control bits in the RCR register.
6.3.8
ESAI RECEIVE DATA REGISTERS (RX3, RX2, RX1, RX0)
RX3, RX2, RX1 and RX0 are 24-bit read-only registers that accept data from the receive shift
registers when they become full (see Figure 6-13 and Figure 6-14). The data occupies the
most significant portion of the receive data registers, according to the ALC control bit setting.
The unused bits (least significant portion, and 8 most significant bits when ALC=1) read as
zeros. The DSP is interrupted whenever RXx becomes full if the associated interrupt is
enabled.
6.3.9
ESAI TRANSMIT SHIFT REGISTERS
The transmit shift registers contain the data being transmitted (see Figure 6-13 and Figure
6-14). Data is shifted out to the serial transmit data pins by the selected (internal/external) bit
clock when the associated frame sync I/O is asserted. The number of bits shifted out before
the shift registers are considered empty and may be written to again can be 8, 12, 16, 20, 24 or
32 bits (determined by the slot length control bits in the TCR register). Data is shifted out of
these registers MSB first if TSHFD=0 and LSB first if TSHFD=1.
6.3.10
ESAI TRANSMIT DATA REGISTERS (TX5, TX4, TX3,
TX2,TX1,TX0)
TX5, TX4, TX3, TX2, TX1 and TX0 are 24-bit write-only registers. Data to be transmitted is
written into these registers and is automatically transferred to the transmit shift registers (see
Figure 6-13 and Figure 6-14). The data written (8, 12, 16, 20 or 24 bits) should occupy the
most significant portion of the TXx according to the ALC control bit setting. The unused bits
(least significant portion, and the 8 most significant bits when ALC=1) of the TXx are don’t
care bits. The DSP is interrupted whenever the TXx becomes empty if the transmit data
register empty interrupt has been enabled.
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ESAI Programming Model
6.3.11
ESAI TIME SLOT REGISTER (TSR)
Freescale Semiconductor, Inc...
The write-only Time Slot Register (TSR) is effectively a null data register that is used when
the data is not to be transmitted in the available transmit time slot. The transmit data pins of all
the enabled transmitters are in the high-impedance state for the respective time slot where
TSR has been written. The Transmitter External Buffer Enable pin (FSR pin when SYN=1,
TEBE=1, RFSD=1) disables the external buffers during the slot when the TSR register has
been written.
6.3.12
TRANSMIT SLOT MASK REGISTERS (TSMA, TSMB)
The Transmit Slot Mask Registers (TSMA and TSMB) are two read/write registers used by
the transmitters in network mode to determine for each slot whether to transmit a data word
and generate a transmitter empty condition (TDE=1), or to tri-state the transmitter data pins.
TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See
Figure 6-15 and Figure 6-16. Bit number N in TSM (TS**) is the enable/disable control bit
for transmission in slot number N.
X:$FFFFB9
11
10
9
8
7
6
5
4
3
2
1
0
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-15 TSMA Register
X:$FFFFBA
11
10
9
8
7
6
5
4
3
2
1
0
TS27
TS26
TS25
TS24
TS23
TS22
TS21
TS20
TS19
TS18
TS17
TS16
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-16 TSMB Register
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ESAI Programming Model
When bit number N in TSM is cleared, all the transmit data pins of the enabled transmitters
are tri-stated during transmit time slot number N. The data is still transferred from the transmit
data registers to the transmit shift registers but neither the TDE nor the TUE flags are set. This
means that during a disabled slot, no transmitter empty interrupt is generated. The DSP is
interrupted only for enabled slots. Data that is written to the transmit data registers when
servicing this request is transmitted in the next enabled transmit time slot.
Freescale Semiconductor, Inc...
When bit number N in TSM register is set, the transmit sequence is as usual: data is
transferred from the TX registers to the shift registers, transmitted during slot number N, and
the TDE flag is set.
Using the slot mask in TSM does not conflict with using TSR. Even if a slot is enabled in
TSM, the user may chose to write to TSR instead of writing to the transmit data registers TXx.
This causes all the transmit data pins of the enabled transmitters to be tri-stated during the
next slot.
Data written to the TSM affects the next frame transmission. The frame being transmitted is
not affected by this data and would comply to the last TSM setting. Data read from TSM
returns the last written data.
After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that
all 32 possible slots are enabled for data transmission.
Note:
6.3.13
When operating in normal mode, bit 0 of the mask register must be set, otherwise
no output is generated.
RECEIVE SLOT MASK REGISTERS (RSMA, RSMB)
The Receive Slot Mask Registers (RSMA and RSMB) are two read/write registers used by the
receiver in network mode to determine for each slot whether to receive a data word and
generate a receiver full condition (RDF=1), or to ignore the received data. RSMA and RSMB
should be considered as each containing half of a 32-bit register RSM. See Table 6-17 and
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ESAI Programming Model
Table 6-18. Bit number N in RSM (RS**) is an enable/disable control bit for receiving data in
slot number N.
Freescale Semiconductor, Inc...
X:$FFFFBB
11
10
9
8
7
6
5
4
3
2
1
0
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-17 RSMA Register
X:$FFFFBC
11
10
9
8
7
6
5
4
3
2
1
0
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-18 RSMB Register
When bit number N in the RSM register is cleared, the data from the enabled receivers input
pins are shifted into their receive shift registers during slot number N. The data is not
transferred from the receive shift registers to the receive data registers, and neither the RDF
nor the ROE flags are set. This means that during a disabled slot, no receiver full interrupt is
generated. The DSP is interrupted only for enabled slots.
When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted
into the enabled receivers shift registers is transferred to the receive data registers and the
RDF flag is set.
Data written to the RSM affects the next received frame. The frame being received is not
affected by this data and would comply to the last RSM setting. Data read from RSM returns
the last written data.
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Operating Modes
After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that
all 32 possible slots are enabled for data reception.
Note:
Freescale Semiconductor, Inc...
6.4
When operating in normal mode, bit 0 of the mask register must be set to one,
otherwise no input is received.
OPERATING MODES
ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR
and SAICR). The main operating mode are described in the following paragraphs.
6.4.1
ESAI AFTER RESET
Hardware or software reset clears the port control register bits and the port direction control
register bits, which configure all ESAI I/O pins as disconnected. The ESAI is in the individual
reset state while all ESAI pins are programmed as GPIO or disconnected, and is active only if
at least one of the ESAI I/O pins is programmed as an ESAI pin.
6.4.2
ESAI INITIALIZATION
The correct way to initialize the ESAI is as follows:
1. Hardware, software, ESAI individual, or STOP reset.
2. Program ESAI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one pin as ESAI pin.
During program execution, all ESAI pins may be defined as GPIO or disconnected, causing
the ESAI to stop serial activity and enter the individual reset state. All status bits of the
interface are set to their reset state; however, the control bits are not affected. This procedure
allows the DSP programmer to reset the ESAI separately from the other internal peripherals.
During individual reset, internal DMA accesses to the data registers of the ESAI are not valid
and data read is undefined.
The DSP programmer must use an individual ESAI reset when changing the ESAI control
registers (except for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure
proper operation of the interface.
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Operating Modes
Note:
6.4.3
If the ESAI receiver section is already operating with some of the receivers,
enabling additional receivers on the fly (i.e. without first putting the ESAI receiver
in the personal reset state) by setting their REx control bits will result in erroneous
data being received as the first data word for the newly enabled receivers.
ESAI INTERRUPT REQUESTS
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The ESAI can generate eight different interrupt requests (ordered from the highest to the
lowest priority):
1. ESAI Receive Data with Exception Status.
Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register),
at least one of the enabled receive data registers is full (RDF=1), and a receiver
overrun error has occurred (ROE=1 in the SAISR register). ROE is cleared by first
reading the SAISR and then reading all the enabled receive data registers.
2. ESAI Receive Even Data
Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one of
the enabled receive data registers is full (RDF=1), the data is from an even slot
(REDF=1), and no exception has occurred (ROE=0 or REIE=0).
Reading all enabled receiver data registers clears RDF and REDF.
3. ESAI Receive Data
Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled
receive data registers is full (RDF=1), no exception has occurred (ROE=0 or REIE=0),
and no even slot interrupt has occurred (REDF=0 or REDIE=0).
Reading all enabled receiver data registers clears RDF.
4. ESAI Receive Last Slot Interrupt
Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode
only) regardless of the receive mask register setting. The receive last slot interrupt may
be used for resetting the receive mask slot register, reconfiguring the DMA channels
and reassigning data memory pointers. Using the receive last slot interrupt guarantees
that the previous frame was serviced with the previous setting and the new frame is
serviced with the new setting without synchronization problems. Note that the
maximum receive last slot interrupt service time should not exceed N-1 ESAI bits
service time (where N is the number of bits in a slot).
5. ESAI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one
transmit data register of the enabled transmitters is empty (TDE=1), and a transmitter
underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and
then writing to all the enabled transmit data registers, or to the TSR register.
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Operating Modes
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6. ESAI Transmit Last Slot Interrupt
Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode
regardless of the transmit mask register setting. The transmit last slot interrupt may be
used for resetting the transmit mask slot register, reconfiguring the DMA channels and
reassigning data memory pointers. Using the transmit last slot interrupt guarantees that
the previous frame was serviced with the previous setting and the new frame is
serviced with the new setting without synchronization problems. Note that the
maximum transmit last slot interrupt service time should not exceed N-1 ESAI bits
service time (where N is the number of bits in a slot).
7. ESAI Transmit Even Data
Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one
of the enabled transmit data registers is empty (TDE=1), the slot is an even slot
(TEDE=1), and no exception has occurred (TUE=0 or TEIE=0).
Writing to all the TX registers of the enabled transmitters or to TSR clears this
interrupt request.
8. ESAI Transmit Data
Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled
transmit data registers is empty (TDE=1), no exception has occurred (TUE=0 or
TEIE=0), and no even slot interrupt has occurred (TEDE=0 or TEDIE=0).
Writing to all the TX registers of the enabled transmitters, or to the TSR clears this
interrupt request.
6.4.4
OPERATING MODES – NORMAL, NETWORK, AND
ON-DEMAND
The ESAI has three basic operating modes and many data/operation formats.
6.4.4.1
Normal/Network/On-Demand Mode Selection
Selecting between the normal mode and network mode is accomplished by clearing or setting
the TMOD0-TMOD1 bits in the TCR register for the transmitter section, and in the
RMOD0-RMOD1 bits in the RCR register for the receiver section.
For normal mode, the ESAI functions with one data word of I/O per frame (per enabled
transmitter or receiver). The normal mode is typically used to transfer data to/from a single
device.
For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to
32 data words of I/O may be received/transmitted. In either case, the transfers are periodic.
The frame sync signal indicates the first time slot in the frame. Network mode is typically
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Operating Modes
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used in time division multiplexed (TDM) networks of codecs, DSPs with multiple words per
frame, or multi-channel devices.
Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects the
on-demand mode. This special case does not generate a periodic frame sync. A frame sync
pulse is generated only when data is available to transmit. The on-demand mode requires that
the transmit frame sync be internal (output) and the receive frame sync be external (input).
Therefore, for simplex operation, the synchronous mode could be used; however, for
full-duplex operation, the asynchronous mode must be used. Data transmission that is data
driven is enabled by writing data into each TX. Although the ESAI is double buffered, only
one word can be written to each TX, even if the transmit shift register is empty. The receive
and transmit interrupts function as usual using TDE and RDF; however, transmit underruns
are impossible for on-demand transmission and are disabled.
6.4.4.2
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESAI may be synchronous or asynchronous – i.e., the
transmitter and receiver sections may use common clock and synchronization signals
(synchronous operating mode), or they may have their own separate clock and sync signals
(asynchronous operating mode). The SYN bit in the SAICR register selects synchronous or
asynchronous operation. Since the ESAI is designed to operate either synchronously or
asynchronously, separate receive and transmit interrupts are provided.
When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are
independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync come
from the transmitter section (either external or internal sources).
Data clock and frame sync signals can be generated internally by the DSP or may be obtained
from external sources. If internally generated, the ESAI clock generator is used to derive high
frequency clock, bit clock and frame sync signals from the DSP internal system clock.
6.4.4.3
Frame Sync Selection
The frame sync can be either a bit-long or word-long signal. The transmitter frame format is
defined by the TFSL bit in the TCR register. The receiver frame format is defined by the
RFSL bit in the RCR register.
1. In the word-long frame sync format, the frame sync signal is asserted during the entire
word data transfer period. This frame sync length is compatible with Motorola codecs,
SPI serial peripherals, serial A/D and D/A converters, shift registers, and
telecommunication PCM serial I/O.
2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock
immediately before the data transfer period. This frame sync length is compatible with
Intel and National components, codecs, and telecommunication PCM serial I/O.
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Operating Modes
The relative timing of the word length frame sync as referred to the data word is specified by
the TFSR bit in the TCR register for the transmitter section, and by the RFSR bit in the RCR
register for the receive section. The word length frame sync may be generated (or expected)
with the first bit of the data word, or with the last bit of the previous word. TFSR and RFSR
are ignored when a bit length frame sync is selected.
Freescale Semiconductor, Inc...
Polarity of the frame sync signal may be defined as positive (asserted high) or negative
(asserted low). The TFSP bit in the TCCR register specifies the polarity of the frame sync for
the transmitter section. The RFSP bit in the RCCR register specifies the polarity of the frame
sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set)
only when the previous frame is completed. If the frame sync goes high before the frame is
completed (or before the last bit of the frame is received in the case of a bit frame sync or a
word length frame sync with RFSR set), the current frame sync is not recognized, and the
receiver is internally disabled until the next frame sync. Frames do not have to be adjacent –
i.e., a new frame sync does not have to immediately follow the previous frame. Gaps of
arbitrary periods can occur between frames. Enabled transmitters are tri-stated during these
gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync are
generated by the transmitter section.
6.4.4.4
Shift Direction Selection
Some data formats, such as those used by codecs, specify MSB first while other data formats,
such as the AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection
is made by programming RSHFD bit in the RCR register for the receiver section, and by
programming the TSHFD bit in the TCR register for the transmitter section.
6.4.5
SERIAL I/O FLAGS
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is
operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD,
TEBE bits in the RCR, RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0)
and the input data bits (IF2, IF1 and IF0) are double buffered to/from the HCKR, FSR and
SCKR pins. Double buffering the flags keeps them in sync with the TX and RX data lines.
Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD,
RCKD=1 for output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when the pin is not
configured as external transmitter buffer enable (TEBE=0) and its direction is selected by
RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by
RHCKD, RHCKD=1 for output and RHCKD=0 for input.
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When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively, are
latched at the same time as the first bit of the receive data word is sampled. Because the input
was latched, the signal on the input flag pin (SCKR, FSR or HCKR) can change without
affecting the input flag until the first bit of the next receive data word. When the received data
words are transferred to the receive data registers, the input flag latched values are then
transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they may be read by
software.
When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by the
contents of the OF0, OF1 and OF2 bits in the SAICR register respectively, and are driven
when the transmit data registers are transferred to the transmit shift registers. The value on
SCKR, FSR and HCKR is stable from the time the first bit of the transmit data word is
transmitted until the first bit of the next transmit data word is transmitted. Software may
change the OF0-OF2 values thus controlling the SCKR, FSR and HCKR pin values for each
transmitted word. The normal sequence for setting output flags when transmitting data is as
follows: wait for TDE (transmitter empty) to be set, first write the flags, and then write the
transmit data to the transmit registers. OF0, OF1 and OF2 are double buffered so that the flag
states appear on the pins when the transmit data is transferred to the transmit shift register
(i.e., the flags are synchronous with the data).
6.5
GPIO - PINS AND REGISTERS
The GPIO functionality of the ESAI port is controlled by three registers: Port C control
register (PCRC), Port C direction register (PRRC) and Port C data register (PDRC).
6.5.1
PORT C CONTROL REGISTER (PCRC)
The read/write 24-bit Port C Control Register (PCRC) in conjunction with the Port C
Direction Register (PRRC) controls the functionality of the ESAI GPIO pins. Each of the
PC(11:0) bits controls the functionality of the corresponding port pin. See Table 6-12 for the
port pin configurations. Hardware and software reset clear all PCRC bits.
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GPIO - Pins and Registers
6.5.2
PORT C DIRECTION REGISTER (PRRC)
The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C
Control Register (PCRC) controls the functionality of the ESAI GPIO pins. Table 6-12
describes the port pin configurations. Hardware and software reset clear all PRRC bits.
Freescale Semiconductor, Inc...
Table 6-12 PCRC and PRRC Bits Functionality
X:$FFFFBF
PDC[i]
PC[i]
Port Pin[i] Function
0
0
disconnected
0
1
GPIO input
1
0
GPIO output
1
1
ESAI
11
10
9
8
7
6
5
4
3
2
1
0
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-19 PCRC Register
X:$FFFFBE
11
10
9
8
7
6
5
4
3
2
1
0
PDC11
PDC10
PDC9
PDC8
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-20 PRRC Register
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6.5.3
PORT C DATA REGISTER (PDRC)
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The read/write 24-bit Port C Data Register (see Table 6-21) is used to read or write data
to/from ESAI GPIO pins. Bits PD(11:0) are used to read or write data from/to the
corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a
GPIO input, then the corresponding PD[i] bit reflects the value present on this pin. If a port
pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit
is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i]
bit is not reset and contains undefined data.
X:$FFFFBD
11
10
9
8
7
6
5
4
3
2
1
0
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 6-21 PDRC Register
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ESAI Initialization Examples
6.6
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6.6.1
ESAI INITIALIZATION EXAMPLES
Initializing the ESAI Using Individual Reset
•
The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000). In
the individual reset state, both the transmitter and receiver sections of the ESAI are
simultaneously reset. The TPR bit in the TCR register may be used to reset just the
transmitter section. The RPR bit in the RCR register may be used to reset just the
receiver section.
•
Configure the control registers (TCCR, TCR, RCCR, RCR) according to the operating
mode, but do not enable transmitters (TE5–TE0 = $0) or receivers (RE3–RE0 = $0). It
is possible to set the interrupt enable bits which are in use during the operation (no
interrupt occurs).
•
Enable the ESAI by setting the PCRC register and PRRC register bits according to
pins which are in use during operation.
•
Write the first data to be transmitted to the transmitters which are in use during
operation.
This step is needed even if DMA is used to service the transmitters.
•
Enable the transmitters and receivers.
•
From now on ESAI can be serviced either by polling, interrupts, or DMA.
Operation proceeds as follows:
•
For internally generated clock and frame sync, these signals are active immediately
after ESAI is enabled (step 3 above).
•
Data is received only when one of the receive enable (REx) bits is set and after the
occurrence of frame sync signal (either internally or externally generated).
•
Data is transmitted only when the transmitter enable (TEx) bit is set and after the
occurrence of frame sync signal (either internally or externally generated). The
transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs.
6.6.2
Initializing Just the ESAI Transmitter Section
•
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI
pin.
•
The transmitter section should be in its personal reset state (TPR = 1).
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ESAI Initialization Examples
•
Configure the control registers TCCR and TCR according to the operating mode,
making sure to clear the transmitter enable bits (TE0 - TE5). TPR must remain set.
•
Take the transmitter section out of the personal reset state by clearing TPR.
•
Write first data to the transmitters which will be used during operation. This step is
needed even if DMA is used to service the transmitters.
•
Enable the transmitters by setting their TE bits.
•
Data is transmitted only when the transmitter enable (TEx) bit is set and after the
occurrence of frame sync signal (either internally or externally generated). The
transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs.
•
From now on the transmitters are operating and can be serviced either by polling,
interrupts, or DMA.
6.6.3
Initializing Just the ESAI Receiver Section
•
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI
pin.
•
The receiver section should be in its personal reset state (RPR = 1).
•
Configure the control registers RCCR and RCR according to the operating mode,
making sure to clear the receiver enable bits (RE0 - RE3). RPR must remain set.
•
Take the receiver section out of the personal reset state by clearing RPR.
•
Enable the receivers by setting their RE bits.
•
From now on the receivers are operating and can be serviced either by polling,
interrupts, or DMA.
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ESAI Initialization Examples
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SECTION
7
SERIAL HOST INTERFACE
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7.1
INTRODUCTION
The Serial Host Interface (SHI) is a serial I/O interface that provides a path for
communication and program/coefficient data transfers between the DSP and an external host
processor. The SHI can also communicate with other serial peripheral devices. The SHI can
interface directly to either of two well-known and widely used synchronous serial buses: the
Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-circuit Control
(I2C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a slave or a
single-master device. To minimize DSP overhead, the SHI supports single-, double-, and
triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30
bytes before generating a receive interrupt, reducing the overhead for data reception.
When configured in the SPI mode, the SHI can:
•
Identify its slave selection (in Slave mode)
•
Simultaneously transmit (shift out) and receive (shift in) serial data
•
Directly operate with 8-, 16- and 24-bit words
•
Generate vectored interrupts, separately for receive and transmit events, and update
status bits
•
Generate a separate vectored interrupt in the event of a receive exception
•
Generate a separate vectored interrupt in the event of a bus-error exception
•
Optionally trigger DMA interrupts to service the transmit and receive events
•
Generate the serial clock signal (in Master mode)
When configured in the I2C mode, the SHI can:
•
Detect/generate start and stop events
•
Identify its slave (ID) address (in Slave mode)
•
Identify the transfer direction (receive/transmit)
•
Transfer data byte-wise according to the SCL clock line
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Serial Host Interface
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Serial Host Interface Internal Architecture
•
Generate ACK signal following a byte receive
•
Inspect ACK signal following a byte transmit
•
Directly operate with 8-, 16- and 24-bit words
•
Generate vectored interrupts separately for receive and transmit events and update
status bits
•
Generate a separate vectored interrupt in the event of a receive exception
•
Generate a separate vectored interrupt in the event of a bus error exception
•
Optionally trigger DMA interrupts to service the transmit and receive events
•
Generate the clock signal (in Master mode)
7.2
SERIAL HOST INTERFACE INTERNAL ARCHITECTURE
The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The
DSP may access the SHI as a normal memory-mapped peripheral using standard polling or
interrupt programming techniques and DMA transfers. Memory mapping allows DSP
communication with the SHI registers to be accomplished using standard instructions and
addressing modes. In addition, the MOVEP instruction allows interface-to-memory and
memory-to-interface data transfers without going through an intermediate register. The DMA
controller may be used to service the receive or transmit data path. The single master
configuration allows the DSP to directly connect to dumb peripheral devices. For that
purpose, a programmable baud-rate generator is included to generate the clock signal for
serial transfers. The host side invokes the SHI, for communication and data transfer with the
DSP, through a shift register that may be accessed serially using either the I2C or the SPI bus
protocols. Figure 7-1 shows the SHI block diagram.
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Serial Host Interface
SHI Clock Generator
Host Accessible
DSP Accessible
DSP
Global
Data
Bus
Clock
Generator
SCK/SCL
HCSR
Freescale Semiconductor, Inc...
MISO/SDA
MOSI/HA0
DSP
DMA
Data
Bus
HCKR
Controller
Logic
Pin
Control
Logic
HTX
INPUT/OUTPUT Shift Register
(IOSR)
SS/HA2
HREQ
HRX
(FIFO)
Slave
Address
Recognition
Unit
(SAR)
HSAR
24 BIT
AA0416 new
Figure 7-1 Serial Host Interface Block Diagram
7.3
SHI CLOCK GENERATOR
The SHI clock generator generates the serial clock to the SHI if the interface operates in the
Master mode. The clock generator is disabled if the interface operates in the Slave mode,
except in I2C mode when the HCKFR bit is set in the HCKR register. When the SHI operates
in the Slave mode, the clock is external and is input to the SHI (HMST = 0). Figure 7-2
illustrates the internal clock path connections. It is the user’s responsibility to select the proper
clock rate within the range as defined in the I2C and SPI bus specifications.
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HMST
SHI Clock
SCK/SCL
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FOSC
Divide
By 2
HMST = 0
Divide By 1
To
Divide By 256
Divide By
1 or 8
HDM0–HDM7
HRS
Clock
Logic
SHI
Controller
HMST = 1
CPHA, CPOL, HI2C
AA0417k new
Figure 7-2 SHI Clock Generator
7.4
SERIAL HOST INTERFACE PROGRAMMING MODEL
The Serial Host Interface programming model is divided in two parts:
•
Host side—see Figure 7-3 below and Section 7.4.1 on page Section 7-6
•
DSP side—see Figure 7-4 on page Section 7-5 and Sections 7.4.2 on page Section 7-7
through 7.4.6 on page Section 7-12 for detailed information.
23
0
I/O Shift Register (IOSR)
IOSR
AA0418
Figure 7-3 SHI Programming Model—Host Side
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HA5
HA6
HA4
21
HA3
20
22
21
20
21
HBER
22
HBUSY
HROE
20
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HRFF
19
19
19
18
18
HA1
18
HRNE
17
17
17
16
16
16
HTDE
15
15
15
HTUE
14
14
14
Reserved bit, read as 0, should be written with 0 for future compatibility.
SHI Transmit Data Register (HTX)
(write only, X: $FFFF93)
23
SHI Receive Data FIFO (HRX)
(read only, X: $FFFF94)
23
23
SHI Control/Status Register (HCSR)
X: $FFFF91
23
SHI Clock Control Register (HCKR)
X: $FFFF90
22
23
SHI I2C Slave Address Register (HSAR)
X: $FFFF92
11
11
11
HTIE
HBIE
HTX
10
HDM7
10
10
FIFO (10 Words Deep)
HRX
HRIE1 HRIE0
12
HFM0
HFM1
13
12
12
13
13
HIDLE
9
HDM6
9
9
HRQE1
8
HDM5
8
8
6
6
5
HDM2
5
5
4
HDM1
4
4
3
HDM0
3
3
HMST HFIFO HCKFR HM1
6
HDM3
HRQE0
7
HDM4
7
7
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HI2C
1
CPOL
1
1
AA0419k new
HM0
2
HRS
2
2
0
0
HEN
0
CPHA
0
0
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Serial Host Interface
Serial Host Interface Programming Model
Figure 7-4 SHI Programming Model—DSP Side
7-5
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Serial Host Interface
Serial Host Interface Programming Model
The interrupt vector table for the Serial Host Interface is shown in Table 7-1 and the
exceptions generated by the SHI are prioritized as shown in Table 7-2.
Table 7-1 SHI Interrupt Vectors
Freescale Semiconductor, Inc...
Program Address
Interrupt Source
VBA:$40
SHI Transmit Data
VBA:$42
SHI Transmit Underrun Error
VBA:$44
SHI Receive FIFO Not Empty
VBA:$48
SHI Receive FIFO Full
VBA:$4A
SHI Receive Overrun Error
VBA:$4C
SHI Bus Error
Table 7-2 SHI Internal Interrupt Priorities
Priority
Highest
Interrupt
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
Lowest
7.4.1
SHI Receive FIFO Not Empty
SHI INPUT/OUTPUT SHIFT REGISTER (IOSR)—HOST SIDE
The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel
and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both
directions (read and write). In compliance with the I2C and SPI bus protocols, data is shifted
in and out MSB first. In single-byte data transfer modes, the most significant byte of the IOSR
is used as the shift register. In 16-bit data transfer modes, the two most significant bytes
become the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the
IOSR (see Figure 7-5).
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Note:
The IOSR cannot be accessed directly either by the host processor or by the DSP.
It is fully controlled by the SHI controller logic.
23
16
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Mode of Operation
15
8-Bit Data
Mode
8
7
16-Bit Data
Mode
0
24-Bit Data
Mode
Stops Data When Data Mode is Selected
Passes Data When Data Mode is Selected
AA0420k
Figure 7-5 SHI I/O Shift Register (IOSR)
7.4.2
SHI HOST TRANSMIT DATA REGISTER (HTX)—DSP SIDE
The Host Transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX
register is 24 bits wide. Writing to the HTX register by DSP core instructions or by DMA
transfers clears the HTDE flag. The DSP may program the HTIE bit to cause a Host transmit
data interrupt when HTDE is set (see 7.4.6.11 HCSR Transmit-Interrupt Enable
(HTIE)—Bit 11 on page 7-15). Data should not be written to the HTX until HTDE is set in
order to prevent overwriting the previous data. HTX is reset to the empty state when in Stop
mode and during hardware reset, software reset, and individual reset.
In the single-byte data transfer mode the most significant byte of the HTX is transmitted; in
the double-byte mode the two most significant bytes, and in the triple-byte mode all the HTX
is transferred.
7.4.3
SHI HOST RECEIVE DATA FIFO (HRX)—DSP SIDE
The 24-bit Host Receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO)
register used for Host-to-DSP data transfers. The serial data is received via the shift register
and then loaded into the HRX. In the single-byte data transfer mode, the most significant byte
of the shift register is transferred to the HRX (the other bits are filled with 0s); in the
double-byte mode the two most significant bytes are transferred (the least significant byte is
filled with 0s), and in the triple-byte mode, all 24 bits are transferred to the HRX. The HRX
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may be read by the DSP while the FIFO is being loaded from the shift register. Reading all
data from HRX will clear the HRNE flag. HRX may be read by DSP core instructions or by
DMA transfers. The HRX FIFO is reset to the empty state (cleared) when the chip is in Stop
mode, and during hardware reset, software reset, and individual reset.
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7.4.4
SHI SLAVE ADDRESS REGISTER (HSAR)—DSP SIDE
The 24-bit Slave Address Register (HSAR) is used when the SHI operates in the I 2C Slave
mode and is ignored in the other operational modes. HSAR holds five bits of the 7-bit slave
address of the device. The SHI also acknowledges the general call address (all 0s, 7-bit
address, and a 0 R/W bit) specified by the I2C protocol, but will treat any following data bytes
as regular data, i.e. the SHI does not differentiate between its dedicated address and the
general call address. HSAR cannot be accessed by the host processor.
7.4.4.1
HSAR Reserved Bits—Bits 17–0,19
These bits are reserved and unused. They read as 0s and should be written with 0s for future
compatibility.
7.4.4.2
HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18
Part of the I2C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR.
The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the
HA0 and HA2 pins to obtain the HA[6:0] slave device address. The full 7-bit slave device
address is compared to the received address byte whenever an I2C master device initiates an
I2C bus transfer. During hardware reset or software reset, HA[6:3] = 1011 while HA1 is
cleared; this results in a default slave device address of 1011_HA2_0_HA0.
7.4.5
SHI CLOCK CONTROL REGISTER (HCKR)—DSP SIDE
The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls the SHI
clock generator operation. The HCKR bits should be modified only while the SHI is in the
individual reset state (HEN = 0 in the HCSR).
Note:
The programmer should not use the combination HRS = 1 and HDM[7:0] =
00000000, since it may cause synchronization problems and improper operation (it
is therefore considered an illegal combination).
Note:
The HCKR bits are cleared during hardware reset or software reset, except for
CPHA, which is set. The HCKR is not affected by the Stop state.
The HCKR bits are described in the following paragraphs.
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7.4.5.1
Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The programmer may select any of four combinations of Serial Clock (SCK) phase and
polarity when operating in the SPI mode (refer to Figure 7-6 on page Section 7-9). The clock
polarity is determined by the Clock Polarity (CPOL) control bit, which selects an active-high
or active-low clock. When CPOL is cleared, it produces a steady-state low value at the SCK
pin of the master device whenever data is not being transferred. If the CPOL bit is set, a high
value is produced at the SCK pin of the master device whenever data is not being transferred.
Freescale Semiconductor, Inc...
SS
SCK
(CPOL = 0, CPHA = 0)
SCK
(CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
SCK
(CPOL = 1, CPHA = 1)
MISO/
MOSI
MSB
6
5
4
3
2
1
LSB
Internal Strobe for Data Capture
AA0421
Figure 7-6 SPI Data-To-Clock Timing Diagram
The Clock Phase (CPHA) bit controls the relationship between the data on the MISO and
MOSI pins and the clock produced or received at the SCK pin. This control bit is used in
conjunction with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit,
in general, selects the clock edge that captures data and allows it to change states. It has its
greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock
transition before the data capture edge.
When in Slave mode and CPHA = 0, the SS line must be deasserted and asserted by the
external master between each successive word transfer. SS must remain asserted between
successive bytes within a word. The DSP core should write the next data word to HTX when
HTDE = 1, clearing HTDE. However, the data will be transferred to the shift register for
transmission only when SS is deasserted. HTDE is set when the data is transferred from HTX
to the shift register.
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When in Slave mode and CPHA = 1, the SS line may remain asserted between successive
word transfers. The SS must remain asserted between successive bytes within a word. The
DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The
HTX data will be transferred to the shift register for transmission as soon as the shift register
is empty. HTDE is set when the data is transferred from HTX to the shift register.
When in Master mode and CPHA = 0, the DSP core should write the next data word to HTX
when HTDE = 1, clearing HTDE; the data is transferred immediately to the shift register for
transmission. HTDE is set only at the end of the data word transmission.
Freescale Semiconductor, Inc...
Note:
The master is responsible for deasserting and asserting the slave device SS line
between word transmissions.
When in Master mode and CPHA = 1, the DSP core should write the next data word to HTX
when HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift register for
transmission as soon as the shift register is empty. HTDE is set when the data is transferred
from HTX to the shift register.
The clock phase and polarity should be identical for both the master and slave SPI devices.
CPHA and CPOL are functional only when the SHI operates in the SPI mode, and are ignored
in the I2C mode. The CPHA bit is set and the CPOL bit is cleared during hardware reset and
software reset.
7.4.5.2
HCKR Prescaler Rate Select (HRS)—Bit 2
The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to
extend the range of the divider when slower clock rates are desired. When HRS is set, the
prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight prescaler is operational.
HRS is ignored when the SHI operates in the Slave mode, except for I2C when HCKFR is set.
The HRS bit is cleared during hardware reset and software reset.
Note:
Use the equations in the SHI datasheet to determine the value of HRS for the
specific serial clock frequency required.
7.4.5.3
HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3
The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio
between 1 and 256 (HDM[7:0] = 0 to $FF) may be selected. When the SHI operates in the
Slave mode [except for I2C when HCKFR is set], the HDM[7:0] bits are ignored. The
HDM[7:0] bits are cleared during hardware reset and software reset.
Note:
7-10
Use the equations in the SHI datasheet to determine the value of HDM[7:0] for the
specific serial clock frequency required.
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7.4.5.4
HCKR Reserved Bits—Bits 23–14, 11
These bits in HCKR are reserved and unused. They are read as 0s and should be written with
0s for future compatibility.
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7.4.5.5
HCKR Filter Mode (HFM[1:0]) — Bits 13–12
The read/write control bits HFM[1:0] specify the operational mode of the noise reduction
filters, as described in Table 7-3 on page Section 7-11. The filters are designed to eliminate
undesired spikes that might occur on the clock and data-in lines and allow the SHI to operate
in noisy environments when required. One filter is located in the input path of the SCK/SCL
line and the other is located in the input path of the data line (i.e., the SDA line when in I2C
mode, the MISO line when in SPI Master mode, and the MOSI line when in SPI Slave mode).
Table 7-3 SHI Noise Reduction Filter Mode
HFM1
HFM0
Description
0
0
Bypassed (Disabled)
0
1
Reserved
1
0
Narrow Spike Tolerance
1
1
Wide Spike Tolerance
When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is
useful when higher bit-rate transfers are required and the SHI operates in a noise-free
environment.
When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected. In this
mode the filters eliminate spikes with durations of up to 50ns. This mode is suitable for use in
mildly noisy environments and imposes some limitations on the maximum achievable bit-rate
transfer.
When HFM1 = 1 and HFM0 = 1, the wide-spike-tolerance filter mode is selected. In this
mode the filters eliminate spikes up to 100ns. This mode is recommended for use in noisy
environments; the bit-rate transfer is strictly limited. The wide-spike- tolerance filter mode is
highly recommended for use in I2C bus systems as it fully conforms to the I2C bus
specification and improves noise immunity.
Note:
HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to
‘00’), the programmer should wait at least ten times the tolerable spike width before enabling
the SHI (setting the HEN bit in the HCSR). Similarly, after changing the I2C bit in the HCSR
or the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode (HFM[1:0]
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not equal to ‘00’), the programmer should wait at least ten times the tolerable spike width
before enabling the SHI (setting HEN in the HCSR).
7.4.6
SHI CONTROL/STATUS REGISTER (HCSR)—DSP SIDE
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The HCSR is a 24-bit read/write register that controls the SHI operation and reflects its status.
Each bit is described in one of the following paragraphs. When in the Stop state or during
individual reset, the HCSR status bits are reset to their hardware-reset state, while the control
bits are not affected.
7.4.6.1
HCSR Host Enable (HEN)—Bit 0
The read/write control bit Host Enable (HEN) enables the overall operation of the SHI. When
HEN is set, SHI operation is enabled. When HEN is cleared, the SHI is disabled (individual
reset state, see below). The HCKR and the HCSR control bits are not affected when HEN is
cleared. When operating in Master mode, HEN should be cleared only after the SHI is idle
(HBUSY = 0). HEN is cleared during hardware reset and software reset.
7.4.6.1.1
SHI Individual Reset
While the SHI is in the individual reset state, SHI input pins are inhibited, output and
bidirectional pins are disabled (high impedance), the HCSR status bits and the
transmit/receive paths are reset to the same state produced by hardware reset or software reset.
The individual reset state is entered following a one-instruction-cycle delay after clearing
HEN.
7.4.6.2
HCSR I2C/SPI Selection (HI2C)—Bit 1
The read/write control bit HI2C selects whether the SHI operates in the I2C or SPI modes.
When HI2C is cleared, the SHI operates in the SPI mode. When HI2C is set, the SHI operates
in the I2C mode. HI2C affects the functionality of the SHI pins as described in Section 2 Pin
Descriptions. It is recommended that an SHI individual reset be generated (HEN cleared)
before changing HI2C. HI2C is cleared during hardware reset and software reset.
7.4.6.3
HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2
The read/write control bits HM[1:0] select the size of the data words to be transferred, as
shown in Table 7-4 on page Section 7-13. HM[1:0] should be modified only when the SHI is
idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset.
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Table 7-4 SHI Data Size
HM1
HMO
Description
0
0
8-bit data
0
1
16-bit data
1
0
24-bit data
1
1
Reserved
7.4.6.4
HCSR I2C Clock Freeze (HCKFR) - Bit 4
The read/write control bit HCSR I2C Clock Freeze (HCKFR) determines the behavior of the
SHI when operating in the I2C Slave mode in cases where the SHI is unable to service the
master request. The HCKFR bit is used only when operating in the I2C Slave mode; it is
ignored otherwise.
If HCKFR is set, the SHI will hold the clock line to GND if it is not ready to send data to the
master during a read transfer, or if the input FIFO is full when the master attempts to execute
a write transfer. In this way, the master may detect that the slave is not ready for the requested
transfer, without causing an error condition in the slave. When HCKFR is set for transmit
sessions, the SHI clock generator must be programmed as if to generate the same serial clock
as produced by the external master, otherwise erroneous operation may result. The
programmed frequency should be equal to or up to 25% less than the external clock
frequency.
If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not
ready will result in an overrun or underrun error condition.
It is recommended that an SHI individual reset be generated (HEN cleared) before changing
HCKFR. HCKFR is cleared during hardware reset and software reset.
7.4.6.5
HCSR Reserved Bits—Bits 23, 18 and 16
These bits in HCSR are reserved and unused. They are read as 0s and should be written with
0s for future compatibility.
7.4.6.6
HCSR FIFO-Enable Control (HFIFO)—Bit 5
The read/write control bit HCSR FIFO-enable control (HFIFO) selects the size of the receive
FIFO. When HFIFO is cleared, the FIFO has a single level. When HFIFO is set, the FIFO has
10 levels. It is recommended that an SHI individual reset be generated (HEN cleared) before
changing HFIFO. HFIFO is cleared during hardware reset and software reset.
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Serial Host Interface Programming Model
7.4.6.7
HCSR Master Mode (HMST)—Bit 6
The read/write control bit HCSR Master (HMST) determines the operating mode of the SHI.
If HMST is set, the interface operates in the Master mode. If HMST is cleared, the interface
operates in the Slave mode. The SHI supports a single-master configuration, in both I 2C and
SPI modes. When configured as an SPI Master, the SHI drives the SCK line and controls the
direction of the data lines MOSI and MISO. The SS line must be held deasserted in the SPI
Master mode; if the SS line is asserted when the SHI is in SPI Master mode, a bus error will
be generated (the HCSR HBER bit will be set—see Section 7.4.6.18Host Bus Error
(HBER)—Bit 21 ). When configured as an I2C Master, the SHI controls the I2C bus by
generating start events, clock pulses, and stop events for transmission and reception of serial
data. It is recommended that an SHI individual reset be generated (HEN cleared) before
changing HMST. HMST is cleared during hardware reset and software reset.
7.4.6.8
HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
The read/write Host-Request Enable control bits (HRQE[1:0]) are used to enable the
operation of the HREQ pin. When HRQE[1:0] are cleared, the HREQ pin is disabled and held
in the high impedance state. If either HRQE0 or HRQE1 are set and the SHI is operating in a
Master mode, the HREQ pin becomes an input that controls SCK: deasserting HREQ will
suspend SCK. If either HRQE0 or HRQE1 are set and the SHI is operating in a Slave mode,
HREQ becomes an output and its operation is defined in Table 7-5. HRQE[1:0] should be
modified only when the SHI is idle (HBUSY = 0). HRQE[1:0] are cleared during hardware
reset and software reset.
Table 7-5 HREQ Function In SHI Slave Modes
HRQE1
HRQE0
HREQ Pin Operation
0
0
High impedance
0
1
Asserted if IOSR is ready to receive a new word
1
0
Asserted if IOSR is ready to transmit a new word
1
1
I2C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive
7.4.6.9
HCSR Idle (HIDLE)—Bit 9
The read/write control/status bit Host Idle (HIDLE) is used only in the I2C Master mode; it is
ignored otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE
is cleared by writing to HTX. To ensure correct transmission of the slave device address byte,
HIDLE should be set only when HTX is empty (HTDE = 1). After HIDLE is set, a write to
HTX will clear HIDLE and cause the generation of a stop event, a start event, and then the
transmission of the eight MSBs of the data as the slave device address byte. While HIDLE is
cleared, data written to HTX will be transmitted ‘as is.’ If the SHI completes transmitting a
word and there is no new data in HTX, the clock will be suspended after sampling ACK. If the
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SHI completes transmitting a word and there is no new data in HTX when HIDLE is set, a
stop event will be generated.
HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If
HIDLE is cleared, the reception will be acknowledged by sending a ‘0’ bit on the SDA line at
the ACK clock tick. If HIDLE is set, the reception will not be acknowledged (a ‘1’ bit is sent).
It is used to signal an end-of-data to a slave transmitter by not generating an ACK on the last
byte. As a result, the slave transmitter must release the SDA line to allow the master to
generate the stop event. If the SHI completes receiving a word and the HRX FIFO is full, the
clock will be suspended before transmitting an ACK. While HIDLE is cleared the bus is busy,
that is, the start event was sent but no Stop event was generated. Setting HIDLE will cause a
stop event after receiving the current word.
Note:
HIDLE is set while the SHI is not in the I2C Master mode.
Care should be taken to ensure that HIDLE be set by the programmer only after
disabling any DMA channel service to HTX.
HIDLE is set during hardware reset, software reset, individual reset, and while the
chip is in the Stop state.
7.4.6.10
HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write HCSR Bus-error Interrupt Enable (HBIE) control bit is used to enable the SHI
bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and the HBER status
bit must be polled to determine if an SHI bus error occurred. If both HBIE and HBER are set,
the SHI will request SHI bus-error interrupt service from the interrupt controller. HBIE is
cleared by hardware reset and software reset.
Note:
Clearing HBIE will mask a pending bus-error interrupt only after a
one-instruction-cycle delay. If HBIE is cleared in a long interrupt service routine,
it is recommended that at least one other instruction separate the instruction that
clears HBIE and the RTI instruction at the end of the interrupt service routine.
7.4.6.11
HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write HCSR Transmit-Interrupt Enable (HTIE) control bit is used to enable the SHI
transmit data interrupts. If HTIE is cleared, transmit interrupts are disabled, and the HTDE
status bit must be polled to determine if the SHI transmit-data register is empty. If both HTIE
and HTDE are set and HTUE is cleared, the SHI will request SHI transmit-data interrupt
service from the interrupt controller. If both HTIE and HTUE are set, the SHI will request SHI
transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by
hardware reset and software reset.
Note:
Clearing HTIE will mask a pending transmit interrupt only after a one-instruction
cycle-delay. If HTIE is cleared in a long interrupt service routine, it is
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recommended that at least one other instruction separate the instruction that clears
HTIE and the RTI instruction at the end of the interrupt service routine.
7.4.6.12
HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write HCSR Receive Interrupt Enable (HRIE[1:0]) control bits are used to enable
the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are disabled, and
the HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if
there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts will be
generated according to Table 7-6.
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Table 7-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0]
Interrupt
Condition
00
Disabled
Not applicable
01
Receive FIFO not empty
Receive Overrun Error
HRNE = 1 and HROE = 0
HROE = 1
10
Reserved
Not applicable
11
Receive FIFO full
Receive Overrun Error
HRFF = 1 and HROE = 0
HROE = 1
Note:
HRIE[1:0] are cleared by hardware and software reset.
Note:
Clearing HRIE[1:0] will mask a pending receive interrupt only after a
one-instruction-cycle delay. If HRIE[1:0] are cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HRIE[1:0] and the RTI instruction at the end of the interrupt
service routine.
7.4.6.13
HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit Host Transmit Underrun Error (HTUE) indicates that a
transmit-underrun error occurred. Transmit-underrun errors can occur only when operating in
the SPI Slave mode or the I2C Slave mode when HCKFR is cleared (in a Master mode,
transmission takes place on demand and no underrun can occur). It is set when both the shift
register and the HTX register are empty and the external master begins reading the next word:
•
When operating in the I2C mode, HTUE is set in the falling edge of the ACK bit. In
this case, the SHI will retransmit the previously transmitted word.
•
When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is
set at the assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector will be
generated. If a transmit interrupt occurs with HTUE cleared, the regular transmit-data
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interrupt vector will be generated. HTUE is cleared by reading the HCSR and then writing to
the HTX register. HTUE is cleared by hardware reset, software reset, SHI individual reset,
and during the Stop state.
7.4.6.14
HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit Host Transmit Data Empty (HTDE) indicates that the HTX register is
empty and can be written by the DSP. HTDE is set when the data word is transferred from
HTX to the shift register, except for a special case in SPI Master mode when CPHA = 0 (see
HCKR). When operating in the SPI Master mode with CPHA = 0, HTDE is set after the end
of the data word transmission. HTDE is cleared when HTX is written by the DSP either with
write instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI
individual reset, and during the Stop state.
7.4.6.15
Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit Host Receive FIFO Not Empty (HRNE) indicates that the Host
Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is not
empty. HRNE is cleared when HRX is read by the DSP (read instructions or DMA transfers),
reducing the number of words in the FIFO to 0. HRNE is cleared during hardware reset,
software reset, SHI individual reset, and during the Stop state.
7.4.6.16
Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit Host Receive FIFO Full (HRFF) indicates that the Host Receive FIFO
(HRX) is full. HRFF is set when the HRX FIFO is full. HRFF is cleared when HRX is read by
the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO.
HRFF is cleared by hardware reset, software reset, SHI individual reset, and during the Stop
state.
7.4.6.17
Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit Host Receive Overrun Error (HROE) indicates that a data-receive
overrun error occurred. Receive-overrun errors can not occur when operating in the I2C
Master mode, since the clock is suspended if the receive FIFO is full; it also cannot occur
when operating in the I2C Slave mode when HCKFR is set. HROE is set when the shift
register (IOSR) is filled and ready to transfer the data word to the HRX FIFO and the FIFO is
already full (HRFF is set). When a receive-overrun error occurs, the shift register is not
transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun
interrupt vector will be generated. If a receive interrupt occurs with HROE cleared, the regular
receive-data interrupt vector will be generated. HROE is cleared by reading the HCSR with
HROE set, followed by reading HRX. HROE is cleared by hardware reset, software reset, SHI
individual reset, and during the Stop state.
7.4.6.18
Host Bus Error (HBER)—Bit 21
The read-only status bit Host Bus Error (HBER) indicates that an SHI bus error occurred
when operating as a master (HMST set). In I2C mode, HBER is set if the transmitter does not
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receive an acknowledge after a byte is transferred; in this case, a stop event will be generated
and then transmission will be suspended. In SPI mode, the bit is set if SS is asserted; in this
case, transmission is suspended at the end of transmission of the current word. HBER is
cleared only by hardware reset, software reset, SHI individual reset, and during the Stop state.
7.4.6.19
HCSR Host Busy (HBUSY)—Bit 22
The read-only status bit Host Busy (HBUSY) indicates that the I 2C bus is busy (when in the
I2C mode) or that the SHI itself is busy (when in the SPI mode). When operating in the I2C
mode, HBUSY is set after the SHI detects a Start event and remains set until a Stop event is
detected. When operating in the Slave SPI mode, HBUSY is set while SS is asserted. When
operating in the Master SPI mode, HBUSY is set if the HTX register is not empty or if the
IOSR is not empty. HBUSY is cleared otherwise. HBUSY is cleared by hardware reset,
software reset, SHI individual reset, and during the Stop state.
7.5
SPI BUS CHARACTERISTICS
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a
Slave Select line (SS).During an SPI transfer, a byte is shifted out one data pin while a
different byte is simultaneously shifted in through a second data pin. It can be viewed as two
8-bit shift registers connected together in a circular manner, where one shift register is located
on the master side and the other on the slave side. Thus the data bytes in the master device and
slave device are effectively exchanged. The MISO and MOSI data pins are used for
transmitting and receiving serial data. When the SPI is configured as a master, MISO is the
master data input line, and MOSI is the master data output line. When the SPI is configured as
a slave device, these pins reverse roles.
Clock control logic allows a selection of clock polarity and a choice of two fundamentally
different clocking protocols to accommodate most available synchronous serial peripheral
devices. When the SPI is configured as a master, the control bits in the HCKR select the
appropriate clock rate, as well as the desired clock polarity and phase format (see Figure 7-6
on page Section 7-9).
The SS line allows individual selection of a slave SPI device; slave devices that are not
selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin in the
high-impedance state). When the SHI is configured as an SPI master device, the SS line
should be held high. If the SS line is driven low when the SHI is in SPI Master mode, a bus
error will be generated (the HCSR HBER bit will be set).
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7.6
I2C BUS CHARACTERISTICS
The I2C serial bus consists of two bi-directional lines, one for data signals (SDA) and one for
clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply
voltage via a pull-up resistor.
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Note:
7.6.1
Within the I2C bus specifications, the standard mode (100 kHz clock rate) and a
fast mode (400 kHz clock rate) are defined. The SHI may operate in both modes.
OVERVIEW
The I2C bus protocol must conform to the following rules:
•
Data transfer may be initiated only when the bus is not busy.
•
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line when the clock line is high will be interpreted as control
signals (see Figure 7-7).
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed
AA0422
Figure 7-7 I2C Bit Transfer
Accordingly, the I2C bus protocol defines the following events:
•
Bus not busy—Both data and clock lines remain high.
•
Start data transfer—The start event is defined as a change in the state of the data
line, from high to low, while the clock is high (see ).
•
Stop data transfer—The stop event is defined as a change in the state of the data line,
from low to high, while the clock is high (see ).
•
Data valid—The state of the data line represents valid data when, after a Start event,
the data line is stable for the duration of the high period of the clock signal. The data
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on the line may be changed during the low period of the clock signal. There is one
clock pulse per bit of data.
SDA
SCL
S
P
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Start Event
Stop Event
AA0423
Figure 7-8 I2C Start and Stop Events
Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put
on the bus by the transmitter when the master device generates an extra acknowledge-related
clock pulse. A slave receiver that is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock
pulse (see Figure 7-9).
Start
Event
SCL From
Master Device
Clock Pulse For
Acknowledgment
1
2
8
9
Data Output
by Transmitter
Data Output
by Receiver
S
AA0424
Figure 7-9 Acknowledgment on the I2C Bus
By definition, a device that generates a signal is called a “transmitter,” and the device that
receives the signal is called a “receiver.” The device that controls the signal is called the
“master” and the devices that are controlled by the master are called “slaves”. A master
receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge
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I2C Bus Characteristics
on the last byte that has been clocked out of the slave device. In this case the transmitter must
leave the data line high to enable the master generation of the stop event. Handshaking may
also be accomplished by use of the clock synchronizing mechanism. Slave devices can hold
the SCL line low, after receiving and acknowledging a byte, to force the master into a wait
state until the slave device is ready for the next byte transfer. The SHI supports this feature
when operating as a master device and will wait until the slave device releases the SCL line
before proceeding with the data transfer.
I2C DATA TRANSFER FORMATS
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7.6.2
I2C bus data transfers follow the following format: after the start event, a slave device address
is sent. This address is 7 bits wide, the eighth bit is a data direction bit (R/W); ‘0’ indicates a
transmission (write), and ‘1’ indicates a request for data (read). A data transfer is always
terminated by a stop event generated by the master device. However, if the master device still
wishes to communicate on the bus, it can generate another start event, and address another
slave device without first generating a stop event (this feature is not supported by the SHI
when operating as an I2C master device). This method is also used to provide indivisible data
transfers. Various combinations of read/write formats are illustrated in Figure 7-10 and Figure
7-11.
ACK from
Slave Device
S
Slave Address
Start
Event
0
A
ACK from
Slave Device
First Data Byte
A
ACK from
Slave Device
Data Byte
A S, P
N = 0 to M
Data Bytes
R/W
AA0425 new
Start or
Stop Event
Figure 7-10 I2C Bus Protocol For Host Write Cycle
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ACK from
Slave Device
S
Slave Address
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Start
Event
1
A
R/W
ACK from
Master Device
No ACK
from Master Device
A
1
Data Byte
Last Data Byte
N = 0 to M
Data Bytes
AA0426 new
P
Stop
Event
Figure 7-11 I2C Bus Protocol For Host Read Cycle
Note:
7.7
The first data byte in a write-bus cycle can be used as a user-predefined control
byte (e.g., to determine the location to which the forthcoming data bytes should be
transferred).
SHI PROGRAMMING CONSIDERATIONS
The SHI implements both SPI and I2C bus protocols and can be programmed to operate as a
slave device or a single-master device. Once the operating mode is selected, the SHI may
communicate with an external device by receiving and/or transmitting data. Before changing
the SHI operational mode, an SHI individual reset should be generated by clearing the HEN
bit. The following paragraphs describe programming considerations for each operational
mode.
7.7.1
SPI SLAVE MODE
The SPI Slave mode is entered by enabling the SHI (HEN = 1), selecting the SPI mode (HI2C
= 0), and selecting the Slave mode of operation (HMST = 0). The programmer should verify
that the CPHA and CPOL bits (in the HCKR) correspond to the external host clock phase and
polarity. Other HCKR bits are ignored. When configured in the SPI Slave mode, the SHI
external pins operate as follows:
•
SCK/SCL is the SCK serial clock input.
•
MISO/SDA is the MISO serial data output.
•
MOSI/HA0 is the MOSI serial data input.
•
SS/HA2 is the SS Slave Select input.
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•
HREQ is the Host Request output.
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In the SPI Slave mode, a receive, transmit, or full-duplex data transfer may be performed.
Actually, the interface simultaneously performs both data receive and transmit. The status bits
of both receive and transmit paths are active; however, the programmer may disable undesired
interrupts and ignore non-relevant status bits. It is recommended that an SHI individual reset
(HEN cleared) be generated before beginning data reception in order to reset the HRX FIFO
to its initial (empty) state (e.g., when switching from transmit to receive data).
If a write to HTX occurs, its contents are transferred to IOSR between data word transfers.
The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP
may write HTX using either DSP instructions or DMA transfers if the HTDE status bit is set.
If no writes to HTX occurred, the contents of HTX are not transferred to IOSR, so the data
that is shifted out when receiving is the same as the data present in the IOSR at the time. The
HRX FIFO contains valid receive data, which may be read by the DSP using either DSP
instructions or DMA transfers, if the HRNE status bit is set.
The HREQ output pin, if enabled for receive (HRQE1–HRQE0 = 01), is asserted when the
IOSR is ready for receive and the HRX FIFO is not full; this operation guarantees that the
next received data word will be stored in the FIFO. The HREQ output pin, if enabled for
transmit (HRQE1–HRQE0 = 10), is asserted when the IOSR is loaded from HTX with a new
data word to transfer. If HREQ is enabled for both transmit and receive (HRQE1–HRQE0 =
11), it is asserted when the receive and transmit conditions are true simultaneously. HREQ is
deasserted at the first clock pulse of the next data word transfer. The HREQ line may be used
to interrupt the external master device. Connecting the HREQ line between two SHI-equipped
DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full
hardware handshaking if operating with CPHA = 1.
The SS line should be kept asserted during a data word transfer. If the SS line is deasserted
before the end of the data word transfer, the transfer is aborted and the received data word is
lost.
7.7.2
SPI MASTER MODE
The SPI Master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode
(HI2C = 0), and selecting the Master mode of operation (HMST = 1). Before enabling the SHI
as an SPI master device, the programmer should program the proper clock rate, phase, and
polarity in HCKR. When configured in the SPI Master mode, the SHI external pins operate as
follows:
•
SCK/SCL is the SCK serial clock output.
•
MISO/SDA is the MISO serial data input.
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•
MOSI/HA0 is the MOSI serial data output.
•
SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
•
HREQ is the Host Request input.
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The external slave device can be selected either by using external logic or by activating a
GPIO pin connected to its SS pin. However, the SS input pin of the SPI master device should
be held deasserted (high) for proper operation. If the SPI master device SS pin is asserted, the
Host Bus Error status bit (HBER) is set. If the HBIE bit is also set, the SHI issues a request to
the DSP interrupt controller to service the SHI Bus Error interrupt.
In the SPI Master mode the DSP must write to HTX to receive, transmit, or perform a
full-duplex data transfer. Actually, the interface performs simultaneous data receive and
transmit. The status bits of both receive and transmit paths are active; however, the
programmer may disable undesired interrupts and ignore non-relevant status bits. In a data
transfer, the HTX is transferred to IOSR, clock pulses are generated, the IOSR data is shifted
out (via MOSI) and received data is shifted in (via MISO). The DSP programmer may write
HTX (if the HTDE status bit is set) using either DSP instructions or DMA transfers to initiate
the transfer of the next word. The HRX FIFO contains valid receive data, which may be read
by the DSP using either DSP instructions or DMA transfers, if the HRNE status bit is set.
Note:
Motorola recommends that an SHI individual reset (HEN cleared) be generated
before beginning data reception in order to reset the receive FIFO to its initial
(empty) state, such as when switching from transmit to receive data.
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared,
and considered if any of them is set. When asserted by the slave device, HREQ indicates that
the external slave device is ready for the next data transfer. As a result, the SPI master sends
clock pulses for the full data word transfer. HREQ is deasserted by the external slave device at
the first clock pulse of the new data transfer. When deasserted, HREQ will prevent the clock
generation of the next data word transfer until it is asserted again. Connecting the HREQ line
between two SHI-equipped DSPs, one operating as an SPI master device and the other as an
SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
7.7.3
I2C SLAVE MODE
The I2C Slave mode is entered by enabling the SHI (HEN = 1), selecting the I2C mode (HI2C
= 1), and selecting the Slave mode of operation (HMST = 0). In this operational mode the
contents of HCKR are ignored. When configured in the I2C Slave mode, the SHI external pins
operate as follows:
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SHI Programming Considerations
•
SCK/SCL is the SCL serial clock input.
•
MISO/SDA is the SDA open drain serial data line.
•
MOSI/HA0 is the HA0 slave device address input.
•
SS/HA2 is the HA2 slave device address input.
•
HREQ is the Host Request output.
When the SHI is enabled and configured in the I2C Slave mode, the SHI controller inspects
the SDA and SCL lines to detect a start event. Upon detection of the start event, the SHI
receives the slave device address byte and enables the slave device address recognition unit. If
the slave device address byte was not identified as its personal address, the SHI controller will
fail to acknowledge this byte by not driving low the SDA line at the ninth clock pulse (ACK =
1). However, it continues to poll the SDA and SCL lines to detect a new start event. If the
personal slave device address was correctly identified, the slave device address byte is
acknowledged (ACK = 0 is sent) and a receive/transmit session is initiated according to the
eighth bit of the received slave device address byte (i.e., the R/W bit).
7.7.3.1
Receive Data in I2C Slave Mode
A receive session is initiated when the personal slave device address has been correctly
identified and the R/W bit of the received slave device address byte has been cleared.
Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following
each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA
line. Data is acknowledged bytewise, as required by the I2C bus protocol, and is transferred to
the HRX FIFO when the complete word (according to HM0–HM1) is filled into IOSR. It is
the responsibility of the programmer to select the correct number of bytes in an I2C frame so
that they fit in a complete number of words. For this purpose, the slave device address byte
does not count as part of the data, and therefore, it is treated separately.
In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited.
The HRX FIFO contains valid data, which may be read by the DSP using either DSP
instructions or DMA transfers if the HRNE status bit is set.
If HCKFR is cleared, when the HRX FIFO is full and IOSR is filled, an overrun error occurs
and the HROE status bit is set. In this case, the last received byte will not be acknowledged
(ACK = 1 is sent) and the word in the IOSR will not be transferred to the HRX FIFO. This
may inform the external I2C master device of the occurrence of an overrun error on the slave
side. Consequently the I2C master device may terminate this session by generating a stop
event.
If HCKFR is set, when the HRX FIFO is full the SHI will hold the clock line to GND not
letting the master device write to IOSR. This effectively eliminates the possibility of reaching
the overrun condition.
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The HREQ output pin, if enabled for receive (HRQE1–HRQE0 = 01), is asserted when the
IOSR is ready to receive and the HRX FIFO is not full; this operation guarantees that the next
received data word will be stored in the FIFO. HREQ is deasserted at the first clock pulse of
the next received word. The HREQ line may be used to interrupt the external I2C master
device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C
master device and the other as an I2C slave device, enables full hardware handshaking.
7.7.3.2
Transmit Data In I2C Slave Mode
A transmit session is initiated when the personal slave device address has been correctly
identified and the R/W bit of the received slave device address byte has been set. Following a
transmit initiation, the IOSR is loaded from HTX (assuming the latter was not empty) and its
contents are shifted out, MSB first, on the SDA line. Following each transmitted byte, the SHI
controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the
transmitted byte was acknowledged (ACK = 0), the SHI controller continues and transmits the
next byte. However, if it was not acknowledged (ACK = 1), the transmit session is stopped
and the SDA line is released. Consequently, the external master device may generate a stop
event in order to terminate the session.
HTX contents are transferred to IOSR when the complete word (according to HM0–HM1) has
been shifted out. It is, therefore, the responsibility of the programmer to select the correct
number of bytes in an I2C frame so that they fit in a complete number of words. For this
purpose, the slave device address byte does not count as part of the data, and therefore, it is
treated separately.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers
are inhibited. When the HTX transfers its valid data word to IOSR, the HTDE status bit is set
and the DSP may write a new data word to HTX using either DSP instructions or DMA
transfers.
When HCKFR is cleared, if both IOSR and HTX are empty when the master device attempts
a transmit session, an underrun condition occurs, setting the HTUE status bit; if this occurs,
the previous word will be retransmitted.
When HCKFR is set, if both IOSR and HTX are empty when the master device attempts a
transmit session, the SHI will hold the clock line to GND eliminating the possibility of
reaching the underrun error condition.
The HREQ output pin, if enabled for transmit (HRQE1–HRQE0 = 10), is asserted when HTX
is transferred to IOSR for transmission. When asserted, HREQ indicates that the slave device
is ready to transmit the next data word. HREQ is deasserted at the first clock pulse of the next
transmitted data word. The HREQ line may be used to interrupt the external I2C master
device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C
master device and the other as an I2C slave device, enables full hardware handshaking.
7-26
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Serial Host Interface
SHI Programming Considerations
7.7.4
I2C MASTER MODE
The I2C Master mode is entered by enabling the SHI (HEN = 1), selecting the I2C mode
(HI2C = 1) and selecting the Master mode of operation (HMST = 1). Before enabling the SHI
as an I2C master, the programmer should program the appropriate clock rate in HCKR.
Freescale Semiconductor, Inc...
When configured in the I2C Master mode, the SHI external pins operate as follows:
•
SCK/SCL is the SCL serial clock output.
•
MISO/SDA is the SDA open drain serial data line.
•
MOSI/HA0 is the HA0 slave device address input.
•
SS/HA2 is the HA2 slave device address input.
•
HREQ is the Host Request input.
In the I2C Master mode, a data transfer session is always initiated by the DSP by writing to the
HTX register when HIDLE is set. This condition ensures that the data byte written to HTX
will be interpreted as being a slave address byte. This data byte must specify the slave device
address to be selected and the requested data transfer direction.
Note:
The slave address byte should be located in the high portion of the data word,
whereas the middle and low portions are ignored. Only one byte (the slave address
byte) will be shifted out, independent of the word length defined by the
HM0–HM1 bits.
In order for the DSP to initiate a data transfer the following actions are to be performed:
•
The DSP tests the HIDLE status bit.
•
If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit
to the most significant byte of HTX.
•
The SHI generates a start event.
•
The SHI transmits one byte only, internally samples the R/W direction bit (last bit),
and accordingly initiates a receive or transmit session.
•
The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value.
If acknowledged (ACK = 0), it starts its receive or transmit session according to the
sampled R/W value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is
set, which will cause an SHI Bus Error interrupt request if HBIE is set, and a stop
event will be generated.
The HREQ input pin is ignored by the I2C master device if HRQE1 and HRQE0 are cleared,
and considered if either of them is set. When asserted, HREQ indicates that the external slave
MOTOROLA
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Serial Host Interface
SHI Programming Considerations
Freescale Semiconductor, Inc...
device is ready for the next data transfer. As a result, the I2C master device sends clock pulses
for the full data word transfer. HREQ is deasserted by the external slave device at the first
clock pulse of the next data transfer. When deasserted, HREQ will prevent the clock
generation of the next data word transfer until it is asserted again. Connecting the HREQ line
between two SHI-equipped DSPs, one operating as an I2C master device and the other as an
I2C slave device, enables full hardware handshaking.
7.7.4.1
Receive Data in I2C Master Mode
A receive session is initiated if the R/W direction bit of the transmitted slave device address
byte is set. Following a receive initiation, data in SDA line is shifted into IOSR MSB first.
Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via
the SDA line if the HIDLE control bit is cleared. Data is acknowledged bytewise, as required
by the I2C bus protocol, and is transferred to the HRX FIFO when the complete word
(according to HM0–HM1) is filled into IOSR. It is the responsibility of the programmer to
select the correct number of bytes in an I2C frame so that they fit in a complete number of
words. For this purpose, the slave device address byte does not count as part of the data, and
therefore, it is treated separately.
If the I2C slave transmitter is acknowledged, it should transmit the next data byte. In order to
terminate the receive session, the programmer should set the HIDLE bit at the last required
data word. As a result, the last byte of the next received data word is not acknowledged, the
slave transmitter releases the SDA line, and the SHI generates the stop event and terminates
the session.
In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are
inhibited. If the HRNE status bit is set, the HRX FIFO contains valid data, which may be read
by the DSP using either DSP instructions or DMA transfers. When the HRX FIFO is full, the
SHI suspends the serial clock just before acknowledge. In this case, the clock will be
reactivated when the FIFO is read (the SHI gives an ACK = 0 and proceeds receiving).
7.7.4.2
Transmit Data In I2C Master Mode
A transmit session is initiated if the R/W direction bit of the transmitted slave device address
byte is cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX
is not empty) and its contents are shifted out, MSB-first, on the SDA line. Following each
transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse, and
inspects the ACK status. If the transmitted byte was acknowledged (ACK = 0), the SHI
controller continues transmitting the next byte. However, if it was not acknowledged (ACK =
1), the HBER status bit is set to inform the DSP side that a bus error (or overrun, or any other
exception in the slave device) has occurred. Consequently, the I2C master device generates a
stop event and terminates the session.
HTX contents are transferred to the IOSR when the complete word (according to HM0–HM1)
has been shifted out. It is, therefore, the responsibility of the programmer to select the right
7-28
DSP56364
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Serial Host Interface
SHI Programming Considerations
number of bytes in an I2C frame so that they fit in a complete number of words. Remember
that for this purpose, the slave device address byte does not count as part of the data.
Freescale Semiconductor, Inc...
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers
are inhibited. When the HTX transfers its valid data word to the IOSR, the HTDE status bit is
set and the DSP may write a new data word to HTX using either DSP instructions or DMA
transfers. If both IOSR and HTX are empty, the SHI will suspend the serial clock until new
data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set
(the SHI reactivates the clock to generate the Stop event and terminate the transmit session).
7.7.5
SHI OPERATION DURING DSP STOP
The SHI operation cannot continue when the DSP is in the Stop state, since no DSP clocks are
active. While the DSP is in the stop state, the following will occur:
•
If the SHI was operating in the I2C mode, the SHI pins will be disabled (high
impedance).
•
If the SHI was operating in the SPI mode, the SHI pins will not be affected.
•
The HCSR status bits and the transmit/receive paths are reset to the same state
produced by hardware reset or software reset.
•
The HCSR and HCKR control bits are not affected.
Note:
Motorola recommends that the SHI be disabled before entering the Stop state.
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Serial Host Interface
Freescale Semiconductor, Inc...
SHI Programming Considerations
7-30
DSP56364
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APPENDIX
A
BOOTSTRAP ROM
Freescale Semiconductor, Inc...
A.1
DSP56364 BOOTSTRAP PROGRAM
; BOOTSTRAP CODE FOR DSP56364 - (C) Copyright 1998 Motorola Inc.
; Revised August 11, 1998.
;
;
; This is the Bootstrap program contained in the DSP56364 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM or from the SHI serial interface.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=0101, then it loads a program RAM segment from consecutive
; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
; The memory is selected by the Address Attribute AA1 and is accessed with
; 31 wait states.
; The EPROM bootstrap code expects to read 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are read least significant byte first followed by the
; mid and then by the most significant byte.
; The program words will be condensed into 24-bit words and stored in
; contiguous PRAM memory locations starting at the specified starting
address.
; After reading the program words, program execution starts from the same
; address where loading started.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=0100, then the bootstrap code jumps to the internal
; Program ROM, without loading the Program RAM.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation mode MD:MC:MB:MA=0111 is used for burn-in testing.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=11xx, then the Program RAM is loaded from the SHI.
;
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A-1
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Bootstrap ROM
Freescale Semiconductor, Inc...
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
page
132,55,0,0,0
opt
cex,mex,mu
;;
;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;
;;
BOOT
equ
$D00000
; this is the location in P memory
; on the external memory bus
; where the external byte-wide
; EPROM would be located
AARV
equ
$D00409
; AAR1 selects the EPROM as CE~
; mapped as P from $D00000 to
; $DFFFFF, active low
PROMADDR equ
$FF1000
; Starting PROM address
MA
MB
MC
MD
EQU
EQU
EQU
EQU
0
1
2
3
;;
;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;
;;
M_AAR1
EQU
$FFFFF8
; Address Attribute Register 1
M_HRX
M_HCSR
hrne
hi2c
hckfr
EQU
EQU
equ
equ
equ
$FFFF94
$FFFF91
17
1
4
;
;
;
;
;
ORG PL:$ff0000,PL:$ff0000
SHI
SHI
SHI
SHI
SHI
Receive FIFO
Control/Status Register
FIFO Not Empty flag
I2C Enable Control Bit
I2C Clock Freeze Control Bit
; bootstrap code starts at $ff0000
START
clr a #$0,r5
jclr #MC,omr,OMRX0XX
jset #MD,omr,SHILD
jset #MB,omr,BURN_RES
jset #MA,omr,EPROMLD
;
;
;
;
;
clear a and init R5 with 0
If MD:MC:MB:MA=x0xx, go to OMRX0XX
If MD:MC:MB:MA=11xx, go load from SHI
If MD:MC:MB:MA=011X, go to BURN/RESERV
If MD:MC:MB:MA=0101, go load from EPROM
;========================================================================
; This is the routine that jumps to the internal Program ROM.
; MD:MC:MB:MA=0100
move #PROMADDR,r1
A-2
; store starting PROM address in r1
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Bootstrap ROM
bra
<FINISH
;========================================================================
; This is the routine that loads from SHI.
; MD:MC:MB:MA=1100 - reserved
; MD:MC:MB:MA=1101 - Bootstrap from SHI (SPI slave)
; MD:MC:MB:MA=1110 - Bootstrap from SHI (I2C slave, HCKFR=1)
; MD:MC:MB:MA=1111 - Bootstrap from SHI (I2C slave, HCKFR=0)
Freescale Semiconductor, Inc...
SHILD
; This is the routine which loads a program through the SHI port.
; The SHI operates in the slave
; mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for
; receive operation. The word size for transfer is 24 bits. The SHI
; operates in the SPI or in the I2C mode, according to the bootstrap mode.
;
; The program is downloaded according to the following rules:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is the program length defined by the first 3 bytes)
; The program words will be stored in contiguous PRAM memory locations
starting
; at the specified starting address.
; After storing the program words, program execution starts from the same
; address where loading started.
move
#$A9,r1
; prepare SHI control value in r1
; HEN=1, HI2C=0, HM1-HM0=10, HCKFR=0, HFIFO=1, HMST=0,
; HRQE1-HRQE0=01, HIDLE=0, HBIE=0, HTIE=0, HRIE1-HRIE0=00
jclr
#MA,omr,SHI_CF
; If MD:MC:MB:MA=11x0, go to SHI clock
freeze
jclr
shi_loop
MOTOROLA
#MB,omr,shi_loop
; If MD:MC:MB:MA=1101, select SPI mode
bset
#hi2c,r1
; otherwise select I2C mode.
movep
r1,x:M_HCSR
; enable SHI
jclr
movep
#hrne,x:M_HCSR,*
x:M_HRX,a0
; wait for no. of words
jclr
movep
move
#hrne,x:M_HCSR,*
x:M_HRX,r0
r0,r1
; wait for starting address
do
jclr
a0,_LOOP2
#hrne,x:M_HCSR,*
; wait for HRX not empty
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A-3
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Bootstrap ROM
movep
nop
x:M_HRX,p:(r0)+
; store in Program RAM
; req. because of restriction
_LOOP2
bra
<FINISH
SHI_CF
Freescale Semiconductor, Inc...
jset
bra
bset
#hi2c,r1
; select I2C mode.
bset
#hckfr,r1
; enable clock freeze in I2C mode.
#MB,omr,shi_loop
; If MD:MC:MB:MA=1110, go to I2C load
<RESERVED
; If MD:MC:MB:MA=1100, go to reserved
;========================================================================
; This is the routine that loads from external EPROM.
; MD:MC:MB:MA=0101
EPROMLD
move #BOOT,r2
movep #AARV,X:M_AAR1
do #6,_LOOP9
movem p:(r2)+,a2
asr #8,a,a
_LOOP9
move a1,r0
move a1,r1
do a0,_LOOP10
do #3,_LOOP11
movem p:(r2)+,a2
asr #8,a,a
_LOOP11
movem a1,p:(r0)+
nop
_LOOP10
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
r2 = address of external EPROM
aar1 configured for SRAM types of access
read number of words and starting address
Get the 8 LSB from ext. P mem.
Shift 8 bit data into A1
starting address for load
save it in r1
a0 holds the number of words
read program words
Each instruction has 3 bytes
Get the 8 LSB from ext. P mem.
Shift 8 bit data into A1
Go get another byte.
Store 24-bit result in P mem.
pipeline delay
and go get another 24-bit word.
Boot from EPROM done
;========================================================================
; This is the exit handler that returns execution to normal
; expanded mode and jumps to the RESET vector.
FINISH
andi #$0,ccr
jmp (r1)
; Clear CCR as if RESET to 0.
; Then go to starting Prog addr.
;========================================================================
; MD:MC:MB:MA=0111 is Burn-in code
; MD:MC:MB:MA=0110 is reserved
A-4
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Bootstrap ROM
BURN_RES
jset #MA,omr,BURN
; If MD:MC:MB:MA=0111, go to BURN
;========================================================================
; The following modes are reserved:
; MD:MC:MB:MA=0110 is reserved
; MD:MC:MB:MA=1100 is reserved
; MD:MC:MB:MA=X0XX are reserved
Freescale Semiconductor, Inc...
OMRX0XX
RESERVED
bra
<*
;========================================================================
; Code for burn-in
;========================================================================
M_OGDB
M_PCRC
M_PDRC
M_PRRC
SCKT
EQU
EQU
EQU
EQU
EQU
$FFFFFC
$FFFFBF
$FFFFBD
$FFFFBE
$3
;;
;;
;;
;;
;;
0
OnCE
Port
Port
Port
SCKT
GDB Register
C GPIO Control Register
C GPIO Data Register
C Direction Register
is GPIO bit #3 in ESAI (Port C)
EQUALDATA
equ
;; 1 if xram and yram are of equal
;; size and addresses, 0 otherwise.
if
start_dram
length_dram
else
start_xram
length_xram
start_yram
length_yram
endif
(EQUALDATA)
equ
0
equ
$1600
equ
equ
equ
equ
0
$0400
0
$0600
;; 1k XRAM
start_pram
length_pram
equ
equ
0
$0200
;; 0.5k PRAM
;;
;; same addresses
;; 1.5k YRAM
BURN
;; get PATTERN pointer
clr b
#PATTERNS,r6
;; b is the error accumulator
move
#<(NUM_PATTERNS-1),m6
;; program runs forever in
;; cyclic form
;; configure SCKT as gpio output.
movep
b,x:M_PDRC
;; clear GPIO data register
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Bootstrap ROM
bclr
output GPIO pin
bset
lua
#SCKT,x:M_PCRC
#SCKT,x:M_PRRC
;; Define SCKT as
;; SCKT toggles means test pass
;; r5 = test fail flag = $000000
;; r7 = test pass flag = $FFFFFF
(r5)-,r7
burnin_loop
do #9,burn1
Freescale Semiconductor, Inc...
;;---------------------------;; test RAM
;; each pass checks 1 pattern
;;---------------------------move
p:(r6)+,x1
move
p:(r6)+,x0
move
p:(r6)+,y0
;; pattern for x memory
;; pattern for y memory
;; pattern for p memory
;; write pattern to all memory locations
if
(EQUALDATA)
;; write x and y memory
clr a
#start_dram,r0
move
#>length_dram,n0
rep
n0
mac x0,x1,a x,l:(r0)+
else
;; x/y ram symmetrical
;; start of x/y ram
;; length of x/y ram
;; exercise mac, write x/y ram
;; x/y ram not symmetrical
;; write x memory
clr a
#start_xram,r0
move
#>length_xram,n0
rep
n0
mac x0,y0,a x1,x:(r0)+
;; write y memory
clr a
#start_yram,r1
move
#>length_yram,n1
rep
n1
mac x1,y0,a x0,y:(r1)+
;; start of xram
;; length of xram
;; exercise mac, write xram
;; start of yram
;; length of yram
;; exercise mac, write yram
endif
;; write p memory
clr a
#start_pram,r2
move
#>length_pram,n2
rep
n2
move
y0,p:(r2)+
;; start of pram
;; length of pram
;; write pram
;; check memory contents
if
A-6
(EQUALDATA)
;; x/y ram symmetrical
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Bootstrap ROM
;; check dram
clr a
#start_dram,r0
do
n0,_loopd
move
x:(r0),a1
eor
x1,a
add
a,b
move
y:(r0)+,a1
eor
x0,a
add
a,b
;; restore pointer, clear a
;; a0=a2=0
;; accumulate error in b
;; a0=a2=0
;; accumulate error in b
Freescale Semiconductor, Inc...
_loopd
else
;; x/y ram not symmetrical
;; check xram
clr a
#start_xram,r0
do
n0,_loopx
move
x:(r0)+,a1
eor
x1,a
add
a,b
;; restore pointer, clear a
;; a0=a2=0
;; accumulate error in b
_loopx
;; check yram
clr a
#start_yram,r1
do
n1,_loopy
move
y:(r1)+,a1
eor
x0,a
add
a,b
;; restore pointer, clear a
;; a0=a2=0
;; accumulate error in b
_loopy
endif
;; check pram
clr a
#start_pram,r2
do
n2,_loopp
move
p:(r2)+,a1
eor
y0,a
add
a,b
;; restore pointer, clear a
;; a0=a2=0
;; accumulate error in b
_loopp
;;--------------------------------------------------;; toggle pin if no errors, stop execution otherwise.
;;--------------------------------------------------;; if error
tne
r5,r7
;; r7=$FFFFFF as long as test pass
;; condition codes preserved
;; this instr can be removed
in case of shortage
movep
r7,x:M_OGDB
;; write pass/fail flag to OnCE
;; condition codes preserved
;; this instr can be removed
in case of shortage
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A-7
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Bootstrap ROM
beq
bclr
enddo
label1
#SCKT,x:M_PDRC
in case of shortage
bra
label1
bchg
<burn1
#SCKT,x:M_PDRC
burn1
;; clear SCKT if error,
;; terminate the loop normally
;; this instr can be removed
;; and stop execution
;; if no error
;; toggle pin and keep on looping
;; test completion
;; enter debug mode if OnCE
debug
Freescale Semiconductor, Inc...
port enabled
;; this instr can be removed
in case of shortage
wait
port disabled)
;; enter wait otherwise (OnCE
BURN_END
PATTERNS
addressing
ORG PL:,PL:
dsm
4
ORG
;; align for correct modulo
PL:BURN_END,PL:BURN_END
dup PATTERNS-*
Boot ROM location
dc *
endm
ORG
; write address in unused
PL:PATTERNS,PL:PATTERNS ;; Each value is written to
all memories
NUM_PATTERNS
dc
dc
dc
dc
$555555
$AAAAAA
$333333
$F0F0F0
equ
*-PATTERNS
;========================================================================
; This code fills the unused bootstrap rom locations with their address
dup $FF00C0-*
dc *
endm
A-8
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Bootstrap ROM
;========================================================================
; Reserved Area in the Program ROM: upper 128 words.
; Address range: $FF2F80 - $FF2FFF
;========================================================================
ORG PL:$FF2F80,PL:$FF2F80
Freescale Semiconductor, Inc...
; This code fills the unused rom locations with their address
dup $FF3000-*
dc *
endm
end
MOTOROLA
DSP56364
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A-9
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Freescale Semiconductor, Inc...
Bootstrap ROM
A-10
DSP56364
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APPENDIX
B
BDSL FILE
Freescale Semiconductor, Inc...
B.1
BSDL FILE
-- M O T O R O L A
S S D T
J T A G
S O F T W A R E
-- BSDL File Generated: Sun Aug 16 10:48:15 1998
--- Revision History:
-entity DSP56364 is
generic (PHYSICAL_PIN_MAP : string := "TQFP100");
port (
TCK:inbit;
TMS:inbit;
TDI:inbit;
TDO:outbit;
MODD:inbit;
MODB:inbit;
MODA:inbit;
FST:inoutbit;
FSR:inoutbit;
SCKT:inoutbit;
SCKR:inoutbit;
SVCC:linkagebit_vector(0
SGND:linkagebit_vector(0
HCKT:inoutbit;
QVCCL:linkagebit_vector(0
QGND:linkagebit_vector(0
HCKR:inoutbit;
SDO0:inoutbit;
QVCCH:linkagebit_vector(0
SDO1:inoutbit;
SDOI23:inoutbit;
SD0I32:inoutbit;
SDOI41:inoutbit;
SDOI50:inoutbit;
SS_N:inbit;
MOSI:inoutbit;
SDA:inoutbit;
SCK:inoutbit;
HREQ_N:inoutbit;
NMI_N:inbit;
MOTOROLA
to 2);
to 2);
to 3);
to 3);
to 3);
DSP56364
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B-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BDSL File
RESET_N:inbit;
PVCC:linkagebit;
PCAP:linkagebit;
PGND:linkagebit;
EXTAL:inbit;
TA_N:inbit;
CAS_N:outbit;
WR_N:outbit;
RD_N:outbit;
CVCC:linkagebit;
CGND:linkagebit;
AA1:outbit;
AA0:outbit;
A:outbit_vector(0 to 17);
AGND:linkagebit_vector(0 to 3);
AVCC:linkagebit_vector(0 to 3);
DVCC:linkagebit;
DGND:linkagebit;
GPIO:inoutbit_vector(0 to 3);
R:linkagebit_vector(1 to 4);
D:inoutbit_vector(0 to 7));
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56364 : entity is "STD_1149_1_1993";
attribute PIN_MAP of DSP56364 : entity is PHYSICAL_PIN_MAP;
constant TQFP100 : PIN_MAP_STRING :=
"MODD:
1, " &
"MODB:
2, " &
"MODA:
3, " &
"FST:
4, " &
"FSR:
5, " &
"SCKT:
6, " &
"SCKR:
7, " &
"SVCC:
(8, 21, 92), " &
"SGND:
(9, 22, 93), " &
"HCKT:
10, " &
"QVCCL:
(11, 37, 66, 87), " &
"QGND:
(12, 36, 65, 88), " &
"HCKR:
13, " &
"SDO0:
14, " &
"QVCCH:
(15, 35, 61, 89), " &
"SDO1:
16, " &
"SDOI23:
17, " &
"SD0I32:
18, " &
"SDOI41:
19, " &
"SDOI50:
20, " &
"SS_N:
23, " &
"MOSI:
24, " &
B-2
DSP56364
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BDSL File
"SDA:
25, " &
"SCK:
26, " &
"HREQ_N:
27, " &
"NMI_N:
28, " &
"RESET_N:
29, " &
"R:
(30, 85, 86, 90), " &
"PVCC:
31, " &
"PCAP:
32, " &
"PGND:
33, " &
"EXTAL:
34, " &
"TA_N:
38, " &
"CAS_N:
39, " &
"WR_N:
40, " &
"RD_N:
41, " &
"CVCC:
42, " &
"CGND:
43, " &
"AA1:
44, " &
"AA0:
45, " &
"A:
(46, 47, 50, 51, 52, 53, 54, 57, 58, 59, 60, 62, 67, 68,
69, 70, 73, 74), " &
"AVCC:
(48, 55, 63, 71), " &
"AGND:
(49, 56, 64, 72), " &
"D:
(75, 76, 77, 78, 81, 82, 83, 84), " &
"DVCC:
79, " &
"DGND:
80, " &
"GPIO:
(91, 94, 95, 96), " &
"TDO:
97, " &
"TDI:
98, " &
"TCK:
99, " &
"TMS:
100 ";
attribute
attribute
attribute
attribute
TAP_SCAN_IN
TAP_SCAN_OUT
TAP_SCAN_MODE
TAP_SCAN_CLOCK
of
of
of
of
TDI
TDO
TMS
TCK
:
:
:
:
signal
signal
signal
signal
is
is
is
is
true;
true;
true;
(20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56364 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56364 : entity is
"EXTEST
(0000)," &
"SAMPLE
(0001)," &
"IDCODE
(0010)," &
"CLAMP
(0011)," &
"HIGHZ
(0100)," &
"ONCE_ENABLE (0110)," &
"DEBUG_REQUEST(0111)," &
"BYPASS
(1111)";
attribute INSTRUCTION_CAPTURE of DSP56364 : entity is "0001";
attribute IDCODE_REGISTER
of DSP56364 : entity is
"0000"
& -- version
MOTOROLA
DSP56364
For More Information On This Product,
Go to: www.freescale.com
B-3
Freescale Semiconductor, Inc.
BDSL File
"000110"
"0001100100"
"00000001110"
"1";
& -- manufacturer’s use
& -- sequence number
& -- manufacturer identity
-- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56364 : entity is
"ONCE[8]
(ONCE_ENABLE,DEBUG_REQUEST)" ;
Freescale Semiconductor, Inc...
attribute BOUNDARY_LENGTH of DSP56364 : entity is 86;
attribute
-- num
"0
"1
"2
"3
"4
"5
"6
"7
"8
"9
"10
"11
"12
"13
"14
"15
"16
"17
"18
"19
-- num
"20
"21
"22
"23
"24
"25
"26
"27
"28
"29
"30
"31
"32
"33
"34
"35
"36
B-4
BOUNDARY_REGISTER of DSP56364 : entity is
cell
port
func
safe [ccell dis rslt]
(BC_1, *,
control,
1)," &
(BC_6, GPIO(3), bidir,
X,
0,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_6, GPIO(2), bidir,
X,
2,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_6, GPIO(1), bidir,
X,
4,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_6, GPIO(0), bidir,
X,
6,
1,
Z),"
(BC_6, D(7),
bidir,
X,
12,
1,
Z),"
(BC_6, D(6),
bidir,
X,
12,
1,
Z),"
(BC_6, D(5),
bidir,
X,
12,
1,
Z),"
(BC_6, D(4),
bidir,
X,
12,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_6, D(3),
bidir,
X,
12,
1,
Z),"
(BC_6, D(2),
bidir,
X,
12,
1,
Z),"
(BC_6, D(1),
bidir,
X,
12,
1,
Z),"
(BC_6, D(0),
bidir,
X,
12,
1,
Z),"
(BC_1, A(17),
output3,
X,
23,
1,
Z),"
(BC_1, A(16),
output3,
X,
23,
1,
Z),"
(BC_1, A(15),
output3,
X,
23,
1,
Z),"
cell
port
func
safe [ccell dis rslt]
(BC_1, A(14),
output3,
X,
23,
1,
Z),"
(BC_1, A(13),
output3,
X,
23,
1,
Z),"
(BC_1, A(12),
output3,
X,
23,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_1, A(11),
output3,
X,
23,
1,
Z),"
(BC_1, A(10),
output3,
X,
23,
1,
Z),"
(BC_1, A(9),
output3,
X,
23,
1,
Z),"
(BC_1, A(8),
output3,
X,
29,
1,
Z),"
(BC_1, A(7),
output3,
X,
29,
1,
Z),"
(BC_1, *,
control,
1)," &
(BC_1, A(6),
output3,
X,
29,
1,
Z),"
(BC_1, A(5),
output3,
X,
29,
1,
Z),"
(BC_1, A(4),
output3,
X,
29,
1,
Z),"
(BC_1, A(3),
output3,
X,
29,
1,
Z),"
(BC_1, A(2),
output3,
X,
29,
1,
Z),"
(BC_1, A(1),
output3,
X,
29,
1,
Z),"
(BC_1, A(0),
output3,
X,
29,
1,
Z),"
DSP56364
For More Information On This Product,
Go to: www.freescale.com
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BDSL File
"37
"38
"39
-- num
"40
"41
"42
"43
"44
"45
"46
"47
"48
"49
"50
"51
"52
"53
"54
"55
"56
"57
"58
"59
-- num
"60
"61
"62
"63
"64
"65
"66
"67
"68
"69
"70
"71
"72
"73
"74
"75
"76
"77
"78
"79
-- num
"80
"81
"82
"83
"84
(BC_1,
(BC_1,
(BC_1,
cell
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_1,
cell
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_6,
(BC_1,
cell
(BC_6,
(BC_1,
(BC_6,
(BC_1,
(BC_1,
MOTOROLA
*,
control,
AA0,
output3,
*,
control,
port
func
AA1,
output3,
*,
control,
RD_N,
output3,
WR_N,
output3,
*,
control,
CAS_N,
output3,
TA_N,
input,
EXTAL,
input,
RESET_N, input,
NMI_N,
input,
*,
control,
HREQ_N,
bidir,
*,
control,
SCK,
bidir,
*,
control,
SDA,
bidir,
*,
control,
MOSI,
bidir,
SS_N,
input,
*,
control,
port
func
SDOI50,
bidir,
*,
control,
SDOI41,
bidir,
*,
control,
SD0I32,
bidir,
*,
control,
SDOI23,
bidir,
*,
control,
SDO1,
bidir,
*,
control,
SDO0,
bidir,
*,
control,
HCKR,
bidir,
*,
control,
HCKT,
bidir,
*,
control,
SCKR,
bidir,
*,
control,
SCKT,
bidir,
*,
control,
port
func
FSR,
bidir,
*,
control,
FST,
bidir,
MODA,
input,
MODB,
input,
1)," &
X,
37,
1,
Z),"
1)," &
safe [ccell dis rslt]
X,
39,
1,
Z),"
1)," &
X,
41,
1,
Z),"
X,
41,
1,
Z),"
1)," &
X,
44,
1,
Z),"
X)," &
X)," &
X)," &
X)," &
1)," &
X,
50,
1,
Z),"
1)," &
X,
52,
1,
Z),"
1)," &
X,
54,
1,
Z),"
1)," &
X,
56,
1,
Z),"
X)," &
1)," &
safe [ccell dis rslt]
X,
59,
1,
Z),"
1)," &
X,
61,
1,
Z),"
1)," &
X,
63,
1,
Z),"
1)," &
X,
65,
1,
Z),"
1)," &
X,
67,
1,
Z),"
1)," &
X,
69,
1,
Z),"
1)," &
X,
71,
1,
Z),"
1)," &
X,
73,
1,
Z),"
1)," &
X,
75,
1,
Z),"
1)," &
X,
77,
1,
Z),"
1)," &
safe [ccell dis rslt]
X,
79,
1,
Z),"
1)," &
X,
81,
1,
Z),"
X)," &
X)," &
DSP56364
For More Information On This Product,
Go to: www.freescale.com
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
B-5
Freescale Semiconductor, Inc.
BDSL File
"85
(BC_1, MODD,
input,
X)";
Freescale Semiconductor, Inc...
end DSP56364;
B-6
DSP56364
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
APPENDIX
C
PROGRAMMER’S REFERENCE
Freescale Semiconductor, Inc...
C.1
INTRODUCTION
This section has been compiled as a reference for programmers. It contains a table
showing the addresses of all the DSPs memory-mapped peripherals, an interrupt
address table, an interrupt exception priority table, a quick reference to the host
interface, and programming sheets for the major programmable registers on the
DSP.
C.1.1
Peripheral Addresses
Table C-1 lists the memory addresses of all on-chip peripherals.
C.1.2
Interrupt Addresses
Table C-2 lists the interrupt starting addresses and sources.
C.1.3
Interrupt Priorities
Table C-3 lists the priorities of specific interrupts within interrupt priority levels.
Table C-1 Internal I/O Memory Map
PERIPHERAL
ADDRESS
REGISTER NAME
$FFFFFF
INTERRUPT PRIORITY REGISTER CORE (IPR-C)
$FFFFFE
INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)
PLL
$FFFFFD
PLL CONTROL REGISTER (PCTL)
ONCE
$FFFFFC
ONCE GDB REGISTER (OGDB)
IPR
MOTOROLA
DSP56364
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C-1
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-1 Internal I/O Memory Map (Continued)
PERIPHERAL
Freescale Semiconductor, Inc...
BIU
DMA
ADDRESS
REGISTER NAME
$FFFFFB
BUS CONTROL REGISTER (BCR)
$FFFFFA
DRAM CONTROL REGISTER (DCR)
$FFFFF9
ADDRESS ATTRIBUTE REGISTER 0 (AAR0)
$FFFFF8
ADDRESS ATTRIBUTE REGISTER 1 (AAR1)
$FFFFF7
ADDRESS ATTRIBUTE REGISTER 2 (AAR2)
$FFFFF6
ADDRESS ATTRIBUTE REGISTER 3 (AAR3)
$FFFFF5
ID REGISTER (IDR)
$FFFFF4
DMA STATUS REGISTER (DSTR)
$FFFFF3
DMA OFFSET REGISTER 0 (DOR0)
$FFFFF2
DMA OFFSET REGISTER 1 (DOR1)
$FFFFF1
DMA OFFSET REGISTER 2 (DOR2)
$FFFFF0
DMA OFFSET REGISTER 3 (DOR3)
$FFFFEF
DMA SOURCE ADDRESS REGISTER (DSR0)
$FFFFEE
DMA DESTINATION ADDRESS REGISTER (DDR0)
$FFFFED
DMA COUNTER (DCO0)
$FFFFEC
DMA CONTROL REGISTER (DCR0)
$FFFFEB
DMA SOURCE ADDRESS REGISTER (DSR1)
$FFFFEA
DMA DESTINATION ADDRESS REGISTER (DDR1)
$FFFFE9
DMA COUNTER (DCO1)
$FFFFE8
DMA CONTROL REGISTER (DCR1)
$FFFFE7
DMA SOURCE ADDRESS REGISTER (DSR2)
$FFFFE6
DMA DESTINATION ADDRESS REGISTER (DDR2)
$FFFFE5
DMA COUNTER (DCO2)
$FFFFE4
DMA CONTROL REGISTER (DCR2)
$FFFFE3
DMA SOURCE ADDRESS REGISTER (DSR3)
$FFFFE2
DMA DESTINATION ADDRESS REGISTER (DDR3)
$FFFFE1
DMA COUNTER (DCO3)
$FFFFE0
DMA CONTROL REGISTER (DCR3)
DMA0
DMA1
DMA2
DMA3
C-2
DSP56364
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MOTOROLA
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-1 Internal I/O Memory Map (Continued)
PERIPHERAL
ADDRESS
REGISTER NAME
$FFFFDF
DMA SOURCE ADDRESS REGISTER (DSR4)
$FFFFDE
DMA DESTINATION ADDRESS REGISTER (DDR4)
$FFFFDD
DMA COUNTER (DCO4)
$FFFFDC
DMA CONTROL REGISTER (DCR4)
$FFFFDB
DMA SOURCE ADDRESS REGISTER (DSR5)
$FFFFDA
DMA DESTINATION ADDRESS REGISTER (DDR5)
$FFFFD9
DMA COUNTER (DCO5)
$FFFFD8
DMA CONTROL REGISTER (DCR5)
$FFFFD7
thru
$FFFFD0
RESERVED
$FFFFCF
PORT B CONTROL REGISTER (PCRB)
$FFFFCE
PORT B DIRECTION REGISTER (PRRB)
$FFFFCD
PORT B GPIO DATA REGISTER (PDRB)
$FFFFCC
thru
$FFFFC0
RESERVED
$FFFFBF
PORT C CONTROL REGISTER (PCRC)
$FFFFBE
PORT C DIRECTION REGISTER (PRRC)
$FFFFBD
PORT C GPIO DATA REGISTER (PDRC)
Freescale Semiconductor, Inc...
DMA4
DMA5
Reserved
PORT B
Reserved
PORT C
MOTOROLA
DSP56364
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C-3
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-1 Internal I/O Memory Map (Continued)
Freescale Semiconductor, Inc...
PERIPHERAL
ESAI
C-4
ADDRESS
REGISTER NAME
$FFFFBC
ESAI RECEIVE SLOT MASK REGISTER B (RSMB)
$FFFFBB
ESAI RECEIVE SLOT MASK REGISTER A (RSMA)
$FFFFBA
ESAI TRANSMIT SLOT MASK REGISTER B (TSMB)
$FFFFB9
ESAI TRANSMIT SLOT MASK REGISTER A (TSMA)
$FFFFB8
ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR)
$FFFFB7
ESAI RECEIVE CONTROL REGISTER (RCR)
$FFFFB6
ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR)
$FFFFB5
ESAI TRANSMIT CONTROL REGISTER (TCR)
$FFFFB4
ESAI COMMON CONTROL REGISTER (SAICR)
$FFFFB3
ESAI STATUS REGISTER (SAISR)
$FFFFB2
RESERVED
$FFFFB1
RESERVED
$FFFFB0
RESERVED
$FFFFAF
RESERVED
$FFFFAE
RESERVED
$FFFFAD
RESERVED
$FFFFAC
RESERVED
$FFFFAB
ESAI RECEIVE DATA REGISTER 3 (RX3)
$FFFFAA
ESAI RECEIVE DATA REGISTER 2 (RX2)
$FFFFA9
ESAI RECEIVE DATA REGISTER 1 (RX1)
$FFFFA8
ESAI RECEIVE DATA REGISTER 0 (RX0)
$FFFFA7
RESERVED
$FFFFA6
ESAI TIME SLOT REGISTER (TSR)
$FFFFA5
ESAI TRANSMIT DATA REGISTER 5 (TX5)
$FFFFA4
ESAI TRANSMIT DATA REGISTER 4 (TX4)
$FFFFA3
ESAI TRANSMIT DATA REGISTER 3 (TX3)
$FFFFA2
ESAI TRANSMIT DATA REGISTER 2 (TX2)
$FFFFA1
ESAI TRANSMIT DATA REGISTER 1 (TX1)
$FFFFA0
ESAI TRANSMIT DATA REGISTER 0 (TX0)
DSP56364
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MOTOROLA
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-1 Internal I/O Memory Map (Continued)
PERIPHERAL
Reserved
Freescale Semiconductor, Inc...
SHI
Reserved
ADDRESS
REGISTER NAME
$FFFF9F
thru
$FFFF95
RESERVED
$FFFF94
SHI RECEIVE FIFO (HRX)
$FFFF93
SHI TRANSMIT REGISTER (HTX)
$FFFF92
SHI I2C SLAVE ADDRESS REGISTER (HSAR)
$FFFF91
SHI CONTROL/STATUS REGISTER (HCSR)
$FFFF90
SHI CLOCK CONTROL REGISTER (HCKR)
$FFFF8F
thru
$FFFF80
RESERVED
Table C-2 DSP56364 Interrupt Vectors
INTERRUPT
STARTING
ADDRESS
INTERRUPT
PRIORITY
LEVEL
RANGE
INTERRUPT SOURCE
VBA:$00
3
Hardware RESET
VBA:$02
3
Stack Error
VBA:$04
3
Illegal Instruction
VBA:$06
3
Debug Request Interrupt
VBA:$08
3
Trap
VBA:$0A
3
Non-Maskable Interrupt (NMI)
VBA:$0C
3
Reserved For Future Level-3 Interrupt Source
VBA:$0E
3
Reserved For Future Level-3 Interrupt Source
VBA:$10
0-2
IRQA
VBA:$12
0-2
IRQB
VBA:$14
0-2
Reserved
VBA:$16
0-2
IRQD
VBA:$18
0-2
DMA Channel 0
VBA:$1A
0-2
DMA Channel 1
VBA:$1C
0-2
DMA Channel 2
VBA:$1E
0-2
DMA Channel 3
MOTOROLA
DSP56364
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C-5
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-2 DSP56364 Interrupt Vectors (Continued)
Freescale Semiconductor, Inc...
INTERRUPT
STARTING
ADDRESS
INTERRUPT
PRIORITY
LEVEL
RANGE
INTERRUPT SOURCE
VBA:$20
0-2
DMA Channel 4
VBA:$22
0-2
DMA Channel 5
VBA:$24
0-2
Reserved
VBA:$26
0-2
Reserved
VBA:$28
0-2
Reserved
VBA:$2A
0-2
Reserved
VBA:$2C
0-2
Reserved
VBA:$2E
0-2
Reserved
VBA:$30
0-2
ESAI Receive Data
VBA:$32
0-2
ESAI Receive Even Data
VBA:$34
0-2
ESAI Receive Data With Exception Status
VBA:$36
0-2
ESAI Receive Last Slot
VBA:$38
0-2
ESAI Transmit Data
VBA:$3A
0-2
ESAI Transmit Even Data
VBA:$3C
0-2
ESAI Transmit Data with Exception Status
VBA:$3E
0-2
ESAI Transmit Last Slot
VBA:$40
0-2
SHI Transmit Data
VBA:$42
0-2
SHI Transmit Underrun Error
VBA:$44
0-2
SHI Receive FIFO Not Empty
VBA:$46
0-2
Reserved
VBA:$48
0-2
SHI Receive FIFO Full
VBA:$4A
0-2
SHI Receive Overrun Error
VBA:$4C
0-2
SHI Bus Error
VBA:$4E
0-2
Reserved
:
:
:
VBA:$FE
0-2
Reserved
C-6
DSP56364
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MOTOROLA
Freescale Semiconductor, Inc.
Programmer’s Reference
Table C-3 Interrupt Sources Priorities Within an IP
PRIORITY
INTERRUPT SOURCE
Level 3 (Nonmaskable)
Highest
Hardware RESET
Stack Error
Illegal Instruction
Freescale Semiconductor, Inc...
Debug Request Interrupt
Trap
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
ESAI Receive Data with Exception Status
ESAI Receive Even Data
ESAI Receive Data
ESAI Receive Last Slot
ESAI Transmit Data with Exception Status
ESAI Transmit Last Slot
ESAI Transmit Even Data
ESAI Transmit Data
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
Lowest
MOTOROLA
SHI Receive FIFO Not Empty
DSP56364
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C-7
Freescale Semiconductor, Inc.
Programmer’s Reference
C.2
PROGRAMMING SHEETS
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The following worksheets list the major programmable registers for the DSP56366.
The programming sheets are grouped in the following order:
•
Central processor,
•
Phase Lock Loop, (PLL),
•
Enhanced Serial Audio Interface (ESAI),
•
Serial Host Interface (SHI),
•
GPIO (Ports B-C).
Each sheet provides a space to write in the value of each bit and the hexadecimal
value for each register. Programmers can photocopy these sheets and reuse them
for each application development project. Refer to the DSP56300 Family Manual for
further details on the DSP56300 family instruction set.
C-8
DSP56364
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Date:
Application:
Programmer:
Sheet 1 of 5
Central Processor
Carry
Over
Zero
Negative
Freescale Semiconductor, Inc...
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
I(1:0)
00
01
10
11
Scaling Mode
S(1:0) Scaling Mode
00 No scaling
01 Scale down
10 Scale up
11 Reserved
Interrupt Mask
Exceptions Masked
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Reserved
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteenth-Bit Arithmetic
Reserved
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
Core Priority
CP(1:0) Core Priority
00
0 (lowest)
01
1
10
2
11
3 (highest)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CP1
CP0
RM
SM
CE
†
*0
SA
FV
Extended Mode Register (MR)
LF
DM
SC
*0
S1
S0
I1
8
7
6
5
4
3
2
1
0
I0
S
L
E
U
N
Z
V
C
Mode Register (MR)
Status Register (SR)
Read/Write
Reset = $C00300
Condition Code Register (CCR)
*
0
= Reserved, Program
as 0
Figure C-1 Status Register (SR)
MOTOROLA
DSP56364
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C-9
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Date:
Application:
Programmer:
Sheet 2 of 5
Central Processor
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MOD(D:A)
Chip Operating Modes
Reset Vector
Description
(See Table 4-1 on page Section 4-3.)
External Bus Disable
Stop Delay
Memory Switch Mode
CDP(1:0)
00
01
10
11
Core-DMA Priority
Core-DMA Priority
Core vs DMA Priority
DMA accesses > Core
DMA accesses = Core
DMA accesses < Core
TA Synchronize Select
Address Priority Disable
Address Tracing Enable
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0 *0
SEN WRP EOV EUN XYS
System Stack Control
Status Register (SCS)
ATE APD
*0 *0 *0
TAS
8
7
CDP1 CDP0 MS
Extended Chip Operating
Mode Register (COM)
6
5
SD
*0
4
3
EBD MD
2
*1
1
MB
0
MA
Chip Operating Mode
Register (COM)
* = Reserved, Program as 0
0
* =Reserved, program as 1
1
Read/Write
Reset = $00030X
Figure C-2 Operating Mode Register (OMR)
C-10
DSP56364
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Date:
Application:
Programmer:
Sheet 3 of 5
CENTRAL PROCESSOR
IRQA Mode
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IAL2
0
1
Trigger
Level
Neg. Edge
IAL1
0
0
1
1
IAL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
IRQB Mode
IBL2
0
1
Trigger
Level
Neg. Edge
IBL1
0
0
1
1
IBL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
IRQD Mode
IDL2
0
1
Trigger
Level
Neg. Edge
IDL1
0
0
1
1
IDL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D5L1 D5L0
D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
IDL2 IDL1
IDL0
8
7
6
5
4
3
2
1
0
*0 *0 *0
IBL2
IBL1
IBL0
IAL2
IAL1
IAL0
*0 = Reserved, Program as 0
Figure C-3 Interrupt Priority Register-Core (IPR-C)
MOTOROLA
DSP56364
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C-11
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Date:
Application:
Programmer:
Sheet 4 of 5
CENTRAL PROCESSOR
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ESAI IPL
ESL1 ESL0 Enabled
0
0
No
0
1
Yes
1
0
Yes
1
1
Yes
IPL
—
0
1
2
SHI IPL
SHL1 SHL0 Enabled
0
0
No
0
1
Yes
1
0
Yes
1
1
Yes
Interrupt Priority
Register (IPR–P)
X:$FFFFFE R/W
Reset = $000000
*
IPL
—
0
1
2
= Reserved, Program as 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
$0
$0
3
2
1
0
SHL1 SHL0 ESL1 ESL0
$0
Figure C-4 Interrupt Priority Register- Peripherals (IPR-P)
C-12
DSP56364
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Application:
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Sheet 5 of 5
PLL
PSTP PEN
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0
1
1
x
0
1
PSTP and PEN Relationship
Operation During STOP Recovery Time
for STOP
PLL
Oscillator
Disabled
Disabled
Long
Disabled
Enabled
Short
Enabled
Enabled
Short
Power Consumption
during STOP
Minimal
Lower
Higher
Bits XTLR and XTLD
have no effect on
Clock Output Disable (COD)
DSP56364 operation
0 = 50% Duty Cycle Clock
1 = Pin Held In High State
XTAL Disable Bit (XTLD)
0 = Enable Xtal Oscillator
1 = EXTAL Driven From
An External Source
Predivision Factor
Bits (PD0 – PD3)
PD3 – Predivision
PD0 Factor PDF
$0
1
$1
2
$2
3
•
•
•
•
•
•
$F
16
Crystal Range Bit (XTLR)
0 = External Xtal Freq > 200KHz
1 = External Xtal Freq < 200KHz
Division Factor Bits (DF0 –
DF2)
DF2 – DF0
Division Factor
DF
$0
20
21
$1
22
$2
•
•
•
•
•
•
27
$7
23 22 21 20 19 18 17 16 15 14 13 12 11 10
PD3
PD2
PD1
PD0
Multiplication Factor
Bits MF0 – MF11
MF11 Multiplicatio
– MF0 n Factor MF
$000
1
$001
2
$002
3
•
•
•
•
•
•
$FFE
4095
$FFF
4096
COD
PEN PSTP XTLD XTLR DF2
DF1
DF0 MF11 MF10
9
8
7
6
5
4
3
2
1
0
MF9
MF8
MF7
MF6
MF5
MF4
MF3
MF2
MF1
MF0
PLL Control
Register (PCTL)
X:$FFFFFD Read/Write
Reset = $010005
Figure C-5 Phase Lock Loop Control Register (PCTL)
MOTOROLA
DSP56364
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C-13
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Application:
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Sheet 1 of 3
SHI
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SHI Slave Address
Register (HSAR)
X:$FFFF92
Reset = $Bx0000
HSAR I2C Slave Address
Slave address = Bits HA6-HA3, HA1 and external pins HA2,
HA0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
HA6 HA5 HA4 HA3
8
7
6
5
4
3
2
1
0
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
HA1
0
0
0
0
SHI Slave Address Register (HSAR)
CPOL CPHA Result
0
0
SCK active low, strobe on rising edge
0
1
SCK active low, strobe on falling edge
1
0
SCK active high, strobe on falling edge
1
1
SCK active high, strobe on rising edge
HFM1 HFM0 SHI Noise Reduction Filter Mode
0
0
Bypassed (Filter disabled)
0
1
Reserved
1
0
Narrow spike tolerance
1
1
Wide spike tolerance
HRS
0
1
SHI Clock Control
Register (HCKR)
X:$FFFF90
Reset = $000001
Result
Prescaler operational
Prescaler bypassed
HCKR Divider Modulus
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0
0
HFM1
HFM0
*0
8
HDM6
HDM7
7
6
HDM4
HDM5
5
4
3
HDM2
HDM3
2
HDM0
HDM1
1
0
CPOL
HRS
CPHA
0
*0 = Reserved, write as 0
SHI Clock Control Register (HCKR)
Figure C-6 SHI Slave Address (HSAR) and Clock Control Register (HCKR)
C-14
DSP56364
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Application:
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Sheet 2 of 3
SHI
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SHI Host Transmit Data Register (HTX) X:$FFFF93 Write Only Reset =
Host Transmit Data Register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
4
3
2
1
0
SHI Host Transmit Data Register (HTX)
SHI Host Receive
Data Register (HRX) X:$FFFF94 Read Only Reset = $xxxxxx
Host Receive Data Register
Contents
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
SHI Host Receive Data Register (HRX) (FIFO) 10 words deep
Figure C-7 SHI Host Transmit Data Register (HTX) and Host Receive Data Register
(HRX) (FIFO)
MOTOROLA
DSP56364
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C-15
C-16
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DSP56364
Reserved, write as 0
SHI Control/Status
Register (HCSR)
X:$FFFF91
Reset = $008200
*=
SPI Mode
*0
HBUSY HBER HROE HRFF
Stop
Not Busy
event
SHI
SS
detects detected(Slave)
Start
-OR-HTX/IOSR
not
empty
23(master)
22 21
I2C
SPI Mode
I 2C
No error
No error
No acknowledge SS asserted
0
H
BI
E
Bus Error
Interrupt
H disabled
TI
Description
E
Description
Descri
ption
*0
HRNE
*0
8
7
6
5
4
0
Descri
ption
3 2 1
HI
2
C
Asserted if OSR ready to receive new
word
HCK
Description
FR
HFIF
Descripti
O
on
0
I2C Slave
Clock freeze
0
1 level
disabled
FIFO
H
H
Descript
M
M
ion
1
0
HMS
Result
T
0
0
8 bit data
H
0
Slave
Descrip
E
mode
tion
N
High Impedance
HRTQE PIN OPERATION
HTDE HTUEHRIE1HRIE0 HTIE HBIE HIDLE HRQE1 HRQE0 HMSTHFIF0 HCKFR HM1 HM0 HI2C HEN
9
1
0
0
0
HR
QE
0
HR
QE
1
Application:
1
HBUS
Y
0
0
1
HBER
Host Receive Overrun Error
Read Only Status Bit
Host Receive FIFO Full
Read Only Status Bit
Host Receive FIFO Not
Empty
Host Transfer Data Empty
Read Only Status Bit
HI
D
L
n.a.
HRNE =1
&HROE=0
HROE=1
Condition
20 19 18 17 16 15 14 13 12 11 10
HRIE HRIE
Interrupt
1
0
0
0
disabled
0
1
Receive FIFO not
empty
0
Receiver Overrun
Error
Host Transmit Underrun Error
Read Only Status Bit
SHI
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Programmer:
Sheet 3 of 3
Figure C-8 SHI Host Control/Status Register (HCSR)
MOTOROLA
TH
CK
D
MOTOROLA
0
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DSP56364
TFSD
THCKD
0
CK
P
Description
TCKD
21
0
Description
THCKP
20
TFSP
19
TCKP
18
TFP3
17
15
TFP2 TFP1
16
TFP0
14
TDC4
13
TDC3
12
11
TDC2
Transmitter Clock Polarity set to clockout on
rising edge of transmitter clock, latch in on falling
edge of transmit clock
Frame sync polarity
TC positive
Description
KP
0
TFS
P
Transmitter High Frequency Clock Polarity set to clockout
on rising edge of transmit clock, latch on falling edge.
External clock source
used
TH
22
0
FST is input
TC
Description
KD
Description
TDC1
10
TDC0
9
TFP
[3:0]
TPSR
8
7
6
TPM
[7:0]
TPM7 TPM6
TP
SR
TPM5
TPM4
TPM3
TPM2
TPM1 TPM0
Specifies the prescaler
divide rate is for the
transmitter clock generator
Range from $00-FF (1-256).
5
4
3
2
1
0
Description
Description
Sets divide rate for
transmission high frequency
clock. Range $0-$F (1-16)
TDC
Description
[4:0]
Description
ESAI
Application:
23
TFS
D
Description
TCCR - ESAI Transmit Clock Control Register
X: $FFFFB6 Reset: $000000
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Programmer:
Figure C-9 ESAI Transmit Clock Control Register (TCCR)
C-17
C-18
0
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DSP56364
22
TIE
23
0
21
20
Description
19
TPR
rsvd PADC
17
15
TFSR TFSL
16
13
12
11
10
9
8
0
0
1
0
7
0
6
0
5
TE5
TE4
4
TE3
3
TE2
2
TE1
1
Transmitter disabled
Description
TE0
0
ESAI
Data shifted out MSB first
Description
Data left aligned
Description
Network mode
Normal mode
TE [0:5]
TSHFD
0
Description
Defines slot and data word
length
TMOD
Description
0
TWA
TMOD
1
TSWS [0:4]
Word-length frame sync
Description
TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
14
Word-length frame sync synchronous
to beginning of data word first slot
0
18
Description
Zero Padding disabled
Description
TFSR
PADC
Transmitter Normal Operation
Description
Transmit Exception Interrupt disabled
0
TEDIE TEIE
0
Description
0
TFSL
TCR - ESAI Transmit Clock Control Register
X: $FFFFB5 Reset: $000000
Transmit Even Slot Data Interrupt disabled
TPR
TEIE
0
Description
Transmit Interrupt disabled
TEDIE
TIE
Transmit Last Slot Interrupt disabled
Description
Application:
TLIE
0
TLIE
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Figure C-10 ESAI Transmit Clock Control Register (TCR)
MOTOROLA
0
1
MOTOROLA
FSR is output
FSR is input
HCKR is output
HCKR is input
23
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DSP56364
22
21
Description
1
0
RHCKP
20
RFSP
19
RCKP
18
16
15
14
RFP3 RFP2 RFP1 RFP0
17
12
11
10
9
8
RPSR
Description
6
5
4
3
2
RPM7 RPM6 RPM5 RPM4 RPM3 RPM2
7
0
RPM1 RPM0
1
Specifies prescaler ratio for the
receive clock generator
Range from $00 - $FF (1 - 256).
See 8.3.3.1
Description
Divide by 8 prescaler bypassed
Divide by 8 prescaler operational
RPM [7:0]
0
1
Description
Controls frame rate dividers
Range 00000 - 11111 (1-32) See 8.3.3.2
RPSR
RDC [4:0]
RDC4 RDC3 RDC2 RDC1 RDC0
13
Clockout on rising edge of receive clock, latch in on
falling edge of receive clock
Clockout on falling edge of receive clock, latch in on
rising edge of receive clock
Description
Frame sync polarity negative
Frame sync polarity positive
RCKP
RFSD RCKD
0
1
RFSP
Description
Sets divide rate for receiver high frequency clock
Range $0 - $F (1 -16). See 8.3.3.4
ESAI
Application:
RHCKD
1
0
Description
RFP [3:0]
RCCR - ESAI Receive Clock Control Register
X: $FFFFB8 Reset: $000000
Clockout on rising edge of receive clock, latch in on
falling edge of receive clock
Clockout on falling edge of receive clock, latch in on
rising edge of receive clock
1
RHCKP
Internal clock source
0
Description
Description
Description
External clock source used
RCKD
RFSD
0
1
RHCKD
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Figure C-11 ESAI Receive Clock Control Register (RCCR)
C-19
C-20
0
1
RIE
0
1
RLIE
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DSP56364
22
21
20
1
0
Description
18
17
16
RFSL
15
13
12
11
10
9
8
6
Rsvd
5
Rsvd
4
RE3
3
Receiver enabled
1
7
Receiver disabled
0
0
RE0
1
RE1
2
RE2
Description
Data shifted in LSB first
Data shifted in MSB first
RE [0:3]
0
1
Description
Diata right aligned
Data left aligned
RSHFD
0
1
Description
AC97
1
RWA
Reserved
0
Network mode
1
1
Network Mode
Normal mode
1
0
0
RMOD1 RMOD0
0
ESAI
Defines slot and data word length
See 8.3.4.9 and table 8-8
Description
1-bit clock period frame sync
RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 RMOD1 RMOD0 RWA RSHFD
14
Word-length frame sync synchronous to beginning of
data word first slot
Word-length frame sync 1 clock before beginning of
data word first slot
19
RFSR
Receiver Normal Operation
Receiver Personal Reset
Description
Word length frame sync
RSWS [0:4]
0
1
RFSL
RCR - ESAI Receive Clock Control Register
X: $FFFFB7 Reset: $000000
Application:
RLIE RIE REDIE REIE RPR Rsvd Rsvd RFSR
23
0
1
Description
Receive Exception Interrupt enabled
1
RPR
Receive Exception Interrupt disabled
0
Description
Receive Even Slot Data Interrupt enabled
1
REIE
Receive Even Slot Data Interrupt disabled
Description
0
REDIE
Receive Interrupt enabled
Receive Interrupt disabled
Description
Receive Last Slot Interrupt enabled
Receive Last Slot Interrupt disabled
Description
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Figure C-12 ESAI Receive Clock Control Register (RCR)
MOTOROLA
MOTOROLA
23
22
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DSP56364
20
19
18
17
16
15
14
13
12
11
10
9
Description
Description
6
SYN
7
TEBE
5
4
3
0
OF0
1
OF1
2
OF2
Holds data to send to OFn pin.
See 8.3.5.1 to .3
8
OF(2:0)
Reserved
Description
Synchronous mode
Asynchronous mode
ALC
0
1
Description
Controls FSR pin.
See 8.3.5.6 and table 8-9
SYN
TEBE
ESAI
Application:
21
Reserved
Description
Data left aligned to bit 23
0
1
Data left aligned to bit 15
Description
ALC
SAICR - ESAI Common Control Register
X: $FFFFB4 Reset: $000000
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Figure C-13 ESAI Common Control Register (SAICR)
C-21
C-22
Transmit underrun error
1
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DSP56364
23
Reserved
22
21
20
19
18
16
TEDE
17
TODE
Transmit odd-data register empty
1
TDE
15
TUE
14
13
TFS
12
11
9
RODF REDF
10
RDF
0
1
7
ROE
6
RFS
1
0
RFS
5
4
2
1
0
IF [0:2]
Description
3
0
IF0
1
IF1
2
IF2
Holds data sent from SCKR pin.
See 8.3.6.1
Holds data sent from FSR pin.
See 8.3.6.2
Holds data sent from HCKR pin.
See 8.3.6.3
Reserved
Description
Receive frame sync did not occur during
word reception
Receive frame sync did occur during
word reception
Description
Description
0 No receiver overrun error
1 Receiver overrun error
ROE
Receive data register full
Receive data register empty
Description
Receive even-data register full
RDF
Receive even-data register empty
1
Description
0
8
REDF
ESAI
Application:
Description
Transmit odd-data register not empty
0
Transmit even-data registers empty
1
Description
Transmit even-data registers not empty
0
TODE
Description
Transmit data registers empty
Transmit data registers not empty
TEDE
0
1
Description
No transmit underrun error
0
TDE
Description
Transmit frame sync occurred during word transmission
1
TUE
Transmit Frame sync did not occur during word transmission
Description
Receive odd-data register full
0
TFS
Description
Receive odd-data register empty
Description
Reserved
0
1
RODF
SAISR - ESAI Status Register
X: $FFFFB3 Reset $000000
Freescale Semiconductor, Inc...
Programmer’s Reference
Freescale Semiconductor, Inc.
Date:
Programmer:
Figure C-14 ESAI Status Register (SAISR)
MOTOROLA
Freescale Semiconductor, Inc.
Programmer’s Reference
Date:
Application:
Programmer:
Sheet 2 of 3
Freescale Semiconductor, Inc...
GPIO
Port B(GPIO)
Port B Control Register
(PCRB)
X:$FFFFCF
ReadWrite
Reset = $0
23
9
8
7
6
5
11
10
9
8
7
6
3
4
*0 *0 *0 *0 *0 *0 *0 *0 *0
23
Port B Direction Register
(PRRB)
X:$FFFFCE
ReadWrite
Reset = $0
11 10
5
4
*0 *0 *0 *0 *0 *0 *0 *0 *0
2
1
0
PC3 PC2 PC1 PC0
3
2 1
0
PDC3 PDC2PDC1PDC0
PCn = 0 & PDCn = 0 -> Port pin PCn disconnected
PCn = 1 & PDCn = 0-> Port pin PCn configured as input
PCn = 0 & PDCn = 1-> Port pin PCn configured as output
PCn = 1 & PDCn = 1 -> Open-Drain Output
23
Port B GPIO Data Register
(PDRB)
X:$FFFFCD
ReadWrite
Reset = $0
11 10
9
8
7
6
5
4
*0 *0 *0 *0 *0 *0 *0 *0 *0
3
2
1
PD3 PD2 PD1
0
PD0
If port pin n is GPIO input, then PDn reflects the value on port pin n
if port pin n is GPIO output, then value written to PDn is reflected on port pin n
* = Reserved, Program as 0
Figure C-15 Port B Registers (PCRB, PRRB, PDRB)
MOTOROLA
DSP56364
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C-23
Freescale Semiconductor, Inc.
Programmer’s Reference
Date:
Application:
Programmer:
Sheet 2 of 3
GPIO
Port C (ESAI)
Freescale Semiconductor, Inc...
Port C Control Register
(PCRC)
X:$FFFFBF
ReadWrite
Reset = $0
23
11 10
9
8
7
6
5
4
*0
PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
11
23
Port C Direction Register
(PRRC)
X:$FFFFBE
ReadWrite
Reset = $0
*0
10
9
PDC11 PDC10 PDC9
8
7
6
5
PDC8
PDC7
PDC6
PDC5
3
2
1
0
PC3 PC2 PC1 PC0
4
3
2 1
0
PDC4 PDC3 PDC2PDC1PDC0
PCn = 0 & PDCn = 0 -> Port pin PCn disconnected
PCn = 1 & PDCn = 0-> Port pin PCn configured as input
PCn = 0 & PDCn = 1-> Port pin PCn configured as output
PCn = 1 & PDCn = 1 -> Port pin configured as ESAI
Port C GPIO Data Register
(PDRC)
X:$FFFFBD
ReadWrite
Reset = $0
23
11 10
9
8
*0
PD11 PD10
PD9
PD8
7
6
PD7 PD6
5
PD5
4
3
2
1
PD4 PD3 PD2 PD1
0
PD0
If port pin n is GPIO input, then PDn reflects the value on port pin n
if port pin n is GPIO output, then value written to PDn is reflected on port pin n
* = Reserved, Program as 0
Figure C-16 Port C Registers (PCRC, PRRC, PDRC)
C-24
DSP56364
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MOTOROLA
Freescale Semiconductor, Inc.
INDEX
Freescale Semiconductor, Inc...
A
adder
modulo, 1-6
offset, 1-7
reverse-carry, 1-7
Address Attribute, 4-2
address attribute, 4-2
Address Generation Unit, 1-6
Address Tracing (AT) Mode, 4-3
Address Tracing Enable (ATE), 4-3
addressing modes, 1-7
AGU, 1-6
B
barrel shifter, 1-5
Block Diagram, 1-2
bootstrap, 4-4
bootstrap modes, 4-3
Bootstrap Program, A-1
bootstrap program options
invoking, 4-5
bootstrap ROM, 3-2
bus
external address, 2-4
external data, 2-4
buses
internal, 1-8
MOTOROLA
emory, 1-3
Enhanced Serial Audio Interface, 2-10, 2-10
ESAI, 2-10, 2-10
ESAI block diagram, 6-1
ESAI Common Control Register (SAICR), C-21
ESAI Receive Clock Control Register (RCCR), C-19
ESAI Receive Clock Control Register (RCR), C-20
ESAI Status Register (SAISR), C-22
ESAI Transmit Clock Control Register (TCCR), C-17
ESAI Transmit Clock Control Register (TCR), C-18
external address bus, 2-4
external bus control, 2-4, 2-6
external data bus, 2-4
External Memory, 1-11
External Memory Expansion Port, 2-4
Features, 1-2
functional signal groups, 2-1
G
Global Data Bus, 1-8
Ground, 2-3
PLL, 2-3
CLKGEN, 1-9
Clock, 2-4
Clock Control Register (HCKR), C-14
Clock divider, 6-14
Clock Generator (CLKGEN), 1-9
configuration, 1-3
CPHA and CPOL (HCKR Clock Phase and Polarity
Controls), 7-9
data ALU, 1-5
registers, 1-6
Divide Factor (DF), 1-9
DMA, 1-9
DO loop, 1-7
DSP56300 core, 1-4
E
F
C
D
DSP56300 Family Manual, 1-5
Dynamic Memory, 1-11
H
HA1, HA3-HA6 (HSAR I2C Slave Address), 7-8
hardware stack, 1-7
HBER (HCSR Bus Error), 7-17
HBIE (HCSR Bus Error Interrupt Enable), 7-15, 7-15
HBUSY (HCSR Host Busy), 7-18
HCKR (SHI Clock Control Register), 7-8
HCSR
Receive Interrupt Enable Bits, 7-16
SHI Control/Status Register, 7-12
HDM0-HDM5 (HCKR Divider Modulus Select), 710
HEN (HCSR SHI Enable), 7-12
HFIFO (HCSR FIFO Enable Control), 7-13, 7-13
HFM0-HFM1 (HCKR Filter Mode), 7-11
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Index-1
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INDEX
HI2C (HCSR Serial Host Interface I2C/SPI
Selection), 7-12
HIDLE (HCSR Idle), 7-14
HM0-HM1 (HCSR Serial Host Interface Mode), 7-12
HMST (HCSR Master Mode), 7-14, 7-14
Host
Receive Data FIFO (HRX), 7-7
Receive Data FIFO—DSP Side, 7-7
Transmit Data Register (HTX), 7-7
Transmit Data Register—DSP Side, 7-7
Host Receive Data Register (HRX) (FIFO), C-15
HREQ Function In SHI Slave Modes, 7-14
HRFF (HCSR Host Receive FIFO Full), 7-17
HRIE0-HRIE1 (HCSR Receive Interrupt Enable), 716, 7-16
HRNE (HCSR Host Receive FIFO Not Empty), 7-17
HROE (HCSR Host Receive Overrun Error), 7-17
HRQE0-HRQE1 (HCSR Host Request Enable), 7-14
HTDE (HCSR Host Transmit Data Empty), 7-17
HTIE (HCSR Transmit Interrupt Enable), 7-15, 7-15
HTUE (HCSR Host Transmit Underrun Error), 7-16
I
I2C, 7-1, 7-19
Bit Transfer, 7-19
Bus Protocol For Host Read Cycle, 7-22
Bus Protocol For Host Write Cycle, 7-21
Data Transfer Formats, 7-21
Master Mode, 7-27
Protocol for Host Write Cycle, 7-21
Receive Data In Master Mode, 7-28
Receive Data In Slave Mode, 7-25
Slave Mode, 7-24
Start and Stop Events, 7-20
Transmit Data In Master Mode, 7-28, 7-28
Transmit Data In Slave Mode, 7-26, 7-26
I2C Bus Acknowledgment, 7-20
I2C Mode, 7-1
Inter Integrated Circuit Bus, 7-1
internal buses, 1-8
Internal Exception Priorities
SHI, 7-6
Internal I/O Memory, C-1
interrupt, 1-7
interrupt and mode control, 2-6, 2-7
interrupt control, 2-6, 2-7
Interrupt Priority Register, 4-7
MOTOROLA
Interrupt Priority Register- Peripherals (IPR-P), C-12
Interrupt Priority Register-Core (IPR-C), C-11
interrupt priority registers, 4-5
Interrupt Vectors
SHI, 7-6
J
JTAG, 1-9, 1-9, 2-13
L
LA register, 1-8
LC register, 1-8
Loop Address register (LA), 1-8
Loop Counter register (LC), 1-8
M
MAC, 1-6
Manual Conventions, xii, xii
Memory, 1-3
memory
bootstrap ROM, 3-2
program RAM, 3-1
X data RAM, 3-3
Y data RAM, 3-3
Memory Configuration, 1-3
Memory Configurations, 3-4
Memory Maps, 3-7, 3-8
Mode C (MC), 4-2
mode control, 2-6, 2-7
modulo adder, 1-6
multiplier-accumulator (MAC), 1-5, 1-6
O
offset adder, 1-7
OMR register, 1-8
OnCE module, 1-10, 2-13
On-Chip Emulation (OnCE) module, 1-10
on-chip memory
program, 3-1
X data RAM, 3-3
Y data RAM, 3-3
Operating Mode Register (OMR), 1-8, 4-1, 4-2, C-10
Operating Modes, 4-3, 4-3
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Index-2
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INDEX
Freescale Semiconductor, Inc...
P
PAB, 1-8
PAG, 1-7
PC register, 1-7
PCU, 1-7
PDB, 1-8
PDC, 1-7
Peripheral I/O Expansion Bus, 1-8
Peripheral modules, 1-3
Peripherals (IPR-P), C-12
Phase Lock Loop Control Register (PCTL), C-13
PIC, 1-7
PLL, 1-9, 2-4
PLL Pre-Divider Factor (PD0-PD3), 4-9
Port A, 2-4
Port B Registers (PCRB, PRRB, PDRB), C-23
Port C, 2-10, 2-10
Port C Registers (PCRC, PRRC, PDRC), C-24
Power, 2-2
Priority, 4-2
priority mechanism, 4-2
Processor Architecture, 1-4
Program Address Bus (PAB), 1-8
Program Address Generator (PAG), 1-7
Program Control Unit (PCU), 1-7
Program Counter register (PC), 1-7
Program Data Bus (PDB), 1-8
Program Decode Controller (PDC), 1-7
Program Interrupt Controller (PIC), 1-7
Program Memory Expansion Bus, 1-8
program RAM, 3-1
Program ROM, 1-10
Programming Model
SHI—DSP Side, 7-5
SHI—Host Side, 7-4
R
Related publications, 1-1
RESET, 2-7
reverse-carry adder, 1-7
ROM
bootstrap, 3-2
S
SC register, 1-8
Serial Audio Interface (ESAI), 1-4
MOTOROLA
Serial Host Interface, 2-8
Serial Host Interface (SHI), 1-4, 7-1
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus, 7-1
SHI, 2-8, 7-1
Block Diagram, 7-3
Clock Control Register—DSP Side, 7-8
Clock Generator, 7-3, 7-4, 7-4
Control/Status Register—DSP Side, 7-12
Data Size, 7-13
Exception Priorities, 7-6
HCKR
Clock Phase and Polarity Controls, 7-9
Divider Modulus Select, 7-10
Prescaler Rate Select, 7-10
HCKR Filter Mode, 7-11
HCSR
Bus Error Interrupt Enable, 7-15
FIFO Enable Control, 7-13
Host Request Enable, 7-14
Idle, 7-14
Master Mode, 7-14
Serial Host Interface I2C/SPI Selection, 7-12
Serial Host Interface Mode, 7-12
SHI Enable, 7-12
Host Receive Data FIFO—DSP Side, 7-7
Host Transmit Data Register—DSP Side, 7-7
HREQ
Function In SHI Slave Modes, 7-14
HSAR
I2C Slave Address, 7-8
Slave Address Register, 7-8
I/O Shift Register, 7-7
Input/Output Shift Register—Host Side, 7-6
Internal Architecture, 7-2, 7-2
Internal Interrupt Priorities, 7-6
Interrupt Vectors, 7-6
Introduction, 7-1
Operation During Stop, 7-29
Programming Considerations, 7-22
Programming Model, 7-4
Programming Model—DSP Side, 7-5
Programming Model—Host Side, 7-4
Slave Address Register—DSP Side, 7-8
SHI Host Control/Status Register (HCSR), C-16
SHI Host Transmit Data Register (HTX), C-15
SHI Noise Reduction Filter Mode, 7-11
SHI Slave Address (HSAR), C-14
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Index-3
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Freescale Semiconductor, Inc...
INDEX
signal groupings, 2-1
signals, 2-1
Sixteen-bit Compatibility, 3-1
Size register (SZ), 1-8
SP, 1-8
SPI, 7-1, 7-18
HCSR
Bus Error, 7-17
Host Busy, 7-18
Host Receive FIFO Full, 7-17
Host Receive FIFO Not Empty, 7-17
Host Receive Overrun Error, 7-17
Host Transmit Data Empty, 7-17
Host Transmit Underrun Error, 7-16
Receive Interrupt Enable, 7-15, 7-16
Master Mode, 7-23
Slave Mode, 7-22
SPI Data-To-Clock Timing, 7-9
SPI Data-To-Clock Timing Diagram, 7-9
SPI Mode, 7-1
SR register, 1-7
SS, 1-8
Stack Counter register (SC), 1-8
Stack Pointer (SP), 1-8
Status Register, 1-12
Status Register (SR), 1-7, C-9
System Stack (SS), 1-8
SZ register, 1-8
Y
Y data RAM, 3-3
Y Memory Address Bus (YAB), 1-8
Y Memory Data Bus (YDB), 1-8
Y Memory Expansion Bus, 1-8
YAB, 1-8
YDB, 1-8
T
TAP, 1-9
Test Access Port (TAP), 1-9
Transmitter High Frequency Clock Divider, 6-14
V
VBA register, 1-8
Vector Base Address register (VBA), 1-8
X
X data RAM, 3-3
X Memory Address Bus (XAB), 1-8
X Memory Data Bus (XDB), 1-8
X Memory Expansion Bus, 1-8
XAB, 1-8
XDB, 1-8
MOTOROLA
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Index-4
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Freescale Semiconductor, Inc.
How to reach us:
USA/Europe/Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
(303) 675-2140
(800) 441-2447
Asia/Pacific:
Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Tai Po, N.T., Hong Kong
852-26629298
Technical Resource Center:
1 (800) 521-6274
DSP helpline email:
[email protected]
Japan:
Nippon Motorola Ltd.
SPD, Strategic Planning Office
4-32-1, Nishi-Gotanda
Shinagawa-ku, Tokyo, Japan
81-3-5487-8488
Internet:
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DSP56364UM/D
Revision 1
09/00
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