ETC HC05C4AGRS

August 5, 1997
CSIC System Design Group
Austin, Texas
A G R E E M E N T
General Release Specification
N O N - D I S C L O S U R E
MC68HC05C4A
MC68HCL05C4A
MC68HSC05C4A
R E Q U I R E D
HC05C4AGRS/D
REV. 4.0
A G R E E M E N T
R E Q U I R E D
General Release Specification
N O N D I S C L O S U R E
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
© Motorola, Inc. 1997
2
MC68HC05C4A — Rev. 4.0
MOTOROLA
List of Sections
Section 1. General Description . . . . . . . . . . . . . . 15
R E Q U I R E D
General Release Specification — MC68HC05C4A
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . 35
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 6. Low-Power Modes . . . . . . . . . . . . . . . 45
Section 7. Input/Output (I/O) Ports . . . . . . . . . . . 49
Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 9. Serial Communications
Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . 63
Section 10. Serial Peripheral Interface (SPI) . . . 81
Section 11. Operating Modes. . . . . . . . . . . . . . . . 91
Section 12. Instruction Set. . . . . . . . . . . . . . . . . . 95
Section 13. Electrical Specifications. . . . . . . . . 113
Section 14. Mechanical Specifications . . . . . . . 131
Section 15. Ordering Information . . . . . . . . . . . 135
Appendix A. MC68HCL05C4A . . . . . . . . . . . . . . 141
Appendix B. MC68HSC05C4A . . . . . . . . . . . . . . 145
Appendix C. M68HC05Cx Family
Feature Comparisons . . . . . . . . . . . . . . . 153
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
List of Sections
3
N O N - D I S C L O S U R E
Section 3. Central Processor Unit (CPU) . . . . . . 31
A G R E E M E N T
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . 25
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
List of Sections
General Release Specification
4
MC68HC05C4A — Rev. 4.0
List of Sections
MOTOROLA
1.1
Contents ...................................................................................15
1.2
Introduction ...............................................................................15
1.3
Features....................................................................................16
1.4
Mask Options............................................................................18
1.5
Functional Pin Description ........................................................18
1.5.1
VDD and VSS........................................................................22
1.5.2
IRQ ......................................................................................22
1.5.3
OSC1 and OSC2.................................................................22
1.5.4
RESET ................................................................................22
1.5.5
TCAP...................................................................................22
1.5.6
TCMP ..................................................................................22
1.5.7
Port A (PA0–PA7) ...............................................................23
1.5.8
Port B (PB0–PB7) ...............................................................23
1.5.9
Port C (PC0–PC7)...............................................................23
1.5.10
Port D (PD0–PD5 and PD7)................................................23
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents ...................................................................................25
Introduction ...............................................................................25
Read-Only Memory (ROM).......................................................25
ROM Security Feature ..............................................................26
Random-Access Memory (RAM) ..............................................26
Section 3. Central Processor Unit (CPU)
3.1
Contents ...................................................................................31
3.2
Introduction ...............................................................................31
3.3
CPU Registers ..........................................................................31
3.3.1
Accumulator ........................................................................32
3.3.2
Index Register .....................................................................32
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Table of Contents
5
R E Q U I R E D
Section 1. General Description
A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
Table of Contents
3.3.3
3.3.4
3.3.5
Program Counter ................................................................ 33
Stack Pointer ...................................................................... 33
Condition Code Register .................................................... 33
Section 4. Interrupts
A G R E E M E N T
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Contents................................................................................... 35
Introduction .............................................................................. 35
Hardware Controlled Interrupt Sequence ................................ 37
Software Interrupt (SWI) .......................................................... 37
External Interrupt (IRQ)............................................................ 39
Timer Interrupt ......................................................................... 39
Serial Communications Interrupt (SCI) .................................... 39
Serial Peripheral Interrupt (SPI)............................................... 40
Section 5. Resets
N O N - D I S C L O S U R E
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Contents................................................................................... 41
Introduction .............................................................................. 41
Power-On Reset (POR) ........................................................... 42
RESET Pin............................................................................... 42
Computer Operating Properly (COP) Reset ............................ 42
Resetting the COP.............................................................. 42
COP During Wait Mode ...................................................... 43
COP During Stop Mode...................................................... 43
COP During Self-Check Mode............................................ 43
Section 6. Low-Power Modes
6.1
6.2
6.3
6.4
6.5
Contents................................................................................... 45
Introduction .............................................................................. 45
Stop Mode................................................................................ 46
Stop Recovery ......................................................................... 47
Wait Mode................................................................................ 47
Section 7. Input/Output (I/O) Ports
7.1
7.2
7.3
7.4
Contents................................................................................... 49
Introduction .............................................................................. 49
Port A ....................................................................................... 49
Port B ....................................................................................... 50
General Release Specification
6
MC68HC05C4A — Rev. 4.0
Table of Contents
MOTOROLA
Section 8. Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Contents ...................................................................................53
Introduction ...............................................................................53
Counter .....................................................................................55
Output Compare Register.........................................................56
Input Capture Register..............................................................57
Timer Control Register..............................................................58
Timer Status Register ...............................................................60
Timer During Wait Mode...........................................................61
Timer During Stop Mode...........................................................61
Section 9. Serial Communications Interface (SCI)
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
Contents ...................................................................................63
Introduction ...............................................................................63
Features....................................................................................64
SCI Data Format.......................................................................64
SCI Operation ...........................................................................65
Transmitter ..........................................................................65
Receiver ..............................................................................68
SCI I/O Registers......................................................................71
SCI Data Register ...............................................................71
SCI Control Register 1 ........................................................72
SCI Control Register 2 ........................................................74
SCI Status Register.............................................................76
Baud Rate Register .............................................................78
Section 10. Serial Peripheral Interface (SPI)
10.1 Contents ...................................................................................81
10.2 Introduction ...............................................................................81
10.3 Features....................................................................................82
10.4 SPI Signal Description ..............................................................82
10.4.1
Master In Slave Out (MISO) ................................................82
10.4.2
Master Out Slave In (MOSI) ................................................82
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Table of Contents
7
A G R E E M E N T
Port C........................................................................................50
Port D........................................................................................51
Input/Output Programming .......................................................51
N O N - D I S C L O S U R E
7.5
7.6
7.7
R E Q U I R E D
Table of Contents
R E Q U I R E D
Table of Contents
10.4.3
Serial Clock (SCK).............................................................. 83
10.4.4
Slave Select (SS) ............................................................... 84
10.5 Functional Description ............................................................. 84
10.6 SPI Registers ........................................................................... 86
10.6.1
Serial Peripheral Control Register ...................................... 87
10.6.2
Serial Peripheral Status Register ....................................... 88
10.6.3
Serial Peripheral Data I/O Register .................................... 90
Section 11. Operating Modes
A G R E E M E N T
11.1 Contents................................................................................... 91
11.2 Introduction .............................................................................. 91
11.3 User Mode ............................................................................... 91
11.4 Self-Check Mode ..................................................................... 92
11.4.1
Self-Check Tests ................................................................ 92
11.4.2
Self-Check Results ............................................................. 93
Section 12. Instruction Set
N O N - D I S C L O S U R E
12.1 Contents................................................................................... 95
12.2 Introduction .............................................................................. 96
12.3 Addressing Modes ................................................................... 96
12.3.1
Inherent .............................................................................. 97
12.3.2
Immediate........................................................................... 97
12.3.3
Direct .................................................................................. 97
12.3.4
Extended ............................................................................ 97
12.3.5
Indexed, No Offset.............................................................. 98
12.3.6
Indexed, 8-Bit Offset........................................................... 98
12.3.7
Indexed,16-Bit Offset.......................................................... 98
12.3.8
Relative............................................................................... 99
12.4 Instruction Types...................................................................... 99
12.4.1
Register/Memory Instructions........................................... 100
12.4.2
Read-Modify-Write Instructions ........................................ 101
12.4.3
Jump/Branch Instructions ................................................. 102
12.4.4
Bit Manipulation Instructions............................................. 104
12.4.5
Control Instructions........................................................... 105
12.5 Instruction Set Summary........................................................ 106
12.6 Opcode Map .......................................................................... 111
General Release Specification
8
MC68HC05C4A — Rev. 4.0
Table of Contents
MOTOROLA
Contents .................................................................................113
Introduction .............................................................................113
Maximum Ratings ...................................................................114
Operating Temperature Range...............................................115
Thermal Characteristics..........................................................115
Power Considerations.............................................................116
5.0 V DC Electrical Characteristics.........................................118
3.3 V DC Electrical Characteristics.........................................119
5.0 V Control Timing ...............................................................122
3.3 V Control Timing ...............................................................123
5.0 V Serial Peripheral Interface Timing .................................126
3.3 V Serial Peripheral Interface Timing .................................127
Section 14. Mechanical Specifications
14.1
14.2
14.3
14.4
14.5
14.6
Contents .................................................................................131
Introduction .............................................................................131
40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03)....................................................................132
42-Pin Plastic Shrink Dual In-Line (SDIP)
Package (Case 858-01).....................................................132
44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02)....................................................................133
44-Lead Quad Flat Pack (QFP)
(Case 824A-01) .................................................................134
Section 15. Ordering Information
15.1
15.2
15.3
15.4
15.5
15.6
15.7
Contents .................................................................................135
Introduction .............................................................................135
MCU Ordering Forms .............................................................135
Application Program Media.....................................................136
ROM Program Verification......................................................137
ROM Verification Units (RVUs)...............................................138
MC Order Numbers ................................................................139
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Table of Contents
9
A G R E E M E N T
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12
N O N - D I S C L O S U R E
Section 13. Electrical Specifications
R E Q U I R E D
Table of Contents
R E Q U I R E D
Table of Contents
Appendix A. MC68HCL05C4A
A.1
A.2
A.3
A.4
A.5
A.6
Contents................................................................................. 141
Introduction ............................................................................ 141
Low-Power Operating Temperature Range ........................... 141
2.5–3.6 V DC Electrical Characteristics ................................. 142
1.8–2.4 V DC Electrical Characteristics ................................. 142
Low-Power Supply Current .................................................... 143
A G R E E M E N T
Appendix B. MC68HSC05C4A
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
Contents................................................................................. 145
Introduction ............................................................................ 145
High-Speed Operating Temperature Range .......................... 146
4.5 –5.5 V High-Speed Supply Currents................................ 147
4.5–5.5 V High-Speed Control Timing ................................... 148
2.4–3.6 V High-Speed Control Timing ................................... 148
4.5–5.5 V High-Speed SPI Timing ......................................... 150
2.4–3.6 V High-Speed SPI Timing ......................................... 151
Appendix C. M68HC05Cx Family
Feature Comparisons
N O N - D I S C L O S U R E
C.1
C.2
Contents................................................................................. 153
Introduction ............................................................................ 153
Table C-1. M68HC05Cx Feature Comparison ...................... 154
General Release Specification
10
MC68HC05C4A — Rev. 4.0
Table of Contents
MOTOROLA
Title
1-1
1-2
1-3
1-4
1-5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
40-Pin Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . .19
42-Pin Plastic Shrink Dual In-Line Package . . . . . . . . . . . . .20
44-Lead Plastic Leaded Chip Carrier . . . . . . . . . . . . . . . . . .21
44-Lead Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6-1
6-2
Stop/Wait Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .47
7-1
7-2
Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8-1
8-2
8-3
8-4
8-5
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
Input Capture Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .58
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .60
9-1
9-2
9-3
SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
SCI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
MC68HC05C4A — Rev. 4.0
MOTOROLA
Page
General Release Specification
List of Figures
11
R E Q U I R E D
Figure
A G R E E M E N T
List of Figures
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
List of Figures
A G R E E M E N T
Figure
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . .71
SCI Control Register (SCCR1) . . . . . . . . . . . . . . . . . . . . . . .72
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . .74
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . .76
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . .78
10-1
10-2
10-3
10-4
10-5
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .83
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . .85
Serial Peripheral Interface
Master-Slave Interconnection . . . . . . . . . . . . . . . . . . . . .86
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . .87
SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . .88
11-1
11-2
User Mode Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Self-Check Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . .94
13-1
13-2
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Maximum Supply Current Versus Internal
Clock Frequency, VDD = 5.5 V . . . . . . . . . . . . . . . . . . .120
Maximum Supply Current Versus Internal
Clock Frequency, VDD = 3.6 V . . . . . . . . . . . . . . . . . . .121
TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . .123
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .124
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . .125
Power-On Reset Timing Diagram . . . . . . . . . . . . . . . . . . .125
SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .128
SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .129
13-4
13-5
13-6
13-7
13-8
13-9
13-10
General Release Specification
12
Page
9-4
9-5
9-6
9-7
9-8
13-3
N O N - D I S C L O S U R E
Title
MC68HC05C4A — Rev. 4.0
List of Figures
MOTOROLA
Title
Page
4-1
Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . .36
7-1
I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
9-1
9-2
9-3
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . .79
Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . . . .80
10-1 Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . . . .88
11-1 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11-2 Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . . . . . .93
12-1
12-2
12-3
12-4
12-5
12-6
12-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .100
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .101
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .103
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
C-1
M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . .154
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
List of Tables
13
R E Q U I R E D
Table
A G R E E M E N T
List of Tables
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
List of Tables
General Release Specification
14
MC68HC05C4A — Rev. 4.0
List of Tables
MOTOROLA
1.2
Introduction ...............................................................................15
1.3
Features....................................................................................16
1.4
Mask Options............................................................................18
1.5
Functional Pin Description ........................................................18
1.5.1
VDD and VSS........................................................................22
1.5.2
IRQ ......................................................................................22
1.5.3
OSC1 and OSC2.................................................................22
1.5.4
RESET ................................................................................22
1.5.5
TCAP...................................................................................22
1.5.6
TCMP ..................................................................................22
1.5.7
Port A (PA0–PA7) ...............................................................23
1.5.8
Port B (PB0–PB7) ...............................................................23
1.5.9
Port C (PC0–PC7)...............................................................23
1.5.10
Port D (PD0–PD5 and PD7)................................................23
1.2 Introduction
The MC68HC05C4A is an enhanced version of the MC68HC05C4. It
includes keyboard scanning logic, a high-current pin, a COP watchdog
timer, and read-only memory (ROM) security.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
General Description
15
R E Q U I R E D
1.1 Contents
A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
1.3 Features
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Description
•
M68HC05 Core
•
Single 3.0- to 5.5-Volt Supply
•
Available Packages:
– 40-Pin Dual In-Line (DIP)
– 42-Pin Plastic Shrink Dual In-Line (SDIP)
– 44-Lead Plastic Leaded Chip Carrier (PLCC)
– 44-Lead Quad Flat Pack (QFP)
•
On-Chip Oscillator for Crystal/Ceramic Resonator
•
Fully Static Operation
•
4160 Bytes of User ROM
•
ROM Security Feature
•
176 Bytes of On-Chip Random-Access Memory (RAM)
•
Asynchronous Serial Communications Interface (SCI) System
•
Synchronous Serial Peripheral Interface (SPI) System
•
16-Bit Capture/Compare Timer System
•
Computer Operating Properly (COP) Watchdog Timer
•
24 Bidirectional Input/Output (I/O) Lines
•
Seven Input-Only Lines
•
User Mode
•
Self-Check Mode
•
Power-Saving Stop and Wait Modes
•
High Current Sink and Source on One Port Pin (PC7)
•
Mask Selectable External Interrupt Sensitivity
•
Mask Programmable Keyscan Logic
General Release Specification
16
MC68HC05C4A — Rev. 4.0
General Description
MOTOROLA
R E Q U I R E D
General Description
Features
PA0
SELF-CHECK ROM — 240 BYTES
PA1
PA2
PORT A
DATA DIRECTION A
USER ROM AND USER VECTORS — 4160 BYTES
PA3
PA4
PA5
PA6
PA7
SRAM — 176 BYTES
ALU
M68HC05 CPU
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
CPU REGISTERS
ACCUMULATOR
PC0
0
0
1
STACK POINTER
PROGRAM COUNTER
0
CONDITION CODE REGISTER
OSC2
OSC1
1
OSCILLATOR
÷2
1
1
1
H
I
N Z
C
PORT D
PC3
PC4
PC5
PC6
PD7
RDI(PD0)
SCI
SYSTEM
VSS
PC2
PC7✝
COP
VDD
PC1
N O N - D I S C L O S U R E
0
INTERNAL
PROCESSOR
CLOCK
0
0
PORT C
0
DATA DIRECTION C
INDEX REGISTER
0
A G R E E M E N T
CPU
CONTROL
PB1*
PORT B
IRQ
RESET
DATA DIRECTION B
PB0*
BAUD RATE
GENERATOR
TDO(PD1)
MISO(PD2)
MOSI(PD3)
SPI
POWER
SCK(PD4)
SS(PD5)
BAUD RATE
GENERATOR
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
TCMP
TCAP
* Port B pins also function as external interrupts.
✝ PC7 has a high current sink and source capability.
Figure 1-1. Block Diagram
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
General Description
17
R E Q U I R E D
1.4 Mask Options
Eight mask options are available to select the pullup/interrupts on port B
on a pin-by-pin basis.
There are also four mask options for:
1. IRQ, edge-sensitive only or edge- and level-sensitive
2. CLOCK, crystal or RC
3. COP, enable or disable
4. STOP, enable or disable
1.5 Functional Pin Description
The MC68HC05C4A is available in a 40-pin DIP (see Figure 1-2), 42-pin
SDIP (see Figure 1-3), 44-pin PLCC (see Figure 1-2), and 44-pin QFP
(see Figure 1-5). The following paragraphs describe the general function
of each pin.
NOTE:
N O N - D I S C L O S U R E
A G R E E M E N T
General Description
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, resistance, capacitance, time, or frequency specified in the
following paragraphs will refer to the nominal values. The exact values
and their tolerance or limits are specified in Section 13. Electrical
Specifications.
General Release Specification
18
MC68HC05C4A — Rev. 4.0
General Description
MOTOROLA
40
VDD
IRQ
2
39
OSC1
NC*
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
PA5
6
35
TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
A G R E E M E N T
1
If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD.
N O N - D I S C L O S U R E
*
RESET
R E Q U I R E D
General Description
Functional Pin Description
Figure 1-2. 40-Pin Dual In-Line Package
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
General Description
19
A G R E E M E N T
R E Q U I R E D
General Description
N O N - D I S C L O S U R E
*
RESET
1
42
VDD
IRQ
2
41
OSC1
NC*
3
40
OSC2
PA7
4
39
TCAP
PA6
5
38
PD7
PA5
6
37
TCMP
PA4
7
36
PD5/SS
PA3
8
35
PD4/SCK
PA2
9
34
PD3/MOSI
PA1
10
33
PD2/MISO
PA0
11
32
PD1/TDO
PB0
12
31
PD0/RDI
PB1
13
30
PC0
PB2
14
29
PC1
PB3
15
28
PC2
NC
16
27
NC
PB4
17
26
PC3
PB5
18
25
PC4
PB6
19
24
PC5
PB7
20
23
PC6
VSS
21
22
PC7
If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD.
Figure 1-3. 42-Pin Plastic Shrink Dual In-Line Package
General Release Specification
20
MC68HC05C4A — Rev. 4.0
General Description
MOTOROLA
NC
IRQ
RESET
VDD
OSC1
OSC2
TCAP
NC
3
2
1
44
43
41
40
24
25
26
27
28
PC7
PC6
PC5
PC4
PC3
PB7
23
21
22
PB6
NC
20
VSS
19
R E Q U I R E D
NC*
18
NC
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
PC2
A G R E E M E N T
PA7
4
42
PA6
5
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
PB5
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
6
General Description
Functional Pin Description
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD.
PC3
PC2
PC1
PC0
PD0/RDI
PD1/TDO
PD2/MISO
PD3/MOSI
PD4/SCK
33 32 31 30 29 28 27 26 25 24 23
34
22
NC
TCAP
35
21
PC4
OSC2
36
20
PC5
OSC1
37
19
PC6
VDD
38
18
PC7
NC
39
17
VSS
PB6
NC*
43
44
1
13
PB5
PB4
3
4
5
6
7
8
PB3
2
12
9 10 11
PB2
PA6
PA7
PB1
14
PB0
42
PA0
IRQ
PA1
PB7
PA2
NC
15
PA3
16
41
PA4
40
PA5
NC
RESET
N O N - D I S C L O S U R E
PD7
PD5/SS
TCMP
Figure 1-4. 44-Lead Plastic Leaded Chip Carrier
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD.
Figure 1-5. 44-Lead Quad Flat Pack
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
General Description
21
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
General Description
1.5.1 VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the
positive supply and VSS is ground.
1.5.2 IRQ
This pin has a mask selectable option that provides two different choices
of interrupt triggering sensitivity. The IRQ pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. Refer to
Section 4. Interrupts for more detail.
1.5.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal, a ceramic resonator, a resistor/capacitor combination, or an
external signal connects to these pins, providing a system clock. The
internal bus rate is one-half the external oscillator frequency.
1.5.4 RESET
This active low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity.
1.5.5 TCAP
This pin controls the input capture feature for the on-chip programmable
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity.
1.5.6 TCMP
The TCMP pin provides an output for the output compare feature of the
on-chip timer subsystem.
General Release Specification
22
MC68HC05C4A — Rev. 4.0
General Description
MOTOROLA
1.5.8 Port B (PB0–PB7)
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as input during poweron or reset. Port B has mask option enabled pullup devices and interrupt
capability by pin. The interrupts and pullups are enabled together. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.9 Port C (PC0–PC7)
These eight I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as input during poweron or reset. PC7 has high current sink and source capability. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.10 Port D (PD0–PD5 and PD7)
These seven port lines comprise port D. PD7 and PD5–PD0 are input
only. PD0 and PD1 are shared with the SCI subsystem and PD2–PD5
are shared with the SPI subsystem. For a detailed description on I/O
programming, refer to 7.7 Input/Output Programming.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
General Description
23
A G R E E M E N T
These eight input/output (I/O) lines comprise port A. The state of any pin
is software programmable and all port A lines are configured as input
during power-on or reset. For detailed information on I/O programming,
see 7.7 Input/Output Programming.
N O N - D I S C L O S U R E
1.5.7 Port A (PA0–PA7)
R E Q U I R E D
General Description
Functional Pin Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Description
General Release Specification
24
MC68HC05C4A — Rev. 4.0
General Description
MOTOROLA
2.2
Introduction ...............................................................................25
2.3
Read-Only Memory (ROM).......................................................25
2.4
ROM Security Feature ..............................................................26
2.5
Random-Access Memory (RAM) ..............................................26
2.2 Introduction
The MC68HC05C4A has an 8-Kbyte memory map, consisting of user
read-only memory (ROM), user random-access memory (RAM), selfcheck ROM, and input/output (I/O) registers. See Figure 2-1 and
Figure 2-2.
2.3 Read-Only Memory (ROM)
The user ROM consists of 48 bytes of page zero ROM from $0020 to
$004F, 4096 bytes of ROM from $0100 to $10FF, and 16 bytes of user
vectors from $1FF0 to $1FFF. The self-check ROM and vectors are
located from $1F00 to $1FEF. See Figure 2-1.
Twelve of the user vectors, $1FF4 through $1FFF, are dedicated to
user-defined reset and interrupt vectors. The remaining four bytes from
$1FF0-$1FF3 are not used.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Memory
25
R E Q U I R E D
2.1 Contents
A G R E E M E N T
Section 2. Memory
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
2.4 ROM Security Feature
A security1 feature has been incorporated into the MC68HC05C4A to
help prevent externally reading of code in the ROM. This feature aids in
keeping customer-developed software proprietary.
2.5 Random-Access Memory (RAM)
The user RAM consists of 176 bytes and is used both for generalpurpose RAM and stack area. The stack begins at address $00FF. The
stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.
See Figure 2-1.
A G R E E M E N T
R E Q U I R E D
Memory
N O N - D I S C L O S U R E
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make
reading or copying the ROM difficult for unauthorized users.
General Release Specification
26
MC68HC05C4A — Rev. 4.0
Memory
MOTOROLA
$001F
$0020
USER ROM
48 BYTES
$004F
$0050
RAM
176 BYTES
$00BF
$00C0
STACK
64 BYTES
$00FF
$0100
USER ROM
4096 BYTES
$10FF
$1100
UNUSED
3548 BYTES
COP REGISTER
$1EFF
$1F00
NOT USED (3 BYTES)
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SCI VECTOR (HIGH)
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
SELF-CHECK
ROM
AND VECTORS
240 BYTES
$1FEF
$1FF0
$1FFF
USER ROM VECTORS
16 BYTES
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
A G R E E M E N T
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
UNUSED
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
UNUSED
UNUSED
UNUSED
I/O REGISTERS
32 BYTES
N O N - D I S C L O S U R E
$0000
R E Q U I R E D
Memory
Random-Access Memory (RAM)
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
Figure 2-1. Memory Map
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Memory
27
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Memory
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
Register
Port A Data
PORTA
Read:
Port B Data
PORTB
Read:
Port C Data
PORTD
Read:
Port D Data
PORTD
Read:
Port A Data Direction
DDRA
Read:
Port B Data Direction
DDRB
Read:
Port C Data Direction
DDRC
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD5
PD4
PD3
PD2
PD1
PD0
Write:
Write:
Write:
PD7
Write:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
SPIF
WCOL
SPD7
SPD6
SPD3
SPD2
SPD1
SPD0
Write:
Write:
Write:
Read:
$0007
Unimplemented
Write:
Read:
$0008
Unimplemented
Write:
Read:
$0009
Unimplemented
Write:
$000A
$000B
$000C
SPI Control Register
SPCR
Read:
SPI Status Register
SPSR
Read:
SPI Data Register
SPDR
Read:
Write:
0
MODF
Write:
SPD5
SPD4
Write:
= Unimplemented
Figure 2-2. Input/Output Registers
General Release Specification
28
MC68HC05C4A — Rev. 4.0
Memory
MOTOROLA
SCI Baud Rate Register
BAUD
Read:
SCI Control 1
SCCR1
Read:
SCI Control 2
SCCR2
Read:
SCI Status Register
SCSR
Read:
SCI Data Register
SCDAT
Read:
Timer Control Register
TCR
Read:
Timer Status Register
TSR
Read:
Input Capture Register
ICR (High)
Read:
Input Capture Register
ICR (Low)
Read:
Output Compare Register
OCR (High)
Read:
Output Compare Register
OCR (Low)
Read:
Timer Counter Register
TCNT (High)
Read:
Timer Counter Register
TCNT (Low)
Read:
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Bit 7
6
0
0
5
4
SCP1
SCP0
3
2
1
Bit 0
SCR2
SCR1
SCR0
0
0
0
SBK
0
Write:
R8
0
T8
M
WAKE
Write:
TIE
TCIE
RIE
ILIE
TE
RE
RMW
TDRE
TC
RDRF
IDLE
OR
NF
FE
SCD7
SCD6
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
0
0
0
ICIE
OCIE
TOIE
IEDGE
OLVL
ICF
OCF
TOF
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
0
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
= Unimplemented
Figure 2-2. Input/Output Registers (Continued)
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Memory
A G R E E M E N T
Register
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory
Random-Access Memory (RAM)
29
Register
Alternate Counter Register
ALTCNT (High)
Read:
$001A
Alternate Counter Register
ALTCNT (Low)
Read:
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
Write:
Write:
Read:
$001C
Unimplemented
Write:
Read:
$001D
Unimplemented
Write:
Read:
$001E
Unimplemented
Write:
Read:
$001F
Reserved
Write:
↓
↑
R E Q U I R E D
Addr.
↑
Read:
$1FF0
User ROM Data
COP Reset
Write:
N O N - D I S C L O S U R E
A G R E E M E N T
Memory
COPC
= Unimplemented
R
= Reserved
Figure 2-2. Input/Output Registers (Continued)
General Release Specification
30
MC68HC05C4A — Rev. 4.0
Memory
MOTOROLA
Section 3. Central Processor Unit (CPU)
3.1 Contents
Introduction ...............................................................................31
3.3
CPU Registers ..........................................................................31
3.3.1
Accumulator ........................................................................32
3.3.2
Index Register .....................................................................32
3.3.3
Program Counter.................................................................33
3.3.4
Stack Pointer .......................................................................33
3.3.5
Condition Code Register .....................................................33
3.2 Introduction
N O N - D I S C L O S U R E
This section describes the CPU registers.
3.3 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt
stacking order is shown in Figure 3-2.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Central Processor Unit (CPU)
A G R E E M E N T
3.2
R E Q U I R E D
General Release Specification — MC68HC05C4A
31
R E Q U I R E D
Central Processor Unit (CPU)
7
0
7
ACCUMULATOR
0
INDEX REGISTER
X
12
0
PC
0
PROGRAM COUNTER
7
12
0
0
0
0
1
0
1
SP
STACK POINTER
CCR
H
A G R E E M E N T
N O N - D I S C L O S U R E
A
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
1
INCREASING
MEMORY
ADDRESSES
R
E
T
U
R
N
0
1
1
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
PCL
STACK
I
N
T
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-1 is a general-purpose 8-bit
register used to hold operands and results of arithmetic calculations or
data manipulations.
3.3.2 Index Register
The index register (X) is an 8-bit register used by the indexed addressing
value to create an effective address. The index register also may be
used as a temporary storage area.
General Release Specification
32
MC68HC05C4A — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
3.3.4 Stack Pointer
The stack pointer (SP) contains the address of the next free location on
the stack. During an MCU reset or the reset stack pointer (RSP)
instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented
as data is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These eight bits are appended to the six
least significant register bits (LSB) to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64
(decimal) locations. If 64 locations are exceeded, the stack pointer
wraps around and loses the previously stored information. A subroutine
call occupies two locations on the stack; an interrupt uses five locations.
3.3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed, and the fifth
bit indicates whether interrupts are masked. These bits can be tested
individually by a program, and specific actions can be taken as a result
of their state. Each bit is explained in the following paragraphs.
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
I — Interrupt
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Central Processor Unit (CPU)
33
A G R E E M E N T
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched.
N O N - D I S C L O S U R E
3.3.3 Program Counter
R E Q U I R E D
Central Processor Unit (CPU)
CPU Registers
R E Q U I R E D
Central Processor Unit (CPU)
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
C — Carry/Borrow
N O N - D I S C L O S U R E
A G R E E M E N T
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
General Release Specification
34
MC68HC05C4A — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
4.1 Contents
4.2
Introduction ...............................................................................35
4.3
Hardware Controlled Interrupt Sequence .................................37
4.4
Software Interrupt (SWI) ...........................................................37
4.5
External Interrupt (IRQ) ............................................................39
4.6
Timer Interrupt ..........................................................................39
4.7
Serial Communications Interrupt (SCI) .....................................39
4.8
Serial Peripheral Interrupt (SPI)................................................40
4.2 Introduction
R E Q U I R E D
Section 4. Interrupts
A G R E E M E N T
General Release Specification — MC68HC05C4A
•
Four maskable hardware interrupts, IRQ (interrupt request), SPI
(serial peripheral interface), SCI (serial communications
interface), and timer
•
Non-maskable software interrupt instruction (SWI)
Port B interrupts, if enabled, are combined with the IRQ to form a single
interrupt source.
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI (return to interrupt) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Interrupts
35
N O N - D I S C L O S U R E
The MCU can be interrupted five different ways:
R E Q U I R E D
Interrupts
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but they are considered pending until the current
instruction is complete.
NOTE:
The current instruction is the one already fetched and being operated on.
A G R E E M E N T
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the Ibit state.
Vector addresses for all interrupts, including reset, are listed in
Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
Flag
Name
N/A
N/A
Reset
N/A
N/A
N/A
N O N - D I S C L O S U R E
Register
CPU
Interrupt
Vector
Address
RESET
$1FFE–$1FFF
Software
SWI
$1FFC–$1FFD
N/A
External Interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
Timer Input Capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer Output
Compare
TIMER
$1FF8–$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8–$1FF9
SCSR
TDRE
Transmit Buffer
Empty
SCI
$1FF6–$1FF7
SCSR
TC
Transmit Complete
SCI
$1FF6–$1FF7
SCSR
RDRF
Receiver Buffer Full
SCI
$1FF6–$1FF7
SCSR
IDLE
Idle Line Detect
SCI
$1FF6–$1FF7
SCSR
OR
Overrun
SCI
$1FF6–$1FF7
SPSR
SPIF
Transfer Complete
SPI
$1FF4–$1FF5
SPSR
MODF
Mode Fault
SPI
$1FF4–$1FF5
Interrupts
General Release Specification
36
MC68HC05C4A — Rev. 4.0
Interrupts
MOTOROLA
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address, which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset, as previously described in
Section 5. Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ),
serial periferal interface, serial communications interface, or timer
interrupt. These individual interrupts have no special wait vectors.
4.4 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt. It is executed regardless of the state of the I bit in the
CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts
which were pending when the SWI was fetched but before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $1FFC and
$1FFD.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Interrupts
37
A G R E E M E N T
Three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts
for hardware interrupts are shown in Figure 4-1.
N O N - D I S C L O S U R E
4.3 Hardware Controlled Interrupt Sequence
R E Q U I R E D
Interrupts
Hardware Controlled Interrupt Sequence
R E Q U I R E D
Interrupts
FROM
RESET
Y
I BIT
IN CCR SET?
N
A G R E E M E N T
IRQ
EXTERNAL
INTERRUPT
?
Y
CLEAR IRQ
REQUEST LATCH
N
INTERNAL
TIMER
INTERRUPT
?
N
Y
INTERNAL
SCI
INTERRUPT
?
N
Y
INTERNAL
SPI
INTERRUPT
?
N
Y
STACK
PC, X, A, CCR
N O N - D I S C L O S U R E
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
SET I BIT IN
CC REGISTER
Y
N
Y
LOAD PC FROM:
SWI: $1FFC-$1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
SCI: $1FF6-$1FF7
RTI
INSTRUCTION
?
N
RESTORE REGISTERS
FROM STACK:
CCR, A, X, PC
EXECUTE
INSTRUCTION
Figure 4-1. Interrupt Flowchart
General Release Specification
38
MC68HC05C4A — Rev. 4.0
Interrupts
MOTOROLA
When any of the port B pullups are enabled, that pin becomes an
additional external interrupt source which is coupled to the IRQ pin logic.
It follows the same edge/edge-level selection that the IRQ pin has. See
Figure 7-1. Port B Pullup Option.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitiveonly trigger operation is selectable by mask option.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.7 Serial Communications Interrupt (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF6 and $1FF7.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Interrupts
39
A G R E E M E N T
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $1FFA and $1FFB.
N O N - D I S C L O S U R E
4.5 External Interrupt (IRQ)
R E Q U I R E D
Interrupts
External Interrupt (IRQ)
4.8 Serial Peripheral Interrupt (SPI)
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF4 and $1FF5.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Interrupts
General Release Specification
40
MC68HC05C4A — Rev. 4.0
Interrupts
MOTOROLA
5.1 Contents
5.2
Introduction ...............................................................................41
5.3
Power-On Reset (POR) ............................................................42
5.4
RESET Pin................................................................................42
5.5
Computer Operating Properly (COP) Reset .............................42
5.5.1
Resetting the COP ..............................................................42
5.5.2
COP During Wait Mode.......................................................43
5.5.3
COP During Stop Mode.......................................................43
5.5.4
COP During Self-Check Mode ............................................43
5.2 Introduction
R E Q U I R E D
Section 5. Resets
A G R E E M E N T
General Release Specification — MC68HC05C4A
N O N - D I S C L O S U R E
The MCU can be reset three ways:
1. Initial power-on reset function
2. Active low input to the RESET pin
3. Computer operating properly (COP) reset
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Resets
41
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Resets
5.3 Power-On Reset (POR)
An internal reset is generated on power-up to allow the internal clock
generator to stabilize. The power-on reset is strictly for power turn-on
conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (tcyc) oscillator
stabilization delay after the oscillator becomes active. If the RESET pin
is low after the end of this 4064-cycle delay, the MCU will remain in the
reset condition until RESET goes high.
For additional information, refer to Figure 13-8. Power-On Reset Timing
Diagram.
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL).
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The
COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP
should time out, a system reset will occur and the device will be
re-initialized in the same fashion as a POR or external reset.
5.5.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This
action will reset the counter and begin the timeout period again. The
COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result
in the user defined ROM data at that location.
General Release Specification
42
MC68HC05C4A — Rev. 4.0
Resets
MOTOROLA
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPC bit to prevent a COP reset.
5.5.3 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an interrupt is
used to exit stop mode, the COP counter will not be reset after the
4064-cycle delay and will have that many cycles already counted when
control is returned to the program.
5.5.4 COP During Self-Check Mode
N O N - D I S C L O S U R E
The COP is disabled by hardware during self-check mode.
A G R E E M E N T
5.5.2 COP During Wait Mode
R E Q U I R E D
Resets
Computer Operating Properly (COP) Reset
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Resets
43
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Resets
General Release Specification
44
MC68HC05C4A — Rev. 4.0
Resets
MOTOROLA
6.1 Contents
6.2
Introduction ...............................................................................45
6.3
Stop Mode ................................................................................46
6.4
Stop Recovery ..........................................................................47
6.5
Wait Mode.................................................................................47
6.2 Introduction
N O N - D I S C L O S U R E
This section describes the two low-power modes — stop and wait.
Figure 6-1 shows the sequence of events caused by the STOP and
WAIT instructions.
R E Q U I R E D
Section 6. Low-Power Modes
A G R E E M E N T
General Release Specification — MC68HC05C4A
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Low-Power Modes
45
R E Q U I R E D
Low-Power Modes
STOP
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
N O N - D I S C L O S U R E
A G R E E M E N T
N
N
EXTERNAL
INTERRUPT
(IRQ)
WAIT
OSCILLATOR ACTIVE
TIMER CLOCK ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT
RESET
RESET
Y
Y
Y
N
EXTERNAL
INTERRUPT
(IRQ)
N
TIMER
INTERRUPT
Y
Y
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
RESTART
PROCESSOR CLOCK
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
N
Y
SCI
INTERRUPT
N
SPI
INTERRUPT
N
Figure 6-1. Stop/Wait Mode Flowchart
6.3 Stop Mode
The STOP instruction places the MCU in its lowest-power consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer
interrupt request and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the condition code register is cleared to
enable external interrupts. All other registers and memory remain
General Release Specification
46
MC68HC05C4A — Rev. 4.0
Low-Power Modes
MOTOROLA
6.4 Stop Recovery
The processor can be brought out of stop mode only by an external
interrupt or reset. See Figure 6-2.
6.5 Wait Mode
The WAIT instruction places the MCU in a low-power consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, SCI, SPI, and the oscillator
remain active. Any interrupt or reset will cause the MCU to exit wait
mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
N O N - D I S C L O S U R E
OSC11
tRL
RESET
tILIH
IRQ2
IRQ3
tILCH
4064 tcyc
INTERNAL CLOCK
INTERNAL ADDRESS BUS
1FFE
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge sensitive option
1FFE
1FFE
1FFE
1FFF
RESET ($1FFE, $1FFF) OR
INTERRUPT ($1FFA, $1FFB)
VECTOR FETCH
Figure 6-2. Stop Recovery Timing Diagram
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Low-Power Modes
A G R E E M E N T
unaltered. All input/output lines remain unchanged. The processor can
be brought out of stop mode only by an external interrupt or reset.
R E Q U I R E D
Low-Power Modes
Stop Recovery
47
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Low-Power Modes
General Release Specification
48
MC68HC05C4A — Rev. 4.0
Low-Power Modes
MOTOROLA
7.2
Introduction ...............................................................................49
7.3
Port A........................................................................................49
7.4
Port B........................................................................................50
7.5
Port C........................................................................................50
7.6
Port D........................................................................................51
7.7
Input/Output Programming .......................................................51
7.2 Introduction
The MC68HC05C4A has three 8-bit input/output (I/O) ports.These 24
port pins are programmable as either inputs or outputs under software
control of the data direction registers. Port D does not have a data
direction register, and its seven pins are input only with the exception of
certain SCI/SPI functions.
NOTE:
To avoid a glitch on the output pins, write data to the I/O port data
register before writing a 1 to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the
ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit
to output mode.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Input/Output (I/O) Ports
49
R E Q U I R E D
7.1 Contents
A G R E E M E N T
Section 7. Input/Output (I/O) Ports
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001,
and the data direction register (DDR) is at $0005. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode. Each of the port B pins has a
mask programmable interrupt capability. This interrupt option also
enables a pullup device when the pin is configured as an input (see
Figure 7-1). The edge or edge and level sensitivity of the IRQ pin also
will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an
output to an input, the data should be preconditioned to a 1 to prevent
an interrupt from occurring.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
VDD
VDD
MASK OPTION
DDR BIT
IRQ
SCHMITT
TRIGGER
PB0
NORMAL PORT CIRCUITRY
AS SHOWN IN
FIGURE 7-2.
TO
INTERRUPT
LOGIC
FROM ALL OTHER PORT B PINS
Figure 7-1. Port B Pullup Option
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. PC7 has a high current sink and
source capability.
General Release Specification
50
MC68HC05C4A — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
7.6 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI
subsystem, and two more are shared with the SCI subsystem. Reset
does not affect the data registers. During reset, all seven bits become
valid input ports because all special function output drivers associated
with the SCI, timer, and SPI subsystems are disabled.
R E Q U I R E D
Input/Output (I/O) Ports
Port D
At power-on or reset, all DDRs are cleared, which configures all I/O pins
as inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin. For further information, refer to Table 7-1 and Figure 7-2.
Table 7-1. I/O Pin Functions
R/W*
DDR
I/O Pin Function
0
0
The I/O pin is in input mode. Data is written into the
output data latch.
0
1
Data is written into the output data latch and output to
the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is
read.
*R/W is an internal signal.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Input/Output (I/O) Ports
51
N O N - D I S C L O S U R E
I/O port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
A G R E E M E N T
7.7 Input/Output Programming
R E Q U I R E D
Input/Output (I/O) Ports
READ DDRx
INTERNAL DATA BUS
WRITE DDRx
RESET
WRITE PORTx
DATA DIRECTION
REGISTER x BIT
PORT x DATA
REGISTER BIT
(LATCHED OUTPUT)
[1]
[3]
READ PORTx
A G R E E M E N T
I/O
PIN
[2]
[1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode).
[2] This input buffer is enabled when DDR bit is 0 (input mode).
[3] This input buffer is enabled when DDR bit is 1 (output mode).
N O N - D I S C L O S U R E
Figure 7-2. I/O Circuitry
General Release Specification
52
MC68HC05C4A — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
8.2
Introduction ...............................................................................53
8.3
Counter .....................................................................................55
8.4
Output Compare Register.........................................................56
8.5
Input Capture Register..............................................................57
8.6
Timer Control Register..............................................................58
8.7
Timer Status Register ...............................................................60
8.8
Timer During Wait Mode...........................................................61
8.9
Timer During Stop Mode...........................................................61
8.2 Introduction
The timer consists of a 16-bit, software-programmable counter driven by
a fixed divide-by-four prescaler. This timer can be used for many
purposes, including input waveform measurements while
simultaneously generating an output waveform. Pulse widths can vary
from several microseconds to many seconds. Refer to Figure 8-1 for a
timer block diagram.
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
NOTE:
The I bit in the condition code register should be set while manipulating
both the high and low byte register of a specific timer function to ensure
that an interrupt does not occur.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Timer
53
R E Q U I R E D
8.1 Contents
A G R E E M E N T
Section 8. Timer
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
Timer
INTERNAL BUS
HIGH
BYTE
INTERNAL
PROCESSOR
CLOCK
LOW
BYTE
8-BIT
BUFFER
÷4
A G R E E M E N T
$16
$17
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
HIGH
BYTE
OUTPUT
COMPARE
CIRCUIT
LOW
BYTE
LOW
BYTE
16-BIT FREE
RUNNING
COUNTER
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
INPUT
CAPTURE
REGISTER
$14
$15
EDGE
DETECT
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
Q
D
N O N - D I S C L O S U R E
CLK
TIMER ICF OCF
STATUS
REGISTER
TOF
OUTPUT
LEVEL
REGISTER
$13
ICIE
OCIE
TOIE
IEDG OLVL
TIMER
CONTROL
REGISTER
$12
C
RESET
OUTPUT
LEVEL
(TCMP)
INTERRUPT
CIRCUIT
EDGE
INPUT
(TCAP)
Figure 8-1. Timer Block Diagram
General Release Specification
54
MC68HC05C4A — Rev. 4.0
Timer
MOTOROLA
The double-byte, free-running counter can be read from either of two
locations, $18, $19 (counter register) or $1A, $1B (counter alternate
register). A read from only the least significant byte (LSB) of the freerunning counter ($19, $1B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB also must be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is
always a read-only register. During a power-on reset, the counter also is
preset to $FFFC and begins running after the oscillator startup delay.
Because the free-running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free-running counter repeats every
262,144 internal bus clock cycles. When the counter rolls over from
$FFFF to $0000, the TOF bit is set. An interrupt also can be enabled
whenever counter rollover occurs by setting its interrupt enable bit
(TOIE).
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Timer
55
A G R E E M E N T
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
N O N - D I S C L O S U R E
8.3 Counter
R E Q U I R E D
Timer
Counter
8.4 Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
The output compare register contents are compared with the contents of
the free-running counter continually, and if a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt also can accompany a successful output
compare, provided the corresponding interrupt enable bit (OCIE) is set.
A G R E E M E N T
R E Q U I R E D
Timer
N O N - D I S C L O S U R E
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is written also. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear. Figure 8-2 shows the logic of the output compare
function.
General Release Specification
56
MC68HC05C4A — Rev. 4.0
Timer
MOTOROLA
0
COUNTER LOW BYTE
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
15
8 7
TCMP
0
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
TOF
ICF
OCF
TOIE
ICIE
OCIE
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
$0012
$0013
Figure 8-2. Output Compare Operation
8.5 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register except when exiting stop
mode.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Timer
57
A G R E E M E N T
COUNTER HIGH BYTE
N O N - D I S C L O S U R E
15
R E Q U I R E D
Timer
Input Capture Register
R E Q U I R E D
Timer
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the freerunning counter transfer, since they occur on opposite edges of the
internal bus clock. Figure 8-3 shows the logic of the input capture
function.
A G R E E M E N T
N O N - D I S C L O S U R E
$0018
15
$0019
8 7
TIMER REGISTER HIGH
EDGE
SELECT/DETECT
LOGIC
TCMP
LATCH
15
0
TIMER REGISTER LOW
8 7
INPUT CAPTURE REGISTER HIGH
$0014
0
INPUT CAPTURE REGISTER LOW
$0015
OCF
TOF
ICF
ICIE
OCIE
TOIE
TIMER
INTERRUPT
REQUEST
TIMER STATUS REGISTER
$0012
$0013
IEDG
TIMER CONTROL REGISTER
Figure 8-3. Input Capture Operation
8.6 Timer Control Register
The TCR is a read/write register containing five control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
Address:
$12
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
Read:
Write:
Reset:
U = Unaffected
Figure 8-4. Timer Control Register (TCR)
General Release Specification
58
MC68HC05C4A — Rev. 4.0
Timer
MOTOROLA
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Timer
59
N O N - D I S C L O S U R E
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
A G R E E M E N T
R E Q U I R E D
Timer
Timer Control Register
8.7 Timer Status Register
The TSR is a read-only register containing three status flag bits.
Address:
$13
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Read:
Write:
A G R E E M E N T
R E Q U I R E D
Timer
Reset:
U = Unaffected
Figure 8-5. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
N O N - D I S C L O S U R E
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the freerunning counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
General Release Specification
60
MC68HC05C4A — Rev. 4.0
Timer
MOTOROLA
1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose
of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
8.8 Timer During Wait Mode
The CPU clock halts during wait mode, the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
the wait mode.
A G R E E M E N T
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
R E Q U I R E D
Timer
Timer During Wait Mode
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If reset is used, the counter is forced to
$FFFC. During stop, if at least one valid input capture edge occurs at the
TCAP pin, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU. But if the MCU exits stop due to an
external interrupt, there is an active input capture flag and data from the
first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid
input capture edge occurred.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Timer
61
N O N - D I S C L O S U R E
8.9 Timer During Stop Mode
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Timer
General Release Specification
62
MC68HC05C4A — Rev. 4.0
Timer
MOTOROLA
9.2
Introduction ...............................................................................63
9.3
Features....................................................................................64
9.4
SCI Data Format.......................................................................64
9.5
SCI Operation ...........................................................................65
9.5.1
Transmitter ..........................................................................65
9.5.1.1
Character Length .............................................................65
9.5.1.2
Character Transmission ...................................................65
9.5.1.3
Break Characters .............................................................67
9.5.1.4
Idle Characters.................................................................67
9.5.1.5
Transmitter Interrupts.......................................................67
9.5.2
Receiver ..............................................................................68
9.5.2.1
Character Length .............................................................69
9.5.2.2
Character Reception ........................................................69
9.5.2.3
Receiver Wakeup.............................................................69
9.5.2.4
Receiver Noise Immunity .................................................70
9.5.2.5
Framing Errors .................................................................70
9.5.2.6
Receiver Interrupts...........................................................70
9.6
SCI I/O Registers......................................................................71
9.6.1
SCI Data Register ...............................................................71
9.6.2
SCI Control Register 1 ........................................................72
9.6.3
SCI Control Register 2 ........................................................74
9.6.4
SCI Status Register.............................................................76
9.6.5
Baud Rate Register .............................................................78
9.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other MCUs.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Communications Interface (SCI)
63
R E Q U I R E D
9.1 Contents
A G R E E M E N T
Section 9. Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
9.3 Features
Features of the SCI module include:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Standard Mark/Space Non-Return-to-Zero Format
•
Full-Duplex Operation
•
32 Programmable Baud Rates
•
Programmable 8-Bit or 9-Bit Character Length
•
Separately Enabled Transmitter and Receiver
•
Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
•
Interrupt-Driven Operation Capability with Five Interrupt Flags:
– Transmitter Data Register Empty
– Transmission Complete
– Receiver Data Register Full
– Receiver Overrun
– Idle Receiver Input
•
Receiver Framing Error Detection
•
1/16 Bit-Time Noise Detection
9.4 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 9-1.
8-BIT DATA FORMAT
BIT M IN SCCR1 CLEAR
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
NEXT
START
BIT
9-BIT DATA FORMAT
BIT M IN SCCR1 SET
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 9-1. SCI Data Format
General Release Specification
64
MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
9.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. The following
paragraphs describe the operation of the SCI transmitter and receiver.
R E Q U I R E D
Serial Communications Interface (SCI)
SCI Operation
9.5.1.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCCR1) determines character length.
When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit (bit 8).
9.5.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to
the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then
writing data to the SCDR begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Communications Interface (SCI)
65
N O N - D I S C L O S U R E
Figure 9-2 shows the structure of the SCI transmitter.
A G R E E M E N T
9.5.1 Transmitter
R E Q U I R E D
Serial Communications Interface (SCI)
When the shift register is not transmitting a character, the PD1/TDO pin
goes to the idle condition, logic 1. If software clears the TE bit during the
idle condition, and while TDRE is set, the transmitter relinquishes control
of the PD1/TDO pin.
INTERNAL DATA BUS
A G R E E M E N T
SCDR ($0011)
TRANSMIT SHIFT REGISTER
1X
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
H 8 7 6 5 4 3 2 1 0 L
PD1/
TDO
N O N - D I S C L O S U R E
BREAK (ALL LOGIC 0s)
PREAMBLE (ALL LOGIC 1s)
SHIFT ENABLE
T8
LOAD FROM SCDR
M
SBK
TRANSMITTER
CONTROL LOGIC
TE
TDRE
TIE
TC
TCIE
SCI
INTERRUPT
REQUEST
SCI
RECEIVE
REQUESTS
BIT 7
BAUD RATE REGISTER (BAUD)
0
SCI CONTROL REGISTER 1 (SCCR1)
R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
0
T8
TCIE
TC
BIT 6
5
SCP1
0
RIE
RDRF
BIT 5
4
SCP0
M
ILIE
IDLR
BIT 4
3
0
WAKE
TE
OR
BIT 3
2
SCR2
0
RE
NF
BIT 2
1
SCR1
0
RWU
FE
BIT 1
BIT 0
SCR0
0
SBK
0
BIT 0
$000D
$000E
$000F
$0010
$0011
Figure 9-2. SCI Transmitter
General Release Specification
66
MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
9.5.1.4 Idle Characters
An idle character contains all logic 1s and has no start or stop bits. Idle
character length depends on the M bit in SCCR1. The preamble is a
synchronizing idle character that begins every transmission.
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin
after the last character to be transmitted is shifted out. The last character
may already be in the shift register, or waiting in the SCDR, or in a break
character generated by writing to the SBK bit. Toggling TE from logic 0
to logic 1 while the last character is in transmission generates an idle
character (a preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
9.5.1.5 Transmitter Interrupts
Two sources can generate SCI transmitter interrupt requests:
1. Transmit Data Register Empty (TDRE) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to the
transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TDRE interrupts.
2. Transmission Complete (TC) — The TC bit in the SCSR indicates
that both the transmit shift register and the SCDR are empty and
that no break or idle character has been generated. TC is a source
of SCI interrupt requests. The transmission complete interrupt
enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Communications Interface (SCI)
67
A G R E E M E N T
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
break character. A break character contains all logic 0s and has no start
and stop bits. Break character length depends on the M bit in SCCR1.
As long as SBK is at logic 1, transmitter logic continuously loads break
characters into the shift register. After software clears the SBK bit, the
shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break
character is to guarantee the recognition of the start bit of the next
character.
N O N - D I S C L O S U R E
9.5.1.3 Break Characters
R E Q U I R E D
Serial Communications Interface (SCI)
SCI Operation
9.5.2 Receiver
Figure 9-3 shows the structure of the SCI receiver.
INTERNAL DATA BUS
SCDR ($0011)
STOP
DATA
RECOVERY
MSB
NF
IDLE
8 7 6 5 4 3 2 1 0
OVERRUN
PIN BUFFER
AND CONTROL
FULL
PD0/
RDI
÷16
START
RECEIVE SHIFT REGISTER
16X
BAUD RATE
CLOCK
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
FE
R8
RE
M
RDRF
N O N - D I S C L O S U R E
SCI
INTERRUPT
REQUEST
RIE
OR
SCI
TRANSMIT
REQUESTS
RIE
IDLE
ILIE
WAKEUP
LOGIC
RWU
BIT 7
0
BAUD RATE REGISTER (BAUD)
R8
SCI CONTROL REGISTER 1 (SCCR1)
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
0
T8
TCIE
TC
BIT 6
5
SCP1
0
RIE
RDRF
BIT 5
4
SCP0
M
ILIE
IDLR
BIT 4
3
0
WAKE
TE
OR
BIT 3
2
SCR2
0
RE
NF
BIT 2
1
SCR1
0
RWU
FE
BIT 1
BIT 0
SCR0
0
SBK
0
BIT 0
$000D
$000E
$000F
$0010
$0011
Figure 9-3. SCI Receiver
General Release Specification
68
MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
9.5.2.2 Character Reception
During reception, the receive shift register shifts characters in from the
PD0/RDI pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character is transferred to the SCDR, setting the receive
data register full (RDRF) flag. The RDRF flag can be used to generate
an interrupt.
9.5.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup enable (RWU) bit in SCI
control register 2 (SCCR2) puts the receiver into a standby state during
which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of
the standby state:
1. Idle input line condition — If the PD0/RDI pin is at logic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift register,
receiver interrupts are again enabled.
2. Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Communications Interface (SCI)
69
A G R E E M E N T
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCCR1) determines character length.
When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit
(bit 8).
N O N - D I S C L O S U R E
9.5.2.1 Character Length
R E Q U I R E D
Serial Communications Interface (SCI)
SCI Operation
R E Q U I R E D
9.5.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
9.5.2.5 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.5.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1. Receive Data Register Full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character
to the SCDR.
2. Receiver Overrun (OR) — The OR bit in the SCSR indicates that
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
N O N - D I S C L O S U R E
A G R E E M E N T
Serial Communications Interface (SCI)
3. Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
11 consecutive logic 1s shifted in from the PD0/RDI pin.
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
SCI I/O Registers
9.6 SCI I/O Registers
•
SCI data register (SCDR)
•
SCI control register 1 (SCCR1)
•
SCI control register 2 (SCCR2)
•
SCI status register (SCSR)
A G R E E M E N T
These I/O registers control and monitor SCI operation:
9.6.1 SCI Data Register
The SCI data register is the buffer for characters received and for
characters transmitted.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read:
Write:
Reset:
Unaffected by Reset
MC68HC05C4A — Rev. 4.0
MOTOROLA
N O N - D I S C L O S U R E
Figure 9-4. SCI Data Register (SCDR)
General Release Specification
Serial Communications Interface (SCI)
71
9.6.2 SCI Control Register 1
SCI control register 1 has these functions:
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Stores ninth SCI data bit received and ninth SCI data bit
transmitted
•
Controls SCI character length
•
Controls SCI wakeup method
Address:
$000E
Bit 7
Read:
6
5
4
3
2
1
Bit 0
T8
0
M
WAKE
0
0
0
R8
Write:
Reset:
Unaffected by Reset
= Unimplemented
Figure 9-5. SCI Control Register (SCCR1)
R8 — Bit 8 (Received)
N O N - D I S C L O S U R E
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit from the receive shift
register at the same time that the SCDR receives the other eight bits.
Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T8 bit.
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
This read/write bit determines whether SCI characters are 8 bits long
or 9 bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Bit
N O N - D I S C L O S U R E
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the MSB position of a received character or
an idle condition of the PD0/RDI pin. Reset has no effect on the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
A G R E E M E N T
M — Character Length
R E Q U I R E D
Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C4A — Rev. 4.0
MOTOROLA
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Serial Communications Interface (SCI)
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9.6.3 SCI Control Register 2
SCI control register 2 has these functions:
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Enables the SCI receiver and SCI receiver interrupts
•
Enables the SCI transmitter and SCI transmitter interrupts
•
Enables SCI receiver idle interrupts
•
Enables SCI transmission complete interrupts
•
Enables SCI wakeup
•
Transmits SCI break characters
Address:
$000F
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read:
Write:
Reset:
Unaffected by Reset
Figure 9-6. SCI Control Register 2 (SCCR2)
N O N - D I S C L O S U R E
TIE — Transmit Interrupt Enable
This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable
This read/write bit enables SCI interrupt requests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
TE — Transmit Enable
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Communications Interface (SCI)
75
A G R E E M E N T
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
N O N - D I S C L O S U R E
ILIE — Idle Line Interrupt Enable
R E Q U I R E D
Serial Communications Interface (SCI)
SCI I/O Registers
9.6.4 SCI Status Register
The SCI status register contains flags to signal the following conditions:
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing Error
Address:
Read:
$0010
Bit 7
6
5
4
3
2
1
TDRE
TC
RDRF
IDLE
OR
NF
FE
Bit 0
0
Write:
Reset:
Unaffected by Reset
= Unimplemented
N O N - D I S C L O S U R E
Figure 9-7. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set, and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
MC68HC05C4A — Rev. 4.0
MOTOROLA
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Serial Communications Interface (SCI)
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A G R E E M E N T
RDRF — Receive Data Register Full
N O N - D I S C L O S U R E
bit by reading the SCSR with TC set, and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
R E Q U I R E D
Serial Communications Interface (SCI)
SCI I/O Registers
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR, and then reading the SCDR. Reset clears
the FE bit.
1 = Framing error
0 = No framing error
9.6.5 Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the
transmitter.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Address:
$000D
Bit 7
6
5
4
3
2
1
Bit 0
0
0
SCP1
SCP0
0
SCR2
SCR1
SCR0
0
0
0
0
0
U
U
U
Read:
Write:
Reset:
U = Unaffected
Figure 9-8. Baud Rate Register (BAUD)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Resets clear both SCP1 and SCP0.
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Serial Communications Interface (SCI)
MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
SCI I/O Registers
SCP0–SCP1
Baud Rate Generator Clock
00
Internal Clock Divided by 1
01
Internal Clock Divided by 3
10
Internal Clock Divided by 4
11
Internal Clock Divided by 13
A G R E E M E N T
Table 9-1. Baud Rate Generator Clock Prescaling
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 9-2. Reset has no effect on the SCR2–SCR0 bits.
SCR2–SCR0
SCI Baud Rate (Baud)
000
Prescaled Clock Divided by 1
001
Prescaled Clock Divided by 2
010
Prescaled Clock Divided by 4
011
Prescaled Clock Divided by 8
100
Prescaled Clock Divided by 16
101
Prescaled Clock Divided by 32
110
Prescaled Clock Divided by 64
111
Prescaled Clock Divided by 128
N O N - D I S C L O S U R E
Table 9-2. Baud Rate Selection
Table 9-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
MC68HC05C4A — Rev. 4.0
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Serial Communications Interface (SCI)
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R E Q U I R E D
Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
A G R E E M E N T
Table 9-3. Baud Rate Selection Examples
SCP1–SCP0
SCR2–SCR0
00
SCI Baud Rate
fOSC = 2 MHz
fOSC = 4 MHz
fOSC = 4.194304 MHz
000
62.50 kBaud
125 kBaud
131.1 kBaud
00
001
31.25 kBaud
62.50 kBaud
65.54 kBaud
00
010
15.63 kBaud
31.25 kBaud
32.77 kBaud
00
011
7813 Baud
15.63 kBaud
16.38 kBaud
00
100
3906 Baud
7813 Baud
8192 Baud
00
101
1953 Baud
3906 Baud
4096 Baud
00
110
976.6 Baud
1953 Baud
2048 Baud
00
111
488.3 Baud
976.6 Baud
1024 Baud
01
000
20.83 kBaud
41.67 kBaud
43.69 kBaud
01
001
10.42 kBaud
20.83 kBaud
21.85 kBaud
01
010
5208 Baud
10.42 kBaud
10.92 kBaud
01
011
2604 Baud
5208 Baud
5461 Baud
01
100
1302 Baud
2604 Baud
2731 Baud
01
101
651.0 Baud
1302 Baud
1365 Baud
01
110
325.5 Baud
651.0 Baud
682.7 Baud
01
111
162.8 Baud
325.5 Baud
341.3 Baud
10
000
15.63 kBaud
31.25 kBaud
32.77 kBaud
10
001
7813 Baud
15.63 kBaud
16.38 kBaud
10
010
3906 Baud
7813 Baud
8192 Baud
10
011
1953 Baud
3906 Baud
4906 Baud
10
100
976.6 Baud
1953 Baud
2048 Baud
10
101
488.3 Baud
976.6 Baud
1024 Baud
10
110
244.1 Baud
488.3 Baud
512.0 Baud
10
111
122.1 Baud
244.1 Baud
256.0 Baud
11
000
4808 Baud
9615 Baud
10.08 kBaud
11
001
2404 Baud
4808 Baud
5041 Baud
11
010
1202 Baud
2404 Baud
2521 Baud
11
011
601.0 Baud
1202 Baud
1260 Baud
11
100
300.5 Baud
601.0 Baud
630.2 Baud
11
101
150.2 Baud
300.5 Baud
315.1 Baud
11
110
75.12 Baud
150.2 Baud
157.5 Baud
11
111
37.56 Baud
75.12 Baud
78.77 Baud
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MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
10.2
Introduction ...............................................................................81
10.3
Features....................................................................................82
10.4 SPI Signal Description ..............................................................82
10.4.1
Master In Slave Out (MISO) ................................................82
10.4.2
Master Out Slave In (MOSI) ................................................82
10.4.3
Serial Clock (SCK) ..............................................................83
10.4.4
Slave Select (SS) ................................................................84
10.5
Functional Description ..............................................................84
10.6 SPI Registers............................................................................86
10.6.1
Serial Peripheral Control Register.......................................87
10.6.2
Serial Peripheral Status Register ........................................88
10.6.3
Serial Peripheral Data I/O Register .....................................90
10.2 Introduction
The serial peripheral interface (SPI) is an interface built into the
MC68HC05 MCU which allows several MC68HC05 MCUs or
MC68HC05 MCU plus peripheral devices to be interconnected within a
single printed circuit board. In an SPI, separate wires are required for
data and clock. In the SPI format, the clock is not included in the data
stream and must be furnished as a separate signal. An SPI system may
be configured in a system containing one master MCU and several slave
MCUs or in a system in which an MCU is capable of being a master or a
slave.
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Serial Peripheral Interface (SPI)
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R E Q U I R E D
10.1 Contents
A G R E E M E N T
Section 10. Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Serial Peripheral Interface (SPI)
10.3 Features
•
Full-Duplex, 4-Wire Synchronous Transfers
•
Master or Slave Operation
•
Bus Frequency Divided by 2 (Maximum) Master Bit Frequency
•
Bus Frequency (Maximum) Slave Bit Frequency
•
Four Programmable Master Bit Rates
•
Programmable Clock Polarity and Phase
•
End of Transmission Interrupt Flag
•
Write Collision Flag Protection
•
Master-Master Mode Fault Protection Capability
10.4 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described in the
following paragraphs. Each signal function is described for both the
master mode and slave mode.
10.4.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit (MSB) sent first.
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Serial Peripheral Interface (SPI)
MOTOROLA
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line one-half cycle before the clock edge (SCK), so the slave
device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI
operation.
SS
A G R E E M E N T
10.4.3 Serial Clock (SCK)
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Signal Description
N O N - D I S C L O S U R E
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
MC68HC05C4A — Rev. 4.0
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Serial Peripheral Interface (SPI)
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R E Q U I R E D
10.4.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.
The SS line on the master must be tied high. If it goes low, a mode fault
error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to VSS as long as CPHA = 1 clock modes are used.
10.5 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full-duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
N O N - D I S C L O S U R E
A G R E E M E N T
Serial Peripheral Interface (SPI)
The SPI data register (SPDR) is double buffered on read, but not on
write. If a write is performed during data transfer, the transfer occurs
uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After
a data byte is shifted, the SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
S
M
INTERNAL
MCU CLOCK
MSB
LSB
MISO
PD2
M
S
8-BIT SHIFT REG
R E Q U I R E D
Serial Peripheral Interface (SPI)
Functional Description
MOSI
PD3
DIVIDER
÷4
÷16
÷32
SELECT
S
CLOCK
LOGIC
M
SPR0
SPR1
CLOCK
SPI CLOCK
(MASTER)
SCK
PD4
A G R E E M E N T
÷2
PIN CONTROL LOGIC
READ DATA BUFF
SS
PD5
MSTR
SPR0
SPR1
CPOL
CPHA
MSTR
SPE
SPIE
SPE
MODF
SPI CONTROL REGISTER
SPI STATUS REGISTER
N O N - D I S C L O S U R E
WCOL
SPIF
SPI CONTROL
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C4A — Rev. 4.0
MOTOROLA
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Serial Peripheral Interface (SPI)
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R E Q U I R E D
Serial Peripheral Interface (SPI)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
N O N - D I S C L O S U R E
A G R E E M E N T
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
I/O PORT
PD5
SS
SPDR ($000C)
SPDR ($000C)
PD4/SCK
SLAVE MCU
MASTER MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.6 SPI Registers
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
10.6.1 Serial Peripheral Control Register
$000A
Bit 7
6
SPID
SPD
0
0
5
4
3
2
1
Bit 0
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
U
0
Read:
Write:
Reset:
0
= Unimplemented
U = Unaffected
A G R E E M E N T
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
MC68HC05C4A — Rev. 4.0
MOTOROLA
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Serial Peripheral Interface (SPI)
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N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Registers
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Selects
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
See Table 10-1.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
0
0
2
0
1
4
1
0
16
1
1
32
10.6.2 Serial Peripheral Status Register
Address:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
$000B
Bit 7
6
SPIF
WCOL
0
0
Read:
5
4
0
3
2
1
Bit 0
0
0
0
0
0
0
U
0
MODF
Write:
Reset:
0
= Unimplemented
0
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
General Release Specification
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MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
Bit 5 — Not implemented
This bit always reads 0.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low.
Setting the MODF bit affects the internal serial peripheral interface
system in the following ways:
• An SPI interrupt is generated if SPIE = 1.
• The SPE bit is cleared. This disables the SPI.
• The MSTR bit is cleared, thus forcing the device into the slave
mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always read 0.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Serial Peripheral Interface (SPI)
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A G R E E M E N T
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is 0, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is 1, a transfer is said to begin the first time SCK
becomes active while SS is low. The transfer ends when the SPIF flag
gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
N O N - D I S C L O S U R E
WCOL — Write Collision
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Registers
10.6.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register is used to transmit and receive
data on the serial bus. Only a write to this register will initiate
transmission/reception of another byte, and this will occur only in the
master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
General Release Specification
90
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
11.2
Introduction ...............................................................................91
11.3
User Mode ................................................................................91
11.4 Self-Check Mode ......................................................................92
11.4.1
Self-Check Tests .................................................................92
11.4.2
Self-Check Results..............................................................93
11.2 Introduction
The MCU has two modes of operation: user mode and self-check mode.
Table 11-1 shows the conditions required to enter into each mode,
where VTST = 2 x VDD.
Table 11-1. Operating Mode Conditions
RESET
IRQ
TCAP
Mode
VSS to VDD
VSS to VDD
User
VTST
VDD
Self-Check
11.3 User Mode
In user mode, the address and data buses are not available externally,
but there are three 8-bit input/output (I/O) ports and one 7-bit input-only
port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU. User
mode is entered on the rising edge of RESET if the IRQ pin is within
normal operating range.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Operating Modes
91
R E Q U I R E D
11.1 Contents
A G R E E M E N T
Section 11. Operating Modes
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Operating Modes
RESET
1
40
VDD
IRQ
2
39
OSC1
NC
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
PA5
6
35
PD6/TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
Figure 11-1. User Mode Pinout
11.4 Self-Check Mode
Self-check mode is entered upon the rising edge of RESET if the IRQ pin
is at VTST and the TCAP pin is at logic 1.
11.4.1 Self-Check Tests
The self-check ROM at mask ROM location $1F00–$1FEF determines
if the MCU is functioning properly. These five tests are performed:
1. I/O — Functional test of ports A, B, and C
2. RAM — Counter test for each RAM byte
3. Timer — Test of counter register and OCF bit
4. SCI — Transmission test checks for RDRF, TDRE, TC, and FE
flags
General Release Specification
92
MC68HC05C4A — Rev. 4.0
Operating Modes
MOTOROLA
R E Q U I R E D
Operating Modes
Self-Check Mode
5. ROM — Exclusive OR with odd ones parity result
6. SPI — Transmission test checks for SPIF and WCOL flags
The self-check circuit is shown in Figure 11-2.
11.4.2 Self-Check Results
Table 11-2 shows the LED codes that indicate self-check test results.
PC2
PC1
PC0
Remarks
Off
On
On
Off
I/O Failure
Off
On
Off
On
RAM Failure
Off
On
Off
Off
Timer Failure
Off
Off
On
On
SCI Failure
Off
Off
On
Off
ROM Failure
Off
Off
Off
On
SPI Failure
Flashing
No Failure
All Others
Device Failure
Perform these three steps to activate the self-check tests:
1. Apply 10 V (2 x VDD) to the IRQ pin.
2. Apply a logic 1 to the TCAP pin.
3. Apply a logic 0 to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR) or
for a time, tRL, for any other reset. (For the tRL value, see 13.9 5.0 V
Control Timing.)
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Operating Modes
93
N O N - D I S C L O S U R E
PC3
A G R E E M E N T
Table 11-2. Self-Check Circuit LED Codes
R E Q U I R E D
Operating Modes
VDD
VDD
10 V
40
VDD
IRQ
2
39
OSC1
NC
3
38
OSC2
PA7
4
37
TCAP
36
PD7
5
PA5
6
35
TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
VDD
10 MΩ
10 kΩ
20 pF
20 pF
1 MΩ
CMOS
BUFFER
(MC74HC125)
330 Ω
PA6
4 MHZ
330 Ω
A G R E E M E N T
1
330 Ω
RESET
4.7 kΩ
N O N - D I S C L O S U R E
VDD
MC68H05C4A
330 Ω
MC34064
VDD
NOTES:
1. VDD = 5.0 V
2. TCMP = NC
Figure 11-2. Self-Check Circuit Schematic
General Release Specification
94
MC68HC05C4A — Rev. 4.0
Operating Modes
MOTOROLA
Section 12. Instruction Set
12.1 Contents
12.3 Addressing Modes ....................................................................96
12.3.1
Inherent ...............................................................................97
12.3.2
Immediate............................................................................97
12.3.3
Direct ...................................................................................97
12.3.4
Extended .............................................................................97
12.3.5
Indexed, No Offset ..............................................................98
12.3.6
Indexed, 8-Bit Offset............................................................98
12.3.7
Indexed,16-Bit Offset...........................................................98
12.3.8
Relative ...............................................................................99
12.4 Instruction Types ......................................................................99
12.4.1
Register/Memory Instructions............................................100
12.4.2
Read-Modify-Write Instructions .........................................101
12.4.3
Jump/Branch Instructions..................................................102
12.4.4
Bit Manipulation Instructions .............................................104
12.4.5
Control Instructions ...........................................................105
12.5
Instruction Set Summary ........................................................106
12.6
Opcode Map ...........................................................................111
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Instruction Set
95
A G R E E M E N T
Introduction ...............................................................................96
N O N - D I S C L O S U R E
12.2
R E Q U I R E D
General Release Specification — MC68HC05C4A
R E Q U I R E D
12.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
N O N - D I S C L O S U R E
A G R E E M E N T
Instruction Set
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
General Release Specification
96
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
R E Q U I R E D
Instruction Set
Addressing Modes
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Instruction Set
97
N O N - D I S C L O S U R E
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
A G R E E M E N T
12.3.2 Immediate
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Instruction Set
12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
General Release Specification
98
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
12.4 Instruction Types
•
Register/Memory instructions
•
Read-Modify-Write instructions
•
Jump/Branch instructions
•
Bit manipulation instructions
•
Control instructions
MC68HC05C4A — Rev. 4.0
MOTOROLA
N O N - D I S C L O S U R E
The MCU instructions fall into the following five categories:
General Release Specification
Instruction Set
A G R E E M E N T
12.3.8 Relative
R E Q U I R E D
Instruction Set
Instruction Types
99
12.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Instruction Set
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
General Release Specification
100
Mnemonic
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
12.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
A G R E E M E N T
Mnemonic
N O N - D I S C L O S U R E
Instruction
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Instruction Set
R E Q U I R E D
Instruction Set
Instruction Types
101
12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Instruction Set
General Release Specification
102
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
R E Q U I R E D
Instruction Set
Instruction Types
Table 12-3. Jump and Branch Instructions
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
MC68HC05C4A — Rev. 4.0
A G R E E M E N T
Branch if Carry Bit Clear
Branch if Bit Clear
MOTOROLA
Mnemonic
N O N - D I S C L O S U R E
Instruction
General Release Specification
Instruction Set
103
12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
A G R E E M E N T
R E Q U I R E D
Instruction Set
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
BSET
N O N - D I S C L O S U R E
Bit Set
General Release Specification
104
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
R E Q U I R E D
Instruction Set
Instruction Types
12.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
MC68HC05C4A — Rev. 4.0
A G R E E M E N T
Clear Carry Bit
Stop Oscillator and Enable IRQ Pin
MOTOROLA
Mnemonic
N O N - D I S C L O S U R E
Instruction
General Release Specification
Instruction Set
105
12.5 Instruction Set Summary
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
C
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
↕
↕
— — ↕
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ —
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
↕ —
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Operation
Opcode
Source
Form
Operand
Table 12-6. Instruction Set Summary
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Instruction Set
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
General Release Specification
106
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
Branch if Higher or Same
BIH rel
BIL rel
REL
22
rr
3
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
Set Bit n
MC68HC05C4A — Rev. 4.0
MOTOROLA
REL
General Release Specification
Instruction Set
107
A G R E E M E N T
BHS rel
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
Description
Effect on
CCR
N O N - D I S C L O S U R E
Branch if Higher
Cycles
BHI rel
H I N Z C
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
H I N Z C
Cycles
Operation
Operand
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Instruction Set
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect on
CCR
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
— — 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
EXCLUSIVE OR Accumulator with Memory Byte
Increment Byte
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
General Release Specification
108
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
↕
dd
ff
dd
ff
dd
ff
dd
ff
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
0 — — — 0
INH
42
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
— — — — —
INH
9D
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
Logical OR Accumulator with Memory
↕
— — 0 ↕
↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
MC68HC05C4A — Rev. 4.0
— — ↕
b0
↕
↕
↕ —
ff
ff
Cycles
— — — — —
DIR
EXT
IX2
IX1
IX
— — ↕
C
b7
Logical Shift Right
MOTOROLA
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Description
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
General Release Specification
Instruction Set
109
A G R E E M E N T
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
— — — — —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
N O N - D I S C L O S U R E
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Opcode
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Effect on
CCR
Description
H I N Z C
Rotate Byte Left through Carry Bit
C
— — ↕
b7
↕
↕
b0
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Instruction Set
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
INH
80
9
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
ff
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
Store Index Register In Memory
Subtract Memory Byte from Accumulator
A ← (A) – (M)
General Release Specification
110
— — ↕
↕
↕
2
MC68HC05C4A — Rev. 4.0
Instruction Set
MOTOROLA
10
TAX
Transfer Accumulator to Index Register
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
Stop CPU Clock and Enable Interrupts
X ← (A)
— — — — —
INH
97
2
— — ↕
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
(M) – $00
A ← (X)
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
dd
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
12.6 Opcode Map
See Table 12-7.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Instruction Set
A G R E E M E N T
83
N O N - D I S C L O S U R E
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Cycles
INH
Effect on
CCR
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Description
Opcode
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Opcode Map
111
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Bit Manipulation
DIR
DIR
MSB
LSB
0
1
2
3
4
5
6
Instruction Set
7
8
9
A
B
C
D
MOTOROLA
MC68HC05C4A — Rev. 4.0
E
F
0
1
Branch
REL
DIR
2
3
Read-Modify-Write
INH
INH
IX1
4
5
6
IX
7
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
DIR 2
REL
1
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
5
3
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
Control
INH
INH
8
9
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
STOP
INH
2
2
WAIT
TXA
INH 1
INH
IMM
DIR
A
B
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
LSB of Opcode in Hexadecimal
0
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
0
C
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
D
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1
IX
E
F
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
MSB
LSB
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
IX
4
STX
IX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Instruction Set
General Release Specification
112
Table 12-7. Opcode Map
13.1 Contents
13.2
Introduction .............................................................................113
13.3
Maximum Ratings ...................................................................114
13.4
Operating Temperature Range...............................................115
13.5
Thermal Characteristics..........................................................115
13.6
Power Considerations.............................................................116
13.7
5.0 V DC Electrical Characteristics.........................................118
13.8
3.3 V DC Electrical Characteristics.........................................119
13.9
5.0 V Control Timing ...............................................................122
13.10 3.3 V Control Timing ...............................................................123
13.11 5.0 V Serial Peripheral Interface Timing .................................126
R E Q U I R E D
Section 13. Electrical Specifications
A G R E E M E N T
General Release Specification — MC68HC05C4A
N O N - D I S C L O S U R E
13.12 3.3 V Serial Peripheral Interface Timing .................................127
13.2 Introduction
This section contains electrical and timing specifications.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
113
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Rating
Supply Voltage
Current Drain Per Pin, Excluding
VDD and VSS
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
VSS – 0.3
to 2 × VDD + 0.3
V
–65 to +150
°C
IRQ Pin Only
Storage Temperature Range
N O N - D I S C L O S U R E
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0 V DC Electrical Characteristics and
13.8 3.3 V DC Electrical Characteristics for guaranteed operating
conditions.
General Release Specification
114
TSTG
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
Characteristic
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
°C
Operating Temperature Range
MC68HC05C4AP, FN, B, FB
MC68HC05C4ACP, CFN, CB, CFB
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. C = Extended temperature range (–40°C to +85°C)
4. B = Shrink dual in-line-package (SDIP)
5. FB = Quad flat pack (QFP)
13.5 Thermal Characteristics
Characteristic
θJA
Value
60
70
95
60
Unit
°C/W
N O N - D I S C L O S U R E
Thermal Resistance
Plastic Dual In-Line Package (PDIP)
Plastic Leaded Chip Carrier (PLCC)
Quad Flat Pack (QFP)
Plastic Shrink Dual In-Line Package (SDIP)
Symbol
A G R E E M E N T
13.4 Operating Temperature Range
R E Q U I R E D
Electrical Specifications
Operating Temperature Range
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
115
13.6 Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ= TA + (PD × θJA)
(1)
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W.
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
For most applications, PI/O « PINT and can be neglected.
Following is an approximate relationship between PD and TJ
neglecting PI/O:
PD = K ÷ (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2 )
(3)
N O N - D I S C L O S U R E
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
General Release Specification
116
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
VDD = 4.5 V
VDD
Pins
R2
SEE TABLE
TEST
POINT
C
SEE TABLE
R E Q U I R E D
Electrical Specifications
Power Considerations
PA7–PA0
PB7–PB0
PC7–PC0
PD5–PD0, PD7
R1
3.26 Ω
R2
2.38 Ω
C
50 pF
R1
SEE TABLE
VDD = 3.0 V
R1
PA7–PA0
PB7–PB0
PC7–PC0
PD5–PD0, PD7
10.91 Ω
R2
6.32 Ω
C
A G R E E M E N T
Pins
50 pF
N O N - D I S C L O S U R E
Figure 13-1. Test Load
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
117
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Electrical Specifications
13.7 5.0 V DC Electrical Characteristics
Characteristic (Note 2)
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD–0.1
—
—
0.1
—
V
VDD–0.8
VDD–0.8
VDD–0.8
—
—
—
—
—
—
Output High Voltage
(ILoad = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –1.6 mA) PD4–PD1
(ILoad = –5.0 mA) PC7
VOH
Output Low Voltage
(ILoad = 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 10 mA) PC7
VOL
—
—
—
—
0.4
0.4
V
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
3.50
1.00
5.25
3.25
mA
mA
—
—
—
1
—
—
20
40
50
µA
µA
µA
V
Supply Current (4.5–5.5 Vdc @ FBus= 2.1 MHz)
Run (Note 3)
Wait (Note 4)
Stop (Note 5)
25 °C
0 °C to 70 °C (Standard)
–40 °C to +85 °C (Standard)
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
Ioz
—
—
±10
µA
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
IIn
—
—
±1
µA
Input Pullup Current (Note 6)
PB7–PB0 (With Pullup)
IIn
60
140
300
µA
COut
CIn
—
—
—
—
12
8
pF
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
4. Wait IDDmeasured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD–0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
General Release Specification
118
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD–0.1
—
—
0.1
—
V
VDD–0.3
VDD–0.3
VDD–0.3
—
—
—
—
—
—
Output High Voltage
(ILoad = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.4 mA) PD4–PD1
(ILoad = –1.5 mA) PC7
VOH
Output Low Voltage
(ILoad = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 6 mA) PC7
VOL
—
—
—
—
0.3
0.3
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
1.00
500
1.60
900
mA
µA
—
—
—
1
—
—
8
16
20
µA
µA
µA
V
V
V
Supply Current (3.0–3.6 Vdc @ fBus = 1.0 MHz)
Run (Note 3)
Wait (Note 4)
Stop (Note 5)
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Standard)
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
—
±10
µA
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
IIn
—
—
±1
µA
Input Pullup Current (Note 6)
PB7–PB0 (With Pullup)
IIn
25
65
140
µA
COut
CIn
—
—
—
—
12
8
pF
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
NOTES:
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
119
A G R E E M E N T
Characteristic (Note 2)
N O N - D I S C L O S U R E
13.8 3.3 V DC Electrical Characteristics
R E Q U I R E D
Electrical Specifications
3.3 V DC Electrical Characteristics
R E Q U I R E D
Electrical Specifications
5.00 mA
VDD = 5.5 V
T = –40 °C TO 85°C
I DD
)
NG
I
AT
R
PE
A G R E E M E N T
SUPPLY CURRENT (IDD)
4.00 mA
N
RU
(O
IT I D
D
WA
3.00 mA
2.00 mA
1.00 mA
50 µA
0.5 MHz
1.0 MHz
STOP IDD
1.5 MHz
MHZ
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
N O N - D I S C L O S U R E
Figure 13-2. Maximum Supply Current
Versus Internal Clock Frequency, VDD = 5.5 V
General Release Specification
120
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
RU
N(
1.00 mA
IT
WA
I DD
500 mA
A G R E E M E N T
SUPPLY CURRENT (IDD)
OP
E
VDD = 3.6 V
T = –40 °C to 85 °C
RA
TIN
G)
I
DD
1.50 mA
R E Q U I R E D
Electrical Specifications
3.3 V DC Electrical Characteristics
STOP IDD
0.5 MHz
1.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
N O N - D I S C L O S U R E
Figure 13-3. Maximum Supply Current
Versus Internal Clock Frequency, VDD = 3.6 V
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
121
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Electrical Specifications
13.9 5.0 V Control Timing
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fosc
—
dc
4.2
4.2
MHz
Cycle Time
Crystal
External Clock
fop
—
dc
2.1
2.1
MHz
Internal Clock Cycle Time
tcyc
480
—
ns
Crystal Oscillator Startup Time
toxov
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tilch
100
ms
RESET Pulse Width
trl
1.5
—
tcyc
tresl
tTH, tTL
tTLTL
4.0
125
Note 3
—
—
—
tcyc
ns
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIL
125
—
ns
Interrupt Pulse Period
tILIL
Note 4
—
tcyc
tOH, tOL
90
—
ns
Timer
Resolution (Note 2)
Input Capture Pulse Width
Input Capture Pulse Period
OSC1 Pulse Width
NOTES:
1. VDD = 5.0 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc.
4. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc.
General Release Specification
122
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fosc
—
dc
2.0
2.0
MHz
Internal Operating Frequency
Crystal
External Clock
fop
—
dc
1.0
1.0
MHz
Internal Clock Cycle Time
tcyc
1000
—
ns
Crystal Oscillator Startup Time
toxov
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tilch
100
ms
RESET Pulse Width
trl
1.5
—
tcyc
tresl
tTH, tTL
tTLTL
4.0
250
Note 3
—
—
—
tcyc
ns
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note 4
—
tcyc
tOH, tOL
200
—
ns
Timer
Resolution (Note 2)
Input Capture Pulse Width
Input Capture Pulse Period
OSC1 Pulse Width
NOTES:
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it tkes to execute the capture interrupt
service routine plus 24 tcyc.
4. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc.
tTH*
tTLTL*
tTL*
TCAP PIN
*Refer
to timer resolution data in Section 8. Timer.
Figure 13-4. TCAP Timing Relationships
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
123
A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
13.10 3.3 V Control Timing
R E Q U I R E D
Electrical Specifications
3.3 V Control Timing
R E Q U I R E D
Electrical Specifications
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tcyc cycles it takes to
execute the interrupt service routine plus 19 tcyc cycles.
tILIH
A G R E E M E N T
IRQ1
NORMALLY
USED WITH
WIRED-OR
.
.
.
IRQn
IRQ
INTERNAL
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt
is recognized.
Figure 13-5. External Interrupt Timing
N O N - D I S C L O S U R E
INTERNAL
CLOCK1
INTERNAL
ADDRESS BUS1
1FFE
INTERNAL
DATA BUS1
RESET2
1FFE
1FFE
1FFE
NEW
PCH
1FFF
NEW
PCL
NEW PC
OP
CODE
tRL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 13-6. External Reset Timing
General Release Specification
124
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
R E Q U I R E D
Electrical Specifications
3.3 V Control Timing
OSC1
tRL
RESET
tILIH
IRQ2
4064 tcyc
A G R E E M E N T
IRQ3
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
NOTES:
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
1FFE
1FFF4
RESET OR INTERRUPT
VECTOR FETCH
N O N - D I S C L O S U R E
Figure 13-7. STOP Recovery Timing Diagram
(NOTE 1)
VDD
OSC1 PIN2
4064 tcyc
INTERNAL
CLOCK3
INTERNAL
ADDRESS BUS3
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
INTERNAL
DATA BUS3
NEW
PCH
1FFF
NEW
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 13-8. Power-On Reset Timing Diagram
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
125
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Electrical Specifications
13.11 5.0 V Serial Peripheral Interface Timing
Num
1
2
3
4
5
6
7
8
9
10
11
12
13
Characteristic
Operating Frequency
Master
Slave
Cycle Time
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High Time
Master
Slave
Clock (SCK) Low Time
Master
Slave
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Slave Access Time
(Time to Data Active from High-Impedance State)
Slave Disable Time (Hold Time to High-Impedance State)
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)‡
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
Symbol
Min
Max
Unit
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
tcyc(M)
tcyc(S)
2.0
480
—
—
tcyc
ns
tLead(M)
tLead(S)
†
240
—
—
ns
tLAG(M)
tLAG(S)
†
720
—
—
ns
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
tSU(M)
tSU(S)
100
100
—
—
ns
tH(M)
tH(S)
100
100
—
—
ns
tA
0
120
ns
tDIS
—
240
ns
tV(M)
tV(S)
0.25
—
—
240
tcyc(M)
ns
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
tRM
tRS
—
—
100
2.0
ns
µs
tFM
tFS
—
—
100
2.0
ns
µs
* VDD = 5.0 Vdc 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Section 8. Timer for timing diagrams.
† Signal production depends on software.
‡ Assumes 200 pF load on all SPI pins
General Release Specification
126
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
13.12 3.3 V Serial Peripheral Interface Timing
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
1.0
fOP
MHz
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2.0
1.0
—
—
tcyc
µs
2
Enable Lead Time
Master
Slave
tLead(M)
tLead(S)
†
500
—
—
ns
3
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
1.5
—
—
ns
µs
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
ns
5
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
ns
6
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
ns
7
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
200
200
—
—
ns
8
Slave Access Time
(Time to Data Active from High-Impedance State)
tA
0
250
ns
9
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
500
ns
10
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
500
tcyc(M)
ns
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tcyc(M)
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
200
2.0
ns
µs
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
200
2.0
ns
µs
A G R E E M E N T
Characteristic
* VDD = 3.3 Vdc 0.3 Vdc;V SS = 0 Vdc, TA = TL to TH. Refer to Section 8. Timer for timing diagrams.
† Signal production depends on software.
‡ Assumes 200 pF load on all SPI pins
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
127
N O N - D I S C L O S U R E
Num
R E Q U I R E D
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
R E Q U I R E D
Electrical Specifications
SS
(INPUT)
SS PIN OF MASTER HELD HIGH
12
1
SCK (CPOL = 0)
(OUTPUT)
13
12
5
NOTE
4
12
SCK (CPOL = 1)
(OUTPUT)
13
5
NOTE
4
6
A G R E E M E N T
MISO
(INPUT)
MSB IN
BITS 6–1
10 (ref)
11
MOSI
(OUTPUT)
7
LSB IN
10
MASTER MSB OUT
11 (ref)
BITS 6–1
MASTER LSB OUT
13
12
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS PIN OF MASTER HELD HIGH
N O N - D I S C L O S U R E
1
SCK (CPOL = 0)
(OUTPUT)
13
12
5
NOTE
4
12
SCK (CPOL = 1)
(OUTPUT)
13
5
NOTE
4
6
MISO
(INPUT)
MSB IN
10 (ref)
BITS 6–1
11
MOSI
(OUTPUT)
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
11
MASTER LSB OUT
13
12
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-9. SPI Master Timing Diagram
General Release Specification
128
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
R E Q U I R E D
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
13
12
12
13
3
5
4
2
SCK (CPOL = 1)
(INPUT)
5
4
SLAVE
MSB OUT
6
MOSI
(OUTPUT)
BITS 6–1
10
7
MSB IN
9
SLAVE LSB OUT
11
NOTE
A G R E E M E N T
8
MISO
(INPUT)
11
BITS 6–1
LSB IN
NOTE: Not defined, but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
13
1
SCK (CPOL = 0)
(INPUT)
12
5
4
2
8
MISO
(OUTPUT)
N O N - D I S C L O S U R E
3
SCK (CPOL = 1)
(INPUT)
5
4
10
NOTE
MOSI
(INPUT)
12
SLAVE
MSB OUT
6
7
13
BITS 6–1
10
MSB IN
9
SLAVE LSB OUT
11
BITS 6–1
LSB IN
NOTE: Not defined, but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1)
Figure 13-10. SPI Slave Timing Diagram
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Electrical Specifications
129
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
130
MC68HC05C4A — Rev. 4.0
Electrical Specifications
MOTOROLA
14.2
Introduction .............................................................................131
14.3
40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03)....................................................................132
14.4
42-Pin Plastic Shrink Dual In-Line (SDIP) Package
(Case 858-01)....................................................................132
14.5
44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02)....................................................................133
14.6
44-Lead Quad Flat Pack (QFP) (Case 824A-01)....................134
14.2 Introduction
This section describes the dimensions of the dual in-line package (DIP),
plastic shrink dual in-line package (SDIP), plastic leaded chip carrier
(PLCC), and quad flat pack (QFP) MCU packages. Package dimensions
available at the time of this publication are provided in this section. To
make sure that you have the latest case outline specifications, contact
one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Mechanical Specifications
131
R E Q U I R E D
14.1 Contents
A G R E E M E N T
Section 14. Mechanical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
14.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
40
NOTES:
1. POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
21
B
1
20
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
A
C
N
J
H
G
F
K
D
M
SEATING
PLANE
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
1°
0°
0.51
1.02
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0°
1°
0.020
0.040
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01)
-A-
N O N - D I S C L O S U R E
A G R E E M E N T
Mechanical Specifications
42
! ! %
! ! ! #
! " $" 22
-B1
21
L
H
C
-T
G
F
D 42 PL
N
K
! M
J 42 PL
°
°
°
°
! General Release Specification
132
MC68HC05C4A — Rev. 4.0
Mechanical Specifications
MOTOROLA
R E Q U I R E D
Mechanical Specifications
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
-N-
0.007(0.180) M T
B
D
Y BRK
L-M S N S
0.007(0.180) M T
U
L-M S N S
Z
V
44
W
1
X
D
G1
0.010 (0.25) S T
VIEW D-D
A
0.007(0.180) M T
L-M S N S
R
0.007(0.180) M T
L-M S N S
0.007(0.180) M T
H
A G R E E M E N T
-M-
-L-
L-M S N S
L-M S N S
Z
J
K1
E
0.004 (0.10)
G
-TG1
0.010 (0.25) S T
L-M S N S
K
SEATING
PLANE
F
0.007(0.180)M T
VIEW S
L-M S N S
N O N - D I S C L O S U R E
C
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940134). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
INCHES
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2°
10°
0.610
0.630
0.040
MC68HC05C4A — Rev. 4.0
MOTOROLA
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
15.50
16.00
1.02
General Release Specification
Mechanical Specifications
133
14.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33
23
B
DETAIL A
S
S
D
D
S
V
H A-B
L
-A,B,DB
M
-B-
B
0.20 (0.008)
-A-
S
22
0.20 (0.008) M C A-B
0.05 (0.002) A-B
34
A G R E E M E N T
R E Q U I R E D
Mechanical Specifications
DETAIL A
44
12
1
11
F
-DA
0.20 (0.008) M C A-B
0.05 (0.002) A-B
S
0.20 (0.008) M H A-B
BASE METAL
S
D
S
S
D
S
N
J
D
M
DETAIL C
0.20 (0.008)
M
C A-B
S
D
S
N O N - D I S C L O S U R E
SECTION B–B
C E
-H-
0.01 (0.004)
-CSEATING
PLANE
H
M
G
M
T
DATUM
PLANE
DATUM
PLANE
-H-
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ĆCĆ.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
General Release Specification
134
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
9.90 10.10
9.90 10.10
2.45
2.10
0.45
0.30
2.10
2.00
0.40
0.30
0.80 BSC
0.25
Ċ
0.23
0.13
0.95
0.65
8.00 REF
10°
5°
0.17
0.13
7°
0°
0.30
0.13
12.95 13.45
Ċ
0.13
Ċ
0°
12.95 13.45
Ċ
0.40
1.6 REF
INCHES
MIN
MAX
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
0.010
Ċ
0.005 0.009
0.026 0.037
0.315 REF
10°
5°
0.005 0.007
7°
0°
0.005 0.012
0.510 0.530
Ċ
0.005
Ċ
0°
0.510 0.530
Ċ
0.016
0.063 REF
MC68HC05C4A — Rev. 4.0
Mechanical Specifications
MOTOROLA
15.2
Introduction .............................................................................135
15.3
MCU Ordering Forms .............................................................135
15.4
Application Program Media.....................................................136
15.5
ROM Program Verification......................................................137
15.6
ROM Verification Units (RVUs)...............................................138
15.7
MC Order Numbers ................................................................139
15.2 Introduction
This section contains instructions for ordering custom-masked ROM
MCUs.
15.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit the
following items when ordering MCUs:
•
A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
•
A copy of the customer specification, if the customer specification
deviates from the Motorola specification for the MCU.
•
Customer’s application program on one of the media listed in 15.4
Application Program Media
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Ordering Information
135
R E Q U I R E D
15.1 Contents
A G R E E M E N T
Section 15. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
The current MCU ordering form is also available through the Motorola
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lowercase letters.
Then press the return key to start the BBS software.
15.4 Application Program Media
Please deliver the application program to Motorola in one of the following
media:
A G R E E M E N T
R E Q U I R E D
Ordering Information
•
Macintosh®1 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
•
MS-DOS®2 or PC-DOSTM3 3 1/2-inch diskette (double-sided 720
K or double-sided high-density 1.44 M)
•
MS-DOS® or PC-DOSTM 5 1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
N O N - D I S C L O S U R E
When submitting the application program on a diskette, clearly label the
diskette with the following information:
•
Customer name
•
Customer part number
•
Project or product name
•
File name of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
136
MC68HC05C4A — Rev. 4.0
Ordering Information
MOTOROLA
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
15.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Ordering Information
137
A G R E E M E N T
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. Refer to the current
MCU ordering form for additional requirements. Motorola may request
pattern re-submission if non-user areas contain any non-zero code.
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Ordering Information
ROM Program Verification
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the it to Motorola. The signed listing verify form
constitutes the contractual agreement for the creation of the custom
mask.
15.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Motorola Quality Assurance.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Ordering Information
General Release Specification
138
MC68HC05C4A — Rev. 4.0
Ordering Information
MOTOROLA
Table 15-1. MC Order Numbers
Operating
Temperature
Range
MC Order Number
40-Pin Plastic Dual In-Line Package
(DIP)
0 °C to 70 °C
MC68HC05C4AP
42-Pin Plastic Shrink Dual In-Line
Package (SDIP)
0 °C to 70 °C
MC68HC05C4AB
44-Lead Plastic Leaded Chip Carrier
(PLCC)
0 °C to 70 °C
MC68HC05C4AFN
44-Lead Quad Flat Pack (QFP)
0 °C to 70 °C
MC68HC05C4AFB
Package Type
Extended Temperature Range
40-Pin Plastic Dual In-Line Package
(DIP)
–40 °C to +85 °C
MC68HC05C4ACP
42-Pin Plastic Shrink Dual In-Line
Package (SDIP)
–40 °C to +85 °C
MC68HC05C4ACB
44-Lead Plastic Leaded Chip Carrier
(PLCC)
–40 °C to +85 °C
MC68HC05C4ACFN
44-Lead Quad Flat Pack (QFP)
–40 °C to +85 °C
MC68HC05C4ACFB
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
Ordering Information
139
A G R E E M E N T
Table 15-1 shows the MC order numbers for the available package
types.
N O N - D I S C L O S U R E
15.7 MC Order Numbers
R E Q U I R E D
Ordering Information
MC Order Numbers
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Ordering Information
General Release Specification
140
MC68HC05C4A — Rev. 4.0
Ordering Information
MOTOROLA
A.2
Introduction .............................................................................141
A.3
Low-Power Operating Temperature Range............................141
A.4
2.5–3.6 V DC Electrical Characteristics..................................142
A.5
1.8–2.4 V DC Electrical Characteristics..................................142
A.6
Low-Power Supply Current.....................................................143
A.2 Introduction
Appendix A introduces the MC68HCL05C4A, a low-power version of the
MC68HC05C4A. The technical data applying to the MC68HC05C4A
applies to the MC68HCL05C4A with the exceptions given in this
appendix.
A.3 Low-Power Operating Temperature Range
The data here should replace the corresponding data found in 13.4
Operating Temperature Range.
Rating
Operating Temperature Range
MC68HCL05C4AP, FN, B, and FB
Symbol
Value
Unit
TA
TL to TH
0 to +70
°C
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. B = Shrink dual in-line-package (SDIP)
4. FB = Quad flat pack (QFP)
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HCL05C4A
141
R E Q U I R E D
A.1 Contents
A G R E E M E N T
Appendix A. MC68HCL05C4A
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
MC68HCL05C4A
A.4 2.5–3.6 V DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Output High Voltage
(ILoad = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.4 mA) PD4–PD1
(ILoad = –1.5 mA) PC7
VOH
Output Low Voltage
(ILoad = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 5.0 mA) PC7
VDD – 0.3
VDD – 0.3
VDD – 0.3
—
—
—
—
—
—
VOL
—
—
—
—
0.3
0.3
V
IIn
10
55
120
µA
Symbol
Min
Typ
Max
Unit
VDD – 0.3
VDD – 0.3
VDD – 0.3
—
—
—
—
—
—
Input Pullup Current
PB7–PB0 with Pullup
Unit
V
A.5 1.8–2.4 V DC Electrical Characteristics
Characteristic
Output High Voltage
(ILoad = –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.2 mA) PD4–PD1
(ILoad = –0.75 mA) PC7
VOH
Output Low Voltage
(ILoad = 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 2.0 mA) PC7
VOL
—
—
—
—
0.3
0.3
V
IIn
3
45
75
µA
Input Pullup Current
PB7–PB0 with Pullup
General Release Specification
142
V
MC68HC05C4A — Rev. 4.0
MC68HCL05C4A
MOTOROLA
Symbol
Supply Current (4.5–5.5 Vdc @ fBus = 2.1 MHz)
Run
Wait
Stop
25 °C
0 °C to +70 °C (Standard)
Supply Current (2.4–3.6 Vdc @ fBus = 1.0 MHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to +70 ° C (Standard)
Supply Current (2.5–3.6 Vdc @ fBus = 500 kHz)
Run
Wait
Stop
25 °C
0 °C to +70 °C (Standard)
Supply Current (1.8–2.4 Vdc @ fBus = 500 kHz)
Run
Wait
Stop
25 °C
0 °C to +70 °C (Standard)
IDD
IDD
IDD
IDD
Min
Typ
Max
Unit
—
—
3.50
1.6
4.25
2.25
mA
mA
—
—
1
—
15
25
µA
µA
—
—
1.00
0.7
1.4
1.0
mA
mA
—
—
1
—
5
10
µA
µA
—
—
500
300
750
500
µA
µA
—
—
1
—
5
10
µA
µA
—
—
300
250
600
400
µA
µA
—
—
1
—
2
5
µA
µA
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs;
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on
OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs; port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs; port B = VDD, all other inputs VIL = 0.2 V,
VIL = VDD–0.2 V
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HCL05C4A
143
A G R E E M E N T
Characteristic (Note 1)
N O N - D I S C L O S U R E
A.6 Low-Power Supply Current
R E Q U I R E D
MC68HCL05C4A
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
MC68HCL05C4A
General Release Specification
144
MC68HC05C4A — Rev. 4.0
MC68HCL05C4A
MOTOROLA
B.2
Introduction .............................................................................145
B.3
High-Speed Operating Temperature Range...........................146
B.4
4.5 –5.5 V High-Speed Supply Currents.................................147
B.5
4.5–5.5 V High-Speed Control Timing ....................................148
B.6
2.4–3.6 V High-Speed Control Timing ....................................149
B.7
4.5 –5.5 V High-Speed SPI Timing.........................................150
B.8
2.4–3.6 V High-Speed SPI Timing..........................................151
B.2 Introduction
Appendix B introduces the MC68HSC05C4A, a high-speed version of
the MC68HC05C4A. The technical data applying to the MC68HC05C4A
applies to the MC68HSC05C4A with the exceptions given in this
appendix.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HSC05C4A
145
R E Q U I R E D
B.1 Contents
A G R E E M E N T
Appendix B. MC68HSC05C4A
N O N - D I S C L O S U R E
General Release Specification — MC68HC05C4A
B.3 High-Speed Operating Temperature Range
The data here replaces the corresponding data in 13.4 Operating
Temperature Range.
Rating
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
°C
Operating Temperature Range
MC68HSC05C4AP, FN, B, FB
MC68HSC05C4ACP, CFN, CB, CFB
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. C = Extended temperature range (–40° to +85°)
4. B = Shrink dual in-line-package (SDIP)
5. FB = Quad flat pack (QFP)
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
MC68HSC05C4A
General Release Specification
146
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MOTOROLA
Characteristic (Note 1)
Symbol
Supply Current (4.5–5.5 Vdc @ fBus = 4.0 MHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
Min
Typ
Max
Unit
—
—
7.00
2.00
11.0
6.50
mA
mA
—
—
—
1
—
—
20
40
50
µA
µA
µA
—
—
2.50
1.00
4.00
2.00
mA
mA
—
—
—
1
—
—
8
16
20
µA
µA
µA
IDD
Supply Current (2.4–3.6 Vdc @ fBus = 2.0 MHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
IDD
Input Pullup Current (VDD = 4.5–5.5 V)
PB7–PB0 with Pullup
IDD
60
140
300
µA
Input Pullup Current (VDD = 2.4–3.6 V)
PB7–PB0 with Pullup
IDD
10
55
140
µA
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs;
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF
on OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs; port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD–0.2 V
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HSC05C4A
147
A G R E E M E N T
The data in 13.7 5.0 V DC Electrical Characteristics applies to the
MC68HSC05C4A with the exceptions given in this table.
N O N - D I S C L O S U R E
B.4 4.5 –5.5 V High-Speed Supply Currents
R E Q U I R E D
MC68HSC05C4A
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
MC68HSC05C4A
B.5 4.5–5.5 V High-Speed Control Timing
The data in 13.9 5.0 V Control Timing applies to the MC68HSC05C4A
with the exceptions in this table.
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fosc
—
dc
8.2
8.2
MHz
Internal Operating Frequency (fosc ÷ 2)
Crystal
External Clock
fOP
—
dc
4.1
4.1
MHz
Cycle Time
tcyc
244
—
ns
Crystal Oscillator Startup Time
tOXOV
100
ms
Stop Recovery Startup Time
tILCH
100
ms
RESET Pulse Width
tRL
1.5
—
tcyc
tresl
tTH or tTL
tTHTL
4.0
64
Note 2
—
—
—
tcyc
ns
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
64
—
ns
Interrupt Pulse Period
tILIL
Note 3
—
tcyc
tOH or tOL
50
—
ns
Timer
Resolution (Note 1)
Input Capture Pulse Width
Input Capture Pulse Width
OSC1 Pulse Width
NOTES:
1. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc.
3. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc.
General Release Specification
148
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MOTOROLA
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fosc
—
dc
4.2
4.2
MHz
Internal Operating Frequency (fosc ÷ 2)
Crystal
External Clock
fOP
—
dc
2.1
2.1
MHz
Cycle Time
tcyc
480
—
ns
Crystal Oscillator Startup Time
tOXOV
100
ms
Stop Recovery Startup Time
tILCH
100
ms
RESET Pulse Width
tRL
1.5
—
tcyc
tresl
tTH or tTL
tTHTL
4.0
125
Note 2
—
—
—
tcyc
ns
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note 3
—
tcyc
tOH or tOL
90
—
ns
Timer
Resolution (Note 1)
Input Capture Pulse Width
Input Capture Pulse Width
OSC1 Pulse Width
NOTES:
1. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc.
3. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc.
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HSC05C4A
149
A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
B.6 2.4–3.6 V High-Speed Control Timing
R E Q U I R E D
MC68HSC05C4A
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
MC68HSC05C4A
B.7 4.5 –5.5 V High-Speed SPI Timing
The data in 13.11 5.0 V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given in the following table.
Num
1
2
3
4
5
6
7
8
9
10
11
12
13
†
‡
Characteristic
Operating Frequency
Master
Slave
Cycle Time
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High Time
Master
Slave
Clock (SCK) Low Time
Master
Slave
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Slave Access Time
(Time to Data Active from High-Impedance State)
Slave Disable Time
(Hold Time to High-Impedance State)
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)‡
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
Min
Max
Unit
fop(M)
fop(S)
dc
dc
0.5
4.1
fOP
MHz
tcyc(M)
tcyc(S)
2.0
244
—
—
tcyc
ns
tLead(M)
tLEAD(S)
†
122
—
—
ns
ns
tLag(M)
tLag(S)
†
366
—
—
ns
ns
tW(SCKH)M
tW(SCKH)S
166
93
—
—
ns
ns
tW(SCKL)M
tW(SCKL)S
166
93
—
—
ns
ns
tSU(M)
tSU(S)
49
49
—
—
ns
ns
tH(M)
tH(S)
49
49
—
—
ns
ns
tA
0
61
ns
tDIS
—
122
ns
tV(M)
tV(S)
0.25
—
—
122
tcyc(M)
ns
tHO(M)
tHO(S)
0.25
0
—
—
tcyc(M)
ns
tRM
tRS
—
—
50
1.0
ns
µs
tFM
tFS
—
—
50
1.0
ns
µs
Signal production depends on software.
Assumes 200 pF load on all SPI pins.
General Release Specification
150
Symbol
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MOTOROLA
Num
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2.0
480
—
—
tcyc
ns
2
Enable Lead Time
Master
Slave
tLead(M)
tLead(S)
†
240
—
—
ns
ns
3
Enable Lag Time
Master
Slave
tLag(M)
tLag(S)
†
720
—
—
ns
ns
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
ns
5
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
ns
6
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
ns
7
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
tA
100
100
0
—
—
120
ns
ns
ns
tDIS
—
240
ns
tV(M)
tV(S)
0.25
—
—
240
tcyc(M)
ns
tHO(M)
tHO(S)
0.25
0
—
—
tcyc(M)
ns
8
9
10
Characteristic
Slave Access Time
(Time to Data Active from High-Impedance State)
Slave Disable Time (Hold Time to High-Impedance State)
Data
Master (Before Capture Edge)
Slave (After Enable Edge)‡
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
†
‡
Signal production depends on software.
Assumes 200 pF load on all SPI pins
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
MC68HSC05C4A
151
A G R E E M E N T
The data in 13.12 3.3 V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given in the following table.
N O N - D I S C L O S U R E
B.8 2.4–3.6 V High-Speed SPI Timing
R E Q U I R E D
MC68HSC05C4A
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
MC68HSC05C4A
General Release Specification
152
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MOTOROLA
Appendix C. M68HC05Cx Family Feature Comparisons
C.1 Contents
Introduction .............................................................................153
Table C-1. M68HC05Cx Feature Comparison .......................154
C.2 Introduction
N O N - D I S C L O S U R E
Refer to Table C-1 for a comparison of the features for all the
M68HC05C Family members.
A G R E E M E N T
C.2
R E Q U I R E D
General Release Specification — MC68HC05C4A
MC68HC05C4A — Rev. 4.0
MOTOROLA
General Release Specification
153
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Release Specification
154
Table C-1. M68HC05Cx Feature Comparison
MC68HC05C4A — Rev. 4.0
MOTOROLA
C4
C4A
705C4A
C8
C8A
705C8
705C8A
C12
C12A
C9
C9A
705C9
705C9A
USER ROM
4160
4160
—
7744
7744
—
—
12,096
12,096
15,760-15,936
15,760-15,936
—
—
USER EPROM
—
—
4160
—
—
7596-7740
7596-7740
—
—
—
—
15,760-15,936
12,096-15,936
CODE
SECURITY
NO
YES
YES
NO
YES
YES
YES
NO
YES
NO
YES
NO
YES
RAM
176
176
176
176
176
176-304
176-304
176
176
176-352
176-352
176-352
176-352
OPTION
REGISTER
(IRQ/RAM/
SEC)
NO
NO
$1FDF
(IRQ/SEC)
NO
NO
$1FDF
(IRQ/RAM/
SEC)
$1FDF
(IRQ/RAM/SEC)
NO
NO
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
MASK
OPTION
REGISTER(S)
NO
NO
$1FF0-1
NO
NO
NO
$1FF0-1
NO
NO
NO
NO
NO
$3FF0-1
PORTB
KEYSCAN
(PULLUP/
INTERRUPT)
NO
YES
MASK
OPTION
YES
MOR
SELECTABLE
NO
YES
MASK
OPTION
NO
YES
MOR
SELECTABLE
YES
MASK
OPTION
YES
MASK
OPTION
NO
YES
MASK
OPTION
NO
YES
MOR
SELECTABLE
PC7 DRIVE
STANDARD
HIGH
CURRENT
HIGH
CURRENT
STANDARD
HIGH
CURRENT
STANDARD
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
STANDARD
HIGH
CURRENT
STANDARD
HIGH
CURRENT
PORT D
PD7, 5-0
INPUT
ONLY
PD7, 5-0
INPUT
ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT
ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
BIDIRECTIONAL
PD7, 5-0
BIDIRECTIONAL
PD7, 5-0
BIDIRECTIONAL
PD7, 5-0
BIDIRECTIONAL
COP
NO
YES
YES
NO
YES
YES
TWO TYPES
YES
YES
YES
YES
YES
TWO TYPES
COP ENABLE
—
MASK
OPTION
MOR
—
MASK
OPTION
SOFTWARE
SOFTWARE+
MOR
MASK
OPTION
MASK
OPTION
SOFTWARE
SOFTWARE
SOFTWARE
SOFTWARE+
MOR
COP
TIMEOUT
—
64 ms
(@4 MHz
osc)
64 ms
(@4 MHz
osc)
—
SOFTWARE
SELECTABLE
SOFTWARE
SELECTABLE
SOFTWARE
SELECTABLE
SOFTWARE+
MOR
SELECTABLE
COP CLEAR
—
CLR $1FF0
CLR $1FF0
—
CLR $1FF0
WRITE
$55/$AA
TO $001D
WRITE $55/$AA
TO $001D
OR
CLR $1FF0
CLR $3FF0
CLR $3FF0
WRITE
$55/$AA
TO $001D
WRITE
$55/$AA
TO $001D
WRITE
$55/$AA
TO $001D
WRITE $55/$AA
TO $001D
OR
CLR $3FF0
CLOCK
MONITOR
NO
NO
NO
NO
NO
YES
YES
NO
NO
YES
YES
YES
YES
(C9A MODE)
ACTIVE
RESET
NO
NO
NO
NO
NO
COP/CLOCK
MONITOR
PROGRAMMABLE
COP/CLOCK
MONITOR
NO
NO
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/C9A COP/
CLOCK
MONITOR
STOP
DISABLE
NO
MASK
OPTION
NO
NO
MASK
OPTION
NO
NO
MASK
OPTION
MASK
OPTION
NO
NO
NO
MOR
SELECTABLE
(C12A MODE)
64 ms
SOFTWARE
(@4 MHz osc) SELECTABLE
SOFTWARE+
MOR
SELECTABLE
64 ms
64 ms
(@4 MHz osc) (@4MHz osc)
NOTES:
1. The expanded RAM map (from $30–$4F and $100–$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A.
2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
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intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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303-675-2140
Mfax™: [email protected] – TOUCHTONE 602-244-6609, US & Canada ONLY 1-800-774-1848
INTERNET: http://motorola.com/sps
JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1997
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