MOTOROLA 68HC705CL16

HC05CL48GRS/H
REV 2.0
68HC05CL48
68HC705CL48
68HC05CL16
68HC705CL16
SPECIFICATION
(General Release)
© June 11, 1997
Hong Kong Design Center
CSIC Group
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
 Motorola, Inc., 1997
June 11, 1997
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 1
GENERAL DESCRIPTION
1.1
FEATURES ...................................................................................................... 1-1
1.2
MCU STRUCTURE.......................................................................................... 1-3
1.3
PIN ASSIGNMENT .......................................................................................... 1-4
1.4
SIGNAL DESCRIPTION .................................................................................. 1-5
1.4.1
VDD and VSS ................................................................................................ 1-5
1.4.2
RESET......................................................................................................... 1-5
1.4.3
IRQ .............................................................................................................. 1-5
1.4.4
IRQ0, IRQ1, IRQ2........................................................................................ 1-6
1.4.5
OSC1, OSC2 ............................................................................................... 1-6
1.4.6
External Clock.............................................................................................. 1-7
1.4.7
PTA0-PTA7.................................................................................................. 1-7
1.4.8
PTB0-PTB7.................................................................................................. 1-7
1.4.9
PTC0-PTC7 ................................................................................................. 1-7
1.4.10 SCK ............................................................................................................. 1-8
1.4.11 MISO, MOSI ................................................................................................ 1-8
1.4.12 SS ................................................................................................................ 1-8
1.4.13 AD0-AD3...................................................................................................... 1-8
1.4.14 TCAP1 ......................................................................................................... 1-8
1.4.15 TCAP2 ......................................................................................................... 1-8
1.4.16 FSK+, FSK–................................................................................................. 1-8
1.4.17 RT_L ............................................................................................................ 1-9
1.4.18 RD1, RD2 .................................................................................................... 1-9
1.4.19 BP0 - BP15 .................................................................................................. 1-9
1.4.20 FP0 - FP44 .................................................................................................. 1-9
1.4.21 VLCD, V0, V1, V2, V3, V4 ........................................................................... 1-9
1.4.22 XFC.............................................................................................................. 1-9
SECTION 2
MEMORY
2.1
2.2
2.2.1
2.3
2.4
2.5
2.6
MEMORY MAP ................................................................................................ 2-1
I/O AND CONTROL REGISTERS ................................................................... 2-1
Option Register ($1F) .................................................................................. 2-1
LCD RAM ......................................................................................................... 2-2
RAM ................................................................................................................. 2-2
ROM................................................................................................................. 2-2
I/O MAPPED REGISTERS .............................................................................. 2-2
MC68HC05CL48
REV 2.0
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
TABLE OF CONTENTS
Section
Page
SECTION 3
CPU
3.1
REGISTERS .................................................................................................... 3-1
3.1.1
Accumulator (A) ........................................................................................... 3-1
3.1.2
Index Register (X)........................................................................................ 3-2
3.1.3
Stack Pointer (SP) ....................................................................................... 3-2
3.1.4
Program Counter (PC)................................................................................. 3-2
3.1.5
Condition Code Register (CCR) .................................................................. 3-3
SECTION 4
INTERRUPTS
4.1
RESET INTERRUPT SEQUENCE .................................................................. 4-3
4.2
SOFTWARE INTERRUPT (SWI) ..................................................................... 4-3
4.3
HARDWARE INTERRUPTS ............................................................................ 4-3
4.3.1
External Interrupt (IRQ) ............................................................................... 4-3
4.3.2
External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7]) ........................................ 4-6
4.3.3
Caller ID Interrupt (RDI/CDI,CDRI).............................................................. 4-8
4.3.4
TIMER Interrupt ........................................................................................... 4-8
4.3.5
SPI Interrupt................................................................................................. 4-9
4.3.6
CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer).......................... 4-9
SECTION 5
RESETS
5.1
5.2
5.3
EXTERNAL RESET (RESET).......................................................................... 5-1
POWER-ON RESET (POR)............................................................................. 5-1
COMPUTER OPERATING PROPERLY RESET (COPR) ............................... 5-2
SECTION 6
LOW POWER MODES
6.1
LOW-POWER MODES .................................................................................... 6-1
6.1.1
STOP Instruction ......................................................................................... 6-1
6.1.2
WAIT Instruction .......................................................................................... 6-1
6.2
DATA-RETENTION MODE.............................................................................. 6-2
6.3
COP WATCHDOG TIMER CONSIDERATIONS ............................................. 6-2
SECTION 7
INPUT/OUTPUT PORTS
7.1
7.2
7.3
7.4
PARALLEL PORTS.......................................................................................... 7-1
PORT A............................................................................................................ 7-2
PORT B............................................................................................................ 7-2
PORT C............................................................................................................ 7-2
MOTOROLA
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MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 8
TIMER
8.1
16-BIT FREE-RUNNING TIMER...................................................................... 8-1
8.1.1
Counter ........................................................................................................ 8-3
8.1.2
Output Compare Registers .......................................................................... 8-5
8.1.3
Input Capture Registers............................................................................... 8-8
8.1.4
Timer Control Register (TCR).................................................................... 8-11
8.1.5
Timer Status Register (TSR) ..................................................................... 8-12
8.1.6
Timer Pin Configuration Register (TIMCONF)........................................... 8-14
8.1.7
Operation During Low Power Mode........................................................... 8-14
8.2
CORE TIMER................................................................................................. 8-14
8.2.1
Computer Operating Properly (COP) Watchdog reset .............................. 8-16
8.2.2
Ctimer Control and Status Register (CTCSR) ........................................... 8-16
8.2.3
Ctimer Counter Register (CTCR)............................................................... 8-17
8.2.4
Operation During Low Power Mode........................................................... 8-18
8.3
ONE SECOND WATCH TIMER..................................................................... 8-19
8.3.1
Watch Timer Control & Status Register (WTCSR) .................................... 8-20
SECTION 9
SERIAL PERIPHERAL INTERFACE
9.1
SIGNAL DESCRIPTION .................................................................................. 9-1
9.1.1
MISO Master In Slave Out........................................................................... 9-1
9.1.2
MOSI Serial Data In (Input) ......................................................................... 9-2
9.1.3
SCK Serial Clock (In/Out) ............................................................................ 9-2
9.1.4
SS SLAVE SELECT (INPUT) ...................................................................... 9-3
9.2
SPI REGISTERS.............................................................................................. 9-3
9.2.1
SPCR SPI Control Register ......................................................................... 9-4
9.2.2
SPSR SPI Status Register........................................................................... 9-6
9.2.3
SPDR SPI Data Register ............................................................................. 9-6
SECTION 10
ANALOG TO DIGITAL CONVERTER
10.1 ANALOG SECTION ....................................................................................... 10-1
10.1.1 Ratiometric Conversion ............................................................................. 10-1
10.1.2 VRH and VRL ........................................................................................................................ 10-1
10.1.3 Accuracy And Precision............................................................................. 10-1
10.2 CONVERSION PROCESS ............................................................................ 10-1
10.3 DIGITAL SECTION ........................................................................................ 10-2
10.3.1 Conversion Time........................................................................................ 10-2
10.3.2 Multi-Channel Operation............................................................................ 10-2
10.4 A/D STATUS AND CONTROL REGISTER (ADCSR) ................................... 10-2
10.4.1 COCO - Conversions Complete ................................................................ 10-2
MC68HC05CL48
REV 2.0
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
TABLE OF CONTENTS
Section
Page
10.4.2 ADRC - A/D RC Oscillator Control............................................................. 10-2
10.4.3 ADON - A/D On ......................................................................................... 10-3
10.4.4 CH2:CH0 - Channel Select Bits................................................................. 10-3
10.5 A/D DATA REGISTER (ADDR)...................................................................... 10-3
10.6 A/D DURING WAIT MODE ............................................................................ 10-3
10.7 A/D DURING STOP MODE ........................................................................... 10-4
SECTION 11
CALLER-ID
11.1 FSK DEMODULATOR ................................................................................... 11-2
11.2 CARRIER DETECTOR .................................................................................. 11-2
11.3 RT_L INTERRUPT......................................................................................... 11-2
11.4 RING DETECTOR ......................................................................................... 11-3
11.5 POWER MANAGEMENT............................................................................... 11-4
11.6 DATA INTERFACE ........................................................................................ 11-5
11.7 CALLER-ID REGISTERS............................................................................... 11-6
11.7.1 Control/Status Register1 (CLCSR1) .......................................................... 11-6
11.7.2 Control/Status Register 2 (CLCSR2) ......................................................... 11-7
11.7.3 Control/Status Register 3 (CLCSR3) ......................................................... 11-8
11.7.4 Caller_ID Data Register (CDDR) ............................................................... 11-9
11.8 DESIGN PARAMETERS................................................................................ 11-9
11.9 MESSAGE FORMAT ................................................................................... 11-11
SECTION 12
LCD DRIVER
12.1 LCD RAM. ...................................................................................................... 12-2
12.2 LCD OPERATION.......................................................................................... 12-4
12.3 LCD VOLTAGE GENERATION ..................................................................... 12-7
12.4 LCD CONTROL REGISTER (LCDCR) .......................................................... 12-8
12.5 ELECTRICAL REQUIREMENTS ................................................................... 12-9
12.5.1 DC Requirements ...................................................................................... 12-9
SECTION 13
PHASE-LOCKED LOOP
13.1
13.2
13.3
13.4
PLL CONTROL AND STATUS REGISTER (PCSR $000D) .......................... 13-2
PLL OPERATIONS ........................................................................................ 13-2
PLL LOCK TIME ............................................................................................ 13-2
PLL CLOCK FREQUENCY............................................................................ 13-2
MOTOROLA
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MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 14
INSTRUCTION SET
14.1 Addressing Modes ......................................................................................... 14-1
14.1.1 Inherent...................................................................................................... 14-1
14.1.2 Immediate .................................................................................................. 14-1
14.1.3 Direct ......................................................................................................... 14-1
14.1.4 Extended.................................................................................................... 14-2
14.1.5 Indexed, No Offset..................................................................................... 14-2
14.1.6 Indexed, 8-Bit Offset .................................................................................. 14-2
14.1.7 Indexed, 16-Bit Offset ................................................................................ 14-2
14.1.8 Relative...................................................................................................... 14-3
14.1.9 Instruction Types ....................................................................................... 14-3
14.1.10 Register/Memory Instructions .................................................................... 14-4
14.1.11 Read-Modify-Write Instructions ................................................................. 14-5
14.1.12 Jump/Branch Instructions .......................................................................... 14-5
14.1.13 Bit Manipulation Instructions...................................................................... 14-7
14.1.14 Control Instructions.................................................................................... 14-7
14.1.15 Instruction Set Summary ........................................................................... 14-8
SECTION 15
ELECTRICAL SPECIFICATIONS
15.1
15.2
15.3
15.4
15.5
15.6
MAXIMUM RATINGS..................................................................................... 15-1
THERMAL CHARACTERISTICS ................................................................... 15-1
DC ELECTRICAL CHARACTERISTICS........................................................ 15-2
POWER DISSIPATION.................................................................................. 15-3
CONTROL TIMING ........................................................................................ 15-4
ESD PROTECTION ....................................................................................... 15-4
SECTION 16
MECHANICAL SPECIFICATIONS
16.1
16.2
112-Pin THIN-QUAD-FLAT-PACKAGE (Case 987-01) ................................. 16-2
100-Pin THIN-QUAD-FLAT-PACKAGE (Case 983-02) ................................. 16-3
APPENDIX A
MC68HC705CL48
A.1
A.2
A.3
A.4
A.4.1
A.4.2
INTRODUCTION..............................................................................................A-1
MEMORY .........................................................................................................A-1
BOOTLOADER MODE ....................................................................................A-1
EPROM PROGRAMMING ...............................................................................A-3
EPROM Program Control Register (EPCR $26) .........................................A-3
Programming Sequence ..............................................................................A-3
MC68HC05CL48
REV 2.0
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
TABLE OF CONTENTS
Section
Page
APPENDIX B
MC68HC05CL16
B.1
B.2
B.3
B.4
INTRODUCTION..............................................................................................B-1
SIGNAL DESCRIPTION ..................................................................................B-1
MEMORY .........................................................................................................B-1
PIN ASSIGNMENT ..........................................................................................B-4
APPENDIX C
MC68HC705CL16
C.1
C.2
C.3
C.4
C.4.1
C.4.2
INTRODUCTION..............................................................................................C-1
MEMORY .........................................................................................................C-1
BOOTLOADER MODE ....................................................................................C-1
EPROM PROGRAMMING ...............................................................................C-3
EPROM Program Control Register (EPCR $26) .........................................C-3
Programming Sequence ..............................................................................C-3
MOTOROLA
vi
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
LIST OF FIGURES
Figure
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
6-1
7-1
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
12-1
12-2
12-3
12-4
13-1
13-2
16-1
16-2
A-1
A-2
B-1
Title
Page
MC68HC05CL48 Block Diagram ..................................................................... 1-3
MC68HC05CL48 Pin Assignments .................................................................. 1-4
Power Supply Decoupling ................................................................................ 1-5
Oscillator Connections ..................................................................................... 1-7
MC68HC05CL48 Memory Map........................................................................ 2-3
MC68HC05CL48 I/O Registers $0000-$000F ................................................. 2-4
MC68HC05CL48 I/O Registers $0010-$001F ................................................. 2-5
MC68HC05CL48 I/O Registers $0020-$002F ................................................. 2-6
MC68HC05 Programming Model ..................................................................... 3-1
Interrupt Processing Flowchart ........................................................................ 4-2
External Interrupts............................................................................................ 4-5
Keyboard Interrupt Circuitry ............................................................................. 4-7
STOP/WAIT Flowchart..................................................................................... 6-3
Port I/O Circuitry............................................................................................... 7-1
16-Bit Free-running Timer Block Diagram........................................................ 8-2
Timer State Diagram For Timer Overflow ........................................................ 8-4
Timer State Timing Diagram For Reset ........................................................... 8-5
Timer State Timing Diagram For Output Compare .......................................... 8-8
Timer State Timing Diagram For Input Capture ............................................. 8-11
Core Timer Block Diagram............................................................................. 8-15
ONE Second Watch Timer............................................................................. 8-20
SPI Clock/Data Relationships .......................................................................... 9-5
Caller ID Block Diagram................................................................................. 11-1
Carrier Detect Interface.................................................................................. 11-2
RT_L Interrupt ................................................................................................ 11-3
Ring Detect Interface ..................................................................................... 11-3
Power Up Sequence from STOP Mode ......................................................... 11-4
Power Up Sequence from WAIT Mode .......................................................... 11-5
8-bit Caller ID Data Timing Diagram .............................................................. 11-6
Single Message Format ............................................................................... 11-11
CLID Timing Diagram................................................................................... 11-11
LCD Driver Block Diagram ............................................................................. 12-1
LCD 5:1 bias waveforms ................................................................................ 12-5
LCD 4:1 bias waveforms ................................................................................ 12-6
Voltage Generator.......................................................................................... 12-7
Phase Lock Loop Block Diagram ................................................................... 13-3
Typical Waveform for PLL.............................................................................. 13-3
112-Pin TQFP Mechanical Dimensions ......................................................... 16-2
100-Pin TQFP Mechanical Dimensions ......................................................... 16-3
MC68HC705CL48 Memory Map......................................................................A-2
EPROM Programming Sequence ....................................................................A-4
MC68HC05CL16 Block Diagram .....................................................................B-2
MC68HC05CL48
REV 2.0
MOTOROLA
vii
GENERAL RELEASE SPECIFICATION
June 11, 1997
LIST OF FIGURES
Figure
B-2
B-3
C-1
C-2
Title
Page
MC68HC05CL16 Memory Map........................................................................B-3
MC68HC05CL16 Pin Assignment....................................................................B-4
MC68HC705CL16 Memory Map......................................................................C-2
EPROM Programming Sequence ....................................................................C-4
MOTOROLA
viii
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
LIST OF TABLES
Table
4-1
7-1
7-2
8-1
8-2
9-1
10-1
11-1
11-2
11-3
12-1
12-2
12-3
12-4
12-5
13-1
14-1
14-2
14-3
14-4
14-5
14-6
14-7
B-1
Title
Page
Vector Address for Interrupts and Reset.......................................................... 4-1
Port I/O Pin Functions ...................................................................................... 7-1
PORT C I/O Configuration ............................................................................... 7-2
RTI and COP Rates at 1.8MHz Bus Frequency............................................. 8-18
RTI and COP Rates 17.5kHz Bus Frequency................................................ 8-19
SPI Clock Rates ............................................................................................... 9-4
A/D Channel Assignments ............................................................................. 10-3
Typical Input parameter ................................................................................. 11-9
Critical Design Characteristic ....................................................................... 11-10
Switching Characteristics (VDD= 5V; TA=25 C) .......................................... 11-10
LCD RAM Organization.................................................................................. 12-2
LCD RAM Organization.................................................................................. 12-3
LCD Voltage Characteristic............................................................................ 12-8
Ladder Voltage Values................................................................................... 12-9
Contrast Resistor Values ............................................................................... 12-9
System Clock Frequency Selection ............................................................... 13-1
Register/Memory Instructions ........................................................................ 14-4
Read-Modify-Write Instructions...................................................................... 14-5
Jump and Branch Instructions........................................................................ 14-6
Bit Manipulation Instructions .......................................................................... 14-7
Control Instructions ........................................................................................ 14-7
Instruction Set Summary............................................................................... 14-8
Opcode Map................................................................................................. 14-14
MC68HC05CL16 and MC68HC05CL48 Differences .......................................B-1
MC68HC05CL48
REV 2.0
MOTOROLA
ix
GENERAL RELEASE SPECIFICATION
June 11, 1997
LIST OF TABLES
Table
MOTOROLA
x
Title
Page
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 1
GENERAL DESCRIPTION
The MC68HC05CL48 HCMOS Microcontroller is a member of the M68HC05
family of low cost single chip microcontrollers. It is particularly suitable as a Caller
ID telephone controller. This 8-bit microcontroller unit (MCU) contains on-chip
oscillator, CPU, RAM, ROM, I/O, Timer, Watchdog Timer, SPI, A/D, Caller ID
subsystem, LCD driver and a 32kHz PLL.
1.1
FEATURES
•
Industry standard M68HC05 8-bit CPU core
•
32kHz PLL to generate the 3.6MHz system clock
•
On-chip clock generator can be driven by crystal or external clock
•
47.5k-bytes of user ROM
•
2k-bytes of user RAM (64 bytes for stack)
•
16-bit Timer with 2 input captures and 2 output compares, the two output
compare are used for interrupt generation only
•
15-stage Multi-function Timer
•
One second Watch Timer
•
COP (Computer Operating Properly) Watchdog Reset
•
Serial Peripheral Interface (SPI)
•
Four channel 8-bit A/D Converter
•
Hardware Caller-ID subsystem
•
45 x 16 or 53 x 8 LCD driver
•
24 Bidirectional I/O lines
•
Three software programmable external interrupts in addition to the
standard IRQ interrupt.
MC68HC05CL48
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
•
Five keyboard interrupts.
•
Power saving STOP and WAIT modes
•
Available in 112-pin TQFP package
NOTE
A line over a signal name indicates an active low signal. Any
reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerance or limits are specified in Section 15.
MOTOROLA
1-2
GENERAL DESCRIPTION
MC68HC05CL48
REV 2.0
June 11, 1997
1.2
GENERAL RELEASE SPECIFICATION
MCU STRUCTURE
ACCUMULATOR
M68HC05
MCU
INDEX REGISTER
RESET
RESET
STACK POINTER
0 0 0 0 0 0 0 0 1 1
PROGRAM COUNTER
CONDITION CODE REGISTER
1 1 1 H I N C Z
PTA7/KB7
PTA6/KB6
PTA5/KB5
PTA4/KB4
PTA3/KB3
PTA2/IRQ2
PTA1/IRQ1
PTA0/IRQ0
PORT A
PORT B
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
IRQ/VPP
DATA DIRECTION REGISTER C
USER RAM — 2.0k BYTES
DATA DIRECTION REGISTER B
USER ROM — 47.5k BYTES
CONFIGURATION REGISTER C
DATA DIRECTION REGISTER A
The block diagram of the MC68HC05CL48 is shown in Figure 1-1
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
CPU CLOCK
DIVIDE
BY TWO
INTERNAL CLOCK
PLL
XFC
WTIMER
COP
WATCHDOG
TCAP1
TIMER
TCAP2
AD1
AD0
AD3
SS
SCK
MOSI
AD2
A/D
SPI
MISO
FP[44:0]
VLCD
LCD DRIVER
BP[15:0]
POWER
V0
V1
V2
V3
V4
VDD
VSS
PTC7/TCAP2
PTC6/TCAP1
PORT C
INTERNAL
OSCILLATOR
CALLER ID
OSC1
OSC2
PTC5/AD3
PTC4/AD2
PTC3/ SS
PTC2/MOSI
PTC1/MISO
PTC0/SCK
FSK+
FSK–
RT_L
RD1
RD2
Figure 1-1. MC68HC05CL48 Block Diagram
MC68HC05CL48
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-3
GENERAL RELEASE SPECIFICATION
1.3
June 11, 1997
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
NC
NC
PTC7/TCAP2
NC
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
VDD
VSS
AD1
AD0
FSK+
FSKRT_L
RD1
RD2
OSC2
OSC1
RESET
XFC
IRQ/VPP*
PTA7/KBI7
PTA6/KBI6
V0
FP18
FP17
FP16
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
NC
V4
FP3
FP2
FP1
FP0
PTA0/IRQ0B
PTA1/IRQ1B
PTA2/IRQ2
PTA3/KBI3
PTA4/KBI4
PTA5/KBI5
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
V1
FP43
FP42
FP41
FP40
FP39
FP38
FP37
FP36
FP35
FP34
FP33
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
V2
NC
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
V3
FP44
BP15/FP45
BP14/FP46
BP13/FP47
BP12/FP48
BP11/FP49
BP10/FP50
BP9/FP51
BP8/FP52
BP7
BP6
BP5
BP4
BP3
BP2
BP1
BP0
NC
NC
VLCD
PTC0/SCK
PTC1/MISO
PTC2/MOSI
PTC3/SS
PTC4/AD2
PTC5/AD3
PTC6/TCAP1
The MC68HC05CL48 pin assignments for the 112-pin TQFP package is shown in
Figure 1-2.
*VPP is available on MC68HC705CL48 only
Figure 1-2. MC68HC05CL48 Pin Assignments
MOTOROLA
1-4
GENERAL DESCRIPTION
MC68HC05CL48
REV 2.0
June 11, 1997
1.4
GENERAL RELEASE SPECIFICATION
SIGNAL DESCRIPTION
The following paragraphs give a description of the general function of each pin.
1.4.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS pins. VDD is connected to a
regulated positive supply and VSS is connected to ground. These pins are located
close to each other for low EMI, Electro Magnetic Interference, emission.
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, take special care to provide good power supply bypassing at the
MCU. Use bypass capacitors with good high-frequency characteristics, and
position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
VDD
1uF
0.47uF (Ceramic)
VSS
Figure 1-3. Power Supply Decoupling
1.4.2 RESET
This pin can be used as an input to reset the MCU to a known start-up state by
pulling it to the low state. The RESET pin contains a steering diode to discharge
any voltage on the pin to VDD, when the power is removed. The RESET pin
contains an internal Schmitt trigger to improve its noise immunity as an input. The
RESET pin has an internal pulldown device that pulls the RESET pin low when
there is an internal COP Watchdog reset or during the power-on reset cycles.
Refer to Section 5.
1.4.3 IRQ
This pin has an option in the option register that provides two different choices of
interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as
part of its input to improve noise immunity. Refer to Section 4.
MC68HC05CL48
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-5
GENERAL RELEASE SPECIFICATION
June 11, 1997
1.4.4 IRQ0, IRQ1, IRQ2
These three pins provide additional sources of interrupt. They are all edgetriggered only. IRQ0 and IRQ1 are both negative-edge triggered only and IRQ2
can be triggered on both rising and falling edges. Refer to Section 4.3.2. The
IRQ0, IRQ1 and IRQ2 pins contain internal Schmitt trigger as part of its input to
improve noise immunity.
1.4.5 OSC1, OSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal, a
ceramic resonator or an external signal to these pins provides the clock to the on
chip PLL.
The OSC1 and OSC2 pins can accept the following:
1. A crystal as shown in Figure 1-4(a)
2. A ceramic resonator as shown in Figure 1-4(a)
3. An external clock signal as shown in Figure 1-4(b)
The system clock can either be the 32kHz external clock or a higher frequency
clock from the PLL. See Section 13.
1.4.5.1
Crystal with no Internal Components
The circuit in Figure 1-4(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. Follow the crystal manufacturer’s recommendations, as the
crystal parameters determine the external component values required to provide
maximum stability and reliable start-up. The load capacitance values used in the
oscillator circuit design should include all stray capacitance. Mount the crystal and
components as close as possible to the pins for start-up stabilization and to
minimize output distortion.
1.4.5.2
Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use
the circuit in Figure 1-4(a) for a ceramic resonator and follow the resonator
manufacturer’s recommendations, as the resonator parameters determine the
external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all
stray capacitance. Mount the resonator and components as close as possible to
the pins for start-up stabilization and to minimize output distortion
MOTOROLA
1-6
GENERAL DESCRIPTION
MC68HC05CL48
REV 2.0
June 11, 1997
To VDD (or STOP)
OSC1
MCU
GENERAL RELEASE SPECIFICATION
To VDD (or STOP)
OSC1
OSC2
MCU
OSC2
10M
unconnected
100k
External Clock
27pF
27pF
∗
(a) Crystal or Ceramic Resonator
Connections
X-tal = Nitsuko EX-0228-0150-NTK
(b) External Clock Source
Connections
∗: Additional capacitance may be required for Ceramic Resonator option. Follow the
Ceramic Resonator manufacturer’s recommendations.
Figure 1-4. Oscillator Connections
1.4.6 External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-4 (b)
1.4.7 PTA0-PTA7
These I/O lines comprise Port A. The state of any pin is software programmable
and all port lines are configured as inputs during power-on or reset. PTA0-PTA7
are also associated with three external IRQ and five Keyboard interrupt functions.
See Section 7 for more details on the I/O ports.
1.4.8 PTB0-PTB7
These I/O lines comprise Port B. The state of any pin is software programmable
and all port lines are configured as inputs during power-on or reset.
1.4.9 PTC0-PTC7
These I/O lines comprise Port C. The state of any pin is software programmable
and all port lines are configured as inputs during power-on or reset. PTC0-PTC7
MC68HC05CL48
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-7
GENERAL RELEASE SPECIFICATION
June 11, 1997
when not used as I/O pins can be configured as two A-to-D pins, two Timer pins
and four SPI pins. See Section 7 for more details on the I/O ports.
1.4.10 SCK
This is the serial clock signal of the SPI. This pin can be configured as PTC0 pin
when the SPI function is not used.
1.4.11 MISO, MOSI
These are the master-in slave-out (MISO) and master-out slave-in (MOSI) data
pins for the SPI. These two pins can be configured as PTC1 and PTC2 pins
respectively when the SPI function is not used.
1.4.12 SS
This is the slave select pin for the SPI. This pin can be configured as PTC3 pin
when the SPI function is not used.
1.4.13 AD0-AD3
These four lines are the A/D inputs. AD2 and AD3 can be configured as PTC4 and
PTC5 pins respectively when not used as A-to-D inputs.
1.4.14 TCAP1
The TCAP1 input controls the input capture 1 feature of the on-chip programmable
timer system. Refer to Section 8 for additional information. This pin can be
configured as PTC6 pin when the timer input capture function is not used.
1.4.15 TCAP2
The TCAP2 input controls the input capture 2 feature of the on-chip programmable
timer system. Refer to Section 8 for additional information. This pin can be
configured as PTC7 pin when the timer input capture function is not used.
1.4.16 FSK+, FSK–
These two inputs are the non-inverting and inverting FSK signals respectively.
MOTOROLA
1-8
GENERAL DESCRIPTION
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
1.4.17 RT_L
This pin should be connected with an external pull-up resistor to vDD. This pin will
be pulled low when RDI1 rises above one volt.
1.4.18 RD1, RD2
These inputs are incoming ring qualifiers.
1.4.19 BP0 - BP15
These are the back plane drivers dedicated to the LCD subsystem. BP8 - BP15
will be used as FP45 - FP52 when the LCD driver is only driving 8 back planes.
1.4.20 FP0 - FP44
These are the front plane drivers dedicated to the LCD subsystem.
1.4.21 VLCD, V0, V1, V2, V3, V4
VLCD is the power supply input for the LCD voltage generator. V0, V1, V2, V3 and
V4 are the internal resistor ladder node voltage. An external cap with one terminal
connected to GND should be connected to each of these four pins.
1.4.22 XFC
One terminal of the Phase-Locked Loop external capacitor should be connected
here, the other terminal should be connected to GND.
XFC
0.1uF
Phase-Locked Loop External Capacitor
MC68HC05CL48
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-9
GENERAL RELEASE SPECIFICATION
MOTOROLA
1-10
June 11, 1997
GENERAL DESCRIPTION
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 2
MEMORY
The MC68HC05CL48 has a 64k-byte memory map, consisting of user ROM, user
RAM, Self-Check ROM, LCD RAM and I/O as shown in Figure 2-1.
2.1
MEMORY MAP
The MC68HC05CL48 memory map is shown in Figure 2-1.
2.2
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000-$002F. The overall
organization of these registers is shown in Figure 2-1. The bit assignments for
each register are shown in Figure 2-2, Figure 2-3 and Figure 2-4. Reading from
unimplemented bits will return unknown states, and writing to unimplemented bits
will be ignored.
2.2.1 Option Register ($1F)
This register can be written to only once following a Power-On-Reset (POR) but
can be read at any time. This register configures the MCU options to suit the
user’s application.
OPT
$001F
7
6
OSC_ON
COP
1
1
5
4
3
2
1
0
READ
INTO
WRITE
POR
U
U
U
U
1
U
U = UNAFFECTED
OSC_ON
1 = Oscillator is switched on in STOP mode.
0 = Oscillator is switched off in STOP mode.
COP
Refer to Section 8 for detailed informations on COP.
1 = Enable the COP watchdog reset.
0 = Disable the COP watchdog reset.
MC68HC05CL48
REV 2.0
MEMORY
MOTOROLA
2-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
INTO
1 = allow negative edge-triggered interrupt on IRQ pin.
0 = allow ‘low’ level-triggered and negative edge-triggered interrupt on
IRQ pin.
2.3
LCD RAM
The LCD RAM consists of 90 bytes at locations ($0930 thru $095C) and ($0A30
thru $0A5C).
2.4
RAM
The total RAM consists of 2.0k bytes (including the stack) at locations $0030 thru
$082F. The stack begins at address $00FF and proceeds down to $00C0. The
stack pointer can access 64 locations from $00FF to $00C0. Using the stack area
for data storage or temporary work locations requires care to prevent it from being
over written due to stacking from an interrupt or subroutine call.
2.5
ROM
There are a total of 47.5k bytes of user ROM from locations $4000 thru $FDFF for
user program storage and 16 bytes for user vectors at locations $FFF0 thru
$FFFF.
2.6
I/O MAPPED REGISTERS
There are 48 internal registers at locations $0000 thru $002F. These are
illustrated in Figure 2-2, Figure 2-3 and Figure 2-4.
MOTOROLA
2-2
MEMORY
MC68HC05CL48
REV 2.0
June 11, 1997
$0000
$002F
$0030
I/O Register
48 Bytes
Port A Data Register
$00
Port B Data Register
$01
RAM
144 Bytes
Port C Data Register
$02
Port A Direction Register
$03
Port B Direction Register
Port C Direction Register
$04
Stack
64 Bytes
Timer Pin Configuration Register
LCD Control Register
$06
Core Timer Control/Status Register
$08
Core Timer Register
Caller ID Control/Status Register 1
$09
$0A
Caller ID Control/Status Register 2
$0B
Caller ID Control/Status Register 3
PLL Status/Data Register
$0C
Caller ID Data Register
Input Capture High Register 2
$0E
Input Capture Low Register 2
$10
Timer Control Register
$11
Timer Status Register
Input Capture High Register 1
$12
Input Capture Low Register 1
$14
Output Compare High Register 1
$15
Output Compare Low Register 1
Output Compare High Register 2
$16
Output Compare Low Register 2
$18
$00C0
$00FF
$0100
RAM
1840 Bytes
$082F
$0830
$092F
$0930
$095C
$095D
$0A2F
$0A30
$0A5C
$0A5D
$3FFF
$4000
$FDFF
$FE00
GENERAL RELEASE SPECIFICATION
Not Used
LCD RAM
45 Bytes Block1
Not Used
LCD RAM
45 Bytes Block2
Not Used
ROM
47.5k Bytes
Self-check ROM
496 Bytes
$FFDF
$FFE0 Self-check Vectors
16 Bytes
$FFEF
$FFF0
User Vectors
16 Bytes
$FFFF
$FFF0
Ctimer/WTimer
$FFF1
$FFF2
IRQn/KBI $FFF3
$FFF4
Caller_ID $FFF5
$FFF6
SPI
$FFF7
$FFF8
Timer
$FFF9
$FFFA
IRQ
$FFFB
$FFFC
SWI
$FFFD
$FFFE
Reset
$FFFF
$05
$07
$0D
$0F
$13
$17
Counter High Register
$19
Counter Low Register
$1A
Alternate Counter High Register
$1B
Alternate Counter Low Register
$1C
External Interrupt Control Register
External Interrupt Status Register
$1D
Option Register
SPI Control Register
$1F
SPI Status Register
SPI Data Register
$21
A/D Control and Status Register
$24
A/D Data Register
$25
Reserved for EPROM (EPCR)
$26
$1E
$20
$22
Watch Timer Control & Status Register $23
$27
Reserved
$2F
Figure 2-1. MC68HC05CL48 Memory Map
MC68HC05CL48
REV 2.0
MEMORY
MOTOROLA
2-3
GENERAL RELEASE SPECIFICATION
ADDR
REGISTER
$0000
PORTA
$0001
PORTB
$0002
PORTC
$0003
DDRA
$0004
DDRB
$0005
DDRC
$0006
TIMCONF
$0007
LCDCR
$0008
CTCSR
$0009
CTCR
$000A
CLCSR1
$000B
CLCSR2
$000C
CLCSR3
$000D
PCSR
$000E
CDDR
$000F
IC2H
ACCESS
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
June 11, 1997
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
CONF7
CONF6
CC3
CC2
CC1
CC0
MX8
BIAS5
CTOF
RTIF
CTOFE
RTIE
0
0
CT7
CT6
CT5
CT4
CT3
CT2
DISON
RT1
RT0
CT1
CT0
RDO
CDO
RD
CD
RDOE
CDOE
W
R
RDIF
W
R
RDPW
W
R
W
R
W
R
W
R
RDIE
CDIF
CDIE
CIDSD
CDPW
CDRE
SDSL
PON
PCLK
CDD7
CDD6
CDD5
CDD4
IC2:15
IC2:14
IC2:13
IC2:12
DRIE
CDRF
FREQ1
FREQ0
CDD3
CDD2
CDD1
CDD0
IC2:11
IC2:10
IC2:9
IC2:8
W
Figure 2-2. MC68HC05CL48 I/O Registers $0000-$000F
MOTOROLA
2-4
MEMORY
MC68HC05CL48
REV 2.0
June 11, 1997
ADDR
REGISTER
$0010
IC2L
$0011
TCR
$0012
TSR
$0013
IC1H
$0014
IC1L
$0015
OC1H
$0016
OC1L
$0017
OC2H
$0018
OC2L
$0019
TCH
$001A
TCL
$001B
ACH
$001C
ACL
$001D
EXICR
$001E
EXISR
$001F
OPT
GENERAL RELEASE SPECIFICATION
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
IC2:7
IC2:6
IC2:5
IC2:4
IC2:3
IC2:2
IC2:1
IC2:0
IC1IE
IC2IE
OC1IE
OC2IE
TOIE
IEDG2
IEDG1
IC1F
IC2F
OC1F
OC2F
TOF
IC1:15
IC1:14
IC1:13
IC1:12
IC1:11
IC1:10
IC1:9
IC1:8
IC1:7
IC1:6
IC1:5
IC1:4
IC1:3
IC1:2
IC1:1
IC1:0
OC1:15
OC1:14
OC1:13
OC1:12
OC1:11
OC1:10
OC1:9
OC1:8
OC1:7
OC1:6
OC1:5
OC1:4
OC1:3
OC1:2
OC1:1
OC1:0
OC2:15
OC14
OC2:13
OC2:12
OC2:11
OC2:10
OC2:9
OC2:8
OC2:7
OC2:6
OC2:5
OC4
OC2:3
OC2:2
OC2:1
OC2:0
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
TIMER RESET
AC15
AC14
AC13
AC7
AC6
AC5
AC12
AC11
AC10
AC9
AC8
AC4
AC3
AC2
AC1
AC0
W
R
W
R
W
R
TIMER RESET
KBE7
KBE6
KBE5
KBE4
KBE3
IRQE2
IRQE1
IRQE0
KBIF7
KBIF6
KBIF5
KBIF4
KBIF3
IRQF2
IRQF1
IRQF0
OSC_ON
COP
W
R
W
INTO
Figure 2-3. MC68HC05CL48 I/O Registers $0010-$001F
MC68HC05CL48
REV 2.0
MEMORY
MOTOROLA
2-5
GENERAL RELEASE SPECIFICATION
ADDR
REGISTER
$0020
SPCR
$0021
SPSR
$0022
SPDR
$0023
WTCSR
$0024
ADSCR
$0025
ADDR
$0026
Reserved for
EPROM (EPCR)
$0027
Not Used
$0028
Not Used
$0029
Not Used
$002A
Not Used
$002B
Not Used
$002C
Not Used
$002D
Not Used
$002E
Reserved for TEST
$002F
TEST
ACCESS
June 11, 1997
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SPIE
SPE
-
MSTR
CPOL
CPHA
SPR1
SPR0
SPIF
WCOL
0
MODF
0
0
0
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
R
W
R
W
R
W
R
WTOFF
W
R
COCO
W
R
W
ADDR7
ADRC
ADON
ADDR6
ADDR5
0
ADDR4
ADDR3
0
WTR
WTOIE
WTOF
CH2
CH1
CH0
ADDR2
ADDR1
ADDR0
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Figure 2-4. MC68HC05CL48 I/O Registers $0020-$002F
MOTOROLA
2-6
MEMORY
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 3
CPU
The MC68HC05CL48 has an 64k memory map. Therefore it uses all 16 bits of the
address bus. The stack has only 64 bytes. Therefore, the stack pointer has been
reduced to only 6 bits and will only decrement down to $00C0 and then wraparound to $00FF. All other instructions and registers behave as described in this
chapter.
3.1
REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memory map. These five registers are shown in Figure 3-1 and are
described in the following paragraphs.
7
15
14
13 12
0
0
0
0
11 10
0
0
9
8
0
0
1
6
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
PC
H
I
N
Z
C
CC
HALF CARRY
INTERRUPT MASK
NEGATIVE
ZERO
CARRY
Figure 3-1. MC68HC05 Programming Model
3.1.1 Accumulator (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
MC68HC05CL48
REV 2.0
CPU
MOTOROLA
3-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
or non-arithmetic operations. The accumulator is unaffected by a reset of the
device.
3.1.2 Index Register (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU finds the operand address by adding the
index register contents to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register
contents to a 16-bit immediate value
The index register can also serve as an auxiliary accumulator for temporary
storage.The index register is unaffected by a reset of the device.
3.1.3 Stack Pointer (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register internally. In devices
with memory maps less than 64 kbytes the unimplemented upper address lines
are ignored. The stack pointer contains the address of the next free location on
the stack. During a reset or the reset stack pointer (RSP) instruction, the stack
pointer is set to $00FF. The stack pointer is then decremented as data is pushed
onto the stack and incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to
0000000011. The six least significant register bits are appended to these ten fixed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 ($40) locations. If 64 locations are exceeded, the
stack pointer wraps around and writes over the previously stored information. A
subroutine call occupies two locations on the stack, and an interrupt uses five
locations.
3.1.4 Program Counter (PC)
The program counter shown in Figure 3-1 is a 16-bit register internally. In devices
with memory maps less than 64 Kbytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
MOTOROLA
3-2
CPU
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
3.1.5 Condition Code Register (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fifth bit is the interrupt
mask. These bits can be individually tested by a program, and specific actions can
be taken as a result of their state. The condition code register should be thought of
as having three additional upper bits that are always ones. Only the interrupt mask
is affected by a reset of the device. The following paragraphs explain the functions
of the lower five bits of the condition code register.
3.1.5.1
Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.1.5.2
Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), STOP, or WAIT instructions.
3.1.5.3
Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often-tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
MC68HC05CL48
REV 2.0
CPU
MOTOROLA
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GENERAL RELEASE SPECIFICATION
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to the state of the flag.
3.1.5.4
Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
3.1.5.5
Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is not set by an INC or DEC instruction.
MOTOROLA
3-4
CPU
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding
interrupt enable bit is set the processor will proceed with interrupt processing.
Otherwise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and finally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table 4-1 will be
serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
Table 4-1. Vector Address for Interrupts and Reset
Interrupts
CPU Interrupt
Vector Addresses
Reset
RESET
$FFFE-$FFFF
Software
SWI
$FFFC-$FFFD
External Interrupt
IRQ
$FFFA-$FFFB
Timer
TCAP1,TCAP2,TCMP1,TCMP2
$FFF8-$FFF9
SPI
SPI
$FFF6-$FFF7
Caller ID
CDI, RDI, CDRI, RT_L
$FFF4-$FFF5
External Interrupt/Keyboard Interrupt
IRQ0, IRQ1, IRQ2, KBI[7:3]
$FFF2-$FFF3
Core Timer/Watch Timer
Ctimer, WTimer
$FFF0-$FFF1
When an interrupt is to be processed the CPU fetches the address of the
appropriate interrupt software service routine from the vector table at locations
$FFF0 thru $FFFF as defined in Table 4-1.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from
the stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
MC68HC05CL48
REV 2.0
INTERRUPTS
MOTOROLA
4-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
From
RESET
Y
Is
I-Bit
Set?
N
IRQ
Interrupt?
Y
Clear IRQ
Latch
N
Timer
Interrupt?
Y
N
SPI
Interrupt?
Y
N
Caller_id
Interrupt?
Y
N
IRQn/KBI
Interrupt?
Y
N
CTimer/WTimer Y
Interrupt?
PC -> (SP,SP-1)
X -> (SP-2)
A -> (SP-3)
CC -> (SP-4)
N
Fetch Next
Instruction
SWI
Instruction?
Set I-Bit in CCR
Y
Load Interrupt
Vectors To PC
N
RTI
Instruction?
N
Restore Registers
From Stack
CC,A,X,PC
Y
Execute
Instruction
Figure 4-1. Interrupt Processing Flowchart
MOTOROLA
4-2
INTERRUPTS
MC68HC05CL48
REV 2.0
June 11, 1997
4.1
GENERAL RELEASE SPECIFICATION
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-1. A low level input on the RESET
pin or internal generated reset signal causes the program to vector to its starting
address which is specified by the contents of memory locations $FFFE and
$FFFF. The I-bit in the condition code register is also set. The MCU is configured
to a known state during this type of reset as described in Section 5.
4.2
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero
(interrupts enabled), the SWI instruction executes after interrupts which were
pending before the SWI was fetched, or before interrupts if interrupts were
generated after the SWI was fetched. The interrupt service routine address is
specified by the contents of memory locations $FFFC and $FFFD.
4.3
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are six types of hardware
interrupts which are explained in the following sections.
4.3.1 External Interrupt (IRQ)
If the IRQ option is both level and edge sensitive triggering (INTO=0), a low level
or an negative edge at the IRQ pin and the interrupt mask bit of the condition code
register is cleared will cause an EXTERNAL Interrupt to occur. If the MCU has
finished with the interrupt service routine, but the IRQ pin is still low, the
EXTERNAL Interrupt will start again. In fact, the MCU will keep on servicing the
EXTERNAL Interrupt as long as the IRQ pin is low. If the IRQ pin goes low for a
while and resumes to high (a negative pulse) before the interrupt mask bit is
cleared, the MCU will not recognize there was an interrupt request, and no
interrupt will occur after the interrupt mask bit is cleared, i.e. there is no latch for
the interrupt signal for the level sensitive triggering.
If the IRQ option is negative edge sensitive triggering (INTO=1), a negative edge
occurs at the IRQ pin and the interrupt mask bit of the condition code register is
cleared will cause an EXTERNAL Interrupt to occur. If the MCU has finished with
the interrupt service routine, but the IRQ pin has not resumed back to high, no
further interrupt will be generated. The interrupt logic recognizes negative edge
transitions and pulses (special case of negative edges) only. If the negative edge
occurs during the interrupt mask bit is set, the interrupt signal will be latched, an
MC68HC05CL48
REV 2.0
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
interrupt will occur as soon as the interrupt mask bit is cleared. The latch will be
cleared by RESET or cleared automatically during fetch of the EXTERNAL
Interrupt vectors. Therefore, one (and only one) external interrupt edge could be
latched during the interrupt mask bit is set.
The service routine address is specified by the contents of $FFFA and $FFFB.
Figure 4-2 shows both a block diagram and the two methods for the interrupt line
(IRQ) to the processor. The first method is single pulses on the interrupt line
spaced far enough apart to be serviced. The minimum time between pulses is a
function of the number of cycles required to execute the interrupt service routine
plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the
MCU software has exited the routine (an RTI occurs). The second configuration
shows several interrupt line “wire-ANDed” to perform the interrupts at the
processor. Thus, if after servicing one interrupt and the interrupt line remains low,
then the next interrupt is recognized.
NOTE
INTO is located at bit-1 of the Option Register at $001F, and is set
by reset. The Option Register can only be written once after reset.
MOTOROLA
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INTERRUPTS
MC68HC05CL48
REV 2.0
June 11, 1997
D
IRQ pin
GENERAL RELEASE SPECIFICATION
Q
Power-On Reset
CK
R
External Reset
External Interrupt
Being Serviced
(read of vectors)
INTO bit
External
Interrupt
Request
I bit (CCR)
(a) Interrupt Functional Block Diagram
Edge-sensitive Trigger Condition
IRQ
The minimum pulse width tILIH is one
internal bus period.
The period tILIL should not be less than the
number of cycles it takes to execute the
interrupt service routine plus 21 cycles
tILIH
tILIL
IRQ1
Level-sensitive Trigger Condition
tILIH
If after servicing an interrupt, the IRQ
remains low, then the next interrupt is
recognized.
Normally used with pull-up resistor for
Wire-Ore connected
IRQn
IRQ
(MCU)
(b) Interrupt Mode Diagram
Figure 4-2. External Interrupts
MC68HC05CL48
REV 2.0
INTERRUPTS
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GENERAL RELEASE SPECIFICATION
June 11, 1997
4.3.2 External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7])
4.3.2.1
IRQ0, IRQ1, IRQ2
IRQ0, IRQ1, IRQ2 interrupt function is associated with PTA[0:2]. IRQ[0:2]
interrupts behave similar to IRQ except these are edge-triggered only. IRQ0 and
IRQ1 are both negative-edge triggered only and IRQ2 can be triggered on both
rising and falling edges. To enable this function, IRQE0, IRQE1 and IRQE2 bit of
the external interrupt control register (EXICR $1D) should be set first. When an
appropriate edge occurring at the IRQ0, IRQ1 or IRQ2 pin and the interrupt mask
bit of the condition code register is cleared will cause an external interrupt to
occur. If the MCU has finished with the service routine, but the external interrupt
pin has not resumed backed to high, no further interrupt will be generated. If the
appropriate triggering edge occurs when the interrupt mask bit is set, the interrupt
signal will be latched, and interrupt will occur as soon as the interrupt mask bit is
cleared. The latch for IRQ0, IRQ1 and IRQ2 are cleared by reset or cleared by
writing a ‘0’ to the IRQF0, IRQF1 and IRQF2 bit in the external interrupt status
register ($1E EXISR) in the service routine.
The interrupt service routine is specified by the contents of the memory locations
$FFF2 and $FFF3.
To prevent unwanted interrupts generated on RQ0, IRQ1 pins. A logic ‘1’ should
be written to these pins before setting their corresponding interrupt enable bits.
Likewise, A logic ‘1’ should be written to IRQ2 pin prior to setting the IRQ2
interrupt enable bit.
4.3.2.2
Keyboard Interrupts
Keyboard Interrupt function is associated with PTA[3:7]. The keyboard interrupt
function is enabled by setting the individual interrupt enable bits KBE[3:7]
(bits[3:7] of EXICR at $001D). When the KBE bit is set, the corresponding Port A
pin will be configured as an input pin, regardless of the DDR setting, and a 100k
ohm pull-up resistor is connected to the pin, as shown in Figure 4-3. When a high
to low transition is sensed on the pin, a keyboard interrupt will be generated,
provided the I-bit in the CCR is cleared.
The interrupt signal is latched, and it should be cleared by writing a ‘0’ to the
corresponding KBIF bit in the external interrupt status register ($1E EXISR) in the
interrupt service routine. This should be cleared after the key is debounced, or
unwanted keyboard interrupt signal will be generated.
The Keyboard Interrupt is negative-edge sensitive only, and the interrupt service
routine is specified by the contents of the memory locations $FFF2 and $FFF3.
MOTOROLA
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INTERRUPTS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
To prevent unwanted interrupts generated on KBI[3:7] pins. A logic ‘1’ should be
written to these pins before setting their corresponding interrupt enable bits.
KBI[3.7]
KBE[3.7]
VDD
100k
DDR(3-7)
Pad
Logic
Internal Data bits [3.7], Port A
External pins PTA[3.7]
Figure 4-3. Keyboard Interrupt Circuitry
4.3.2.3
External Interrupt Control Register (EXICR $001D)
EXICR
$001D
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
READ
WRITE
RESET
KBE[7:3]
1 = Enable Keyboard interrupt on PTA[7:3] respectively.
0 = Disable Keyboard interrupt on PTA[7:3] respectively.
IRQE[2:0]
1 = Enable IRQ interrupt on PTA[2:0] respectively.
0 = Disable IRQ interrupt PTA[2:0] respectively.
MC68HC05CL48
REV 2.0
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
4.3.2.4
June 11, 1997
External Interrupt Status Register (EXISR)
EXISR
$001E
READ
7
6
5
4
3
2
1
0
KBIF7
KBIF6
KBIF5
KBIF4
KBIF3
IRQF2
IRQF1
IRQF0
0
0
0
0
0
0
0
0
WRITE
RESET
KBIF[7:3]
The keyboard interrupt flag bit is set to ‘1’ when a negative edge has been
detected at the pin and the corresponding enable bit has been set. Writing a ‘0’
to this bit will clear the corresponding interrupt flag. This bit should be cleared
by software in the keyboard interrupt service routine, or the CPU will keep on
serving this interrupt.
IRQF[2:0]
The external IRQ flag bit is set to ‘1’ when an appropriate edge has been
detected at the pin and the corresponding enable bit has been set. Writing a “0”
to this bit will clear the IRQ interrupt flag. This bit should be cleared by software
in the keyboard interrupt service routine, or the CPU will keep on serving this
interrupt.
4.3.3 Caller ID Interrupt (RDI/CDI,CDRI)
This interrupt is caused by the Caller ID module when a valid RT_L signal, a Ring
is detected, a Carrier is detected or when the 8-bit Called ID data is ready to be
read. The enable and flag bits for the Ring Detect and the Carrier detect are
located in CLCSR1 register and the enable and flag bits for the Called ID data
ready are located in CLCSR3 register. The RT_L is always active once it is
enabled by a metal mask, see Section 11. All four interrupts will vector to the
same interrupt service routine located at the addresses specified by the contents
of memory locations $FFF4-$FFF5. The RT_L interrupt will wake up the MCU
from the STOP and WAIT mode whereas the Ring Detect, Carrier Detect and
Data Ready interrupts will wake up the CPU from Wait mode. See Section 6.
4.3.4 TIMER Interrupt
The TIMER interrupt is generated by the multi-function Timer when a timer
overflow or an input capture or a output compare has occurred as described in
Section 8. The interrupt enable bit and flag for the Timer interrupt are located in
the Timer Control and Status Registers TCR and TSR located at $0011 and $0012
respectively. The I-bit in the CCR must be clear in order for the Timer interrupt to
MOTOROLA
4-8
INTERRUPTS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
be enabled. This interrupt will vector to the interrupt service routine located at the
address specified by the contents of memory locations $FFF8 and $FFF9.
4.3.5 SPI Interrupt
The SPI interrupt is generated by serial peripheral interface as described in
Section 9. The interrupt enable bits for the SPI interrupt is in the SPI Control
Register (SPCR) at location $0020. The I-bit in the CCR must be clear in order for
the SPI interrupt to be enabled. These interrupts will vector to the same interrupt
service routine located at the address specified by the contents of memory
locations $FFF6 and $FFF7.
4.3.6 CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer)
4.3.6.1
Core Timer Interrupt
The CTIMER interrupt is generated by the Core Timer when a core timer overflow,
or real time interrupt has occurred as described in Section 8. The interrupt enable
bits and flags for the Core Timer interrupts are located in the Core Timer Control
and Status Register (CTCSR) located at $0008. The I-bit in the CCR must be
clear in order for the CTIMER interrupt to be enabled.
4.3.6.2
Watch Timer Interrupt
The WTimer interrupt is generated by the Watch Timer when a 1 second timer
overflow interrupt has occurred as described in Section 8. The interrupt enable
bits and flags for the Watch Timer interrupt are located in the Watch Timer Control
and Status Register (WTCSR) located at $0023. The I-bit in the CCR must be
clear in order for the WTIMER interrupt to be enabled.
4.3.6.3
Interrupt Vector
The above two interrupts will vector to the same interrupt service routine located
at the address specified by the contents of memory locations $FFF0 and $FFF1.
MC68HC05CL48
REV 2.0
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
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INTERRUPTS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
The MCU can be reset in three ways:
5.1
•
by the initial power-on reset function, (POR)
•
by an active low input to the RESET pin, (RESET)
•
by a COP watchdog timer reset, (COPR)
EXTERNAL RESET (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a
Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. This external reset occurs
whenever the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low input will
generate the RST signal and reset the CPU and peripherals. Termination of the
external RESET input can alter the operating mode of the MCU.
The RESET pin can also be pulled to a low state by an internal pulldown that is
activated by the internal COP Watchdog or Power-on resets. This RESET pin
pulldown device will only be activated for one cycle of the internal clock, PH2,
when a COP Watchdog reset occurs; or will remain activated as long as counting
the power-on reset cycles or the low voltage is detected.
5.2
POWER-ON RESET (POR)
The internal POR is generated on power-up to allow the clock oscillator to
stabilize. The POR is strictly for power turn-on conditions and is not able to detect
a drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 488 internal processor bus clock cycles (PH2) after the oscillator
becomes active. The RESET pin will be pulled down internally during these
cycles.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this 488 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
MC68HC05CL48
REV 2.0
RESETS
MOTOROLA
5-1
GENERAL RELEASE SPECIFICATION
5.3
June 11, 1997
COMPUTER OPERATING PROPERLY RESET (COPR)
The internal COPR reset is generated automatically (if enabled) by a time-out of
the COP Watchdog Timer. This time-out occurs if the counter in the COP
Watchdog Timer is not reset (cleared) within a specific time by a program reset
sequence. The COP Watchdog Timer can be enabled by setting bit 6 of the Option
Register at $001F. Refer to Section 8 for more information on this time-out
feature.
The COP Watchdog reset will activate the internal pulldown device connected to
the RESET pin for one cycle of the internal clock, PH2.
The COP register shares the same address ($FFF0) with the MS byte of the Core
Timer Interrupt Vector as shown below. Reading this location will return the MS
byte of the Core Timer Interrupt Vector. Writing $00 to this location clears the COP
watchdog timer.
7
COPR
$FFF0
6
5
4
3
2
1
0
READ
WRITE
POR
COPR
U
U
U
U
U
U
U
0
U = UNAFFECTED
MOTOROLA
5-2
RESETS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 6
LOW POWER MODES
6.1
LOW-POWER MODES
The MC68HC05CL48 has two low-power operational modes. The WAIT and
STOP instructions provide two modes that reduce the power required for the MCU
by stopping various internal clocks and/or the on-chip oscillator. The STOP and
WAIT instructions are not normally used if the COP Watchdog Timer is enabled.
The flow of the STOP and WAIT modes is shown in Figure 6-1.
6.1.1 STOP Instruction
Execution of the STOP instruction, places the MCU in its lowest power
consumption mode. In the STOP Mode the internal oscillator is turned off, halting
all internal processing, including the COP Watchdog Timer.
When the CPU enters STOP Mode, the I-bit in the Condition Code Register will be
cleared automatically. This enable the external hardware interrupt to wake up the
MCU. All other registers and memory remain unaltered. All input/output lines
remain unchanged.
The MCU can be brought out of the STOP Mode only by a Caller ID (RT_L)
interrupt, WTIMER interrupt, a hardware interrupt “IRQ, IRQ(n), KBI(n)” or an
externally generated RESET. When exiting the STOP Mode the internal oscillator
will resume after a 488 internal processor clock cycle oscillator stabilization delay.
6.1.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Other Internal clocks
remain active, permitting interrupts to be generated from the functional blocks, or
a reset to be generated from the COP Watchdog Timer. The Timer may be used to
generate a periodic exit from the WAIT Mode. Execution of the WAIT instruction
automatically clears the I-bit in the Condition Code Register, so that any hardware
interrupt can wake up the MCU. All other registers, memory, and input/output lines
remain in their previous states.
MC68HC05CL48
REV 2.0
LOW POWER MODES
MOTOROLA
6-1
GENERAL RELEASE SPECIFICATION
6.2
June 11, 1997
DATA-RETENTION MODE
The contents of RAM and CPU registers are retained at supply voltage as low as
2.0 VDC. This is called the data-retention mode where the data is held, but the
device is not guaranteed to operate. The RESET pin must be held low during
data-retention mode.
To put CPU into data retention mode with the lowest power:
•
Clear OSC_ON bit in OPTION register.
•
Run system with Oscillator clock.
•
Execute STOP instruction to put CPU in STOP mode.
•
Drive RESET pin to logical zero.
•
Lower the VDD voltage. The RESET must remain low continuously
during data retention mode.
To take the CPU out of data retention mode:
6.3
•
Return VDD to normal operating level.
•
Return the RESET pin to logical one.
COP WATCHDOG TIMER CONSIDERATIONS
If the COP Watchdog Timer is selected by setting the enable bit, any execution of
the STOP instruction (either intentional or inadvertent due to the CPU being
disturbed) will be executed as a WAIT instruction. It is because, if a STOP
instruction could be executed, while the COP was enabled. The STOP instruction
will cause the oscillator to halt and prevent the COP Watchdog Timer from timing
out. Therefore, the STOP instruction will put the MCU into WAIT mode, instead of
STOP mode, if COP is enabled.
If the COP Watchdog Timer is selected, the COP will reset the MCU when it times
out. Therefore, it is recommended that the COP Watchdog should be disabled for
a system that must have intentional uses of the WAIT Mode for periods longer
than the COP time-out period.
MOTOROLA
6-2
LOW POWER MODES
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
STOP
WAIT
Stop External Oscillator,
Stop Internal Timer CLock,
and Reset Start-up Delay
External Oscillator Active,
and Internal
Timer Clock Active
Stop Internal Processor Clock,
Clear I-Bit in CCR
Stop Internal Processor Clock,
Clear I-Bit in CCR
External
RESET?
Y
Y
External
RESET?
N
External
H/W
Interrupt?
N
Y
Y
Internal
COP
Reset?
N
N
Caller_ID (RT_L) Y
Interrupt?
Restart External Oscillator,
and Stabilization Delay
N
WTimer
Interrupt?
N
Y
Y
N
Y
N
End
of Start-up
Delay?
External
H/W
Interrupt?
Internal
Interrupt?
N
Y
Y
Restart
Internal Processor Clock
Caller_id
Interrupt?
N
1. Fetch Reset Vector
or
2. Service Interrupt
a. Stack
b.Set I-Bit
c.Vector to Interrupt Routine
Figure 6-1. STOP/WAIT Flowchart
MC68HC05CL48
REV 2.0
LOW POWER MODES
MOTOROLA
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GENERAL RELEASE SPECIFICATION
MOTOROLA
6-4
June 11, 1997
LOW POWER MODES
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 7
INPUT/OUTPUT PORTS
In single-chip mode there are 24 pins arranged as 3 8-bit I/O port. The I/O ports
are programmable as either inputs or outputs under software control of the data
direction registers.
To avoid a glitch on the output pins, write data to the I/O Port Data Register before
writing a one to the corresponding Data Direction Register.
7.1
PARALLEL PORTS
Port A and B and C are 8-bit bidirectional port. Each Port pin is controlled by the
corresponding bits in a data direction register and a data register as shown in
Figure 7-1. The functions of the I/O pins are summarized in Table 7-1.
Read/Write DDR
Data Direction
Register
Data
Register Bit
Write Data
OUTPUT
I/O
Pin
Read Data
Internal HC05
Data Bus
Reset
(RST)
Figure 7-1. Port I/O Circuitry
Table 7-1. Port I/O Pin Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
MC68HC05CL48
REV 2.0
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MOTOROLA
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GENERAL RELEASE SPECIFICATION
7.2
June 11, 1997
PORT A
Port A is an 8-bit bidirectional port. The port A data register is at $0000 and the
data direction register (DDRA) is at $0003. Reset does not affect the data register,
but clears the data direction register, thereby returning the ports to inputs. Writing
a one to a DDR bit sets the corresponding port bit to output mode. In addition to
normal I/O port function, PTA0-PTA2 are also used as additional external interrupt
inputs and PTA3-PTA7 are also associated with the KEYBOARD interrupt
function. See Section 4.3.2 for detail description on External and Keyboard
interrupts.
7.3
PORT B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the
data direction register (DDRB) is at $0004. Reset does not affect the data register,
but clears the data direction register, thereby returning the ports to inputs. Writing
a one to a DDR bit sets the corresponding port bit to output mode.
7.4
PORT C
Port C is an 8-bit bidirectional port which shares its pins with subsystems A-2-D,
SPI and Timer under the control of the A-2-D status and control register ADCSR,
the SPI control register SPCR and the Timer pin configuration register TIMCONF.
The port C data register is at $0002, the data direction register (DDRC) is at
$0005. Reset does not affect the data register, but clears the data direction,
thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. Writing a ‘1’ to the SPE-bit of the SPI
control register SPCR configures PTC[0:3] as dedicated SPI pins. Setting
CONF6-bit and CONF7-bit of the Timer pin configuration register TIMCONF to ‘1’
configures PTC6 and PTC7 as Timer input capture pins respectively.
PTC[4:5] will always be available as IO port pins even after the ADON-bit is set.
When ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control
register is set to select channel-2, PTC[4] becomes an A-2-D input pin. When
ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control register
is set to select channel-3, PTC[5] becomes an A-2-D input pin.
Table 7-1. summarizes the PORT C function when used as sub-system pins.
Table 7-2. PORT C I/O Configuration
MOTOROLA
7-2
PORT C
I/O Mode
PTC0
Input
Output
Sub-System Function
SCK: SPI slave clock-in (MSTR = ‘0’, SPE=1).
SCK: SPI master clock-out (MSTR = ‘1’, SPE=1).
INPUT/OUTPUT PORTS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Table 7-2. PORT C I/O Configuration
PORT C
I/O Mode
PTC1
Input
Output
MISO: SPI slave data out (MSTR=0, SPE=1)
MISO: SPI master data in (MSTR=1, SPE=1)
PTC2
Input
Output
MOSI: SPI slave data in (MSTR=0, SPE=1)
MOSI: SPI master data out (MSTR=1, SPE=1)
MC68HC05CL48
REV 2.0
Sub-System Function
PTC3
Input
SS: SPI slave select signal (SPE=1)
Note: This pin is internally connected to VDD when
(MSTR=1), this means that PTC3 can be used as a
normal port pin.
PTC4
Input
AD2: A-to-D input (ADON=1 and Channel-2
selected)
PTC5
Input
AD3: A-to-D input (ADON=1 and Channel-3
selected)
PTC6
Input
TCAP1: Timer input capture1 (CONF6=1).
PTC7
Input
TCAP2: Timer input capture2 (CONG7=1).
INPUT/OUTPUT PORTS
MOTOROLA
7-3
GENERAL RELEASE SPECIFICATION
MOTOROLA
7-4
June 11, 1997
INPUT/OUTPUT PORTS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 8
TIMER
The MC68HC05CL48 has three timers:
8.1
•
16-bit free-running timer
•
15-stage multi-functional (core) timer
•
One second timer
16-BIT FREE-RUNNING TIMER
The 16-bit free-running counter is driven by a fixed divide-by-four prescaler. This
timer can be used for many purposes, including input waveform measurements
while simultaneously generating an output waveform. Pulse widths can vary from
several microseconds to many seconds. Refer to Figure 8-1 for a timer block
diagram.
Because the timer has a 16-bit architecture, each specific functional segment
(capability) is represented by two registers. These registers contain the high and
low byte of that functional segment. Generally, accessing the low byte of a specific
timer function allows full control of that function; however, an access of the high
byte inhibits that specific timer function until the low byte is also accessed.
NOTE
The I bit in the CCR should be set while manipulating both the high
and low byte register of a specific timer function to ensure that an
interrupt does not occur.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
MC68HC05 Internal Bus
Internal
Timer Clock
(NTF1)
8-bit
Buffer
High
Byte
Output
Compare
Register 1
Output
Compare
Register 2
OC1H
& OC1L
Output
Compare
Circuit 1
Low
Byte
16-bit Free TCH
Running & TCL
Counter
÷4
OC2H
& OC2L
Alternate
Counter
Register
Output
Compare
Circuit 2
TSR
OC1F OC2F TOF IC1F IC2F
Overflow
Detect
Circuit
& IC1L
IC1H
Input
Capture
Register 1
& IC2L
IC2H
Input
Capture
Register 2
ACH
& ACL
Edge
Detect
Circuit1
TCR
OC1IEOC2IE TOIE IC1IE IC2IE IEDG1IEDG2
Edge
Detect
Circuit2
TCAP2
TCAP1
Interrupt Circuit
Interrupt Logic
Figure 8-1. 16-Bit Free-running Timer Block Diagram
MOTOROLA
8-2
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
8.1.1 Counter
TCH
$0019
READ
READ
READ
4
3
2
1
0
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
Counter Reset
1
1
1
1
1
1
0
0
7
6
5
4
3
2
1
0
AC15
AC14
AC13
AC12
AT11
AC10
AC9
AC8
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
1
0
0
WRITE
RESET
ACL
$001C
5
WRITE
RESET
ACH
$001B
6
WRITE
RESET
TCL
$001A
7
READ
WRITE
RESET
Counter Reset
1
1
1
1
1
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2.2 microseconds if the
internal bus clock is 1.8MHz. The counter is incremented during the low portion of
the internal bus clock. Software can read the counter at any time without affecting
its value.
The double-byte, free-running counter can be read from either of two locations,
$19-$1A (counter register) or $1B-$1C (counter alternate register). A read from
only the least significant byte (LSB) of the free-running counter ($1A, $1C)
receives the count value at the time of the read. If a read of the free-running
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
counter or counter alternate register first addresses the most significant byte
(MSB) ($19, $1B), the LSB ($1A, $1C) is transferred to a buffer. This buffer value
remains fixed after the first MSB read, even if the user reads the MSB several
times. This buffer is accessed when reading the free-running counter or counter
alternate register LSB ($1A or $1C) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate
register, if the MSB is read, the LSB must also be read to complete the sequence.
The counter alternate register differs from the counter register in one respect: a
read of the counter register MSB can clear the timer overflow flag (TOF).
Therefore, the counter alternate register can be read at any time without the
possibility of missing timer overflow interrupts due to clearing of the TOF.
Internal Processor Clock
T00
Internal
Timer
Clocks
T01
T10
T11
Counter (16 bit) $FFFE
$FFFF
$0000
$0001
$0002
Timer Overflow Flag (TOF)
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is
cleared by read of the Timer Status Register during the internal processor clock time
followed by a read of the counter low register.
Figure 8-2. Timer State Diagram For Timer Overflow
The free-running counter is configured to $FFFC during reset and is always a
read-only register. During a power-on reset, the counter is also preset to $FFFC
and begins running after the oscillator start-up delay. Because the free-running
counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the
free-running counter repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also
be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE).
In some particular timing control applications it may be desirable to reset the 16bit free running counter under software control. When the low byte of the counter
($1A or $1C) is written to, the counter is configured to its reset value ($FFFC).
MOTOROLA
8-4
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
The divide-by-4 prescaler is also reset and the counter resumes normal counting
operation. All of the flags and enable bits remain unaltered by this operation. If
access has previously been made to the high byte of the free running counter
($19 or $1B), then the reset counter operation terminates the access sequence.
Internal Processor Clock
Internal Reset
T00
Internal
Timer
Clocks
T01
T10
T11
$FFFC
Counter (16bit)
$FFFD
$FFFE
$FFFF
RESET (External or POR)
NOTE: The Counter Register and Timer Control Register are the only ones affected by RESET.
Figure 8-3. Timer State Timing Diagram For Reset
8.1.2 Output Compare Registers
There are two output compare registers: output compare register 1 and output
compare register 2. Output compare registers can be used for several purposes
such as controlling an output waveform or indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the
output compare register can be used as storage locations.
8.1.2.1
Output Compare Register 1
OC1H
$0015
6
5
4
3
2
1
0
OC1:15
OC1:14
OC1:13
OC1:12
OC1:11
OC1:10
OC1:9
OC1:8
U
U
U
U
U
U
U
U
READ
WRITE
RESET
MC68HC05CL48
REV 2.0
7
TIMER
MOTOROLA
8-5
GENERAL RELEASE SPECIFICATION
OC1L
$0016
June 11, 1997
7
6
5
4
3
2
1
0
OC1:7
OC1:6
OC1:5
OC1:4
OC1:3
OC1:2
OC1:1
OC1:0
U
U
U
U
U
U
U
U
READ
WRITE
RESET
The 16-bit output compare register 1 is made up of two 8-bit registers at locations
$15 (MSB) and $16 (LSB). The output compare register contents are compared
with the contents of the free-running counter once every four internal processor
clock cycles. If a match is found, the corresponding output compare flag OC1F (bit
5 of timer status register $12) is set.
The output compare register values should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany
a successful output compare provided the corresponding interrupt enable bit
OC1IE (bit 5 of timer control register $11) is set.
After a processor write cycle to the output compare register containing the MSB
($15), the output compare function is inhibited until the LSB ($16) is also written.
The user must write both bytes (locations) if the MSB is written first. A write made
only to the LSB ($16) will not inhibit the compare function. The free-running
counter is updated every four internal bus clock cycles. The minimum time
required to update the output compare register is a function of the program rather
than the internal hardware.
The processor can write to either byte of the output compare register without
affecting the other byte.
Because the output compare flag OC1F and the output compare register 1 are
undetermined at power on, and are not affected by external reset, care must be
exercised when initializing the output compare function. The following procedure
is recommended:
1. Write the high byte to the compare register 1 to inhibit further compares
until the low byte is written.
2. Read the status register to arm the OC1F if it is already set.
3. Write the output compare register 1 low byte to enable the output
compare 1 function with flag clear.
The purpose of this procedure is to prevent the OC1F bit from being set between
the time it is read and the write to the corresponding output compare register.
MOTOROLA
8-6
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
8.1.2.2
GENERAL RELEASE SPECIFICATION
Output Compare Register 2
OC2H
$0017
6
5
4
3
2
1
0
OC2:15
OC2:14
OC2:13
OC2:12
OC2:11
OC2:10
OC2:9
OC2:8
U
U
U
U
U
U
U
U
7
6
5
4
3
2
1
0
OC2:7
OC2:6
OC2:5
OC2:4
OC2:3
OC2:2
OC2:1
OC2:0
U
U
U
U
U
U
U
U
READ
WRITE
RESET
OC2L
$0018
7
READ
WRITE
RESET
The 16-bit output compare register 2 is made up of two 8-bit registers at locations
$17 (MSB) and $18 (LSB). The output compare register contents are compared
with the contents of the free-running counter once every four internal processor
clock cycles. If a match is found, the corresponding output compare flag OC2F (bit
4 of timer status register $12) is set.
The output compare register values should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany
a successful output compare provided the corresponding interrupt enable bit
OC2IE (bit 4 of timer control register $11) is set.
After a processor write cycle to the output compare register containing the MSB
($17), the output compare function is inhibited until the LSB ($18) is also written.
The user must write both bytes (locations) if the MSB is written first. A write made
only to the LSB ($18) will not inhibit the compare function. The free-running
counter is updated every four internal bus clock cycles. The minimum time
required to update the output compare register is a function of the program rather
than the internal hardware.
The processor can write to either byte of the output compare register without
affecting the other byte.
Because the output compare flag OC2F and the output compare register 2 are
undetermined at power on, and are not affected by external reset, care must be
exercised when initializing the output compare function. A procedure as
recommended for Compare Register 1 should be followed.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-7
GENERAL RELEASE SPECIFICATION
June 11, 1997
Internal Processor Clock
T00
Internal
Timer
Clocks
T01
T10
T11
Counter (16 bit) $FFEB
$FFEC
$FFED
$FFEE
$FFEF
1
CPU writes $FFED
Compare Register
$FFED
2
Compare Register Latch
3
Output Compare Flag (OCF)
1. The CPU writes to the Compare Register may take place at any time, but a compare
only occurs at timer state T01. Thus, a 4-cycle different may exist between the write
to the Compare Register and the actual compare.
2. Internal compare takes place during timer state T01.
3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this
example).
Figure 8-4. Timer State Timing Diagram For Output Compare
8.1.3 Input Capture Registers
8.1.3.1
Input Capture Register 1
IC1H
$0013
READ
6
5
4
3
2
1
0
IC1:15
IC1:14
IC1:13
IC1:12
IC1:11
IC1:10
IC1:9
IC1:8
U
U
U
U
U
U
U
U
WRITE
RESET
MOTOROLA
8-8
7
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
READ
IC1L
$0014
GENERAL RELEASE SPECIFICATION
7
6
5
4
3
2
1
0
IC1:7
IC1:6
IC1:5
IC1:4
IC1:3
IC1:2
IC1:1
IC1:0
U
U
U
U
U
U
U
U
WRITE
RESET
Two 8-bit registers, which make up the 16-bit input capture register, these are
read-only and are used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a defined transition. The level
transition which triggers the counter transfer is defined by the corresponding input
edge bit (IEDG1). Reset does not affect the contents of the input capture register.
•
IEDG1 = 0: Capture on negative edge
•
IEDG1 = 1: Capture on positive edge
An interrupt can also accompany a capture provided the corresponding interrupt
enable bit, ICI1E (bit 7 of the timer control register $11) is set.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution
is one count of the free-running counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture flag (IC1F) is
set or clear. The input capture register always contains the free-running counter
value that corresponds to the most recent input capture.
After a read of the input capture register ($13) MSB, the counter transfer is
inhibited until the LSB ($14) is also read. This characteristic causes the time used
in the input capture software routine and its interaction with the main program to
determine the minimum pulse period.
A read of the input capture register LSB ($14) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-9
GENERAL RELEASE SPECIFICATION
8.1.3.2
June 11, 1997
Input Capture Register 2
IC2H
$000F
READ
6
5
4
3
2
1
0
IC2:15
IC2:14
IC2:13
IC2:12
IC2:11
IC2:10
IC2:9
IC2:8
U
U
U
U
U
U
U
U
7
6
5
4
3
2
1
0
IC2:7
IC2:6
IC2:5
IC2:4
IC2:3
IC2:2
IC2:1
IC2:0
U
U
U
U
U
U
U
U
WRITE
RESET
IC2L
$0010
7
READ
WRITE
RESET
Two 8-bit registers, which make up the 16-bit input capture register, these are
read-only and are used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a defined transition. The level
transition which triggers the counter transfer is defined by the corresponding input
edge bit (IEDG2). Reset does not affect the contents of the input capture register.
•
IEDG2 = 0: Capture on negative edge
•
IEDG2 = 1: Capture on positive edge
An interrupt can also accompany a capture provided the corresponding interrupt
enable bit, ICI2E (bit 6 of the timer control register $11) is set.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution
is one count of the free-running counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture flag (IC2F) is
set or clear. The input capture register always contains the free-running counter
value that corresponds to the most recent input capture.
After a read of the input capture register ($0F) MSB, the counter transfer is
inhibited until the LSB ($10) is also read. This characteristic causes the time used
in the input capture software routine and its interaction with the main program to
determine the minimum pulse period.
A read of the input capture register LSB ($10) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
MOTOROLA
8-10
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Internal Processor Clock
T00
Internal
Timer
Clocks
T01
T10
T11
Counter (16 bit) $FFEB
$FFEC
$FFED
$FFEE
$FFEF
Input Edge
note
Input Capture Latch
$????
Capture Register
$FFED
Input Capture Flag (ICF)
NOTE: If the input edge occurs in the shaded area from one timer state T10 to the other
timer state T10 the Input Capture Flag is set during the next state T11.
Figure 8-5. Timer State Timing Diagram For Input Capture
8.1.4 Timer Control Register (TCR)
The timer control registers TCR is a read/write register. Five bits control interrupts
associated with the timer status register flags IC1F, IC2F, OC1F, OC2F and TOF.
The other two bits control which edge is significant to the input capture edge
detector (i.e., negative or positive). The timer control register and the free running
counter are the only sections of the timer affected by reset. The timer control
registers are illustrated below by a definition of each bit.
TCR
$0011
7
6
5
4
3
IC1IE
IC2IE
OC1IE
OC2IE
TOIE
0
0
0
0
0
2
1
0
IEDG2
IEDG1
U
U
READ
WRITE
RESET
X
U = UNAFFECTED
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-11
GENERAL RELEASE SPECIFICATION
June 11, 1997
IC1IE - Input Capture 1 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
IC2IE - Input Capture 2 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OC1IE - Output Compare 1 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OC2IE - Output Compare 2 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
IEDG2 - Input Edge 2
Value of the input edge determines which level transition on TCAP2 pin will
trigger a free running counter transfer to the input capture register. Reset does
not affect the IEDG2 bit.
1 = positive edge
0 = negative edge
IEDG1 - Input Edge
Value of the input edge determines which level transition on TCAP1 pin will
trigger a free running counter transfer to the input capture register. Reset does
not affect the IEDG1 bit.
1 = positive edge
0 = negative edge
8.1.5 Timer Status Register (TSR)
The timer status register is a read-only register and is illustrated below followed by
a definition of each bit. Refer to timing diagrams shown in Figure 8-3, Figure 8-2
and Figure 8-4 for timing relationship to the timer status register bits.
TSR
$0012
READ
7
6
5
4
3
IC1F
IC2F
OC1F
OC2F
TOF
U
U
U
U
U
2
1
0
U
U
0
WRITE
RESET
U = UNAFFECTED
MOTOROLA
8-12
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
IC1F - Input Capture Flag
1 = Flag set when a selected polarity edge has been sensed by the
input capture edge detector.
0 = Flag cleared by reading the timer status register (with IC1F set)
followed by accessing the low byte ($14) of the input capture
register.
IC2F - Input Capture Flag
1 = Flag set when a selected polarity edge has been sensed by the
input capture edge detector.
0 = Flag cleared by reading the timer status register (with IC2F set)
followed by accessing the low byte ($10) of the input capture
register.
OC1F - Output Compare 1 Flag
1 = Flag set when the output compare register 1 contents matches the
contents of the free running counter.
0 = Flag cleared by reading the timer status register (with OC1F set)
and then accessing the low byte ($16) of the output compare 1
register.
OC2F - Output Compare 2 Flag
1 = Flag set when the output compare register 2 contents matches the
contents of the free running counter.
0 = Flag cleared by reading the timer status register (with OC2F set)
and then accessing the low byte ($18) of the output compare 1
register.
TOF - Timer OVerflow Flag
1 = Flag set by transition of the free running counter from $FFFF to
$0000.
0 = Flag cleared by reading the timer status register (with TOF set)
followed by an access of the free running counter least significant
byte ($1A).
Accessing the timer status register satisfies the first condition required to clear
status bits. The remaining step is to access the register corresponding to the
status bit.
A problem can occur when using the timer overflow function and reading the freerunning counter at random times to measure an elapsed time. Without
incorporating the proper precautions into software, the timer overflow flag could
unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose of
servicing the flag.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-13
GENERAL RELEASE SPECIFICATION
June 11, 1997
The counter alternate register at address $1B and $1C contains the same value
as the free-running counter (at address $19 and $1A); therefore, this alternate
register can be read at any time without affecting the timer overflow flag in the
timer status register.
8.1.6 Timer Pin Configuration Register (TIMCONF)
The timer pin configuration register is a read/write register, this is used to control
PTC[6:7] pin function.
TIMCONF
$0006
7
6
CONF7
CONF6
0
0
5
4
3
2
1
0
U
U
U
U
U
0
READ
WRITE
RESET
U = UNAFFECTED
CONF7- Pin configuration 7
1 = Configures PTC7 as timer input capture pin.
0 = PTC7 used as normal I/O port pin.
CONF6- Pin configuration 6
1 = Configures PTC6 as timer input capture pin.
0 = PTC6 used as normal I/O port pin.
8.1.7 Operation During Low Power Mode
During the wait and stop modes, the timer stops and holds at its current state,
retaining all data, and resumes operation from this point when external interrupt
(IRQ), or internal interrupt is received.
8.2
CORE TIMER
The MC68HC05CL48 Core Timer (or Ctimer) for is a 15-stage multi-functional
ripple counter. The features include Timer Over Flow, Power-On Reset (POR),
Real Time Interrupt, and COP Watchdog Timer.
As seen in Figure 8-6, the Timer is driven by the internal bus clock divided by four
with a fixed prescaler. This signal drives an 8-bit ripple counter. The value of this
8-bit ripple counter can be read by the CPU at any time by accessing the Ctimer
Counter Register (CTCR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt at the
rate of E/1024. One additional stages produce the POR function at E/2064. The
Timer Counter Bypass circuitry (available only in Test Mode) is at this point in the
MOTOROLA
8-14
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
timer chain. This circuit is followed by two more stages, with the resulting clock (E/
16384) driving the Real Time Interrupt circuit. The RTI circuit consists of three
divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided
by eight to drive the optional COP Watchdog Timer circuit. The RTI rate selector
bits, and the RTI and CTOF enable bits and flags are located in the Ctimer Control
and Status Register(CTCSR) at location $08.
Internal Bus
8 8
fop Internal
Processor
Clock
2
fop/2
÷4
$09 CTCR
Core Timer Counter Register (TCR)
TCR
COP
Clear
fop/210
7-bit counter
POR
TCBP
RTI Select Circuit
Overflow
Detect
Circuit
$08 CTCSR
CTimer Control & Status Register
TCSR
CTOF
RTIF CTOFE RTIE
-
-
RT1
RT0
COP Watchdog
Resetable Timer(÷8)
Interrupt Circuit
To Interrupt
Logic
To Reset
Logic
Figure 8-6. Core Timer Block Diagram
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-15
GENERAL RELEASE SPECIFICATION
June 11, 1997
8.2.1 Computer Operating Properly (COP) Watchdog reset
The COP watchdog timer function is implemented on this device by using the
output of the RTI circuit and further dividing it by eight. The minimum COP reset
rates are listed in Table 8-1. If the COP circuit times out, an internal reset is
generated and the normal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit 0 of address $FFF0. This
location is shared with User ROM byte. And reading this location will return the
User ROM data. When the COP is cleared, only the final divide by eight stage
(output of the RTI) is cleared. If the COP (Computer Operating Properly)
Watchdog Timer circuit times out, an internal reset is generated and the reset
vector is fetched.
This function is software selectable by setting the COP bit in the Option Register.
The COP bit is set after reset, i.e. the COP function is defaulted. The COP
function can be disable by writing a ‘0’ to this bit.
NOTE
COP is located at bit 6 of the Option Register at $001F, which can
only be written once after reset.
8.2.2 Ctimer Control and Status Register (CTCSR)
The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and
the real time interrupt rate select bits.
CTCSR
$0008
7
6
5
4
CTOF
RTIF
CTOFE
RTIE
0
0
0
0
READ
3
2
0
0
1
0
RT1
RT0
1
1
WRITE
RESET
0
0
CTOF - Core Timer Over Flow
This is a clearable, read-only status bit and is set when the 8-bit ripple counter
rolls over from $FF to $00.
1 = No effect
0 = Clearing the TOF
RTIF - Real Time Interrupt Flag
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4
selector. The clock frequency that drives the RTI circuit is E/213 with three
additional divider stages. This flag is a clearable, read-only status bit and is set
MOTOROLA
8-16
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
when the output of the chosen (1 of 4 selection) stage goes active.
1 = No effect
0 = Clearing the RTIF
CTOFE - Core Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the TOF bit is
set, provided the I bit in CCR is cleared.
1 = Interrupt enable
0 = Interrupt disable
RTIE - Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the RTIF bit is
set, provided the I bit in the CCR is cleared.
1 = Interrupt enable
0 = Interrupt disable
RT1:RT0 - Rate Select
These two bits select one of four taps from the Real Time Interrupt circuit. The
settings for RTI is listed in Table 8-1. Reset sets these RT0 and RT1, selecting
the lowest periodic rate and therefore the maximum time in which to alter these
bits if necessary.
NOTE
Care should be taken when altering RT0 and RT1 if the time-out
period is imminent or uncertain. If the selected tap is modified during
a cycle in which the counter is switching, an RTIF could be missed
or an additional one could be generated. To avoid problems, the
COP should be cleared before changing RTI taps.
8.2.3 Ctimer Counter Register (CTCR)
The Core Timer Counter Register is a read-only register which contains the
current value of the 8-bit ripple counter at the beginning of the timer chain. This
counter is clocked at fop divided by 4 and can be used for various functions
including a software input capture. Extended time periods can be attained using
the TOF function to increment a temporary RAM storage location thereby
simulating a 16-bit (or more) counter.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-17
GENERAL RELEASE SPECIFICATION
CTCR
$0009
READ
June 11, 1997
7
6
5
4
3
2
1
0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0
0
0
0
0
0
0
0
WRITE
RESET
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 2016 cycles, the power-on reset circuit is released which again
clears the counter chain and allows the device to come out of reset. At this point, if
RESET is not asserted, the timer will start counting up from zero and normal
device operation will begin. When RESET is asserted any time during operation
(other than POR), the counter chain will be cleared.
8.2.4 Operation During Low Power Mode
The timer is cleared when going into STOP mode. When STOP is exited by an
external interrupt or an external RESET, the internal oscillator will resume,
followed by 2016 cycles internal processor stabilization delay. The timer is then
cleared and operation resumes.
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
Table 8-1. RTI and COP Rates at 1.8MHz Bus Frequency
BUS FREQUENCY = 1.8 MHz
MOTOROLA
8-18
RT1:RT0
Div. Ratio
RTI Rate
COP Rate (RTIx7)
00
214
9.1 ms
63.7 ms
01
215
18.2ms
127.4 ms
10
216
36.4 ms
254.8 ms
11
217
72.8 ms
509.6 ms
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Table 8-2. RTI and COP Rates 17.5kHz Bus Frequency
BUS FREQUENCY = 17.5 kHz
8.3
RT1:RT0
Div. Ratio
RTI Rate
COP Rate (RTIx7)
00
214
0.94 s
6.58 s
01
215
1.88 s
13.16 s
10
216
3.76 s
26.32 s
11
217
7.52 s
52.64 s
ONE SECOND WATCH TIMER
The 1 second Watch Timer is a 15-bit free running counter which runs off the
32kHz external clock directly and is therefore not affected by Stop Mode or Wait
Mode. The Watch Timer is used to generate interrupts at 1 second interval to
wake up the CPU when the I-bit in the CCR is cleared. See Figure 8-7. The Watch
Timer overflow flag WTOF is set when the a transition from $7FFF to $0000
occurs and will cause an interrupt if the WTOIE-bit of the Watch Timer control and
status register (WTCSR $0023) is set to ‘1’. This flag is latched and should be
cleared by the Watch Timer interrupt service routine to prevent unwanted
interrupts. Writing a ‘0’ to the WTOF-bit or reset clears the WTOF-bit.
Power on or external reset has no effect on the free running counter and therefore
the counter state is unknown after reset. However, the Watch Timer can be reset
to a known state by writing a ‘1’ to the WTR-bit in the Watch Timer control and
status register. The WTOF flag is prevented from being set during software reset.
Reading the WTR-bit will always return a ‘0’.
The Watch Timer can be disabled by writing a ‘1’ to the WTOFF-bit of the Watch
Timer control and status register, the value of the Watch Timer is retained during
the off period.
MC68HC05CL48
REV 2.0
TIMER
MOTOROLA
8-19
GENERAL RELEASE SPECIFICATION
June 11, 1997
15-bit
Free Running
Counter
32kHz
External Clock
OFF
RESET
1 second overflow
WTOFF WRT WTOIE WTOF
WTimer Interrupt
Figure 8-7. ONE Second Watch Timer
8.3.1 Watch Timer Control & Status Register (WTCSR)
7
WTCSR
$0023
6
5
4
3
READ
2
0
WTOFF
WRITE
RESET
1
0
WTOF
WTOIE
WTR
-
-
-
-
0
0
0
0
U = UNAFFECTED
WTOFF
1 = Disable Watch Timer
0 = Enable Watch Timer
WTR
Writing a ‘1’ to this bit will generate a reset pulse to reset the Watch Timer.
Reading this bit will always return a ‘0’.
WTOIE
1 = Enable 1 second interrupt.
0 = Disable 1 second interrupt.
WTOF
1 = Flag set by transition of the 15-bit free running counter from $7FFF
to $0000
0 = Flag cleared by writing a 0 to the WTOF bit.
MOTOROLA
8-20
TIMER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 9
SERIAL PERIPHERAL INTERFACE
The term “serial peripheral” refers to the fact that this interface requires separate
wires (signals) for data and clock. In this format, data does not contain an explicit
clock. The SPI scheme may be used to interconnect microcomputers located at a
short distance (usually within a single “black box” or on the same PC card). This
may comprise a system of one microcomputer and several slaves or may be a
system of microcomputers, each having the capability of either master or slave.
A practical system may include:
1) MISO master in slave out
2) MOSI master out slave in
3) SCK serial clock
4) SS (n) slave select(s)
9.1
SIGNAL DESCRIPTION
9.1.1 MISO Master In Slave Out
9.1.1.1
Slave Mode
MISO is the signal which is used in Slave Mode to present data from a Slave
device to the bus. The MISO pin will be placed in the hi-Z state whenever a Slave
device is “not” selected (SS=1) by the bus master. Figure 9-1 shows the clock
(SCK) and data relationship. Four possible timing relationships may be chosen by
use of the control bits (CPOL) and (CPHA). The Slave device and a Master device
must be programmed to be in similar timing modes for proper data transfer.
9.1.1.2
Master Mode
In the master mode (control bit MSTR=1), the function of MOSI and MISO are
inverted within the device. Therefore, the MISO pin becomes the data input pin for
a device which is in the master mode. (Also, the function of SCK switches from
being an input for system clock to one of outputting the system clock.)
MC68HC05CL48
REV 2.0
SERIAL PERIPHERAL INTERFACE
MOTOROLA
9-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
9.1.2 MOSI Serial Data In (Input)
9.1.2.1
Slave Mode
MOSI is the signal used to receive data from some Master device. Figure 9-1
shows the serial clock and data timing relationship.
It should be noted that when a Master device transmits data to a second device
via the MOSI line, the slave device (if it has the capability) will respond by sending
data into the MISO pin of the master device. This implies full duplex transmission
with both data-out and data-in synchronized to the same clock signal which is
provided by the master. Moreover, the SAME shift register is used for data out and
data in. Thus, the byte transmitted is replaced by the byte received, removing the
need for separate status bits for XMIT EMPTY and REC FULL. A single status bit,
SPIF, is used to signify IO operation complete.
9.1.2.2
Master Mode
As noted above, the function of MOSI and MISO are inverted in the master mode.
The MOSI pin becomes the data output pin when the device is in the master
mode. When a transfer of data is not taking place with a Slave device the Master
drives the MOSI line high. The Master always allows the data onto the MOSI pin a
half-cycle before the clock edge (SCK) needed for the Slave to latch the data
internally.
9.1.3 SCK Serial Clock (In/Out)
9.1.3.1
Slave Mode
The serial clock is used to move data both in and out of the device through its
MOSI and MISO pins. The Master and Slave device are capable of exchanging a
byte of information during a sequence of eight clock pulses if wired to do so. In the
slave mode, the SCK pin becomes an input for the external clock being sent from
the Master device. In this case SCK is asynchronous to the Slave device’s phase
1-2 clocks and read/write control, therefore synchronization must take place prior
to transmission and after reception. This must be done on the byte level. The type
of clock and its’ relationship with the data is controlled by bits CPOL and CPHA.
Reference Figure 9-1. The clock rate control bits SPR1 and SPR0 have no
function while the part is in the Slave mode.
9.1.3.2
Master Mode
In this mode, the clock is generated within the Master device by a circuit driven
MOTOROLA
9-2
SERIAL PERIPHERAL INTERFACE
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
from the bus clock. The clock rate is selected by bits (SPR1,SPR0) in the control
register. The SCK pin on the Master device becomes a fixed output providing the
system clock to an enabled Slave or Slaves. The clock is used by the Master to
latch incoming Slave data on the MISO pin and shift out data to the Slave device
on the MOSI pin. The Master and Slave must be operated in the same timing
mode. The type of clock and its’ relationship with the data is controlled by bits
CPOL and CPHA. Reference Figure 9-1.
9.1.4 SS SLAVE SELECT (INPUT)
9.1.4.1
Slave Mode
The slave select (SS input) is generated by the master (parallel port may be used)
and used to “enable one” of several slaves to accept and/or return data or “enable
several” slaves to accept data. To insure a data byte transfer, the SS signal must
be low prior to occurrence of SCK and must not become high until after the 8th
(last) SCK cycle. Figure 9-1 shows the clock (SCK) and data relationship.
Depending on the state of the CPHA control bit, the SS pin pulled low: (1) allows
the first bit of data onto the MISO system line for transfer and (2) prevents the
Slave from reading or writing the data register. A further description of the affect of
the (SS) pin and (CPHA) control bit on the i/o data register is given in the
description of the (WCOL) status flag. The (WCOL) flag warns the Slave if it has
had a conflict between a transmission and a write of the data register. A high level
on SS forces MISO to the hi-Z state. Also, SCK and MOSI are ignored by the
disabled slave.
9.1.4.2
Master Mode
In this mode, Slave Select (SS) input is monitored to assure that it stays false
(high). If Slave Select becomes true, the device immediately exits the master
mode and becomes a slave (MSTR=0). Also, control bit (SPE) is forced to a zero
causing all SPI system pins to be inputs. An interrupt flag (MODF) is set warning
the device that the above events have occurred. The significance of this is that a
collision has occurred; that is, two devices have both become masters. This is
normally the result of software error, although some systems may allow the
default master to “knock all other masters off the bus” if an erroneous bus state is
detected. This is, of course, a catastrophic event and it is the responsibility of the
default master to completely “clean up” the system.
9.2
SPI REGISTERS
The register addresses only show the low order address bits i.e ABL(1:0). The
registers can be placed anywhere in the device memory map by generating an
appropriate ‘Module Select’ signal in the map logic.
MC68HC05CL48
REV 2.0
SERIAL PERIPHERAL INTERFACE
MOTOROLA
9-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
9.2.1 SPCR SPI Control Register
SPCR
$0020
7
6
5
4
3
2
1
0
SPIE
SPE
-
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
-
0
0
1
U
U
READ
WRITE
RESET
SPIE SPI Interrupt Enable
When this bit is set to a one a hardware interrupt sequence is requested each
time the SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is
clear or if the I-bit in the CC-Register is one.
SPE SPI System Enable
Setting the SPE-bit to ‘1’ will enable the SPI function and automatically
configure PTC[3:0] as dedicated SPI pins.
MSTR Master/Slave Mode Select
0 = Slave mode
1 = Master mode
CPOL Clock Polarity
CPHA Clock Phase
These two bits are used to specify the clock format to be used in SPI
operations. Please refer to Figure 9-1.
SPR1, SPR0 SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Table 9-1. SPI Clock Rates
MOTOROLA
9-4
SPR1
SPR0
E Clock
divided-by
Frequency
Eclk = 1.8 MHz (baud
rate)
0
0
2
0.9 MHz
0
1
4
450 kHz
1
0
16
112.5 kHz
1
1
32
56.25 kHz
SERIAL PERIPHERAL INTERFACE
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
begin
Transfer
end
SCK
Sample(I)
Change(O)
MSB
LSB
Sel SS
CPOL:CPOA = 0:0
Transfer
begin
end
SCK
Sample(I)
Change(O)
MSB
LSB
Sel SS
CPOL:CPOA = 0:1
Transfer
begin
end
SCK
Sample(I)
Change(O)
MSB
LSB
Sel SS
CPOL:CPOA = 1:0
Transfer
begin
end
SCK
Sample(I)
Change(O)
MSB
LSB
Sel SS
CPOL:CPOA = 1:1
Figure 9-1. SPI Clock/Data Relationships
MC68HC05CL48
REV 2.0
SERIAL PERIPHERAL INTERFACE
MOTOROLA
9-5
GENERAL RELEASE SPECIFICATION
June 11, 1997
9.2.2 SPSR SPI Status Register
SPSR
$0021
READ
7
6
5
4
3
2
1
0
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
WRITE
RESET
SPIF SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by
reading the SPSR register (with SPIF set) followed by an access (read or write)
to the SPI Data Register.
WCOL Write Collision Status Flag
This error status flag is used to indicate that a serial transfer was in progress
when the MCU tried to write new data into the SPDR data register. The MCU
write is disabled to avoid writing over the data being transmitted. No interrupt is
generated because the error status flag can be read upon completion of the
transfer that was in progress at the time of the error. This flag is automatically
cleared by a read of the SPSR (with WCOL set) followed by an access (read or
write) to the SPDR register.
MODFSPI Mode Error Interrupt Status Flag
This bit is set automatically by SPI hardware if the MSTR control bit is set to
one and the Slave Select input pin becomes zero. This condition is not
permitted in normal operation. This flag is automatically cleared by a read of
the SPSR (with MODF set) followed by a write to the SPCR register.
9.2.3 SPDR SPI Data Register
SPDR
$0022
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
U
U
U
U
U
U
U
U
READ
WRITE
RESET
This 8-bit register is both the input and output register for SPI data. In the SPI
system the 8-bit data register in the master and the 8-bit data register in the slave
are linked by the MOSI and MISO wires to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially shifted eight
bit positions by the SCK clock from the master so the data is effectively
MOTOROLA
9-6
SERIAL PERIPHERAL INTERFACE
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
exchanged between the master and the slave. Note that some slave devices are
very simple and either accept data from the master without returning data to the
master or pass data to the master without requiring data from the master.
When writing the SPDR, the data is written directly into the shift register and
always shifted out MSB first.
When reading the SPDR, a Read Data Buffer is actually accessed. This buffer
contains the last data byte received by the SPI, and is updated during the cycle
that SPIF is set (reception complete).
MC68HC05CL48
REV 2.0
SERIAL PERIPHERAL INTERFACE
MOTOROLA
9-7
GENERAL RELEASE SPECIFICATION
MOTOROLA
9-8
June 11, 1997
SERIAL PERIPHERAL INTERFACE
MC68HC05CL48
REV 2.0
June 6, 1997
GENERAL RELEASE SPECIFICATION
SECTION 10
ANALOG TO DIGITAL CONVERTER
The MC68HC05CL48 includes a 8-channel, 8-bit, multiplexed input, successive
approximation A/D converter, with four of the input channels available on external
pins and another four internal channels are used for calibration purpose.
10.1
ANALOG SECTION
10.1.1 Ratiometric Conversion
The A/D is ratiometric, with two dedicated pins supplying the reference voltages
(VRH and VRL). An input voltage equal to VRH converts to $FF (full scale) and an
input voltage equal to VRL converts to $00. An input voltage greater than VRH will
convert to $FF with no overflow indication. For ratiometric conversions, the source
of each analog input should use VRH as the supply voltage and be referenced to
VRL.
10.1.2 VRH and VRL
VRH and VRL are generated internally on chip to reduce pin counts.
10.1.3 Accuracy And Precision
The 8-bit conversions shall be accurate to within ±11/2 LSB including quantization
when averaged over four readings.
10.2
CONVERSION PROCESS
The A/D reference inputs are applied to a precision internal digital-to-analog
converter. Control logic drives this D/A and the analog output is successively
compared to the selected analog input which was sampled at the beginning of the
conversion time. The conversion process is monotonic and has no missing codes.
MC68HC05CL48
REV 2.0
ANALOG TO DIGITAL CONVERTER
MOTOROLA
10-1
GENERAL RELEASE SPECIFICATION
10.3
June 6, 1997
DIGITAL SECTION
10.3.1 Conversion Time
Each channel of conversion takes 32 clock cycles, which must be at a frequency
equal to or greater than 1 MHz.
10.3.2 Multi-Channel Operation
In User Mode a multiplexer allows the single A/D converter to select one of eight analog
signals, two of which are VRH and VRL. The ATD3:0 are input signals to the multiplexer.
10.4
A/D STATUS AND CONTROL REGISTER (ADCSR)
The following paragraphs describe the function of the A/D Status and Control Register.
7
ADSCR
$0024
READ
6
5
ADRC
ADON
U
U
COCO
4
3
2
1
0
CH2
CH1
CH0
U
U
U
0
WRITE
RESET
U
U
U
10.4.1 COCO - Conversions Complete
This read-only status bit is set when a conversion is completed, indicating that the A/D
Data Register contains valid results. This bit is cleared whenever the A/D Status and
Control Register is written and a new conversion automatically started, or whenever the
A/D Data Register is read. Once a conversion has been started by writing to the A/D
Status and Control Register, conversions of the selected channel will continue every 32
cycles until the A/D Status and Control Register is written again. In this continuous
conversion mode the A/D Data Register will be filled with new data, and the COCO bit set,
every 32 cycles. Data from the previous conversion will be overwritten regardless of the
state of the COCO bit prior to writing.
10.4.2 ADRC - A/D RC Oscillator Control
When the RC oscillator is selected (ADRC = 1) to be the A/D clock source, it requires a
time tADRC to stabilize. Results can be inaccurate during this time. If the CPU clock is
running below 1 Mhz, the RC oscillator must be used.
When ADRC =0, the A/D uses the CPU clock.
MOTOROLA
10-2
ANALOG TO DIGITAL CONVERTER
MC68HC05CL48
REV 2.0
June 6, 1997
GENERAL RELEASE SPECIFICATION
10.4.3 ADON - A/D On
When the A/D is turned on (ADON = 1), it requires a time tADON for the current sources to
stabilize, and results can be inaccurate during this time. This bit turns on the charge pump.
If the ADRC is set, clearing this bit disables the RC oscillator to save power.
10.4.4 CH2:CH0 - Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select one of eight A/D channels.
Channels 0-3 correspond to the analog input pins: ATD(3:0) in the MCU. Channels 4-7
are used for internal reference points. The following table shows the signals selected by
the channel select field.
CHANNEL
SIGNAL
0
ATD0 pin
1
ATD1 pin
2
ATD2/PTC[4] pin
3
ATD3/PTC[5] pin
4
VRH
5
VRL
6
(VRH - VRL)/4
7
(VRH - VRL)/2
Table 10-1. A/D Channel Assignments
10.5
A/D DATA REGISTER (ADDR)
One 8-bit result register is provided. This register is updated each time COCO is set
ADDR
$0025
6
5
4
3
2
1
0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
U
U
U
U
U
U
U
U
READ
WRITE
RESET
10.6
7
A/D DURING WAIT MODE
The A/D continues normal operation during WAIT mode. To decrease power consumption
during WAIT, it is recommended that both the ADON and ADRC bits in the A/D Status and
Control Register be cleared if the A/D converter is not being used. If the A/D converter is
in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit
be cleared.
MC68HC05CL48
REV 2.0
ANALOG TO DIGITAL CONVERTER
MOTOROLA
10-3
GENERAL RELEASE SPECIFICATION
10.7
June 6, 1997
A/D DURING STOP MODE
In STOP mode the comparator and charge pump are turned off and the A/D ceases to
function. Any pending conversion is aborted. When the clocks begin oscillation upon
leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize
enough to provide conversions to the specified accuracy. The delays built into the
MC68HC05 when coming out of STOP mode are sufficient for this purpose, therefore no
explicit delays need to be built into the software.
MOTOROLA
10-4
ANALOG TO DIGITAL CONVERTER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 11
CALLER-ID
The Caller ID module demodulates the Bell 202 and CCITT V.23 1200 baud FSK
asynchronous data. This module consists of four major building blocks - FSK
demodulator, Carrier Detect, Ring Detect and the Power Management circuit.
The block diagram of this module is shown in Figure 11-1.
Tip
–
Ring
+
202
Demod
BPF
Ring Det 1
Ring Det 2
Ring
Detect
Circuit
VAG
Valid
Data
Detect
Carrier
Detect
Circuit
Demod
Data
Serial
Data
Select
Power CTL
from CPU
Power
Management
Ring Time
Ring
Detect
Interface
Carrier
Detect
Interface
CPU
Interrupt
Interrupt
Circuit
Control/Status Register 1
Control/Status Register 2
Control/Status Register 3
SDSL
MCU Data Bus
Figure 11-1. Caller ID Block Diagram
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-1
GENERAL RELEASE SPECIFICATION
11.1
June 11, 1997
FSK DEMODULATOR
The recovered signal consists of both the channel seizure information and the
message words. The original serial raw data is made available via the MCU
registers. See Section 11.7.2.
11.2
CARRIER DETECTOR
The Carrier Detect block will validate the carrier signal from the filter section. The
asynchronous carrier signal is considered valid if present for a minimum of 25ms.
A carrier dropout is confirmed if it is silent for more than 8ms. The carrier detect
signal will remain low until a dropout condition is detected. The carrier detect
output is available in a read-only register (CD) in Control/Status Register 2
(CLCSR2). It can also be overwritten by writing to CDO (Carrier Detect Override)
in the Control/Status Register 1 (CLCSR1) when enabled by writing a ‘1’ to CDOE
(Carrier Detect Override Enable) in the CLCSR3 register. A valid carrier can also
produce an interrupt to the CPU when enabled by the CDIE bit in CLCSR1. See
Section 11.7.1 and Section 11.7.2
Carrier Detect
Read
DB
CD
CDOE
CDIF
Interrupt
CDO
CDIE
Figure 11-2. Carrier Detect Interface
11.3
RT_L INTERRUPT
Figure 11-3 shows that the RT_L pin connected to a ring time circuit. When RDI1
is ‘low’, RT_L is pulled high by the external pull-up resistor. When RDI1 rises
above 1.0 volt, RT_L will be pulled low by the open-drain NMOS transistor and an
interrupt will be generated.
Note: RT_L interrupt is permanently disabled in the current design and can only
be enabled by a Metal Mask Option.
MOTOROLA
11-2
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
VDD
270kΩ typical
External Pull-up
RT_L
RDI1
0.02µF typical
External Cap
RT_L Interrupt
Figure 11-3. RT_L Interrupt
11.4
RING DETECTOR
The ring detect circuit validates the input ring signal (RD2) and the ring detect
output is available in a read-only register (RD) in Control/Status Register 2
(CLCSR2). It can also be overwritten by writing to RDO (Ring Detect Override) in
the Control/Status Register 1(CLCSR1) when enabled by writing a ‘1’ to RDOE
(Ring Detect Override Enable) in the CLCSR3 register. A valid ring signal can also
produce an interrupt to the CPU when enabled by the RDIE bit in CLCSR1. See
Section 11.7.1 and Section 11.7.2.
Ring Detect
Read
DB
RD
RDOE
RDIF
Interrupt
RDO
RDIE
Figure 11-4. Ring Detect Interface
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-3
GENERAL RELEASE SPECIFICATION
11.5
June 11, 1997
POWER MANAGEMENT
If the Ring Detect module is used, it should be enabled by setting the RDPW bit
before executing the STOP instruction. When the RT signal is below the threshold
(see Figure 11-9) the oscillator circuit is forced on and the Ring Signal is
validated. If the RT rises above the threshold before the Ring Signal is validated
the oscillator will stop and the MCU will stay in the STOP mode. However, if a valid
ring is detected an interrupt is generated provided the Ring Detect Interrupt
Enable bit (RDIE) is set. The interrupt will wake the MCU from the STOP mode
and the clocks to all enabled modules will start. At this time if the CPU is not
required the WAIT mode can be entered.
If the Carrier Detect module is enabled before entering the wait mode by CDPW
bit, it will start processing the incoming data. When a valid carrier is detected an
interrupt is generated if enabled by the CDIE bit. The interrupt will take the CPU
out of the WAIT mode.
CPU STOP MODE
VALID
RT?
NO
CDPW?
YES
RDPW?
NO
NO
YES
POWER ON
CARRIER DETECT
YES
POWER ON
RING DETECT
NO
CDIE?
RDIE?
NO
YES
CD INTERRUPT
YES
RD INTERRUPT/
START PLL CLOCK
WAKE UP CPU
CPU WAIT MODE
Figure 11-5. Power Up Sequence from STOP Mode
MOTOROLA
11-4
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
CPU WAIT MODE
CDPW?
NO
YES
POWER ON
CARRIER DETECT
CDIE?
NO
YES
CD INTERRUPT
WAKE UP CPU
Figure 11-6. Power Up Sequence from WAIT Mode
11.6
DATA INTERFACE
The demodulated data from this module is available in bit-serial and 8-bit format.
The serial data can be read from CIDSD (bit 2) of the CLCSR2 register and the 8bit data is available from the Caller_ID data register CDDR. This data includes the
alternate 0 and 1 pattern, 150 ms marking which precedes data. At all other times
the demodulator output bit is high.
The Caller_ID data ready flag CDRF bit-2 of CLCSR3 will be set to indicate that
the 8-bit data is ready to be read. The data ready flag will generate an CPU
interrupt if the data ready interrupt enable DRIE bit-3 of CLCSR3 is set and the Ibit of the CCR is cleared. The Caller_ID data register CDDR acts as data buffer for
the serial to parallel data conversion register and should be read by the CPU
within 8.3msec after receiving the interrupt. Failure to do so will result data lost.
Reading the Caller_ID data register CDDR clears the Caller_ID data ready flag.
Figure 11-9 shows the timing diagram for the serial to parallel data conversion.
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-5
GENERAL RELEASE SPECIFICATION
June 11, 1997
Start-bit = ‘0’
Stop-bit = ‘1’
Mark-bit = ‘1’
Bit-Serial Cooked Data
Mark-bits (0-10 bits)
8-bit word 1
Start-bit
Mark-bits (0-10 bits)
8-bit word 1
Stop-bit
8-bit word 1
Stop-bit
Start-bit
RDRF Cleared
by CPU reading CDDR
RDRF Cleared
by CPU reading CDDR
CDRF
Stop-bit
Start-bit
Figure 11-7. 8-bit Caller ID Data Timing Diagram
11.7
CALLER-ID REGISTERS
11.7.1 Control/Status Register1 (CLCSR1)
7
CLCSR1
$000A
READ
6
RDIF
5
0
RESET
0
3
2
1
0
RDO
CDO
1
1
CDIF
RDIE
WRITE
4
CDIE
0
0
0
0
U
U
CDO, BIT0
Carrier Detect Override, when enabled by the CDOE bit in the CLCSR3
register, the carrier detect can be forced by writing a zero to this bit. On reset
this bit is set to one.
RDO, BIT1
Ring Detect Override, when enabled by RDOE in the CLCSR3 register, the ring
detect can be forced by writing a zero to this bit. On reset this bit is set to one.
CDIE, Bit4 (Carrier Detect Interrupt Enable)
When set enables the carrier detect interrupt to be generated when a carrier is
detected or forced by writing to CDO.
MOTOROLA
11-6
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
CDIF, BIT5 (Carrier Detect Interrupt Flag)
Provided the carrier detect interrupt is enabled by setting the CDIE, this bit is
set when the carrier is detected. When this flag is one an interrupt is generated.
This bit shares the interrupt vector address with Ring Detect interrupt. The
CDIF bit must be cleared by writing a zero.
RDIE, Bit6 (Ring Detect Interrupt Enable)
When set enables the ring detect interrupt to be generated when a ring is
detected or forced by writing to RDO.
RDIF, BIT7 (Ring Detect Interrupt Flag)
Provided the ring detect interrupt is enabled by setting the RDIE, this bit is set
when the ring is detected. When this flag is one an interrupt is generated. This
bit shares the interrupt vector address with Carrier Detect interrupt. The RDIF
bit must be cleared by writing a zero.
11.7.2 Control/Status Register 2 (CLCSR2)
7
CLCSR2
$000B
6
5
RDPW
CDPW
0
0
4
3
READ
2
1
0
CIDSD
RD
CD
U
1
1
WRITE
RESET
U
U
U
U = UNAFFECTED
CD, Bit0 (Carrier Detect)
This read only bit returns the value of the Carrier Detect signal which goes low
when a valid carrier is detected and remains low while the carrier remains valid.
RD, Bit1 (Ring Detect)
This read only bit returns the value of the Ring Detect signal which goes low
when a valid ringing signal is detected and remains low as long as the ringing
signal remains valid.
CIDSD, Bit2 (Caller ID Serial Data)
This read only bit returns the value of the Caller ID Serial Data (output of the on
chip demodulator) whenever the CD is low. This data includes the alternate 0
and 1 pattern, 150 ms marking which precedes the data. At all other times the
demodulator output is high.
CDPW, Bit5 (Carrier Detect Power Up)
This bit when set is used to enable carrier detection. An interrupt will be
generated when a valid carrier is detected and if the CDIE bit in the CLCSR1
register is set.
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-7
GENERAL RELEASE SPECIFICATION
June 11, 1997
RDPW, Bit6 (Ring Detect Power Up)
This bit when set is used to enable ring detection. An interrupt will be generated
when a valid ring is detected and if the RDIE bit in the CLCSR1 register is set.
11.7.3 Control/Status Register 3 (CLCSR3)
7
CLCSR3
$000C
6
5
4
3
CDRE
DRIE
U
0
2
1
0
RDOE
CDOE
0
0
CDRF
READ
SDSL
WRITE
RESET
0
U
U
0
U = UNAFFECTED
CDOE, Bit-0
Carrier Detect Override Enable, when set this bit disables the carrier detect
module output and allows the user to force the carrier detect signal by writing a
zero to CDO, bit 0 in the CLCSR1 register.
RDOE, Bit-1
Ring Detect Override Enable, when set this bit disables the ring detect module
output and allows the user to force the ring detect signal by writing a zero to
RDO, bit 1 in the CLCSR1 register.
CDRF, Bit-2
Caller_ID data ready flag. This is set to ‘1’ when the 8-bit data is ready to be
read. Reading CDDR ($000E) clears this bit.
DRIE, Bit-3 (Data Ready Interrupt Enable)
1 = Enable CDRF to cause an interrupt.
0 = Disable CDRF from generating an interrupt.
CDRE, Bit-4 (Caller_ID Receiver Enable)
1 = Enable Caller_ID 8-bit data receiver.
0 = Disable Caller_ID 8-bit data receiver.
SDSL, Bit-7 (Serial Data Select)
0 = Select cooked data to be routed to the Caller ID parallel data
receiver.
1 = Select raw data to be routed to the Caller ID parallel data receiver.
MOTOROLA
11-8
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
11.7.4 Caller_ID Data Register (CDDR)
CDDR[7:0] is the Caller ID data in byte format.
READ
CDDR
$000E
7
6
5
4
3
2
1
0
CDD7
CDD6
CDD5
CDD4
CDD3
CDD2
CDD1
CDD0
U
U
U
U
0
0
0
0
WRITE
RESET
U = UNAFFECTED
11.8
DESIGN PARAMETERS
The data signalling interface conforms to the recommended operating ranges of
the physical layer test parameters for TYPE 1 CPE as described in Bellcore
Publication SR-NWT-003004.
Table 11-1. Typical Input parameter
Parameters
Operating Range
Units
Mark Frequency
1188 ~ 1212
Hz
Space Frequency
2178 ~ 2222
Hz
Mark Level (600 ohm)
-12 ~ -32
dBm
Space Level (600 ohm)
-12 ~ -36
dBm
Carrier Frequency
1700
Hz
Twist Immunity (600 ohm)
+/- 10
dBm
Baud Rate
1188 ~ 1212
baud
Ringing Frequency
10 to 55
Hz
Noise Immunity
(Signal to Noise Ratio)
-20 (for noise below 200 and
above 3200 Hz)
25 (for noise between 200 and
3200 Hz)
dB
Channel Seizure Delay
250 ~ 3600
ms
Input Impedance
500
kΩ
Immunity to CS and MS
10
ms
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-9
GENERAL RELEASE SPECIFICATION
June 11, 1997
Table 11-2. Critical Design Characteristic
Characteristics
Typ
Unit
Input Tip/Ring Sensitivity (600 ohm)
-40
dBm
Ring/Tip Common Mode Rejection Ratio
60
dB
Bandpass Filter (BPF)
Frequency Response (relative to 1700
Hz @ 0 dB)
60 Hz
1000 Hz
2400 Hz
>=3300 Hz
-58
-1
-1
-34
dB
Carrier Detect Sensitivity (600 ohm)
-40 (-48 min)
dBm
Ring Detect Threshold (RDI2)
0.39*Vdd ± 0.1volt
Volts
RDI Threshold to keep RT_L=’1’
< 1.0
Volts
Table 11-3. Switching Characteristics (VDD= 5V; TA=25 C)
Description
Symbol
Min
Typ
Max
Unit
PLL Clock Start-up Time
tDOSC
-
-
10
ms
Carrier Detect Acquisition
tDAQ
-
14
25
ms
End of Carrier Detect
tDCH
8
-
-
ms
The transmission level from the terminating C.O will be -13.5 dBm +/- 1.0. The
expected worst case attenuation through the loop is expected to be -20dB. The
receiver therefore, should have a sensitivity of approximately -34.5 dB to handle
the worst case installations.
MOTOROLA
11-10
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
11.9
GENERAL RELEASE SPECIFICATION
MESSAGE FORMAT
2 Sec
4 Sec
2 Sec
.5 Sec
.5 Sec
0101 1
Channel
Seizure
Mark
Signal
DATA
Message
Type
Word
Message
Length
Word
Message
Word(s)
Chk sum
Word
Mark bits (0-10)
Figure 11-8. Single Message Format
2 Sec
4 Sec
.5 Sec
Ring Input
Data Word
0101 1
2 Sec
.5 Sec
DATA
Ring Time
Ring Detect
Flag cleared by SW
Ring Detect
Interrupt Flag
Carrier Detect
Carrier Detect
Interrupt Flag
Flag cleared by SW
Demodulated
Serial Data
Figure 11-9. CLID Timing Diagram
MC68HC05CL48
REV 2.0
CALLER-ID
MOTOROLA
11-11
GENERAL RELEASE SPECIFICATION
MOTOROLA
11-12
June 11, 1997
CALLER-ID
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 12
LCD DRIVER
The LCD driver module supports a 45 frontplanes by 16 backplanes or a 53
frontplanes by 8 backplanes display. This allows a maximum of 720 LCD
segments to be driven. Each segment is controlled by a corresponding bit in the
LCD RAM. On reset or on power-up, the drivers are disabled via a Display on
(DISON) bit in the LCD Control (LCDCTR) register. Figure 12-1 shows a block
diagram of the LCD subsystem.
Internal Data bus
8
Internal Address bus
13
Display RAM
LCD data latch
Backplane
Driver
Internal signals
Control Logic
45X16
BP[0:7]
BP[8:15]/
FP[45:52]
FP[0:44]
Voltage
Generator
VLCD
V0
V1
V2
V3
V4
Segment driver
Figure 12-1. LCD Driver Block Diagram
MC68HC05CL48
REV 2.0
LCD DRIVER
MOTOROLA
12-1
GENERAL RELEASE SPECIFICATION
12.1
June 11, 1997
LCD RAM.
The data to be displayed by the LCD is written to a 90 byte display RAM located at
locations $0930 thru $095C and $0A30 thru $0A5C in the memory map. The bits
are organized according to Table 12-1 and Table 12-2, with a 1 stored in a given
location resulting in the corresponding display segment being activated. The LCD
RAM is a dual port RAM that interfaces with the internal address and data buses
of the MCU. It is possible to read from LCD RAM locations for scrolling purposes.
When the display is disabled, the LCD RAM can be used as on-chip RAM.
Table 12-1. LCD RAM Organization
DATA
ADDR
0
1
2
3
4
5
6
7
$0930
FP0-BP0
FP0-BP1
FP0-BP2
FP0-BP3
FP0-BP4
FP0-BP5
FP0-BP6
FP0-BP7
$0931
FP1-BP0
FP1-BP1
FP1-BP2
FP1-BP3
FP1-BP4
FP1-BP5
FP1-BP6
FP1-BP7
$0932
FP2-BP0
FP2-BP1
FP2-BP2
FP2-BP3
FP2-BP4
FP2-BP5
FP2-BP6
FP2-BP7
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
$095A
FP42-BP0
FP42-BP1
FP42-BP2
FP42-BP3
FP42-BP4
FP42-BP5
FP42-BP6
FP42-BP7
$095B
FP43-BP0
FP43-BP1
FP43-BP2
FP43-BP3
FP43-BP4
FP43-BP5
FP43-BP6
FP43-BP7
$095C
FP44-BP0
FP44-BP1
FP44-BP2
FP44-BP3
FP44-BP4
FP44-BP5
FP44-BP6
FP44-BP7
MOTOROLA
12-2
LCD DRIVER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Table 12-2. LCD RAM Organization
DATA
ADDR
0
1
2
3
4
5
6
7
FP0-BP8
FP0-BP9
FP0-BP10
FP0-BP11
FP0-BP12
FP0-BP13
FP0-BP14
FP0-BP15
FP45-BP0
FP45-BP1
FP45-BP2
FP45-BP3
FP45-BP4
FP45-BP5
FP45-BP6
FP45-BP7
FP1-BP8
FP1-BP9
FP1-BP10
FP1-BP11
FP1-BP12
FP1-BP13
FP1-BP14
FP1-BP15
FP46-BP0
FP46-BP1
FP46-BP2
FP46-BP3
FP46-BP4
FP46-BP5
FP46-BP6
FP46-BP7
FP2-BP8
FP2-BP9
FP2-BP10
FP2-BP11
FP2-BP12
FP2-BP13
FP2-BP14
FP2-BP15
FP47-BP0
FP47-BP1
FP47-BP2
FP47-BP3
FP47-BP4
FP47-BP5
FP47-BP6
FP47-BP7
FP3-BP8
FP3-BP9
FP3-BP10
FP3-BP11
FP3-BP12
FP3-BP13
FP3-BP14
FP3-BP15
FP48-BP0
FP48-BP1
FP48-BP2
FP48-BP3
FP48-BP4
FP48-BP5
FP48-BP6
FP48-BP7
FP4-BP8
FP4-BP9
FP4-BP10
FP4-BP11
FP4-BP12
FP4-BP13
FP4-BP14
FP4-BP15
FP49-BP0
FP49-BP1
FP49-BP2
FP49-BP3
FP49-BP4
FP49-BP5
FP49-BP6
FP49-BP7
FP5-BP8
FP5-BP9
FP5-BP10
FP5-BP11
FP5-BP12
FP5-BP13
FP5-BP14
FP5-BP15
FP50-BP0
FP50-BP1
FP50-BP2
FP50-BP3
FP50-BP4
FP50-BP5
FP50-BP6
FP50-BP7
FP6-BP8
FP6-BP9
FP6-BP10
FP6-BP11
FP6-BP12
FP6-BP13
FP6-BP14
FP6-BP15
FP51-BP0
FP51-BP1
FP51-BP2
FP51-BP3
FP51-BP4
FP51-BP5
FP51-BP6
FP51-BP7
FP7-BP8
FP7-BP9
FP7-BP10
FP7-BP11
FP7-BP12
FP7-BP13
FP7-BP14
FP7-BP15
FP52-BP0
FP52-BP1
FP52-BP2
FP52-BP3
FP52-BP4
FP52-BP5
FP52-BP6
FP52-BP7
$0A38
FP8-BP8
FP8-BP9
FP8-BP10
FP8-BP11
FP8-BP12
FP8-BP13
FP8-BP14
FP8-BP15
$0A39
FP9-BP8
FP9-BP9
FP9-BP10
FP9-BP11
FP9-BP12
FP9-BP13
FP9-BP14
FP9-BP15
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
$0A5A
FP42-BP8
FP42-BP9
FP42-BP10
FP42-BP11
FP42-BP12
FP42-BP13
FP42-BP14
FP42-BP15
$0A5B
FP43-BP8
FP43-BP9
FP43-BP10
FP43-BP11
FP43-BP12
FP43-BP13
FP43-BP14
FP43-BP15
$0A5C
FP44-BP8
FP44-BP9
FP44-BP10
FP44-BP11
FP44-BP12
FP44-BP13
FP44-BP14
FP44-BP15
$0A30
$0A31
$0A32
$0A33
$0A34
$0A35
$0A36
$0A37
MC68HC05CL48
REV 2.0
LCD DRIVER
MOTOROLA
12-3
GENERAL RELEASE SPECIFICATION
12.2
June 11, 1997
LCD OPERATION
Figure 12-2 shows the backplane waveforms and some examples of frontplane
waveforms which are dependent on the LCD segments to be driven as defined in
the LCD RAM. Each “on” segment must have a differential driving voltage (BP-FP)
applied to it once in each frame; the LCD driver module hardware uses the data in
the LCD RAM to construct the frontplane waveform to meet this criterion. The
backplane waveforms are continuous and repetitive (every 2 frames); they are
fixed and not affected by the data in the LCD RAM. During WAIT mode the LCD
drivers function as normal and will keep the display active if the DISON bit (bit0 of
$07) is set.
The LCD drivers can be configured to operate with either 16 backplanes or 8
backplanes under software control.
The bias ratio can be set 1:4 or 1/5 under software control for both a 8 and 16
backplane LCD. The voltage levels required are generated internally by a resistive
divider between VLCD and VSS.
MOTOROLA
12-4
LCD DRIVER
MC68HC05CL48
REV 2.0
June 11, 1997
BP0
GENERAL RELEASE SPECIFICATION
Vlcd
V4
V3
V2
V1
V0
BP1 Vlcd
V4
V3
V2
V1
V0
BP2 Vlcd
V4
V3
V2
V1
V0
BP7 Vlcd
V4
V3
V2
V1
V0
FPX
FPY
FPZ
Vlcd
V4
V3
V2
V1
V0
Vlcd
V4
V3
V2
V1
V0
Vlcd
V4
V3
V2
V1
V0
Frame One
Figure 12-2. LCD 5:1 bias waveforms
MC68HC05CL48
REV 2.0
LCD DRIVER
MOTOROLA
12-5
GENERAL RELEASE SPECIFICATION
BP0
Vlcd
V3
V2
V1
V0
BP1
Vlcd
V3
V2
V1
V0
BP2
Vlcd
V3
V2
V1
V0
BP7
FPX
FPY
FPZ
June 11, 1997
Vlcd
V3
V2
V1
V0
Vlcd
V3
V2
V1
V0
Vlcd
V3
V2
V1
V0
Vlcd
V3
V2
V1
V0
Frame One
Figure 12-3. LCD 4:1 bias waveforms
MOTOROLA
12-6
LCD DRIVER
MC68HC05CL48
REV 2.0
June 11, 1997
12.3
GENERAL RELEASE SPECIFICATION
LCD VOLTAGE GENERATION
Figure 12-4 shows the resistive divider chain network that is used to produce the
various LCD waveforms outlined in the previous section. The LCD system can be
disabled by setting the DISON bit to 0. The voltage levels of the LCD driver
waveforms and hence the contrast of the LCD can be altered by selecting
appropriate resistors by setting the corresponding values to the CC0 to CC3 bits
in the LCDCTR register.
VLCD
DISON
V5
RL5
V4
External Caps
RL4
V3
BIAS5
RL3
V2
RL2
V1
RL1
V0
CC3
RC3
CC2
RC2
CC1
RC1
CC0
RC0
Figure 12-4. Voltage Generator
MC68HC05CL48
REV 2.0
LCD DRIVER
MOTOROLA
12-7
GENERAL RELEASE SPECIFICATION
June 11, 1997
Table 12-3. LCD Voltage Characteristic
12.4
VLCD=5.0volts
4:1 bias Voltage (volts)
Typical Values
5:1 bias Voltage (volts)]
Typical Values
V5
5.0
5.0
V4
3.75
4.0
V3
2.5
3.0
V2
2.5
2.0
V1
1.25
1.0
V0
0.0
0.0
LCD CONTROL REGISTER (LCDCR)
LCDCR
$0007
7
6
5
4
3
2
CC3
CC2
CC1
CC0
MX8
BIAS5
1
1
1
1
0
0
1
0
READ
DISON
WRITE
RESET
-
0
U = UNAFFECTED
DISON - BIT 0
1 = The Display is on when this bit is ’1’ and
0 = off when this bit is ’0’. Setting this bit to ’0’ also disconnects the
voltage generator resistor chain from VSS, thus reducing power.
BIAS5 - Bits 2
1 = Select 5:1 bias voltage levels.
0 = Select 4:1 bias voltage levels.
MX8 - bit 3
1 = the system operates with 53 frontplanes and 8 backplanes,
0 = the system operates with 45 frontplanes and 16 backplanes.
CC0 - CC3 - bits 4,5,6,7
These bits can be used to select the values of the contrast control resistors.
1 = the corresponding resistor will be shorted. On reset these bits are
set to 1.
MOTOROLA
12-8
LCD DRIVER
MC68HC05CL48
REV 2.0
June 11, 1997
12.5
GENERAL RELEASE SPECIFICATION
ELECTRICAL REQUIREMENTS
Table 12-4. Ladder Voltage Values
VLCD=5.0 volts
4:1 Bias
V5-V4
1.25 ± 4%
V4-V3
1.25 ± 4%
V3-V2
0 ± 4%
V2-V1
1.25 ± 4%
V1-V0
1.25 ± 4%
Table 12-5. Contrast Resistor Values
Resistor
Resistor Values (ohm)
+/- 25%
RC0
10k
RC1
20k
RC2
40k
RC3
80k
R1
100k
R2
100k
R3
100k
R4
100k
R5
100k
The contrast network will be monotonic under the normal operating conditions.
Note: Both ladder resistors and the contrast resistors are implemented using poly
resistor to minimize process and temperature variation.
12.5.1 DC Requirements
The DC voltage between Front-plane to Back-plane will be less than 50mV,
average over one frame. For VLCD = 3 to 5 volts and temperature range of –10°C
to 70°C.
MC68HC05CL48
REV 2.0
LCD DRIVER
MOTOROLA
12-9
GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
12-10
LCD DRIVER
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 13
PHASE-LOCKED LOOP
System clock can be obtained either from the external 32kHz oscillator or from the
PLL. During power on or external reset, the system is defaulted to use the 32 kHz
clock from the external oscillator. This is to prevent the system from using
otherwise, an unstable clock from the PLL during reset. To use the PLL clock after
power on or external reset, the PON-bit should be set ‘1’ first to switch the PLL on,
a minimum of 10msec should then be allowed for the PLL clock to stabilize before
setting the PCLK-bit to ‘1’ to switch to use the PLL clock. Power on or external
reset clears the PCLK-bit.
Four clocks at different frequencies are available to the system from the PLL using
the frequency select bits FREQ0 and FREQ1 of the PCSR, see Table 13-1.
The PLL can be powered down to save power by setting the PON-bit to ‘0’. When
the PLL is powered up after it has been powered down, again the system should
allow a minimum of 10msec before switching onto the PLL clock. The PLL when it
is powered up, will also provide the 1.8MHz clock for the Caller ID module. Before
switching the PLL off, the PCLK-bit must be cleared thus selecting the 32kHz
crystal clock as the system clock. A minimum of 2*OSC cycles should be allowed
for the system to switch from the PLL clock to the oscillator clock.
Table 13-1. System Clock Frequency Selection
MC68HC05CL48
REV 2.0
FREQ1
FREQ0
System Clock
0
0
3.6MHz
0
1
1.8MHz
1
0
900kHz
1
1
450kHz
PHASE-LOCKED LOOP
MOTOROLA
13-1
GENERAL RELEASE SPECIFICATION
13.1
June 11, 1997
PLL CONTROL AND STATUS REGISTER (PCSR $000D)
PCSR
$000D
7
6
PON
PCLK
0
0
5
4
3
2
1
FREQ1
FREQ0
0
0
0
READ
WRITE
RESET
X
X
X
X
PON - PLL power on/off bit.
1 = PLL is switched on.
0 = PLL is switched off.
PCLK - PLL Clock select bit.
1 = Use PLL clock.
0 = Use external clock.
FREQ1 - Frequency select bit 1.
FREQ0 - Frequency select bit 0.
13.2
PLL OPERATIONS
The PLL consists of an on chip VCO, a phase comparator and a divider. A filter is
required to filter the phase comparator output to provide a DC signal to control the
VCO frequency Figure 13-1.
13.3
PLL LOCK TIME
The PLL will lock in less than 10msec after the PON-bit is set. The PCLK should
not be set before the PLL is locked.
13.4
PLL CLOCK FREQUENCY
When the PLL is in lock, the VCO output frequency is given by:
Fvco = 114 * Fosc
where Fosc = oscillator frequency
Example: Fosc = 32.768kHz, Fvco = 3.604MHz.
The VCO output frequency is further divided by a frequency divider circuit to give
three other frequencies as shown in Figure 13-1.
MOTOROLA
13-2
PHASE-LOCKED LOOP
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
OSCILLATOR
External
Capacitor
XFC
32 kHz
32kHz
DIVIDE
BY 4
R2
OSC
Vss
PLLT_IN
8 kHz
Phase
R1
VCO
PLLT
Detector
32kHz
MUX
Divider
CLID clock
(1.8MHz)
PON
MUX
PCLK
Frequency
Select
System clock
FREQ1
FREQ0
PCSR
PLL_CLK
Figure 13-1. Phase Lock Loop Block Diagram
The phase comparator compares the rising edge of a 8kHz reference signal
derived from the 32kHz crystal clock to the rising edge of the VCO clock after
being divided by the divider. When there is a phase difference between the two
signals, the phase comparator output will adjust the DC level input to the VCO to
change the VCO frequency, see Figure 13-2.
Reference
Signal
8 kHz
VCO out
After divider
Phase
Detector
Output
VCO in
Figure 13-2. Typical Waveform for PLL
MC68HC05CL48
REV 2.0
PHASE-LOCKED LOOP
MOTOROLA
13-3
GENERAL RELEASE SPECIFICATION
MOTOROLA
13-4
June 11, 1997
PHASE-LOCKED LOOP
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 14
INSTRUCTION SET
This section describes the addressing modes and instruction types.
14.1
ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, No Offset
•
Indexed, 8-Bit Offset
•
Indexed, 16-Bit Offset
•
Relative
14.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long.
14.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
14.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
MC68HC05CL48
REV 2.0
INSTRUCTION SET
MOTOROLA
14-1
GENERAL RELEASE SPECIFICATION
June 11, 1997
14.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
14.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations
$0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
14.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in
the index register, and the address of the beginning of the table is in the byte following the opcode.
14.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
MOTOROLA
14-2
INSTRUCTION SET
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
14.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is
not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address
of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
14.1.9 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
MC68HC05CL48
REV 2.0
INSTRUCTION SET
MOTOROLA
14-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
14.1.10Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory.
Table 14-1 lists the register/memory instructions.
Table 14-1. Register/Memory Instructions
Instruction
MOTOROLA
14-4
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
INSTRUCTION SET
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
14.1.11Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 14-2 lists the
read-modify-write instructions.
Table 14-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
14.1.12Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
third byte to the program counter if the specified bit tests true. The bit to be tested
MC68HC05CL48
REV 2.0
INSTRUCTION SET
MOTOROLA
14-5
GENERAL RELEASE SPECIFICATION
June 11, 1997
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 14-3 lists the jump and branch instructions.
Table 14-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
Branch Never
BRN
Branch if Bit Set
MOTOROLA
14-6
Mnemonic
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
INSTRUCTION SET
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
14.1.13Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 14-4 lists these instructions.
Table 14-4. Bit Manipulation Instructions
Instruction
Clear Bit
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
14.1.14Control Instructions
These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 14-5, use inherent addressing.
Table 14-5. Control Instructions
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
MC68HC05CL48
REV 2.0
Mnemonic
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
INSTRUCTION SET
MOTOROLA
14-7
GENERAL RELEASE SPECIFICATION
June 11, 1997
14.1.15Instruction Set Summary
Table 14-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
◊ — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
◊ — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
38
48
58
68
78
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
0
b7
b0
C
b7
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — ◊ ◊ ◊
— — — — —
ff
ff
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
MOTOROLA
14-8
INSTRUCTION SET
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
Branch if Half-Carry
Bit Set
BHI rel
Branch if Higher
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Cycles
BHCS rel
H I N Z C
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Continued)
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
Description
PC ← (PC) + 2 + rel ? H = 1
Effect on
CCR
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
Branch Never
MC68HC05CL48
REV 2.0
20
rr
3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ◊
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ◊
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
PC ← (PC) + 2 + rel ? 1 = 0
INSTRUCTION SET
REL
MOTOROLA
14-9
GENERAL RELEASE SPECIFICATION
June 11, 1997
Operand
Cycles
Operation
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect on
CCR
H I N Z C
Mn ← 1
Address
Mode
Source
Form
Opcode
Table 14-6. Instruction Set Summary (Continued)
BSET n opr
Set Bit n
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
— — ◊ ◊ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — ◊ ◊ 1
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
— — ◊ ◊ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
MOTOROLA
14-10
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
INSTRUCTION SET
— — 0 1 —
— — ◊ ◊ —
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Continued)
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
0 — — — 0
INH
42
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
— — ◊ ◊ —
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
X ← (M)
C
0
b7
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
Negate Byte
(Two’s Complement)
NOP
No Operation
MC68HC05CL48
REV 2.0
b0
— — 0 ◊ ◊
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
— — — — —
INSTRUCTION SET
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
5
3
3
6
5
2
MOTOROLA
14-11
GENERAL RELEASE SPECIFICATION
June 11, 1997
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — ◊ ◊ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
39
49
59
69
79
dd
— — ◊ ◊ ◊
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
Effect on
CCR
Description
H I N Z C
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
C
b7
b0
ff
Cycles
Opcode
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary (Continued)
2
3
4
5
4
3
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
◊ ◊ ◊ ◊ ◊
INH
80
6
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
A ← (A) – (M) – (C)
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
C
b7
— — ◊ ◊ ◊
b0
ff
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ◊ ◊ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — ◊ ◊ —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
MOTOROLA
14-12
Store Index
Register In Memory
M ← (A)
M ← (X)
INSTRUCTION SET
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
2
3
4
5
4
3
Subtract Memory
Byte from
Accumulator
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Software Interrupt
INH
83
10
TAX
Transfer
Accumulator to
Index Register
— — — — —
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock
and Enable
Interrupts
— ◊ — — —
INH
8F
2
A ← (A) – (M)
X ← (A)
(M) – $00
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
MC68HC05CL48
REV 2.0
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
INSTRUCTION SET
dd
ff
Cycles
— — ◊ ◊ ◊
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Operation
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary (Continued)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MOTOROLA
14-13
MSB
LSB
0
1
2
3
4
MOTOROLA
14-14
5
6
7
8
9
A
B
C
D
E
INSTRUCTION SET
F
Table 14-7. Opcode Map
INH
INH
IMM
DIR
Control
IX
2
2
2
2
2
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
2
2
IMM 2
LDA
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
6
2
IMM 2
ADD
BSR
0
3
IX2
IX1
IX
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
EXT
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
IX1 1
5
IX1 1
4
IX1 1
4
AND
BIT
LDA
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
JSR
LDX
STX
DIR Number of Bytes/Addressing Mode
4
F
IX2 2
5
IX2 2
5
IX2 2
6
IX2 2
5
IX2 2
7
IX2 2
5
IX2 2
6
IX2 2
SUB
E
5
D
STX
LDX
JSR
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
BIT
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
IX2 2
5
SUB
C
SUB
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
4
Register/Memory
DIR 3
3
DIR 3
3
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
EXT 3
STX
5 Number of Cycles
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
BIT
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
DIR 3
3
SUB
IX1
2
INH
Read-Modify-Write
INH
6
RTS
INH
10
INH
SWI
INH
2
CLC
INH 2
2
INH 2
2
SEC
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
REL 2
2
3
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
MSB
0
LSB
2
INH 2
2
INH
TXA
SUB
INH
2
DIR
1
9
REL
5
IX 1
5
IX
5
IX
5
RTI
DIR
5
DIR
Bit Manipulation Branch
COM
LSR
ROR
ASR
IX 1
B
IX1 1
6
6
IX1 1
IX1 1
6
COM
LSR
ROR
NEG
A
6
9
3
3
NEG
8
3
7
RORX
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
6
3
11
COMA
INH
3
MUL
INH 1
NEGA
5
5
1
DIR 1
NEG
5
INH 1
3
INH 1
LSRA
3
IX1 1
6
ASR
IX
5
IX
5
1
1
1
1
2
1
STOP
IX
5
1
INH 1
WAIT
INH
2
IX
5
IX
4
IX
5
IX 1
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
ASL/LSL
IX1 1
6
IX1 1
6
ROL
IX1 1
6
IX1 1
5
6
IX1 1
DEC
INC
TST
IX1 1
6
IX1 1
CLR
2
4
3
2
3
BRA
COM
DIR 1
5
DIR 1
LSR
RORA
INH 2
3
ASRX
INH 2
3
INH 2
3
ROLX
INH 2
3
3
INH 2
DECX
INCX
INH 2
3
TSTX
INH 2
3
INH 2
CLRX
TAX
2
5
REL 2
3
BRN
REL
3
BHI
REL
3
BLS
REL 2
3
BCC
5
INH 1
3
ASRA
INH 1
3
INH 1
3
ROLA
INH 1
3
3
INH 1
DECA
INCA
INH 1
3
TSTA
INH 1
3
INH 1
CLRA
1
1
BSET0
DIR 2
5
BCLR0
DIR 2
5
BSET1
DIR 2
5
BCLR1
DIR 2
5
BSET2
REL 2
3
ROR
DIR 1
5
ASR
DIR 1
5
5
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET3
DIR 2
5
BCLR3
DIR 2
5
BSET4
DIR 2
5
BCLR4
DIR 2
5
BSET5
DIR 2
5
BCLR5
DIR 2
5
BSET6
DIR 2
5
BCLR6
DIR 2
5
BSET7
DIR 2
5
DIR 2
BCLR7
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
0
5
BRSET0
3
DIR 2
5
BRCLR0
3
DIR 2
5
BRSET1
3
DIR 2
5
BRCLR1
3
DIR 2
5
BRSET2
3
DIR 2
5
BRCLR2
3
DIR 2
5
BRSET3
3
DIR 2
5
BRCLR3
3
DIR 2
5
BRSET4
3
DIR 2
5
BRCLR4
3
DIR 2
5
BRSET5
3
DIR 2
5
BRCLR5
3
DIR 2
5
BRSET6
3
DIR 2
5
BRCLR6
3
DIR 2
5
BRSET7
3
DIR 2
5
DIR 2
BRCLR7
3
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
2
IX
5
IX
3
IX
4
IX
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
SECTION 15
ELECTRICAL SPECIFICATIONS
15.1
MAXIMUM RATINGS
(Voltages referenced to VSS)
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
LCD Supply Voltage
VLCD
VDD to +6.0
V
Input Voltage
VIN
VSS – 0.3 to VDD + 0.3
V
Self-Check Mode (IRQ/IRQ Pin only)
VIN
VSS – 0.3 to 2xVDD +0.3
V
I
25
mA
TA
–10 to 70
°C
TSTG
–65 to 150
°C
Current Drain per pin excluding VDD and VSS
Operating Temperature Range
Storage Temperature Range
NOTE
Maximum current drain per pin is for one pin at a time, limited by an
external resistor.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to
this high-impedance circuit. For proper operation, it is recommended that VIN and
VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is
enhanced if unused inputs are connected to an appropriate logic voltage level
(e.g., either VSS or VDD).
15.2
THERMAL CHARACTERISTICS
Rating
Thermal resistance (Plastic)
MC68HC05CL48
REV 2.0
Symbol
Value
Unit
θJA
60
°C/W
ELECTRICAL SPECIFICATIONS
MOTOROLA
15-1
GENERAL RELEASE SPECIFICATION
15.3
June 11, 1997
DC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 VDC ±10%, VSS = 0 VDC, TA =–10°C to +70 °C, unless otherwise noted)
CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Output Voltage
ILOAD = –10µA
ILOAD = 10µA
VOL
VOH
—
VDD–0.1
—
—
0.1
—
V
V
Output High Voltage
ILOAD = 0.8mA
PTA0-7,PTB0-7, PTC0-7
VOH
VDD–0.8
—
Output Low Voltage
ILOAD = 1.6mA
PTA0-7, PTB0-7,PTC0-7
VOL
—
—
0.4
V
Input High Voltage
PTA0-7,PTB0-7,PTC0-7,RESET, IRQ, OSC1,
VIH
0.8xVDD
—
VDD
V
VIL
VSS
—
0.2xVDD
V
Output Sink Current (from 5V)
PTA0-7,PTB0-7, PTC0-7
ISINK
—
—
3.0
mA
Output Source Current (into 2.5V)
PTA0-7,PTB0-7, PTC0-7
ISINK
—
3.0
—
mA
IOZ
—
—
±100
nA
IOZ
—
—
±10
µA
CIN
COUT
—
—
12
12
pF
pF
Input Low Voltage
PTA0-7, PTB0-7, PTC0-7,RESET, IRQ, OSC1,
TCAP1,TCAP2
I/O Ports High-Z leakage
PTA0-7,PTB0-7,PTC0-7
Measured with input at (VDD - 0.1) volts and
(VSS + 0.1) volts.
Input Current
RESET, IRQ, IRQ0, IRQ1, IRQ2, OSC1, TCAP1
TCAP2
Capacitance
All input or output.
—
V
Notes:
(1) All values shown reflect average measurements.
(2) Typical values at midpoint of voltage range, 25°C only.
(3) Wait IDD : Only timer system active.
(4) Run (Operating) IDD , Wait IDD : Measured with all inputs 0.2 V from rail; no D.C. loads, less than 50pF on all
outputs, CL = 20 pF on OSC2.
(5) Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 V, VIH = VDD–0.2 V.
(6) Stop IDD measured with OSC1 = VSS.
(7) Wait IDD is affected linearly by the OSC2 capacitance.
MOTOROLA
15-2
ELECTRICAL SPECIFICATIONS
MC68HC05CL48
REV 2.0
June 11, 1997
15.4
GENERAL RELEASE SPECIFICATION
POWER DISSIPATION
(VDD = 3.3Vdc, VSS = 0 Vdc, TA =–10°C to +70 °C, unless otherwise noted)
Symbol
Max
(HC705CL48)
Max
(HC05CL48)
Unit
RUNNING
(a)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
LCD = active
ATD = active
SPI = active
CLID = active
IDD
6.34
6.5
mA
RUNNING
(b)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
LCD = active
IDD
3.82
2.8
mA
RUNNING
(c)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
ATD = active
LCD = active
IDD
4.13
3.0
mA
WAIT
(d)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
ATD = active
LCD = active
IDD
2.67
1.0
mA
RUNNING
(e)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
ATD = active
CLID = active
LCD = active
IDD
6.36
6.5
mA
WAIT
(f)
System Clock = 3.6MHz
PLL = active
Core Timer = active
WTimer = active
ATD = active
CLID = active
LCD = active
IDD
4.90
2.5
mA
Mode
Conditions
STOP
(g)
System Clock = 32kHz
LCD = active
WTimer = active
IDD
80
80
µA
STOP
(h)
No Oscillator
All modules switched off.
IDD
7
7
µA
MC68HC05CL48
REV 2.0
ELECTRICAL SPECIFICATIONS
MOTOROLA
15-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
Mode
Conditions
Symbol
Max
(HC705CL48)
Max
(HC05CL48)
Unit
Data
Retention
(i)
VDD=2.0, RESETB = “0”
No Oscillator
IDD
5
5
µA
Start Up
(j)
VDD= 0 to 3V, RESETB = “0”
IDD
3.0
3.0
mA
Note: The above IDD measurements include the 32kHz oscillator IDD configured as in Figure 1-4 (a) except for
case (h) and (i).
15.5
CONTROL TIMING
(VDD = 3.3 VDC ±10%, VSS = 0 VDC, TA = –10°C to +70°C, unless otherwise noted)
CHARACTERISTIC
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock
fOSC
fIN
32.768
—
32.768
—
kHz
MHz
Internal operating frequency
Crystal option
External clock
fOP
fOP
0.016384
—
1.802
—
MHz
MHz
Cycle time
tCYC
61035
555
ns
Crystal Oscillator Start-up time. (Refer to Figure 1-4 (a))
“From supply=Vdd to the end of POR cycles.”
tOXOV
—
3
s
Crystal Oscillator Start-up Voltage
tOXOV
2.7
5.0
Volts
AV
10
25
Stop recovery Start-up time (crystal oscillator + POR cycles)
tILCH
—
70
ms
PLL lock time (after asserting PON-bit)
tPLL
—
10
ms
RESET pulse width
tRL
1.5
IOUT
tCYC
Interrupt pulse width (Edge triggered)
tILIH
119
IIN
ns
Interrupt pulse period
tILIL
See note1
—
tCYC
t
270
280
ns
Crystal Oscillator Small Signal Voltage Gain
OSC1 Pulse Width
Notes:
(1) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt
service routine plus 21 tCYC.
15.6
ESD PROTECTION
All pads are designed to withstand 2kV of ESD.
MOTOROLA
15-4
ELECTRICAL SPECIFICATIONS
MC68HC05CL48
REV 2.0
June 10, 1997
GENERAL RELEASE SPECIFICATION
SECTION 16
MECHANICAL SPECIFICATIONS
This section outlines the mechanical dimensions of the 112-pin TQFP and 100-pin
TQFP packages.
MC68HC05CL48
REV 2.0
MECHANICAL SPECIFICATIONS
MOTOROLA
16-1
GENERAL RELEASE SPECIFICATION
16.1
June 10, 1997
112-PIN THIN-QUAD-FLAT-PACKAGE (CASE 987-01)
0.20 T L–M N
4X
PIN 1
IDENT
0.20 T L–M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
X
X=L, M OR N
G
108X
VIEW Y
V
B
L
M
B1
28
J
V1
57
29
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
AA
F
D
56
0.13
N
M
BASE
METAL
T L–M N
SECTION J1–J1
ROTATED 90 _ COUNTERCLOCKWISE
A1
S1
A
S
C2
C
VIEW AB
q2
0.050
0.10 T
112X
SEATING
PLANE
q3
T
q
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 PER SIDE. DIMENSIONS A AND B INCLUDE
MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
q1
(Y)
(Z)
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
q
q1
q2
q3
VIEW AB
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
–––
1.600
0.050
0.150
1.350
1.450
0.270
0.370
0.450
0.750
0.270
0.330
0.650 BSC
0.090
0.170
0.500 REF
0.325 BSC
0.100
0.200
0.100
0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090
0.160
0°
8°
3°
7°
11°
13°
11°
13°
Figure 16-1. 112-Pin TQFP Mechanical Dimensions
MOTOROLA
16-2
MECHANICAL SPECIFICATIONS
MC68HC05CL48
REV 2.0
June 10, 1997
16.2
GENERAL RELEASE SPECIFICATION
100-PIN THIN-QUAD-FLAT-PACKAGE (CASE 983-02)
0.2 T L±M N
4X
G
0.2 T L±M N
4X 25 TIPS
76
100
CL
1
X
X = L, M OR N
AB
75
AB
L
VIEW Y
M
B V
BASE METAL
F
3X
VIEW Y
V1
B1
25
J
U
D
51
PLATING
0.08
26
N
A1
M
T L±M N
50
SECTION AB±AB
S1
ROTATED 90 CLOCKWISE
A
S
4X
C
2
0.08 T
100X
SEATING
PLANE
T
4X
3
VIEW AA
0.05
(W)
1
R1
2X R
0.25
C2
GAGE PLANE
(K)
E
C1
(Z)
VIEW AA
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07.
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
1
2
3
MILLIMETERS
MAX
MIN
14.00 BSC
7.00 BSC
14.00 BSC
7.00 BSC
±±±
1.70
0.05
0.20
1.30
1.50
0.10
0.30
0.45
0.75
0.15
0.23
0.50 BSC
0.07
0.20
0.50 REF
0.08
0.20
16.00 BSC
8.00 BSC
0.09
0.16
16.00 BSC
8.00 BSC
0.20 REF
1.00 REF
0
7
0
±±±
12 REF
12 REF
Figure 16-2. 100-Pin TQFP Mechanical Dimensions
MC68HC05CL48
REV 2.0
MECHANICAL SPECIFICATIONS
MOTOROLA
16-3
GENERAL RELEASE SPECIFICATION
MOTOROLA
16-4
June 10, 1997
MECHANICAL SPECIFICATIONS
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
APPENDIX A
MC68HC705CL48
This appendix describes the differences between the MC68HC705CL48 and
MC68HC05CL48.
This part is for user system evaluation and debugging only, and is not
recommended for mass production.
A.1
INTRODUCTION
The MC68HC705CL48 is an EPROM version of the MC68HC05CL48, and is
available for user system evaluation and debugging only. The MC68HC705CL48
is functionally identical to the MC68HC05CL48 with the exception of the 47.5kbyte user ROM replaced by 47.5k-byte user EPROM and, the self-check routine is
replaced by a bootstrap routine.
A.2
MEMORY
The MC68HC705CL48 memory map is shown in Figure A-1.
A.3
BOOTLOADER MODE
Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is
at VTST and the PTB7 pin is at logic one. The Bootloader program and vectors are
masked in the ROM area from $FE00 to $FFEF. This program handles copying of
user code from an external EPROM into the on-chip EPROM. The bootload
function has to be done from an external EPROM. The bootloader performs one
programming pass at 1ms per byte then does a verify pass.
The user code must be a one-to-one correspondence with the internal EPROM
addresses.
MC68HC05CL48
REV 2.0
MOTOROLA
A-1
GENERAL RELEASE SPECIFICATION
$0000
$002F
$0030
June 11, 1997
I/O Register
48 Bytes
Port A Data Register
$00
Port B Data Register
$01
RAM
144 Bytes
Port C Data Register
$02
Port A Direction Register
$03
Port B Direction Register
Port C Direction Register
$04
Stack
64 Bytes
Timer Pin Configuration Register
LCD Control Register
$06
Core Timer Control/Status Register
$08
Core Timer Register
Caller ID Control/Status Register 1
$09
$0A
Caller ID Control/Status Register 2
$0B
Caller ID Control/Status Register 3
PLL Status/Data Register
$0C
Caller ID Data Register
Input Capture High Register 2
$0E
Input Capture Low Register 2
$10
Timer Control Register
$11
Timer Status Register
Input Capture High Register 1
$12
Input Capture Low Register 1
$14
Output Compare High Register 1
$15
Output Compare Low Register 1
Output Compare High Register 2
$16
Output Compare Low Register 2
$18
$00C0
$00FF
$0100
RAM
1840 Bytes
$082F
$0830
$092F
$0930
$095C
$095D
$0A2F
$0A30
$0A5C
$0A5D
$3FFF
$4000
$FDFF
$FE00
Not Used
LCD RAM
45 Bytes Block1
Not Used
LCD RAM
45 Bytes Block2
Not Used
EPROM
47.5k Bytes
Bootstrap ROM
496 Bytes
$FFDF
$FFE0 Bootstrap Vectors
16 Bytes
$FFEF
$FFF0
User Vectors
16 Bytes
$FFFF
$FFF0
Ctimer/WTimer
$FFF1
$FFF2
IRQn/KBI $FFF3
$FFF4
Caller_ID $FFF5
$FFF6
SPI
$FFF7
$FFF8
Timer
$FFF9
$FFFA
IRQ
$FFFB
$FFFC
SWI
$FFFD
$FFFE
Reset
$FFFF
$05
$07
$0D
$0F
$13
$17
Counter High Register
$19
Counter Low Register
$1A
Alternate Counter High Register
$1B
Alternate Counter Low Register
$1C
External Interrupt Control Register
External Interrupt Status Register
$1D
Option Register
SPI Control Register
$1F
SPI Status Register
SPI Data Register
$21
A/D Control and Status Register
$24
A/D Data Register
$25
EPROM Program Control Register
$26
$1E
$20
$22
Watch Timer Control & Status Register $23
$27
Reserved
$2F
Figure A-1. MC68HC705CL48 Memory Map
MOTOROLA
A-2
MC68HC05CL48
REV 2.0
June 11, 1997
A.4
GENERAL RELEASE SPECIFICATION
EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control
Register located at address $26.
Please contact Motorola for programming board availability.
A.4.1 EPROM Program Control Register (EPCR $26)
This register is provided for programming the on-chip EPROM in the
MC68HC705CL48.
bit-7
EPCR
$0026
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
ELAT
PGM
0
0
Read
RESERVED
Write
Reset
0
0
0
0
0
0
ELAT—EPROM LATch control
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming (writes
to EPROM cause address and data to be latched). EPROM is in
programming mode and cannot be read if ELAT is 1. This bit should
not be set when no programming voltage is applied to the Vpp pin.
PGM—EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT ≠ 1,
then PGM = 0.
A.4.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
MC68HC05CL48
REV 2.0
MOTOROLA
A-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure A-2 shows the flow required to successfully program the EPROM.
START
ELAT=1
Write EPROM byte
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write
additional
byte?
N
END
Figure A-2. EPROM Programming Sequence
MOTOROLA
A-4
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
APPENDIX B
MC68HC05CL16
This appendix describes the differences between the MC68HC05CL16 and
MC68HC05CL48. The entire MC68HC05CL48 data sheet applies to the
MC68HC05CL16, with exceptions outlined in this appendix.
B.1
INTRODUCTION
The MC68HC05CL16 is functionally identical to the MC68HC05CL48, except the
following:
Table B-1. MC68HC05CL16 and MC68HC05CL48 Differences
MC68HC05CL16
MC68HC05CL48
16k-bytes user ROM
47.5k-bytes user ROM
—
LCD driver output voltages:
V0, V1, V2, V3, V4
100-pin TQFP
112-pin TQFP
Figure B-1 shows a block diagram of the MC68HC05CL16.
B.2
SIGNAL DESCRIPTION
The LCD driver voltages from the resistor ladder, V0, V1, V2, V3, and V4 on the
MC68HC05CL48 are not available on the MC68HC05CL16.
B.3
MEMORY
The MC68HC05CL16 has 16k-bytes of user ROM.
The MC68HC05CL16 memory map is shown in Figure B-2.
MC68HC05CL48
REV 2.0
MOTOROLA
B-1
IRQ/VPP
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
ACCUMULATOR
M68HC05
MCU
INDEX REGISTER
RESET
RESET
STACK POINTER
0 0 0 0 0 0 0 0 1 1
PROGRAM COUNTER
CONDITION CODE REGISTER
1 1 1 H I N C Z
PTA7/KB7
PTA6/KB6
PTA5/KB5
PTA4/KB4
PTA3/KB3
PTA2/IRQ2
PTA1/IRQ1
PTA0/IRQ0
PORT A
PORT B
USER RAM — 2k BYTES
DATA DIRECTION REGISTER C
USER ROM — 16k BYTES
DATA DIRECTION REGISTER B
DATA DIRECTION REGISTER A
June 11, 1997
CONFIGURATION REGISTER C
GENERAL RELEASE SPECIFICATION
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
CPU CLOCK
DIVIDE
BY TWO
INTERNAL CLOCK
PLL
XFC
WTIMER
COP
WATCHDOG
TCAP1
TIMER
TCAP2
AD2
AD3
SS
SCK
MOSI
AD1
AD0
A/D
SPI
MISO
VLCD
LCD DRIVER
FP[44:0]
POWER
BP[15:0]
VDD
VSS
PTC7/TCAP2
PTC6/TCAP1
PORT C
INTERNAL
OSCILLATOR
CALLER ID
OSC1
OSC2
PTC5/AD3
PTC4/AD2
PTC3/ SS
PTC2/MOSI
PTC1/MISO
PTC0/SCK
FSK+
FSK–
RT_L
RD1
RD2
Figure B-1. MC68HC05CL16 Block Diagram
MOTOROLA
B-2
MC68HC05CL48
REV 2.0
June 11, 1997
$0000
$002F
$0030
I/O Register
48 Bytes
Port B Data Register
$01
$02
Port A Direction Register
$03
Port B Direction Register
Port C Direction Register
$04
Stack
64 Bytes
Timer Pin Configuration Register
LCD Control Register
$06
Core Timer Control/Status Register
$08
Core Timer Register
Caller ID Control/Status Register 1
$09
$0A
Caller ID Control/Status Register 2
$0B
Caller ID Control/Status Register 3
PLL Status/Data Register
$0C
Caller ID Data Register
Input Capture High Register 2
$0E
RAM
Not Used
LCD RAM
45 Bytes Block1
Not Used
LCD RAM
45 Bytes Block2
Not Used
$BDFF
$BE00
$FDFF
$FE00
$00
Port C Data Register
1840 Bytes
$082F
$0830
$092F
$0930
$095C
$095D
$0A2F
$0A30
$0A5C
$0A5D
Port A Data Register
RAM
144 Bytes
$00C0
$00FF
$0100
GENERAL RELEASE SPECIFICATION
ROM
16k Bytes
Self-check ROM
496 Bytes
$FFDF
$FFE0 Self-check Vectors
16 Bytes
$FFEF
$FFF0
User Vectors
16 Bytes
$FFFF
$FFF0
Ctimer/WTimer
$FFF1
$FFF2
IRQn/KBI $FFF3
$FFF4
Caller_ID $FFF5
$FFF6
SPI
$FFF7
$FFF8
Timer
$FFF9
$FFFA
IRQ
$FFFB
$FFFC
SWI
$FFFD
$FFFE
Reset
$FFFF
$05
$07
$0D
$0F
Input Capture Low Register 2
$10
Timer Control Register
$11
Timer Status Register
Input Capture High Register 1
$12
$13
Input Capture Low Register 1
$14
Output Compare High Register 1
$15
Output Compare Low Register 1
Output Compare High Register 2
$16
Output Compare Low Register 2
$18
$17
Counter High Register
$19
Counter Low Register
$1A
Alternate Counter High Register
$1B
Alternate Counter Low Register
$1C
External Interrupt Control Register
External Interrupt Status Register
$1D
Option Register
SPI Control Register
$1F
SPI Status Register
SPI Data Register
$21
A/D Control and Status Register
$24
A/D Data Register
$25
Reserved for EPROM (EPCR)
$26
$1E
$20
$22
Watch Timer Control & Status Register $23
$27
Reserved
$2F
Figure B-2. MC68HC05CL16 Memory Map
MC68HC05CL48
REV 2.0
MOTOROLA
B-3
GENERAL RELEASE SPECIFICATION
B.4
June 11, 1997
PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
FP44
BP15/FP45
BP14/FP46
BP13/FP47
BP12/FP48
BP11/FP49
BP10/FP50
BP9/FP51
BP8/FP52
BP7
BP6
BP5
BP4
BP3
BP2
BP1
BP0
VLCD
PTC0/SCK
PTC1/MISO
PTC2/MOSI
PTC3/SS
PTC4AD2
PTC5/AD3
PTC6/TCAP1
The MC68HC05CL16 pin assignment for the 100-pin TQFP package is shown in
Figure B-3.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MC68HC05CL16
PTC7/TCAP2
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
VDD
VSS
AD1
AD0
FSK+
FSK–
RT_L
RD1
RD2
OSC2
OSC1
RESET
XFC
IRQ/VPP*
PTA7/KBI7
PTA6/KBI6
PTA4/KBI4
PTA5/KBI5
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
PTA0/IRQ0B
PTA1/IRQ1B
PTA2/IRQ2
PTA3/KBI3
FP18
FP17
FP16
FP15
FP14
FP13
FP12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
FP43
FP42
FP41
FP40
FP39
FP38
FP37
FP36
FP35
FP34
FP33
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
*VPP is available on MC68HC705CL16 only
Figure B-3. MC68HC05CL16 Pin Assignment
MOTOROLA
B-4
MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
APPENDIX C
MC68HC705CL16
This appendix describes the differences between the MC68HC705CL16 and
MC68HC05CL16.
This part is for user system evaluation and debugging only, and is not
recommended for mass production.
C.1
INTRODUCTION
The MC68HC705CL16 is an EPROM version of the MC68HC05CL16, and is
available for user system evaluation and debugging only. The MC68HC705CL16
is functionally identical to the MC68HC05CL16 with the exception of the 16k-byte
user ROM replaced by 16k-byte user EPROM and, the self-check routine is
replaced by a bootstrap routine.
C.2
MEMORY
The MC68HC705CL16 memory map is shown in Figure C-1.
C.3
BOOTLOADER MODE
Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is
at VTST and the PTB7 pin is at logic one. The Bootloader program and vectors are
masked in the ROM area from $FE00 to $FFEF. This program handles copying of
user code from an external EPROM into the on-chip EPROM. The bootload
function has to be done from an external EPROM. The bootloader performs one
programming pass at 1ms per byte then does a verify pass.
The user code must be a one-to-one correspondence with the internal EPROM
addresses.
MC68HC05CL48
REV 2.0
MOTOROLA
C-1
GENERAL RELEASE SPECIFICATION
$0000
$002F
$0030
June 11, 1997
I/O Register
48 Bytes
Port A Data Register
$00
Port B Data Register
$01
RAM
144 Bytes
Port C Data Register
$02
Port A Direction Register
$03
Port B Direction Register
Port C Direction Register
$04
Stack
64 Bytes
Timer Pin Configuration Register
LCD Control Register
$06
Core Timer Control/Status Register
$08
Core Timer Register
Caller ID Control/Status Register 1
$09
$0A
Caller ID Control/Status Register 2
$0B
Caller ID Control/Status Register 3
PLL Status/Data Register
$0C
Caller ID Data Register
Input Capture High Register 2
$0E
Input Capture Low Register 2
$10
Timer Control Register
$11
Timer Status Register
Input Capture High Register 1
$12
Input Capture Low Register 1
$14
Output Compare High Register 1
$15
Output Compare Low Register 1
Output Compare High Register 2
$16
Output Compare Low Register 2
$18
$00C0
$00FF
$0100
RAM
1840 Bytes
$082F
$0830
$092F
$0930
$095C
$095D
$0A2F
$0A30
$0A5C
$0A5D
Not Used
LCD RAM
45 Bytes Block1
Not Used
LCD RAM
45 Bytes Block2
Not Used
$BDFF
$BE00
$FDFF
$FE00
EPROM
16k Bytes
Bootstrap ROM
496 Bytes
$FFDF
$FFE0 Bootstrap Vectors
16 Bytes
$FFEF
$FFF0
User Vectors
16 Bytes
$FFFF
$FFF0
Ctimer/WTimer
$FFF1
$FFF2
IRQn/KBI $FFF3
$FFF4
Caller_ID $FFF5
$FFF6
SPI
$FFF7
$FFF8
Timer
$FFF9
$FFFA
IRQ
$FFFB
$FFFC
SWI
$FFFD
$FFFE
Reset
$FFFF
$05
$07
$0D
$0F
$13
$17
Counter High Register
$19
Counter Low Register
$1A
Alternate Counter High Register
$1B
Alternate Counter Low Register
$1C
External Interrupt Control Register
External Interrupt Status Register
$1D
Option Register
SPI Control Register
$1F
SPI Status Register
SPI Data Register
$21
A/D Control and Status Register
$24
A/D Data Register
$25
EPROM Program Control Register
$26
$1E
$20
$22
Watch Timer Control & Status Register $23
$27
Reserved
$2F
Figure C-1. MC68HC705CL16 Memory Map
MOTOROLA
C-2
MC68HC05CL48
REV 2.0
June 11, 1997
C.4
GENERAL RELEASE SPECIFICATION
EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control
Register located at address $26.
Please contact Motorola for programming board availability.
C.4.1 EPROM Program Control Register (EPCR $26)
This register is provided for programming the on-chip EPROM in the
MC68HC705CL16.
bit-7
EPCR
$0026
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
ELAT
PGM
0
0
Read
RESERVED
Write
Reset
0
0
0
0
0
0
ELAT—EPROM LATch control
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming (writes
to EPROM cause address and data to be latched). EPROM is in
programming mode and cannot be read if ELAT is 1. This bit should
not be set when no programming voltage is applied to the Vpp pin.
PGM—EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT ≠ 1,
then PGM = 0.
C.4.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
MC68HC05CL48
REV 2.0
MOTOROLA
C-3
GENERAL RELEASE SPECIFICATION
June 11, 1997
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure C-2 shows the flow required to successfully program the EPROM.
START
ELAT=1
Write EPROM byte
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write
additional
byte?
N
END
Figure C-2. EPROM Programming Sequence
MOTOROLA
C-4
MC68HC05CL48
REV 2.0
How to reach us:
MFAX: [email protected] – TOUCHTONE 602-244-6609
INTERNET: http://www.mot-sps.com/csic
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Colorado 80217. 303-675-2140 or 1-800-441-2447
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku,
Tokyo 135, Japan. 03-81-3521-8315
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road,
Tai Po, N.T., Hong Kong. 852-26629298
HC05CL48GRS/H