ETC HC705JB2GRS

Freescale Semiconductor, Inc.
HC705JB2GRS/H
REV 1.1
Freescale Semiconductor, Inc...
68HC705JB2
SPECIFICATION
(General Release)
August 28, 1998
Consumer Systems Group
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
 Motorola, Inc., 1998
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Title
Page
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
FEATURES ...................................................................................................... 1-1
MASK OPTIONS.............................................................................................. 1-2
MCU STRUCTURE.......................................................................................... 1-3
FUNCTIONAL PIN DESCRIPTIONS ............................................................... 1-4
VDD, VSS .................................................................................................... 1-4
OSC1, OSC2 ............................................................................................... 1-4
RESET......................................................................................................... 1-6
IRQ/VPP ...................................................................................................... 1-6
PA0-PA7 ...................................................................................................... 1-7
PB0-PB2 ...................................................................................................... 1-7
D+, D– ......................................................................................................... 1-7
3.3V ............................................................................................................. 1-7
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
2.5
MEMORY MAP ................................................................................................ 2-1
I/O AND CONTROL REGISTERS ................................................................... 2-2
RAM ................................................................................................................. 2-3
EPROM ............................................................................................................ 2-3
BOOTLOADER ROM....................................................................................... 2-3
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A)........................................................................................ 3-2
INDEX REGISTER (X) ..................................................................................... 3-2
STACK POINTER (SP) .................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-3
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
Half Carry Bit (H-Bit) .................................................................................... 3-3
Interrupt Mask (I-Bit) .................................................................................... 3-3
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-4
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
CPU INTERRUPT PROCESSING ................................................................... 4-1
RESET INTERRUPT SEQUENCE .................................................................. 4-2
SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4
HARDWARE INTERRUPTS ............................................................................ 4-4
MC68HC705JB2
REV 1.1
MOTOROLA
i
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
TABLE OF CONTENTS
Section
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
Title
Page
External Interrupt (IRQ) ............................................................................... 4-4
IRQ Control/status Register (ICSR) $0A ..................................................... 4-5
Optional External Interrupts (PA0-PA3)....................................................... 4-6
Timer1 Interrupt (TIMER1)........................................................................... 4-7
USB Interrupt (USB) .................................................................................... 4-7
MFT Interrupt (MFT) .................................................................................... 4-7
Freescale Semiconductor, Inc...
SECTION 5
RESETS
5.1
EXTERNAL RESET (RESET).......................................................................... 5-2
5.2
INTERNAL RESETS ........................................................................................ 5-2
5.2.1
Power-On Reset (POR) ............................................................................... 5-2
5.2.2
USB Reset ................................................................................................... 5-2
5.2.3
Illegal Address Reset (ILADR)..................................................................... 5-3
5.2.4
Low Voltage Reset (LVR) ............................................................................ 5-3
SECTION 6
LOW POWER MODES
6.1
6.2
6.3
STOP MODE.................................................................................................... 6-1
WAIT MODE .................................................................................................... 6-1
DATA-RETENTION MODE.............................................................................. 6-3
SECTION 7
INPUT/OUTPUT PORTS
7.1
PORT A............................................................................................................ 7-2
7.1.1
Port A Data Register.................................................................................... 7-2
7.1.2
Port A Data Direction Register..................................................................... 7-2
7.1.3
Port A Pulldown Register............................................................................. 7-3
7.1.4
Port A Drive Capability................................................................................. 7-3
7.1.5
Port A I/O Pin Interrupts............................................................................... 7-3
7.2
PORT B............................................................................................................ 7-4
7.2.1
Port B Data Register.................................................................................... 7-4
7.2.2
Port B Data Direction Register..................................................................... 7-5
7.2.3
Slow Output Falling-Edge Transition ........................................................... 7-5
7.2.4
Port B Pulldown/Pullup Register.................................................................. 7-5
7.3
I/O PORT PROGRAMMING ............................................................................ 7-6
7.3.1
Pin Data Direction........................................................................................ 7-6
7.3.2
Output Pin.................................................................................................... 7-6
7.3.3
Input Pin....................................................................................................... 7-6
7.3.4
I/O Pin Transitions ....................................................................................... 7-7
7.3.5
I/O Pin Truth Tables..................................................................................... 7-7
MOTOROLA
ii
MC68HC705JB2
REV 1.1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Title
Page
SECTION 8
MULTI-FUNCTION TIMER
8.1
TIMER REGISTERS ........................................................................................ 8-2
8.1.1
Timer Counter Register (TCNT) $09 ........................................................... 8-2
8.1.2
Timer Control/Status Register (TCSR) $08 ................................................. 8-3
8.2
OPERATION DURING STOP MODE .............................................................. 8-4
Freescale Semiconductor, Inc...
SECTION 9
PROGRAMMABLE TIMER
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-3
INPUT CAPTURE REGISTERS ...................................................................... 9-5
OUTPUT COMPARE REGISTERS ................................................................. 9-6
TIMER CONTROL REGISTER (TCR) ............................................................. 9-8
TIMER STATUS REGISTER (TSR)................................................................. 9-9
TIMER OPERATION DURING WAIT MODE................................................. 9-10
TIMER OPERATION DURING STOP MODE ................................................ 9-10
SECTION 10
UNIVERSAL SERIAL BUS MODULE
10.1 FEATURES .................................................................................................... 10-1
10.2 OVERVIEW.................................................................................................... 10-2
10.2.1 USB Protocol ............................................................................................. 10-3
10.2.2 Reset Signaling.......................................................................................... 10-8
10.2.3 Suspend..................................................................................................... 10-9
10.2.4 Resume After Suspend.............................................................................. 10-9
10.2.5 Low Speed Device................................................................................... 10-10
10.3 CLOCK REQUIREMENTS........................................................................... 10-11
10.4 HARDWARE DESCRIPTION....................................................................... 10-11
10.4.1 Voltage Regulator .................................................................................... 10-11
10.4.2 USB Transceiver...................................................................................... 10-12
10.4.3 Receiver Characteristics.......................................................................... 10-13
10.4.4 USB Control Logic ................................................................................... 10-15
10.5 I/O REGISTER DESCRIPTION ................................................................... 10-18
10.5.1 USB Address Register (UADDR)............................................................. 10-19
10.5.2 USB Interrupt Register 0 (UIR0) .............................................................. 10-19
10.5.3 USB Interrupt Register 1 (UIR1) .............................................................. 10-20
10.5.4 USB Control Register 0 (UCR0) .............................................................. 10-22
10.5.5 USB Control Register 1 (UCR1) .............................................................. 10-23
10.5.6 USB Control Register 2 (UCR2) .............................................................. 10-24
10.5.7 USB Status Register (USR)..................................................................... 10-25
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-26
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-26
MC68HC705JB2
REV 1.1
MOTOROLA
iii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
TABLE OF CONTENTS
Section
Title
Page
10.6 USB INTERRUPTS...................................................................................... 10-27
10.6.1 USB End of Transaction Interrupt............................................................ 10-27
10.6.2 Resume Interrupt ..................................................................................... 10-28
10.6.3 End of Packet Interrupt ............................................................................ 10-28
Freescale Semiconductor, Inc...
SECTION 11
EPROM
11.1 EPROM .......................................................................................................... 11-1
11.2 BOOTLOADER .............................................................................................. 11-1
11.2.1 Bootloader Mode ....................................................................................... 11-1
11.3 EPROM PROGRAMMING ............................................................................. 11-2
11.3.1 EPROM Program Control Register (PCR)................................................. 11-2
11.3.2 Programming Sequence ............................................................................ 11-2
11.4 MASK OPTION REGISTER (MOR), $01FF................................................... 11-4
SECTION 12
INSTRUCTION SET
12.1 ADDRESSING MODES ................................................................................. 12-1
12.1.1 Inherent...................................................................................................... 12-1
12.1.2 Immediate .................................................................................................. 12-1
12.1.3 Direct ......................................................................................................... 12-2
12.1.4 Extended.................................................................................................... 12-2
12.1.5 Indexed, No Offset..................................................................................... 12-2
12.1.6 Indexed, 8-Bit Offset .................................................................................. 12-2
12.1.7 Indexed, 16-Bit Offset ................................................................................ 12-3
12.1.8 Relative...................................................................................................... 12-3
12.1.9 Instruction Types ....................................................................................... 12-3
12.1.10 Register/Memory Instructions .................................................................... 12-4
12.1.11 Read-Modify-Write Instructions ................................................................. 12-5
12.1.12 Jump/Branch Instructions .......................................................................... 12-5
12.1.13 Bit Manipulation Instructions...................................................................... 12-7
12.1.14 Control Instructions.................................................................................... 12-7
12.1.15 Instruction Set Summary ........................................................................... 12-8
SECTION 13
ELECTRICAL SPECIFICATIONS
13.1
13.2
13.3
13.4
13.5
13.6
13.7
MAXIMUM RATINGS..................................................................................... 13-1
THERMAL CHARACTERISTICS ................................................................... 13-1
DC ELECTRICAL CHARACTERISTICS........................................................ 13-2
USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-3
USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-4
CONTROL TIMING ........................................................................................ 13-5
EPROM PROGRAMMING SPECIFICATIONS .............................................. 13-5
MOTOROLA
iv
MC68HC705JB2
REV 1.1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Title
Page
SECTION 14
MECHANICAL SPECIFICATIONS
20-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) ..................................... 14-1
20-PIN SURFACE-MOUNT SMALL OUTLINE PACKAGE (SOIC) ............... 14-2
Freescale Semiconductor, Inc...
14.1
14.2
MC68HC705JB2
REV 1.1
MOTOROLA
v
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
TABLE OF CONTENTS
Title
Page
Freescale Semiconductor, Inc...
Section
MOTOROLA
vi
MC68HC705JB2
REV 1.1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
LIST OF FIGURES
Freescale Semiconductor, Inc...
Figure
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
3-1
4-1
4-2
4-3
5-1
6-1
7-1
7-2
7-3
8-1
8-2
8-3
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Title
Page
MC68HC705JB2 Block Diagram...................................................................... 1-3
Pin Assignments for 20-Pin Package............................................................... 1-4
Oscillator Connections ..................................................................................... 1-5
MC68HC705JB2 Memory Map ........................................................................ 2-1
I/O Registers .................................................................................................... 2-2
I/O Registers $0000-$000F.............................................................................. 2-4
I/O Registers $0010-$001F.............................................................................. 2-5
I/O Registers $0020-$003F.............................................................................. 2-6
Mask Option Register $01FF ........................................................................... 2-6
MC68HC05 Programming Model ..................................................................... 3-1
Interrupt Processing Flowchart ........................................................................ 4-3
External Interrupt (IRQ) Logic .......................................................................... 4-4
IRQ Control and Status Register (ICSR)......................................................... 4-5
Reset Block Diagram ....................................................................................... 5-1
STOP/WAIT Flowchart..................................................................................... 6-2
Port A I/O Circuitry ........................................................................................... 7-2
Port B I/O Circuitry ........................................................................................... 7-4
Port B Data Direction Register ......................................................................... 7-5
Multi-Function Timer Block Diagram ................................................................ 8-1
Timer Counter Register.................................................................................... 8-2
Timer Control/Status Register (TCSR)............................................................. 8-3
Programmable Timer Block Diagram ............................................................... 9-1
Programmable Timer Counter Block Diagram ................................................. 9-2
Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3
Alternate Counter Block Diagram..................................................................... 9-4
Alternate Counter Registers (ACRH, ACRL).................................................... 9-4
Timer Input Capture Block Diagram................................................................. 9-5
Input Capture Registers (ICRH, ICRL)............................................................. 9-6
Timer Output Compare Block Diagram ............................................................ 9-7
Output Compare Registers (OCRH, OCRL) .................................................... 9-7
Timer Control Register (TCR) .......................................................................... 9-8
Timer Status Registers (TSR) .......................................................................... 9-9
USB Block Diagram ....................................................................................... 10-2
Supported Transaction Types per Endpoint................................................... 10-3
Supported USB Packet Types ....................................................................... 10-4
Sync Pattern................................................................................................... 10-4
SOP, Sync Signaling and Voltage Levels ...................................................... 10-5
CRC Block Diagram for Address and Endpoint Fields................................... 10-6
CRC Block Diagram for Data Packets ........................................................... 10-7
EOP Transaction Voltage Levels ................................................................... 10-8
EOP Width Timing.......................................................................................... 10-8
External Low Speed Device Configuration................................................... 10-10
Regulator Electrical Connections ................................................................. 10-11
MC68HC705JB2
REV 1.1
MOTOROLA
vii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
LIST OF FIGURES
Freescale Semiconductor, Inc...
Figure
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
11-1
14-1
14-2
Title
Page
Low Speed Driver Signal Waveforms .......................................................... 10-12
Differential Input Sensitivity Over Entire Common Mode Range ................. 10-13
Data Jitter..................................................................................................... 10-14
Data Signal Rise and Fall Time.................................................................... 10-14
NRZI Data Encoding .................................................................................... 10-16
Flow Diagram for NRZI ................................................................................ 10-16
Bit Stuffing.................................................................................................... 10-16
Flow Diagram for Bit Stuffing ....................................................................... 10-17
USB Address Register (UADDR) ................................................................. 10-19
USB Interrupt Register 0 (UIR0) .................................................................. 10-19
USB Interrupt Register 1(UIR1) ................................................................... 10-20
USB Control Register 0 (UCR0)................................................................... 10-22
USB Control Register 1 (UCR1)................................................................... 10-23
USB Control Register 2 (UCR2)................................................................... 10-24
USB Status Register (USR) ......................................................................... 10-25
USB Endpoint 0 Data Register (UE0D0-UE0D7)......................................... 10-26
USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)...................... 10-26
OUT Token Data Flow for Receive Endpoint 0 ............................................ 10-29
SETUP Token Data Flow for Receive Endpoint 0........................................ 10-30
IN Token Data Flow for Transmit Endpoint 0 ............................................... 10-31
IN Token Data Flow for Transmit Endpoint 1/ Endpoint 2............................ 10-32
EPROM Programming Sequence .................................................................. 11-3
20-Pin PDIP Mechanical Dimensions ............................................................ 14-1
20-Pin SOIC Mechanical Dimensions ............................................................ 14-2
MOTOROLA
viii
MC68HC705JB2
REV 1.1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
LIST OF TABLES
Freescale Semiconductor, Inc...
Table
Title
Page
4-1
Reset/Interrupt Vector Addresses .................................................................... 4-2
7-1
Port A I/O Pin Functions................................................................................... 7-7
7-2
Port B I/O Pin Functions................................................................................... 7-7
10-1 Supported Packet Identifiers .......................................................................... 10-5
10-2 Register Summary ....................................................................................... 10-18
11-1 Operation Mode Condition After Reset .......................................................... 11-1
12-1 Register/Memory Instructions ........................................................................ 12-4
12-2 Read-Modify-Write Instructions...................................................................... 12-5
12-3 Jump and Branch Instructions........................................................................ 12-6
12-4 Bit Manipulation Instructions .......................................................................... 12-7
12-5 Control Instructions ........................................................................................ 12-7
12-6 Instruction Set Summary............................................................................... 12-8
12-7 Opcode Map................................................................................................. 12-14
13-1 Maximum Ratings .......................................................................................... 13-1
13-2 Thermal Characteristics ................................................................................. 13-1
13-3 DC Electrical Characteristics.......................................................................... 13-2
13-4 USB DC Electrical Characteristics ................................................................. 13-3
13-5 USB Low Speed Source Electrical Characteristics ........................................ 13-4
13-6 Control Timing................................................................................................ 13-5
13-7 EPROM Programming Electrical Characteristics ........................................... 13-5
MC68HC705JB2
REV 1.1
MOTOROLA
ix
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
LIST OF TABLES
Title
Page
Freescale Semiconductor, Inc...
Table
MOTOROLA
x
MC68HC705JB2
REV 1.1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION
The MC68HC705JB2 is a member of the low-cost, high-performance MC68HC05
Family of 8-bit microcontroller units (MCUs). The MC68HC05 Family is based on
the Customer-Specified Integrated Circuit (CSIC) design strategy. All MCUs in the
family use the popular MC68HC05 central processing unit (CPU) and are
available with a variety of subsystems, memory sizes and types, and package
types. The MC68HC705JB2 is specifically designed to be used in applications
where a Universal Serial Bus (USB) interface is required.
1.1
FEATURES
•
Industry standard M68HC05 CPU core
•
Memory-mapped Input/Output (I/O) registers
•
2048 Bytes of user EPROM
•
128 Bytes of user RAM
•
Fully compliant Low Speed USB with 3 Endpoints:
– 1 Control Endpoint (2 x 8-byte buffer)
– 2 Interrupt Endpoints (1 x 8-byte buffer shared)
•
3.3Volt dc output pin for USB pullup resistors
•
Multi-Function Timer
•
16-Bit Input Capture/Output Compare Timer
•
11 Bidirectional I/O pins with the following features:
– 9 I/Os have software programmable pull-down capability
– 2 open-drain I/Os have software programmable pull-up, 25mA current
sink capability
– 4 I/Os with external interrupt capability
•
Low Voltage Reset (LVR) circuit
•
Power saving STOP and WAIT Modes
•
Available in 20-Pin PDIP and 20-pin SOIC packages
MC68HC705JB2
REV 1.1
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.2
August 28, 1998
MASK OPTIONS
Freescale Semiconductor, Inc...
The mask options on the MC68HC705JB2 are handled with five EPROM bits in
the Mask Option Register ($01FF). These options are:
•
External interrupt pins (IRQ, PA0 to PA3):
[edge-triggered or edge-and-level-triggered]
•
Port A and port B pull-down/pull-up resistors:
[connected or disconnected]
•
PA0-PA3 external interrupt capability:
[enabled or disabled]
•
OSC, crystal/ceramic resonator startup delay:
[4064 or 128 internal bus cycles]
•
Low Voltage Reset (LVR):
[enabled or disabled]
To program the MOR, the MORON bit in the Program Control Register
(bit 3 of $3E) must be set to “1”.
bit-7
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
IRQTRIG
PULLREN
PAINTEN
OSCDLY
LVREN
1
1
1
1
1
Read
MOR
$01FF
Write
Erased
0
0
0
Reset
Unaffected
IRQTRIG – IRQ, PA0-PA3 Interrupt Options
1 = Edge-trigger only
0 = Edge-and-level-triggered
PULLREN – Port A and B Pullup/Pulldown Options
1 = Connected
0 = Disconnected
PAINTEN – PA0-PA3 External Interrupt Options
1 = Disabled
0 = Enabled
OSCDLY – Oscillator Delay Option
1 = 128 internal clock cycles
0 = 4064 internal clock cycles
LVREN – LVR Option
1 = Enabled
0 = Disabled
MOTOROLA
1-2
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
1.3
GENERAL RELEASE SPECIFICATION
MCU STRUCTURE
Figure 1-1 shows the block diagram of the MC68HC705JB2.
PA1①
PA2①
PA4②
PORT A
PA3①
PA5②
PA7②
PB1➂
PB2➂
CPU CONTROL
ALU
LVR
VREF
POWER
SUPPLY
VSS
3.3V
68HC05 CPU
RESET
and
IRQ
ACCUM
CPU REGISTERS
RESET
IRQ
INDEX REG.
Core
TImer
DATA DIRECTION REG. B
PB0➃
PORT B
Freescale Semiconductor, Inc...
PA6②
VDD
DATA DIRECTION REG. A
PA0①
OSC
÷2
0 0 0 0 0 0 0 0 1 1 STK PNTR
PROGRAM COUNTER
OSC1
OSC2
16-bit Timer
TCAP➃
Low Speed
USB
D+
COND CODE REG. 1 1 1 H I N Z C
128 Bytes RAM
D–
2048 Bytes EPROM
①: External edge interrupt capability,
with Schmitt trigger input
②: 8 mA current sink capability
➂: 25 mA current sink, open-drained
with internal pullup, slow transition O/P
➃: TCAP is shared with PB0
Figure 1-1. MC68HC705JB2 Block Diagram
MC68HC705JB2
REV 1.1
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1-3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
August 28, 1998
RESET
1
20
VDD
PA0
2
19
OSC1
PA1
3
18
OSC2
PA2
4
17
VSS
PA3
5
16
3.3V
PA4
6
15
D+
PB0/TCAP
7
14
D–
PB1
8
13
PA7
PB2
9
12
PA6
10
11
PA5
IRQ/VPP
Figure 1-2. Pin Assignments for 20-Pin Package
1.4
FUNCTIONAL PIN DESCRIPTIONS
The following paragraphs give a description of the general function of each pin
assigned in Figure 1-2.
1.4.1 VDD, VSS
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply,
and VSS is ground. The MCU operates from a single power supply.
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, special care should be taken to provide good power supply
bypassing at the MCU by using bypass capacitors with good high-frequency
characteristics that are positioned as close to the MCU as possible. Bypassing
requirements vary, depending on how heavily the MCU pins are loaded.
1.4.2 OSC1, OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The
OSC1 and OSC2 pins can accept the following sets of components:
MOTOROLA
1-4
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
1. A crystal as shown in Figure 1-3(a)
2. A ceramic resonator as shown in Figure 1-3(a)
3. An external clock signal as shown in Figure 1-3(b)
Freescale Semiconductor, Inc...
The frequency, fOSC, of the oscillator or external clock source is divided by two to
produce the internal operating frequency, fOP. If the internal operating frequency is
3MHZ, then the external oscillator frequency will be 6MHz. For LS USB 1.5MHz
frequency clock can be derived from a divided by 4 circuit. The type of oscillator is
selected by a mask option.
1.4.2.1
Crystal Oscillator
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. The crystal manufacturer’s recommendations should be
followed, as the crystal parameters determine the external component values
required to provide maximum stability and reliable start-up. The load capacitance
values used in the oscillator circuit design should include all stray capacitances.
The crystal and components should be mounted as close as possible to the pins
for start-up stabilization and to minimize output distortion. An internal start-up
resistor of typically 2MΩ is provided between OSC1 and OSC2 for the crystal type
oscillator.
MCU
MCU
2MΩ
OSC1
OSC1
OSC2
OSC2
unconnected
37 pF
37 pF
External Clock
(a) Crystal or Ceramic Resonator
Connections
(b) External Clock
Source Connection
Figure 1-3. Oscillator Connections
1.4.2.2
Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of the
crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The
resonator manufacturer’s recommendations should be followed, as the resonator
parameters determine the external component values required for maximum
stability and reliable starting. The load capacitance values used in the oscillator
circuit design should include all stray capacitances. The ceramic resonator and
MC68HC705JB2
REV 1.1
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
components should be mounted as close as possible to the pins for start-up
stabilization and to minimize output distortion. An internal start-up resistor of 2MΩ
(typical) is provided between OSC1 and OSC2 for the ceramic resonator type
oscillator.
1.4.2.3
External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b).
Freescale Semiconductor, Inc...
1.4.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a known
start-up state by pulling it to the low state. The RESET pin contains a steering
diode to discharge any voltage on the pin to VDD, when the power is removed. An
internal pull-up is also connected between this pin and VDD. The RESET pin
contains an internal Schmitt trigger to improve its noise immunity as an input. This
pin is an output pin if LVR triggers an internal reset.
1.4.4 IRQ/VPP
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ
interrupt function has a mask option to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
option is selected to include level-sensitive triggering, the IRQ input requires an
external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains
an internal Schmitt trigger as part of its input to improve noise immunity.
NOTE
Each of the PA0 thru PA3 I/O pins may be connected as an OR
function with the IRQ interrupt function by a mask option. This
capability allows keyboard scan applications where the transitions or
levels on the I/O pins will behave the same as the IRQ pin, except
for the inverted phase. The edge or level sensitivity selected by a
separate mask option for the IRQ pin also applies to the I/O pins
OR’ed to create the IRQ signal.
In Bootloader mode, this pin (VPP) is used to supply the required programming
voltage to the EPROM array.
MOTOROLA
1-6
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
1.4.5 PA0-PA7
These eight I/O lines comprise PortA. PA0 to PA7 are push-pull pins with pulldown
devices. PA4 to PA7 are also capable of sinking 8 mA.
The state of any pin is software programmable and all Port A lines are configured
as inputs during power-on or reset. The lower four I/O pins (PA0 thru PA3) can be
connected via an internal OR gate to the IRQ interrupt function enabled by a mask
option. See Section 7 on Input/Output Ports for further details.
Freescale Semiconductor, Inc...
1.4.6 PB0-PB2
These three I/O lines comprise Port B. PB1 and PB2 are open-drain I/O lines with
pullup devices, whereas PB0 (shared with TCAP), is a push-pull I/O line with
pulldown device.
The state of any pin is software programmable and is configured as an input
during power-on or reset. PB1 and PB2 are also slow transition outputs, each
capable of sinking 25mA typical current at 0.5V VOL Max. See Section 7 on
Input/Output Ports for further details.
1.4.7 D+, D–
D+ and D– are the differential data lines used by the USB module. See
Section 10 on Universal Serial Bus Module.
1.4.8 3.3V
This is the 3.3V output of the on-chip voltage regulator from the MCU. It is used to
supply the voltage for the external pullup resistor required by the USB on D–. This
regulator output is also used internally for the USB data driver circuitry. This 3.3V
pin should be decoupled using a 1µF (or greater) capacitor and a 0.1µF bypass
capacitor.
MC68HC705JB2
REV 1.1
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1-7
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
1-8
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 2
MEMORY
2.1
MEMORY MAP
Freescale Semiconductor, Inc...
The MC68HC705JB2 has an 8-Kbyte memory map consisting of user EPROM,
RAM, burn-in ROM, and input/output (I/O), as shown in Figure 2-1.
$0000
$003F
$0040
0000
I/O
64 Bytes
unimplemented
64 Bytes
$00FF
$01FF
0063
0064
User RAM
128 Bytes
Stack
EPROM Program Control
Reserved
$003E
Reserved
$1FF0
Reserved
$1FF1
Reserved
$1FF2
$003F
0255
unimplemented
MOR Register
unimplemented
5276 Bytes
1535
5632
$05FF
$1600
User EPROM
2048 Bytes
$1DFF
$1E00
7679
7680
Bootstrap ROM
496 Bytes
$1FEF
8175
User Vectors
16 Bytes
$1FFF
$0000
Total 64 bytes
(see Figure 2-2)
0127
0128
$007F
$0080
$00C0
I/O
Registers
8191
Reserved
$1FF3
MFT Vector (High Byte)
$1FF4
MFT Vector (Low Byte)
$1FF5
Timer1 Vector (High Byte)
$1FF6
Timer1 Vector (Low Byte)
$1FF7
USB Vector (High Byte)
$1FF8
USB Vector (Low Byte)
$1FF9
IRQ Vector (High Byte)
$1FFA
IRQ Vector (Low Byte)
$1FFB
SWI Vector (High Byte)
$1FFC
SWI Vector (Low Byte)
$1FFD
Reset Vector (High Byte)
$1FFE
Reset Vector (Low Byte)
$1FFF
Figure 2-1. MC68HC705JB2 Memory Map
MC68HC705JB2
REV 1.1
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
2.2
August 28, 1998
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside at locations $0000-$003F. The outline of
these registers are shown in Figure 2-2. The bit assignments for each register are
shown in Figure 2-3, Figure 2-4, and Figure 2-5. Reading from unimplemented
bits will return unknown states, and writing to unimplemented bits will be ignored.
Port A Data Register
$0000
Port B Data Register
$0001
Freescale Semiconductor, Inc...
unimplemented (2)
Port A Data Direction Register
$0004
Port B Data Direction Register
$0005
unimplemented (2)
Timer Control & Status Register
$0008
Timer Counter Register
$0009
IRQ Control & Status Register
$000A
unimplemented (5)
Port A Pulldown Register
$0010
Port B Pulldown/up Register
$0011
Timer1 Registers (10)
$0012 to
$001B
unimplemented (4)
USB Endpoint0 Data Registers (8)
USB Endpoint1 Data Registers (8)
$0020 to
$0027
$0028 to
$002F
USB Control2 Register
$0037
USB Address Register
$0038
USB Interrupt0 Register
$0039
USB Interrupt1 Register
$003A
USB Control0 Register
$003B
USB Control1 Register
$003C
USB Status Register
$003D
EPROM Program Control Register
$003E
Reserved
$003F
Mask Option Register
$01FF
Figure 2-2. I/O Registers
MOTOROLA
2-2
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
2.3
GENERAL RELEASE SPECIFICATION
RAM
The user RAM consists of 128 bytes (including the stack) located from $0080 to
$00FF. The stack begins at address $00FF and proceeds down to $00C0. Using
the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
2.4
EPROM
The on-chip user EPROM consists of 2048 bytes of EPROM from $1600 to
$1DFF and 16 bytes of user vectors from $1FF0 to $1FFF.
Freescale Semiconductor, Inc...
The bootloader ROM and vectors are located from $1E00 to $1FEF.
12 of the user vectors, $1FF4-$1FFF, are dedicated to reset and interrupt vectors.
The four remaining locations, $1FF0-$1FF3, are reserved for test functions. The
Mask Option Register is located at $01FF.
2.5
BOOTLOADER ROM
Addresses $1E00 to $1FEF are reserved ROM addresses that contain the
instructions for the bootloader functions. (See Section 11.)
MC68HC705JB2
REV 1.1
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
DDRA2
DDRA1
DDRA0
DDRB2
DDRB1
DDRB0
RT1
RT0
$0000
$0001
R/W
PORT A DATA
R
(PORTA)
W
PORT B DATA
R
(PORTB)
W
$0002
UNIMPLEMENTED
$0003
UNIMPLEMENTED
$0004
Freescale Semiconductor, Inc...
REGISTER
$0005
W
(DDRA)
W
PORT B DATA DIR
R
(DDRB)
W
$0007
UNIMPLEMENTED
$0008
MFT CONTROL &
STATUS (TCSR)
$000B
R
R
UNIMPLEMENTED
$000A
W
PORT A DATA DIR
$0006
$0009
R
R
R
$000F
UNIMPLEMENTED
SLOWE
TOF
RTIF
W
TMR7
IRQE
0
0
TOFR
RTIFR
TMR4
TMR3
TMR2
TMR1
TMR0
0
IRQF
0
0
0
TOFE
RTIE
TMR6
TMR5
0
0
W
IRQ CONTROL &
STATUS (ICSR)
UNIMPLEMENTED
DDRA3
W
R
$000E
DDRA4
R
W
$000D UNIMPLEMENTED
DDRA5
W
TCNT
$000C UNIMPLEMENTED
DDRA6
R
MFT COUNTER
UNIMPLEMENTED
DDRA7
IRQR
R
W
R
W
R
W
R
W
R
W
Figure 2-3. I/O Registers $0000-$000F
MOTOROLA
2-4
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
ADDR
$0010
$0011
$0012
$0013
Freescale Semiconductor, Inc...
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
REGISTER
R/W
PORT A PULLDOWN/UP
R
(PDURA)
W
PORT B PULLDOWN/UP
R
(PDURB)
W
TIMER CONTROL
R
(TCR)
W
TIMER STATUS
R
(TSR)
W
INPUT CAPTURE HIGH
R
(ICH)
W
INPUT CAPTURE LOW
R
(ICL)
W
OUTPUT COMPARE HIGH
R
(OCH)
W
OUTPUT COMPARE LOW
R
(OCL)
W
TIMER HIGH
R
(TCNTH)
W
TIMER LOW
R
(TCNTL)
W
ALT COUNTER HIGH
R
(ACNTH)
W
ALT COUNTER LOW
R
(ACNTL)
W
$001C UNIMPLEMENTED
$001D UNIMPLEMENTED
$001E
UNIMPLEMENTED
$001F
UNIMPLEMENTED
GENERAL RELEASE SPECIFICATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDRA7
PDRA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
PURB2
PURB1
PURB0
ICIE
OCIE
TOIE
0
0
0
ICF
OCF
TOF
0
0
0
0
0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
IEDG
0
R
W
R
W
R
W
R
W
Figure 2-4. I/O Registers $0010-$001F
MC68HC705JB2
REV 1.1
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
ADDR
REGISTER
R/W
BIT 6
$0020
to
$0027
USB ENDPOINT0
DATA REG. 0 TO 7
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
(UD0R0-7)
W
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0028
to
$002F
USB ENDPOINT1
DATA REG. 0 TO 7
R
(UD1R0-7)
W
$0030
to
$0036
Freescale Semiconductor, Inc...
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
BIT 7
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
R
UNIMPLEMENTED
W
USB CONTROL2
R
0
(UCR2)
W
TX1STR
USB ADDRESS
R
(UADR)
W
USB INTERRUPT0
R
USBEN UADD6
TXD0F
(UIR0)
W
0
USB INTERRUPT1
R
TXD1F
0
(UIR1)
W
USB CONTROL 0
R
(UCR0)
W
USB CONTROL1
R
(UCR1)
W
USB STATUS
R
(USR)
W
PROG. CONTROL
R
(PCR)
W
RESERVED
TX1ST
0
UADD5
UADD4
RXD0F
RSTF
0
0
EOPF RESUMF
UADD3
UADD2
SUSPND TXD0IE RXD0IE
0
0
RESUMFR
T0SEQ STALL0
TX0E
RX0E
T1SEQ ENDADD
TX1E
RSEQ
0
ENABLE2 ENABLE1 STALL2 STALL1
TXD1IE
EOPIE
UADD1
UADD0
0
0
TXD0FR RXD0FR
0
0
TXD1FR EOPFR
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
SETUP
RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
MORON
ELAT
PGM
BIT 2
BIT 1
BIT 0
OSCDLY
LVREN
R
W
Figure 2-5. I/O Registers $0020-$003F
ADDR
$01FF
REGISTER
R/W
MASK OPTION
R
(MOR)
W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
IRQTRIG PULLREN PAINTEN
Figure 2-6. Mask Option Register $01FF
MOTOROLA
2-6
MEMORY
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 3
CENTRAL PROCESSING UNIT
Freescale Semiconductor, Inc...
The MC68HC705JB2 has a 8Kbyte memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1
REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memory map. These five registers are shown in Figure 3-1 and are
described in the following paragraphs.
7
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
1
6
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
PC
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1. MC68HC05 Programming Model
MC68HC705JB2
REV 1.1
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
3-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
3.2
August 28, 1998
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
or non-arithmetic operations. The accumulator is not affected by a reset of the
device.
3.3
INDEX REGISTER (X)
Freescale Semiconductor, Inc...
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU finds the operand address by adding the
index register content to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register
content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary
storage. The index register is not affected by a reset of the device.
3.4
STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with
memory space less than 64 Kbytes the unimplemented upper address lines are
ignored. The stack pointer contains the address of the next free location on the
stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to $00FF. The stack pointer is then decremented as data is pushed onto the
stack and incremented as data is pulled off the stack.
When accessing memory, the ten most significant bits are permanently set to
0000000011. The six least significant register bits are appended to these ten fixed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the
stack pointer wraps around and overwrites the previously stored information. A
subroutine call occupies two locations on the stack and an interrupt uses five
locations.
MOTOROLA
3-2
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
3.5
GENERAL RELEASE SPECIFICATION
PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices
with memory space less than 64 Kbytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
Freescale Semiconductor, Inc...
Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
3.6
CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fifth bit is the interrupt
mask. These bits can be individually tested by a program, and specific actions can
be taken as a result of their states. The condition code register should be thought
of as having three additional upper bits that are always ones. Only the interrupt
mask is affected by a reset of the device. The following paragraphs explain the
functions of the lower five bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
MC68HC705JB2
REV 1.1
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
3-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the flag.
Freescale Semiconductor, Inc...
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
MOTOROLA
3-4
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
Freescale Semiconductor, Inc...
The MCU can be interrupted in six different ways:
4.1
•
Non-maskable Software Interrupt Instruction (SWI)
•
External Interrupt (IRQ)
•
Optional External Interrupt via IRQ on PA0-PA3 (mask option)
•
USB Interrupt
•
Timer1 Interrupt (16-bit Timer)
•
Multi-Function Timer Interrupt
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding
interrupt enable bit is set the processor will proceed with interrupt processing.
Otherwise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and finally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table 4-1 will be
serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the
appropriate interrupt software service routine from the vector table at locations
$1FF4 to $1FFF as defined in Table 4-1.
MC68HC705JB2
REV 1.1
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Freescale Semiconductor, Inc...
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Control
Bit
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-On Logic
RESET Pin
Low Voltage Reset
Illegal Address Reset
USB Reset
—
—
—
1
$1FFE–$1FFF
Software
Interrupt (SWI)
User Code
—
—
—
Same Priority
As Instruction
$1FFC–$1FFD
External
Interrupt (IRQ)
IRQ Pin
—
I Bit
IRQE Bit
2
$1FFA–$1FFB
USB
Interrupts
TXD0F
TXD1F
RESUMF
—
I Bit
TXD0IE
TXD1IE
—
3
$1FF8–$1FF9
Timer1
Interrupts
ICF Bit
OCF Bit
TOF Bit
—
I Bit
ICIE Bit
OCIE Bit
TOIE Bit
4
$1FF6–$1FF7
MFT
Interrupts
TOF Bit
RTIF
—
I Bit
TOFE Bit
RTIE Bit
5
$1FF4–$1FF5
Reserved
$1FF2–$1FF3
Reserved
$1FF0–$1FF1
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from
the stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
4.2
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-1. A low level input on the RESET
pin or an internally generated RST signal causes the program to vector to its
starting address which is specified by the contents of memory locations $1FFE
and $1FFF. The I-bit in the condition code register is also set.
MOTOROLA
4-2
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
FROM
RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
Freescale Semiconductor, Inc...
NO
USB
INTERRUPT?
YES
NO
TIMER1
INTERRUPT?
YES
NO
MFT
INTERRUPT?
YES
NO
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL.
NO
EXECUTE INSTRUCTION.
Figure 4-1. Interrupt Processing Flowchart
MC68HC705JB2
REV 1.1
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
4.3
August 28, 1998
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is
executed regardless of the state of the I-bit in the CCR. As with any instruction,
interrupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware
interrupts which are explained in the following sections.
4.4.1 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in Figure 4-2.
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
VDD
PA0
PA1
IRQ
LATCH
PA2
R
EXTERNAL
INTERRUPT
REQUEST
PA3
IRQ Level
(Mask Option)
Port A External Interrupt
(Mask Option)
IRQR
IRQF
RST
IRQ VECTOR FETCH
IRQE
Freescale Semiconductor, Inc...
4.4
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-2. External Interrupt (IRQ) Logic
MOTOROLA
4-4
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.
Freescale Semiconductor, Inc...
Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes
from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on
any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled. If "edge-only"
sensitivity is chosen by a mask option, only the IRQ latch output can activate an
IRQF flag which creates a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
•
Falling edge on the IRQ pin.
•
Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the active high state the signal to the clock input of
the IRQ latch can also activate an IRQF flag which creates an IRQ request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt
sensitive to the following cases:
•
Low level on the IRQ pin.
•
Falling edge on the IRQ pin.
•
High level on any PA0- PA3 pin with IRQ enabled (via mask option).
•
Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).
The IRQE enable bit controls whether an active IRQF flag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specified by the contents of $1FFA and $1FFB.
The IRQ latch is automatically cleared by entering the interrupt service routine IF
IRQE enable bit is cleared. If IRQE enable bit is also set, the only way of clearing
IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one to
the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF flag. As
long as the output state of the IRQF flag bit is active the CPU will continuously reenter the IRQ interrupt sequence until the active state is removed or the IRQE
enable bit is cleared.
4.4.2 IRQ Control/status Register (ICSR) $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
BIT 7
ICSR
R
$000A
reset:
W
IRQE
1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
IRQF
0
0
0
0
0
0
0
0
IRQR
0
0
Figure 4-3. IRQ Control and Status Register (ICSR)
MC68HC705JB2
REV 1.1
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Freescale Semiconductor, Inc...
IRQR - IRQ Interrupt Acknowledge
The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.
The IRQR acknowledge bit will always read as a logic zero.
1 = Writing a logic one to the IRQR acknowledge bit will clear the IRQ
latch.
0 = Writing a logic zero to the IRQR acknowledge bit will have no effect
on the IRQ latch.
IRQF - IRQ Interrupt Request Flag
Writing to the IRQF flag bit will have no effect on it. If the additional setting of
IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
1 = Indicates that an IRQ request is pending.
0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF flag bit is cleared once the IRQ vector is fetched.
The IRQF flag bit can be cleared by writing a logic one to the IRQR
acknowledge bit to clear the IRQ latch and also conditioning the
external IRQ sources to be inactive (if the level sensitive interrupts
are enabled via mask option). Doing so before exiting the service
routine will mask out additional occurrences of the IRQF.
IRQE - IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt
sequence.
1 = Enables IRQF interrupt, that is, the IRQF flag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 = The IRQF flag bit cannot generate an interrupt sequence.
4.4.3 Optional External Interrupts (PA0-PA3)
The IRQ interrupt can also be triggered by the inputs on the PA0 thru PA3 port
pins if enabled by a single mask option. If enabled, the lower four bits of Port A
can activate the IRQ interrupt function, and the interrupt operation will be the
same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of
these input pins to be OR’ed with the input present on the IRQ pin. All PA0 thru
PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3
interrupt sources are also controlled by the IRQE enable bit.
MOTOROLA
4-6
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ
pin itself, and not to the output of the logic OR function with the PA0
thru PA3 pins. The state of the individual Port A pins can be checked
by reading the appropriate Port A pins as inputs.
Freescale Semiconductor, Inc...
NOTE
If enabled, the PA0 to PA3 pins will cause an IRQ interrupt
regardless of whether these pins are configured as inputs or
outputs.
4.4.4 Timer1 Interrupt (TIMER1)
The TIMER interrupt is generated by the timer when either a timer1 overflow or a
input capture or output compare has occurred as described in Section 9. The
interrupt flags and enable bits for the Timer1 interrupts are located in the Timer1
Control & Status Register (TSR) located at $0012, $0013. The I-bit in the CCR
must be clear in order for the TIMER1 interrupt to be enabled. Either of these
three interrupts will vector to the same interrupt service routine located at the
address specified by the contents of memory locations $1FF6 and $1FF7.
4.4.5 USB Interrupt (USB)
The USB interrupt is generated by the USB module as described in Section 10.
The interrupt enable bits for the USB interrupt are located at bit3-bit2 of UIR0
REG and bit3-bit2 of UIR1 REG. Also Once the device goes into Suspend Mode,
any bus activities will cause the USB to generate an interrupt to CPU to come out
from the Suspend mode. The I-bit in the CCR must be clear in order for the USB
interrupt to be enabled. Either of these two interrupts will vector to the same
interrupt service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
4.4.6 MFT Interrupt (MFT)
The MFT interrupt is generated by the MFT module as described in Section 8.
These interrupts will vector to the same interrupt service routine located at the
address specified by the contents of memory locations $1FF4 and $1FF5.
MC68HC705JB2
REV 1.1
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4-7
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
4-8
INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
Freescale Semiconductor, Inc...
The MCU can be reset in five ways:
•
by an active low input to the RESET pin,
•
by initial power-on reset,
•
by an USB reset,
•
by an illegal address access, and
•
by a low voltage reset function.
The RESET pin is an I/O pin as shown in Figure 5-1. The internal steering diode
for discharge and pull-up device are not shown here. All the peripheral modules
which drive external pins will be reset by the synchronous reset signal (RST)
coming from a latch, which is synchronized to the internal bus clock and set by
any of the five reset sources.
USB RESET DETECTION
LOW VOLTAGE RESET
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
RST
D
RESET
LATCH
RESET
TO CPU
AND
SUBSYSTEMS
R
INTERNAL
CLOCK
Figure 5-1. Reset Block Diagram
MC68HC705JB2
REV 1.1
RESETS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
5.1
August 28, 1998
EXTERNAL RESET (RESET)
Freescale Semiconductor, Inc...
The RESET pin is the only external source of a reset. This pin is connected to a
Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. This external reset occurs
whenever the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low input will
generate the RST signal and reset the CPU and peripherals. This pin is also an
output pin whenever the LVR triggers an internal reset. Termination of the external
RESET input or the USB reset or LVR are the only reset sources that can alter the
operating mode of the MCU.
NOTE
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
5.2
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
USB reset flag reset, the illegal address detector reset and the low voltage reset
(LVR). Termination of the external RESET input or LVR or USB reset or ILADR are
the reset sources that can alter the operating mode of the MCU. The other internal
resets will not have any effect on the mode of operation when their reset state
ends.
5.2.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to
stabilize. The POR is strictly for power turn-on conditions and is not able to detect
a drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 128 or 4064 internal processor bus clock cycles (PH2) for Ceramic
Resonator or Crystal after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this 128 or 4064 cycle delay, the RST signal will
remain in the reset condition until the other reset condition(s) end.
5.2.2 USB Reset
The USB reset is generated by a detection on the USB bus reset signal. For
MC68HC705JB2, seeing a single-end zero on its upstream port for 4 to 8 bit times
will set RSTF bit in UIR0 register. The detections will also generate the RST signal
to reset the CPU and other peripherals in the MCU.
MOTOROLA
5-2
RESETS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
5.2.3 Illegal Address Reset (ILADR)
The internal ILADR reset is generated when an instruction opcode fetch occurs
from an address which is not implemented in the RAM ($0080 - $00FF) nor ROM
($1600-$1FFF). The ILADR will generate the RST signal which will reset the CPU
and other peripherals. If any other reset function is active at the end of the ILADR
reset signal, the RST signal will remain in the reset condition until the other reset
condition(s) end. Notice that ILADR also forces the RESET pin low
Freescale Semiconductor, Inc...
5.2.4 Low Voltage Reset (LVR)
The internal LVR reset is generated when VDD falls below the specified LVR
trigger value VLVR for at least one tCYC. In typical applications, the power supply
decoupling circuit will eliminate negative-going voltage glitches of less than one
tCYC. This reset will hold the MCU in the reset state until VDD rises above VLVR.
Whenever VDD is above VLVR and below 4.2V, the MCU is guaranteed to operate
although not within specification. The output from the LVR is connected directly to
the internal reset circuitry and also forces the RESET pin low. The internal reset
will be removed once the power supply voltage rises above VLVR, at which time a
normal power-on-reset sequence occurs. LVR function will still be active during
Stop or Suspend mode.
MC68HC705JB2
REV 1.1
RESETS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-3
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
5-4
RESETS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 6
LOW POWER MODES
Freescale Semiconductor, Inc...
The MC68HC705JB2 has two low-power operating modes: STOP mode and
WAIT mode.
The STOP and WAIT instructions provide two modes that reduce the power
required for the MCU by stopping various internal clocks and/or the oscillator. The
flow of the STOP, and WAIT modes are shown in Figure 6-1.
6.1
STOP MODE
Execution of the STOP instruction in this mode places the MCU in its lowest
power consumption mode. In the STOP Mode the internal oscillator is turned off,
halting all internal processing.
Execution of the STOP instruction automatically clears the I-bit in the Condition
Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so
that the IRQ external interrupt is enabled. All other registers, including the other
bits in the TCSR, and memory remain unaltered. All input/output lines remain
unchanged.
The MCU can be brought out of the STOP Mode by an IRQ external interrupt or a
USB coming out from Suspend Mode Interrupt (Bus activity detection) or an
externally generated RESET, USB Reset or an LVR reset. When exiting the STOP
Mode the internal oscillator will resume after a 128 or 4064 internal processor
clock cycle oscillator stabilization delay.
6.2
WAIT MODE
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Execution of the
WAIT instruction automatically clears the I-bit in the Condition Code Register and
sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ
external interrupt is enabled. All other registers, memory, and input/output lines
remain in their previous states.
The WAIT Mode may be exited when an external IRQ or a USB or Timer1 or MFT
interrupt, an LVR reset or an external RESET occurs.
MC68HC705JB2
REV 1.1
LOW POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
WAIT
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET START-UP DELAY
EXTERNAL OSCILLATOR ACTIVE,
INTERNAL TIMER CLOCK ACTIVE
STOP INTERNAL PROCESSOR CLOCK,
CLEAR I-BIT IN CCR,
SET IRQE IN ICSR
STOP INTERNAL PROCESSOR CLOCK,
CLEAR I-BIT IN CCR,
SET IRQE IN ICSR
Freescale Semiconductor, Inc...
STOP
EXTERNAL
RESET?
YES
YES
NO
NO
IRQ
EXTERNAL
INTERRUPT?
YES
YES
IRQ
EXTERNAL
INTERRUPT?
NO
NO
YES
USB
INTERRUPT
OR RESET?
EXTERNAL
RESET?
YES
USB
RESET OR
INTERRUPT?
NO
NO
YES
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
NO
YES
END OF
STABILIZATION
DELAY?
TIMER1
INTERNAL
INTERRUPT?
YES
MFT
INTERNAL
INTERRUPT?
NO
NO
RESTART INTERNAL PROCESSOR CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-1. STOP/WAIT Flowchart
MOTOROLA
6-2
LOW POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
6.3
GENERAL RELEASE SPECIFICATION
DATA-RETENTION MODE
The contents of RAM and CPU registers are retained at supply voltages as low as
2.0Vdc. This is called the data-retention mode where the data is held, but the
device is not guaranteed to operate. The RESET pin must be held low during
data-retention mode.
NOTE
Freescale Semiconductor, Inc...
The voltage threshold of the LVR is higher than the Data-Retention
Mode minimum voltage, therefore the Data-Retention mode will not
be available if the LVR function is enabled in the mask option.
MC68HC705JB2
REV 1.1
LOW POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-3
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
6-4
LOW POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Freescale Semiconductor, Inc...
SECTION 7
INPUT/OUTPUT PORTS
In the Normal Operating Mode, there are 11 bidirectional I/O lines arranged as
one 8-bit I/O port (Port A), and one 3-bit I/O port (Port B). Each port line can be
programed as either input or output, under software control, by the data direction
registers (DDR’s). Also, if enabled by a mask option, all Port A and Port B I/O pins
may have individual software programmable pulldown or pullup devices. PA4 to
PA7 and PB1 & PB2 pins have the additional properties of sinking higher current.
PA0 to PA3 may function as additional IRQ interrupt input sources (mask option).
PB1 and PB2 have open drain output drivers, with optional slow falling-edge
output transitions. The transition delay is 170ns (typical), with a bus rate of 3MHz
and a loading of 50pF.
MC68HC705JB2
REV 1.1
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
7-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.1
August 28, 1998
PORT A
Port A is an 8-bit bidirectional port which shares four of its pins with the IRQ
interrupt system as shown in Figure 7-1. Each Port A pin is controlled by the
corresponding bits in a data direction register, a data register, and a pulldown
register. The Port A Data Register is located at address $0000. The Port A Data
Direction Register (DDRA) is located at address $0004. The Port A Pulldown
Register (PDURA) is located at address $0010. Reset clears the DDRA and the
PDURA. The Port A Data Register is unaffected by reset.
Read $0004
Freescale Semiconductor, Inc...
Write $0004
Data Direction
Register Bit
Write $0000
Data
Register Bit
Output
8 mA Sink
Capability
(Bits 4-7 Only)
Read $0000
Write $0010
Pulldown
Register Bit
Internal HC05
Data Bus
I/O Pin
Reset
(RST)
100 µA
Pulldown
Mask Option
(Software Pulldown Inhibit)
Note: each I/O port pin can have pulldown device
PA0-PA3 only: to IRQ
interrupt system
Figure 7-1. Port A I/O Circuitry
7.1.1 Port A Data Register
Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a
Port A pin is programmed as an output the state of the corresponding data
register bit determines the state of the output pin. When a Port A pin is
programmed as an input, any read of the Port A Data Register will return the logic
state of the corresponding I/O pin. The Port A data register is unaffected by reset.
7.1.2 Port A Data Direction Register
Each Port A I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRA, or programmed as an output by setting the
corresponding bit in the DDRA. The DDRA can be accessed at address $0004.
The DDRA is cleared by reset.
MOTOROLA
7-2
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
7.1.3 Port A Pulldown Register
All Port A I/O pins may have software programmable pulldown devices enabled by
a mask option. If the pulldown/up mask option is selected, the pulldown is
activated whenever the corresponding bit in the PDURA is clear. If the
corresponding bit in the PDURA bit is set or the mask option for pulldown is not
chosen, the pulldown will be disabled. A pulldown on an I/O pin is activated only if
the I/O pin is programmed as an input.
Freescale Semiconductor, Inc...
The PDURA is a write-only register. Any reads of location $0010 will return
undefined results. Since reset clears both the DDRA and the PDURA, all pins will
initialize as inputs with the pulldown active (if enabled by mask option).
7.1.4 Port A Drive Capability
The outputs of the PA4, PA5, PA6 and PA7 are capable of sinking 8 mA (typical) of
current to VSS.
7.1.5 Port A I/O Pin Interrupts
The inputs to PA0, PA1, PA2, PA3 may be connected to the IRQ input of the CPU
if enabled by a mask option. PA0 to PA4 also has a Schmitt trigger circuit
implemented as part of its input circuitry.
When connected as an alternate source of an IRQ interrupt, PA0-3 input pins will
behave the same as the IRQ pin itself, except that their active state is a logical one
or a rising edge. The IRQ pin has an active state that is a logical zero or a falling
edge.
If the mask option for edge-and-level trigger sensitivity interrupts are chosen, the
presence of a logic one or occurrence of a rising edge on any one of the lower four
Port A pins will cause an IRQ interrupt request. If the edge-only sensitivity is
selected, the occurrence of a rising edge on any one of the lower four Port A pins
will cause an IRQ interrupt request. As long as any one of the lower four Port A
IRQ inputs remains at a logic one level, the other of the lower four Port A IRQ
inputs are effectively ignored.
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ
pin itself, and not to the internal IRQ input to the CPU. Therefore BIH
and BIL cannot be used to test the state of the lower four Port A
input pins as a group.
MC68HC705JB2
REV 1.1
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
7-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.2
August 28, 1998
PORT B
Port B is a 3-bit bidirectional port which functions as shown in Figure 7-2. Each
Port B pin is controlled by the corresponding bits in a data direction register, a
data register, and a pulldown/up register. The Port B Data Register is located at
address $0001. The Port B Data Direction Register (DDRB) is located at address
$0005. The Port B Pulldown/up Register (PDURB) is located at address $0011.
Reset clears the DDRB and the PDURB. The Port B Data Register is unaffected
by reset.
Freescale Semiconductor, Inc...
PB0 is a standard push-pull I/O pin with pulldown option; and is shared with TCAP.
PB1 and PB2 are of open-drain type, with pullup option, each capable of sinking
25mA (typical) current at VOL 0.5V max. These two pins may be connected
together to constitute a single pin capable of sinking 50mA (typical). In this case,
both PB1 and PB2 data bits will have to be written with the same value at the
same write cycle.
VDD
Read $0005
100K
Pullup
Write $0005
Data Direction
Register Bit
Write $0001
Data
Register Bit
Output
I/O Pin
Read $0001
Write $0011
Pulldown/up
Register Bit
Internal HC05
Data Bus
Reset
(RST)
100 µA
Pulldown
Mask Option
(Software Pulldown/up Inhibit)
Note: Each I/O port pin can have either pullup or pulldown device, but not both.
PB1 and PB2 output drivers are of open-drain type
Figure 7-2. Port B I/O Circuitry
7.2.1 Port B Data Register
All Port B I/O pins have a corresponding bit in the Port B Data Register. When a
Port B pin is programmed as an output the state of the corresponding data
register bit determines the state of the output pin. When a Port B pin is
programmed as an input, any read of the Port B Data Register will return the logic
state of the corresponding I/O pin. The Port B data register is unaffected by reset.
Unused bits will always read as logic zeros, and any write to these bits will be
ignored. The Port B data register is unaffected by reset.
MOTOROLA
7-4
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
7.2.2 Port B Data Direction Register
Port B I/O pins may be programmed as an input by clearing the corresponding bit
in the DDRB, or programmed as an output by setting the corresponding bit in the
DDRB. The DDRB can be accessed at address $0005. Unused bits will always
read as logic zeros, and any write to these bits will be ignored. The DDRB is
cleared by reset.
Freescale Semiconductor, Inc...
If configured as output pins, PB1 and PB2 have slow output falling-edge transition
feature. The slow transition feature is controlled by the SLOWE bit of DDRB.
SLOWE bit, if set and if the pin is configured as an output pin, enables the slow
falling-edge output transition feature of PB1 and PB2.
7.2.3 Slow Output Falling-Edge Transition
BIT 7
DDRB
R
$0005
W
reset:
BIT 6
BIT 5
BIT 4
BIT 3
SLOWE
0
0
0
0
BIT 2
BIT 1
BIT 0
DDRB2
DDRB1
DDRB0
0
0
0
0
Figure 7-3. Port B Data Direction Register
SLOWE - Slow Transition Enable
The slow transition feature is controlled by the SLOWE bit of DDRB (Port B
Data Direction Register). Default value of SLOWE bit is clear on reset.
1 = Enables the slow falling-edge output transition feature on both PB1
and PB2, if the pin is configured as an output pin. PB2 falling edge
transition is a sharp falling edge transition delayed by tCYC/2 after
the write cycle to PB2 data register. PB1 is a true slow transition I/O
line.
0 = Disables slow falling-edge output transition feature on both PB1 and
PB2.
7.2.4 Port B Pulldown/Pullup Register
All Port B I/O pins may have software programmable pulldown/pullup devices
enabled by a mask option. If the pulldown/pullup mask option is selected, the
pulldown/pullup is activated whenever the corresponding bit in the PDURB is
clear. A pulldown on an I/O pin is activated only if the I/O pin is programmed as an
input; whereas a pullup device on an I/O pin is always activated whenever
enabled, regardless of port direction.
The PDURB is a write-only register. Any reads of location $0011 will return
undefined results. Since reset clears both the DDRB and the PDURB, all pins will
initialize as inputs with the pulldown devices active and pullup devices active (if
chosen via mask option).
Typical value of PB1 and PB2 pullup is 100KΩ (typical).
MC68HC705JB2
REV 1.1
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
7-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.3
August 28, 1998
I/O PORT PROGRAMMING
All I/O pins can be programmed as inputs or outputs, with or without pulldown/
pullup devices.
7.3.1 Pin Data Direction
Freescale Semiconductor, Inc...
The direction of a pin is determined by the state of its corresponding bit in the
associated port Data Direction Register (DDR). A pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its
corresponding DDR bit is cleared to a logic zero.
The data direction bits DDRB0 thru DDRB2 and DDRA0 thru DDRA7 are read/
write bits which can be manipulated with read-modify-write instructions. At poweron or reset, all DDR’s are cleared which configures all port pins as inputs. If the
pulldown/up mask option is chosen, all pins will initially power-up with their
software programmable Pulldown/ups enabled.
7.3.2 Output Pin
When an I/O pin is programmed as an output pin, the state of the corresponding
data register bit will determine the state of the pin. The state of the data register
bits can be altered by writing to address $0000 for Port A and address $0001 for
Port B. Reads of the corresponding data register bit at address $0000 or $0001
will return the state of the data register bit (not the state of the I/O pin itself).
Therefore bit manipulation is possible on all pins programmed as outputs.
If the corresponding bit in the pulldown/up register is clear (and the pulldown/up
mask option is chosen), only output pins with pullups have an activated pullup
device connected to the pin. For those pins with pulldowns and configured as
output pins, the pulldowns will be inactivated regardless of the state of the
corresponding pulldown/up register bit. Since the pulldown/up register bits are
write-only, bit manipulation should not be used on these register bits.
7.3.3 Input Pin
When an I/O pin is programmed as an input pin, the state of the pin can be
determined by reading the corresponding data register bit. Any writes to the
corresponding data register bit for an input pin will be ignored in the sense that the
written value will not be reflected on the pin, rather it is only reflected in the port
data register. Please refer to Table 7-1 and Table 7-2 for details.
If the corresponding bit in the pulldown/up register is clear (and the pulldown/up
mask option is chosen) the input pin will also have an activated pulldown/up
device. Since the pulldown/up register bits are write-only, bit manipulation should
not be used on these register bits.
MOTOROLA
7-6
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
7.3.4 I/O Pin Transitions
A "glitch" can be generated on an I/O pin when changing it from an input to an
output unless the data register is first preconditioned to the desired state before
changing the corresponding DDR bit from a zero to a one.
Freescale Semiconductor, Inc...
If pulldowns are enabled by mask option, a floating input can be avoided by
clearing the pulldown/pullup register bit before changing the corresponding DDR
from a one to a zero. This will insure that the pulldown device will be activated
before the I/O pin changes from a driven output to a pulled low/high input.
7.3.5 I/O Pin Truth Tables
Every pin on Port A and Port B may be programmed as an input or an output
under software control as shown in Table 7-1 and Table 7-2. All port I/O pins may
also have software programmable pulldown/pullup devices if selected by the
appropriate mask option.
Table 7-1. Port A I/O Pin Functions
DDRA
Accesses to
PDURA
at $0010
I/O Pin Mode
Read
0
1
IN, Hi-Z
OUT
NOTE:
U
U
Write
Accesses
to DDRA
@ $0004
Read/Write
PDURA0-7 DDRA0-7
PDURA0-7 DDRA0-7
U is undefined.
Accesses to
Data Register
@ $0000
Read
Write
I/O Pin
PA0-7
*
PA0-7
* Does not affect input,
but stored to data register
Table 7-2. Port B I/O Pin Functions
DDRA
Accesses to
PDURB
at $0011
I/O Pin Mode
Read
0
1
NOTE:
MC68HC705JB2
REV 1.1
IN, Hi-Z
OUT
U
U
Write
Accesses
to DDRB
@ $0005
Read/Write
PDURB0-2 DDRB0-2
PDURB0-2 DDRB0-2
U is undefined.
Accesses to
Data Register
@ $0001
Read
Write
I/O Pin
PB0-2
*
PB0-2
* Does not affect input,
but stored to data register
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
7-7
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
7-8
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 8
MULTI-FUNCTION TIMER
The MC68HC705JB2 core timer is a multi-function ripple counter. The features
include Timer Over Flow (TOF) and Power-On Reset (POR).
Freescale Semiconductor, Inc...
MCU Internal Bus
8
8
Timer Counter Register ($09)
fOP÷22
÷4
Internal
Timer Clock
(NTF1)
÷210
7-bit counter
÷217
÷216
÷215
÷214
RTI Select Circuit
Overflow
Detect
Circuit
Timer Control & Status Register ($08)
TOF
RTIF
TOFE RTIE TOFR RTIFR
RT1
RT0
Interrupt Circuit
To CPU interrupt
Figure 8-1. Multi-Function Timer Block Diagram
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by
four (÷4). NTF1 has the same phase and frequency as the processor bus clock,
PH2, but is not stopped by the WAIT Modes. This signal drives an 8-bit ripple
counter. The value of this 8-bit ripple counter can be read by the CPU at any time
by accessing the Timer Counter Register (TCNT) at address $09. A timer overflow
MC68HC705JB2
REV 1.1
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
8-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Freescale Semiconductor, Inc...
function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of fop/1024. Two additional stages produce the POR function
at fop/4064. The Timer Counter Bypass circuitry (available only in Expanded Test
Mode) is at this point in the timer chain. This circuit is followed by two more
stages, with the resulting clock (fop/16384) driving the Real Time Interrupt circuit.
The RTI circuit consists of three divider stages with a 1 of 4 selector. The RTI rate
selector bits, and the RTI and TOF enable bits and flags are located in the Timer
Control and Status Register at location $08.
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4
selector. The clock frequency that drives the RTI circuit is fop/214 (or fop/16384)
with three additional divider stages giving a maximum interrupt period of fop/217
(or fop/131072).
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 128 or 4064 cycles, the power-on reset circuit is released which
again clears the counter chain and allows the device to come out of reset. At this
point, if RESET is not asserted, the timer will start counting up from zero and
normal device operation will begin. If RESET is asserted at any time during
operation the counter chain will be cleared.
8.1
TIMER REGISTERS
The 15-stage Multi-function Timer contains two registers: a Timer Counter
Register and a Timer Control/Status Register.
8.1.1 Timer Counter Register (TCNT) $09
The Timer Counter Register is a read-only register which contains the current
value of the 8-bit ripple counter at the beginning of the timer chain. This counter is
clocked at fop divided by 4 and can be used for various functions including a
software input capture. Extended time periods can be attained using the TOF
function to increment a temporary RAM storage location thereby simulating a 16bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2.
This register is cleared by reset.
TCNT
R
$0009
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
0
0
0
0
0
0
0
0
Figure 8-2. Timer Counter Register
MOTOROLA
8-2
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
8.1.2 Timer Control/Status Register (TCSR) $08
The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and
the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will
read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR
following reset.
TCSR
R
$0008
W
Freescale Semiconductor, Inc...
reset:
BIT 7
BIT 6
TOF
RTIF
0
0
BIT 5
BIT 4
TOFE
RTIE
0
0
BIT 3
BIT 2
0
0
TOFR
RTIFR
0
0
BIT 1
BIT 0
RT1
RT0
1
1
Figure 8-3. Timer Control/Status Register (TCSR)
TOF - Timer Overflow Flag
The TOF is a read-only flag bit.
1 = Set when the 8-bit ripple counter rolls over from $FF to $00. A
TIMER Interrupt request will be generated if TOFE is also set.
0 = Reset by writing a logical one to the TOF acknowledge bit, TOFR.
Writing to the TOF flag bit has no effect on its value. This bit is
cleared by reset.
RTIF - Real Time Interrupt Flag
The RTIF is a read-only flag bit.
1 = Set when the output of the chosen (1 of 4 selections) Real Time
Interrupt stage goes active. A TIMER Interrupt request will be
generated if RTIE is also set.
0 = Reset by writing a logical one to the RTIF acknowledge bit, RTIFR.
Writing to the RTIF flag bit has no effect on its value. This bit is
cleared by reset.
TOFE - Timer Overflow Enable
The TOFE is an enable bit that allows generation of a TIMER Interrupt upon
overflow of the Timer Counter Register.
1 = When set, the TIMER Interrupt is generated when the TOF flag bit is
set.
0 = When cleared, no TIMER interrupt caused by TOF bit set will be
generated. This bit is cleared by reset.
RTIE - Real Time Interrupt Enable
The RTIE is an enable bit that allows generation of a TIMER Interrupt by the
RTIF bit.
1 = When set, the TIMER Interrupt is generated when the RTIF flag bit is
set.
0 = When cleared, no TIMER interrupt caused by RTIF bit set will be
generated. This bit is cleared by reset.
MC68HC705JB2
REV 1.1
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
8-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
TOFR - Timer Overflow Acknowledge
The TOFR is an acknowledge bit that resets the TOF flag bit. This bit is
unaffected by reset. Reading the TOFR will always return a logical zero.
1 = Clears the TOF flag bit.
0 = Does not clear the TOF flag bit.
Freescale Semiconductor, Inc...
RTIFR - Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is
unaffected by reset. Reading the RTIFR will always return a logical zero.
1 = Clears the RTIF flag bit.
0 = Does not clear the RTIF flag bit.
RT1, RT0 - Real Time Interrupt period select bits
These two bits select one of the four real time interrupt periods.
Bus Frequency, fBUS =fOP =3.0 MHz
8.2
RT1
RT0
Divide Ratio
RTI Rate
0
0
214
5.46ms
0
1
215
10.92ms
1
0
216
21.85ms
1
1
217
43.69ms
OPERATION DURING STOP MODE
When STOP is exited by an external interrupt or an LVR reset or an external
RESET, the internal oscillator will resume, followed by a 128 or 4064 internal
processor oscillator stabilization delay.
MOTOROLA
8-4
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 9
PROGRAMMABLE TIMER
Freescale Semiconductor, Inc...
This 16-bit Programmable Timer (Timer1) has an Input Capture function and an
Output Compare function. Figure 9-1 shows a block diagram of the 16-bit
programmable timer.
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
ICF
TCAP
IEDG
TMRH ($0018) TMRL ($0019)
ACRH ($001A) ACRL ($001B)
÷4
OVERFLOW (TOF)
16-BIT COUNTER
INTERNAL
CLOCK
(fOSC ÷ 2)
16-BIT COMPARATOR
OCF
OCRH ($0016) OCRL ($0017)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
TOF
OCF
ICF
IEDG
TOIE
OCIE
ICIE
RESET
TIMER STATUS REGISTER
$0012
$0013
INTERNAL DATA BUS
Figure 9-1. Programmable Timer Block Diagram
MC68HC705JB2
REV 1.1
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a
specific timer function allows full control of that function; however, an access of
the high byte inhibits that specific timer function until the low byte is also
accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four
prescaler, the counter rolls over every 262,144 internal clock cycles. Timer
resolution with a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt flags can be read from the timer status register (TSR) located at
$0013.
9.1
TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 9-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
LATCH
READ
TMRH
READ
RESET
($FFFC)
TMRH ($0018)
READ
TMRL
TMRL ($0019)
TMR LSB
÷4
16-BIT COUNTER
OVERFLOW (TOF)
INTERNAL
CLOCK
(fOSC ÷ 2)
TIMER
INTERRUPT
REQUEST
TOF
TOIE
Freescale Semiconductor, Inc...
The basis of the 16-bit Timer is a 16-bit free-running counter which increases in
count with each internal bus clock cycle. The counter is the timing reference for
the input capture and output compare functions. The input capture and output
compare functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms and timing
delays. Software can read the value in the 16-bit free-running counter at any time
without affect the counter sequence.
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-2. Programmable Timer Counter Block Diagram
MOTOROLA
9-2
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations
which contain the current high and low bytes of the 16-bit free-running counter.
Writing to the timer registers has no effect. Reset of the device presets the timer
counter to $FFFC.
TMRH
R
$0018
W
reset:
TMRL
R
$0019
W
Freescale Semiconductor, Inc...
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
1
1
1
1
1
1
1
1
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
1
0
0
Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL)
The TMRL latch is a transparent read of the LSB until the a read of the TMRH
takes place. A read of the TMRH latches the LSB into the TMRL location until the
TMRL is again read. The latched value remains fixed even if multiple reads of the
TMRH take place before the next read of the TMRL. Therefore, when reading the
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if
the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag
bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any
order or any number of times does not have any effect on the 16-bit free-running
counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH
and TMRL, set the I bit in the condition code register (CCR) before
reading TMRH and clear the I bit after reading TMRL.
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
MC68HC705JB2
REV 1.1
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
Freescale Semiconductor, Inc...
LATCH
READ
ACRH
READ
RESET
($FFFC)
READ
ACRL
ACRL ($001B)
TMR LSB
ACRH ($001A)
INTERNAL
CLOCK
(fOSC ÷ 2)
÷4
16-BIT COUNTER
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
ACRH
R
$001A
W
reset:
ACRL
R
$001B
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
1
0
0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains fixed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF flag bit.
MOTOROLA
9-4
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
NOTE
To prevent interrupts from occurring between readings of the ACRH
and ACRL, set the I bit in the condition code register (CCR) before
reading ACRH and clear the I bit after reading ACRL.
INPUT CAPTURE REGISTERS
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is
possible to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input
capture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter
values at successive edges of opposite polarity measures the pulse width of the
signal.
INTERNAL
DATA
BUS
READ
ICRH
RESET
ICRH ($0014)
ICRL ($0015)
16-BIT COUNTER
READ
ICRL
÷4
INPUT CAPTURE (ICF)
INTERNAL
CLOCK
(fOSC ÷ 2)
TIMER
INTERRUPT
REQUEST
IEDG
($FFFC)
LATCH
TIMER CONTROL REG.
ICF
EDGE
SELECT
& DETECT
LOGIC
IEDG
PB0/TCAP
ICIE
Freescale Semiconductor, Inc...
9.3
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-6. Timer Input Capture Block Diagram
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt
MC68HC705JB2
REV 1.1
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
trigger to improve noise immunity. The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in the TCR. Reset does not affect the
contents of the input capture registers.
Freescale Semiconductor, Inc...
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
ICRH
R
$0014
W
reset:
ICRL
R
$0015
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
U
U
U
U
U
U
U
U
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
U
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 9-7. Input Capture Registers (ICRH, ICRL)
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does
not inhibit transfer of the free-running counter. There is no conflict between
reading the ICRL and transfers from the free-running timer counters. The input
capture registers always contain the free-running timer counter value which
corresponds to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH
and ICRL, set the I bit in the condition code register (CCR) before
reading ICRH and clear the I bit after reading ICRL.
9.4
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16bit timer counter reaches a selected value as shown in Figure 9-8. Software
writes the selected value into the output compare registers. On every fourth
internal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the output compare interrupt
flag, OCF is set. A timer interrupt request to the CPU is generated if the output
compare interrupt enable is set, i.e. OCIE=1.
MOTOROLA
9-6
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Software can use the output compare register to measure time periods, to
generate timing delays, or to generate a pulse of specific duration or a pulse train
of specific frequency and duty cycle.
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF).
OCRH ($0016)
R/W
OCRL
OCRL ($0017)
16-BIT COMPARATOR
($FFFC)
INTERNAL
CLOCK
(fOSC ÷ 2)
÷4
16-BIT COUNTER
OUTPUT COMPARE
(OCF)
RESET
TIMER
INTERRUPT
REQUEST
OCF
OCIE
Freescale Semiconductor, Inc...
R/W
OCRH
TIMER STATUS REG.
TIMER CONTROL REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 9-8. Timer Output Compare Block Diagram
OCRH
R
$0016
W
reset:
OCRL
R
$0017
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
U
U
U
U
U
U
U
U
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
U
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 9-9. Output Compare Registers (OCRH, OCRL)
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
MC68HC705JB2
REV 1.1
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
Freescale Semiconductor, Inc...
A software example of this procedure is shown below.
9B
...
...
B7
B6
BF
...
...
9A
9.5
SEI
...
...
STA
LDA
STX
...
...
CLI
16
13
17
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
OCRH
TSR
OCRL
TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 9-10 performs the following
functions:
•
Enables input capture interrupts
•
Enables output compare interrupts
•
Enables timer overflow interrupts
•
Control the active edge polarity of the TCAP signal on pin PB0/TCAP
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
TCR
R
$0012
W
reset:
BIT 7
BIT 6
BIT 5
ICIE
OCIE
TOIE
0
0
0
BIT 4
BIT 3
BIT 2
0
0
0
0
0
0
BIT 1
IEDG
Unaffected
BIT 0
0
0
Figure 9-10. Timer Control Register (TCR)
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB0/
TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
MOTOROLA
9-8
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by a successful compare between
the timer counter and the output compare registers. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
Freescale Semiconductor, Inc...
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
1 = Timer overflow interrupts enabled.
0 = Timer overflow interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative
transition on the TCAP pin triggers a transfer of the contents of the timer
register to the input capture register. Reset has no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
9.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 9-11 contains flags for the
following events:
•
An active signal on the PB0/TCAP pin, transferring the contents of the
timer registers to the input capture registers.
•
A match between the 16-bit counter and the output compare registers
•
An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the flag bits in the TSR.
TSR
R
$0013
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 9-11. Timer Status Registers (TSR)
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
MC68HC705JB2
REV 1.1
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Reset has no effect on OCF.
Freescale Semiconductor, Inc...
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Reset has no effect on TOF.
9.7
TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may
generate an interrupt to trigger the MCU out of the WAIT mode.
9.8
TIMER OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
time the counter resumes from its stopped value as if nothing had happened. If
STOP mode is exited via an external reset (logic low applied to the RESET pin)
the counter is forced to $FFFC.
If a valid input capture edge occurs at the PB0/TCAP pin during the STOP mode
the input capture detect circuitry will be armed. This action does not set any flags
or “wake up” the MCU, but when the MCU does “wake up” there will be an active
input capture flag (and data) from the first valid edge. If the STOP mode is exited
by an external reset, no input capture flag or data will be present even if a valid
input capture edge was detected during the STOP mode.
MOTOROLA
9-10
PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 10
UNIVERSAL SERIAL BUS MODULE
Freescale Semiconductor, Inc...
This USB Module is designed for USB application in LS products. With minimized
software effort, it can fully comply with USB LS device specification. See USB
specification version 1.0 for the detail description of USB.
10.1
FEATURES
•
Integrated 3.3 Volt Regulator with 3.3V Output Pin
•
Integrated USB transceiver supporting Low Speed functions
•
USB Data Control Logic
– Packet decoding/generation
– CRC generation and checking
– NRZI encoding/decoding
– Bit-stuffing
•
USB reset support
•
Control Endpoint 0 and Interrupt Endpoints 1 and 2
•
Two 8-byte transmit buffers
•
One 8-byte receive buffer
•
Suspend and resume operations
•
Remote Wake-up support
•
USB generated interrupts
•
transaction interrupt driven
•
Resume interrupt
•
End of Packet interrupt
•
STALL, NAK, and ACK handshake generation
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.2
August 28, 1998
OVERVIEW
A block diagram of the USB module is shown Figure 10-1. The USB module
manages communications between the host and the USB function. The module is
partitioned into four functional blocks. These blocks consist of a 3.3 volt regulator,
a dual function transceiver, the USB control logic, and the endpoint registers. The
blocks are further detailed in Section 10.4.
CPU BUS
USB REGISTERS
RCV
VPIN
VMIN
VPOUT
TRANSCEIVER
USB CONTROL LOGIC
Freescale Semiconductor, Inc...
This section provides an overview of the Universal Serial Bus (USB) module in the
MC68HC705JB2. This USB module is designed to serve as a low-speed (LS)
USB device per the Universal Serial Bus Specification Rev 1.0. Three types of
USB data transfers are supported: control, interrupt, and bulk (transmit only).
Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2
can function as interrupt or bulk, but only in the transmit direction.
D+
D–
USB
Upstream
Port
VMOUT
REGULATOR
3.3 V OUT
Figure 10-1. USB Block Diagram
MOTOROLA
10-2
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
10.2.1 USB Protocol
Figure 10-2 shows the various transaction types supported by the
MC68HC705JB2 USB module. The transactions are portrayed as error free. The
effect of errors in the data flow are discussed later.
ENDPOINT 0 TRANSACTIONS:
Control Write
Freescale Semiconductor, Inc...
SETUP
DATA0
ACK
OUT
DATA0
OUT
ACK
DATA1
ACK
OUT
DATA0/1
IN
ACK
ACK
DATA1
Control Read
SETUP
DATA0
ACK
IN
DATA0
IN
ACK
DATA1
ACK
IN
DATA0/1
OUT
ACK
ACK
DATA1
No-Data Control
DATA0
SETUP
ACK
IN
DATA1
ACK
ENDPOINTS 1 & 2 TRANSACTIONS:
KEY:
Interrupt
IN
DATA0/1
ACK
Unrelated Bus
Traffic
Host
Generated
Bulk Transmit
IN
DATA0/1
ACK
Device
Generated
Figure 10-2. Supported Transaction Types per Endpoint
Each USB transaction is comprised of a series of packets. The MC68HC705JB2
USB module supports the packet types shown in Figure 10-3. Token packets are
generated by the USB host and decoded by the USB device. Data and
Handshake packets are both decoded and generated by the USB device
depending on the type of transaction.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Token Packet:
IN
OUT
SYNC
PID
PID
SYNC
PID
PID
ADDR
ENDP
CRC5
EOP
CRC5
EOP
SETUP
Data Packet:
DATA0
DATA1
DATA
0 - 8 bytes
Freescale Semiconductor, Inc...
Handshake Packet:
ACK
NAK
SYNC
PID
PID
EOP
STALL
Figure 10-3. Supported USB Packet Types
The following sections will give some detail on each segment used to form a
complete USB transaction.
10.2.1.1 Sync Pattern
The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a
synchronization pattern and is prefixed to each packet. This pattern is equivalent
to a data pattern of seven 0’s followed by a 1 (0x80).
SYNC PATTERN
NRZI Data
Encoding
Idle
PID0
PID1
Figure 10-4. Sync Pattern
The start of a packet (SOP) is signaled by the originating port by driving the D+
and D- lines from the idle state (also referred to as the “J” state) to the opposite
logic level (also referred to as the “K” state). This switch in levels represents the
first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels
for the start of packet and the sync pattern.
MOTOROLA
10-4
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
VOH (min)
VSE (max)
VSE (min)
VOL (min)
VSS
FIRST BIT OF PACKET
Freescale Semiconductor, Inc...
BUS IDLE
SOP
END OF SYNC
Figure 10-5. SOP, Sync Signaling and Voltage Levels
10.2.1.2 Packet Identifier Field
The Packet Identifier field is an eight bit number comprised of the four bit packet
identification (PID) and its complement. The field follows the sync pattern and
determines the direction and type of transaction on the bus. Table 10-1 shows the
PID values for the supported packet types.
Table 10-1. Supported Packet Identifiers
PID Value
PID Type
%1001
IN Token
%0001
OUT Token
%1101
SETUP Token
%0011
DATA0 Packet
%1011
DATA1 Packet
%0010
ACK Handshake
%1010
NAK Handshake
%1110
STALL Handshake
10.2.1.3 Address Field (ADDR)
The Address field is a seven bit number that is used to select a particular USB
device. This field is compared to the lower seven bits of the UADDR register to
determine if a given transaction is targeting the MC68HC705JB2 USB device.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.2.1.4 Endpoint Field (ENDP)
The Endpoint field is a four bit number that is used to select a particular endpoint
within a USB device. For the MC68HC705JB2, this will be a binary number
between zero and two inclusive. Any other value will cause the transaction to be
ignored.
Freescale Semiconductor, Inc...
10.2.1.5 Cyclic Redundancy Check (CRC)
Cyclic Redundancy Checks are used to verify the address and data stream of a
USB transaction. This field is five bits wide for token packets and sixteen bits wide
for data packets. CRCs are generated in the transmitter and sent on the USB data
lines after both the endpoint field and the data field. Figure 10-6 shows how the
five bit CRC value is calculated from the data stream and verified for the address
and endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRC
value is calculated and either transmitted or verified for the data packet of a given
transaction.
Update every bit time
Reset to ones at SOP
Generator Polynomial:
0 0 1 0 1
Data Stream
5
next bit
0
5
0
MUX
1
5
Expected Residual:
0 1 1 0 0
5
5
Good CRC
Y
Equal?
N
Bad CRC
Figure 10-6. CRC Block Diagram for Address and Endpoint Fields
MOTOROLA
10-6
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
Update every bit time
Reset to ones at SOP
GENERAL RELEASE SPECIFICATION
Generator Polynomial:
1 0 0 0 0 0 0 0 0 0 0 001 01
Input / Output
Data Stream
16
next bit
0
Freescale Semiconductor, Inc...
16
0
Output
Data Stream
TRANSMIT
MUX
1
16
16
CRC16 Transmitted
MSB first after final
data byte.
Expected Residual:
RECEIVE
1 0 0 0 0 0 0 0 0 0 00 1 1 01
16
Equal?
Good CRC
Y
N
Bad CRC
Figure 10-7. CRC Block Diagram for Data Packets
10.2.1.6 End Of Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The
single-ended 0 state is indicated by both D+ and D- being below 0.8 V. EOP will be
signaled by driving D+ and D- to the single-ended 0 state for two bit times followed
by driving the lines to the idle state for one bit time. The transition from the singleended 0 to the idle state defines the end of the packet. The idle state is asserted
for one bit time and then both the D+ and D- output drivers are placed in their
high-impedance state. The bus termination resistors hold the bus in the idle state.
Figure 10-8 shows the data signaling and voltage levels for an end of packet
transaction.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
LAST BIT OF
PACKET
EOP
STROBE
BUS DRIVEN TO
IDLE STATE
BUS FLOATS
BUS IDLE
VOH (min)
VSE (max)
VSE (min)
VOL (min)
Freescale Semiconductor, Inc...
VSS
Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width is
measured with the same capacitive load used for maximum rise and fall times and
is measured at the same level as the differential signal crossover points of the
data lines.
tPeriod
DIFFERENTIAL
DATA LINES
DATA
CROSSOVER
LEVEL
EOP
WIDTH
Figure 10-9. EOP Width Timing
10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USB
data pins of a device. The reset signaling is specified to be present for a minimum
of 10 ms. An active device (powered and not in the suspend state) seeing a
single-ended zero on its USB data inputs for more than 2.5µs may treat that signal
as a reset, but must have interpreted the signaling as a reset within 5.5 µs. For a
Low speed device, an SE0 condition between 4 and 8 low speed bit times
represents a valid USB reset.
A USB sourced reset will hold the MC68HC705JB2 in reset for the duration of the
reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be
set after the internal reset is removed (See Section 10.5.2 for more detail).
MOTOROLA
10-8
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
After a reset is removed, the device will be in the attached, but not yet addressed
or configured state (refer to Section 9.1 of the USB specification). The device must
be able to accept a device address via a SET_ADDRESS command (refer to
section 9.4 of the USB specification) no later than 10 ms after the reset is
removed.
Reset can wake a device from the suspended mode. A device may take up to
10ms to wake up from the suspended state.
Freescale Semiconductor, Inc...
10.2.3 Suspend
The MC68HC705JB2 supports suspend mode for low power. Suspend mode
should be entered when the USB data lines are in the idle state for more than 3.0
ms. Entry into Suspend mode is controlled by the SUSPND bit in the USB
Interrupt Register. Any low speed bus activity should keep the device out of the
suspend state. Low speed devices are kept awake by periodic low speed EOP
signals from the host. This is referred to as Low speed keep alive (refer to Section
11.2.5.1 of the USB specification).
Firmware should monitor the EOPF flag and enter suspend mode by setting the
SUSPND bit if an EOP is not detected for 3 ms.
Per the USB specification, the MC68HC705JB2 is required to draw less than
500 µA from the VDD supply when in the suspend state. This includes the current
supplied by the voltage regulator to the 15 KΩ to ground termination resistors
placed at the host end of the USB bus. This low current requirement means that
firmware is responsible for entering STOP mode once the USB module has been
placed in the suspend state.
10.2.4 Resume After Suspend
The MC68HC705JB2 can be activated from the suspend state by normal bus
activity, a USB reset signal, or by a forced resume driven from the
MC68HC705JB2.
10.2.4.1 Host Initiated Resume
The host signals resume by initiating resume signalling (“K” state) for at least 20
ms followed by a standard low speed EOP signal. This 20 ms ensures that all
devices in the USB network are awakened.
After resuming the bus, the host must begin sending bus traffic within 3 ms to
prevent the device from re-entering suspend mode.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.2.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode. A device may take up to 10
ms to wake up from the suspended state.
10.2.4.3 Remote Wake-up
Freescale Semiconductor, Inc...
The MC68HC705JB2 also supports the remote wake-up feature. The firmware
has the ability to exit suspend mode by signaling a resume state to the upstream
Host or Hub. A non-idle state (“K” state) on the USB data lines is accomplished by
asserting the FRESUM bit in the UCR1 register.
When using the remote wake-up capability, the firmware must wait for at least 5
ms after the bus is in the idle state before sending the remote wake-up resume
signaling. This allows the upstream devices to get into their suspend state and
prepare for propagating resume signaling. The FRESUM bit should be asserted to
cause the resume state on the USB data lines for at least 10ms, but not more than
15ms. Note that the resume signalling is controlled by the FRESUM bit and
meeting the timing specifications is dependent on the firmware. When FRESUM is
cleared by firmware, the data lines will return to their high impedance state. Refer
to Section 10.5.5 for more information about how the Force Resume (FRESUM)
bit can be used to initiate the remote wake-up feature.
10.2.5 Low Speed Device
Externally, low speed devices are configured by the position of a pull-up resistor
on the USB D- pin of the MC68HC705JB2. Low speed devices are terminated as
shown in Figure 10-10 with the pull-up on the D- line.
3.3V Regulator Out
68HC705JB2
1.5KΩ
D+
USB Low Speed Cable
D–
Figure 10-10. External Low Speed Device Configuration
For low speed transmissions, the transmitter’s EOP width must be between
1.25µs and 1.50µs. These ranges include timing variations due to differential
buffer delay and rise/fall time mismatches and to noise and other random effects.
A low speed receiver must accept a 670 ns wide SE0 followed by a J transition as
a valid EOP. An SE0 narrower than 330 ns or an SE0 not followed by a J transition
must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected
or accepted as above. Any SE0 that is 2.5µs or wider is automatically a reset.
MOTOROLA
10-10
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
10.3
GENERAL RELEASE SPECIFICATION
CLOCK REQUIREMENTS
Freescale Semiconductor, Inc...
The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the
oscillator circuits is the clock source for the USB module and requires that a 6
MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted
frequency tolerance for low speed functions is approximately ±1.5% (15000 ppm).
This tolerance includes inaccuracies from all sources: initial frequency accuracy,
crystal capacitive loading, supply voltage on the oscillator, temperature, and
aging. The jitter in the low speed data rate must be less than 10 ns. This tolerance
allows the use of resonators in low cost, low speed devices.
10.4
HARDWARE DESCRIPTION
The USB module as previously shown in Figure 10-1 contains four functional
blocks: a 3.3 volt Regulator, a LS USB transceiver, the USB control logic, and the
USB registers. The following will detail the function of the regulator, transceiver
and control logic. See Section 10.5 for the register discussion.
10.4.1 Voltage Regulator
The USB data lines are required by the USB Specification to have a maximum
output voltage between 2.8V and 3.6V. The data lines are also required to have an
external 1.5KΩ pullup resistor connected between a data line and a voltage
source between 3.0V and 3.6V. Since the power provided by the USB cable is
specified to be between 4.4V and 5.0V, an on-chip regulator is used to drop the
voltage to the appropriate level for sourcing the USB transceiver and external
pullup resistor. An output pin driven by the regulator voltage is provided to source
the 1.5KΩ external resistor. Figure 10-11 shows the worst case electrical
connection for the voltage regulator.
4.4V
3.3V
Regulator
USB Data Lines
R1
LS
Transceiver
Host
or
Hub
USB Cable
R2
R2
R1 = 1.5KΩ ±5%
R2 = 15KΩ ±5%
Figure 10-11. Regulator Electrical Connections
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-11
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.4.2 USB Transceiver
The USB transceiver provides the physical interface to the USB D+ and D- data
lines. The transceiver is composed of two parts: an output drive circuit and a
differential receiver.
Freescale Semiconductor, Inc...
10.4.2.1 Output Driver Characteristics
The USB transceiver uses a differential output driver to drive the USB data signal
onto the USB cable. The static output swing of the driver in its low state is below
the VOL of 0.3 V with a 1.5 kΩ load to 3.6 V and in its high state is above the VOH
of 2.8 V with a 15 kΩ load to ground. The output swings between the differential
high and low state are well balanced to minimize signal skew. Slew rate control on
the driver is used to minimize the radiated noise and cross talk. The driver’s
outputs support three-state operation to achieve bi-directional half duplex
operation. The driver can tolerate a voltage on the signal pins of -0.5 V to 3.8 V
with respect to local ground reference without damage.
10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics
The rise and fall time of the signals on this cable are greater than 75 ns to keep
RFI emissions under FCC class B limits, and less than 300 ns to limit timing
delays and signaling skews and distortions. The driver reaches the specified static
signal levels with smooth rise and fall times, and minimal reflections and ringing
when driving the cable. This driver is used only on network segments between low
speed devices and the ports to which they are connected.
ONE BIT
TIME
(1.5 Mb/s)
VSE (max)
VSE (min)
SIGNAL PINS
PASS OUTPUT SPEC
LEVELS WITH MINIMAL
REFLECTIONS AND RINGING
VSS
Figure 10-12. Low Speed Driver Signal Waveforms
MOTOROLA
10-12
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
10.4.3 Receiver Characteristics
The receiver features an input sensitivity of 200 mV when both differential data
inputs are in the range of 0.8 V to 2.5 V with respect to the local ground reference.
This is called the common mode input voltage range. Proper data reception is also
achieved when the differential data lines are outside the common mode range, as
shown in Figure 10-13. The receiver can tolerate static input voltages between
–0.5V to 3.8 V with respect to its local ground reference without damage. In
addition to the differential receiver, there is a single-ended receiver (schmitt
trigger) for each of the two data lines.
MINIMUM DIFFERENTIAL SENSITIVITY (VOLTS)
Freescale Semiconductor, Inc...
USB data transmission is done with differential signals. A differential input receiver
is used to accept the USB data signal. A differential 1 on the bus is represented by
D+ being at least 200 mV more positive than D- as seen at the receiver, and a
differential 0 is represented by D- being at least 200 mV more positive than D+ as
seen at the receiver. The signal cross over point must be between 1.3V and 2.0V.
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
COMMON MODE INPUT VOLTAGE (VOLTS)
Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range
10.4.3.1 Receiver Data Jitter
The data receivers for all types of devices must be able to properly decode the
differential data in the presence of jitter. The more of the bit cell that any data edge
can occupy and still be decoded, the more reliable the data transfer will be. Data
receivers are required to decode differential data transitions that occur in a
window plus and minus a nominal quarter bit cell from the nominal (centered) data
edge position.
Jitter will be caused by the delay mismatches and by mismatches in the source
and destination data rates (frequencies). The receive data jitter budget for low
speed is given in the electrical section of the this specification. The specification
includes the consecutive (next) and paired transition values for each source of
jitter.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-13
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.4.3.2 Data Source Jitter
The source of data can have some variation (jitter) in the timing of edges of the
data transmitted. The time between any set of data transitions is N * TPERIOD ±
jitter time, where ‘N’ is the number of bits between the transitions and TPERIOD is
defined as the actual period of the data rate. The data jitter is measured with the
same capacitive load used for maximum rise and fall times and is measured at the
crossover points of the data lines as shown in Figure 10-14.
Freescale Semiconductor, Inc...
tPeriod
CROSSOVER
POINTS
DIFFERENTIAL
DATA LINES
CONSECUTIVE
TRANSITIONS
PAIRED
TRANSITIONS
Figure 10-14. Data Jitter
For low speed transmissions, the jitter time for any consecutive differential data
transitions must be within ±25 ns and within ±10 ns for any set of paired
differential data transitions. These jitter numbers include timing variations due to
differential buffer delay, rise/fall time mismatches, internal clock source jitter, and
to noise and other random effects.
10.4.3.3 Data Signal Rise and Fall Time
The output rise time and fall time are measured between 10% and 90% of the
signal. Edge transition time for the rising and falling edges of low speed signals is
75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into a
capacitive load of 350 pF. The rising and falling edges should be smooth
transitional (monotonic) when driving the cable to avoid excessive EMI.
FALL TIME
RISE TIME
CL
90%
90%
DIFFERENTIAL
DATA LINES
10%
10%
CL
tR
tF
LOW SPEED: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 10-15. Data Signal Rise and Fall Time
MOTOROLA
10-14
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
10.4.4 USB Control Logic
Freescale Semiconductor, Inc...
The USB control logic manages data movement between the CPU and the
transceiver. The control logic handles both transmit and receive operations on the
USB. It contains the logic used to manipulate the transceiver and the endpoint
registers. The logic contains byte count buffers for transmit operations that load
the active transmit endpoints byte count and use this to determine the number of
bytes to transfer. This same buffer is used for receive transactions to count the
number of bytes received and, upon the end of the transaction, transfer that
number to the receive endpoints byte count register.
When transmitting, the control logic handles parallel to serial conversion, CRC
generation, NRZI encoding, and bit stuffing.
When Receiving, the control logic handles Sync detection, packet identification,
end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and
serial to parallel conversion. Errors detected by the control logic include bad CRC,
time-out while waiting for EOP, and bit stuffing violations.
10.4.4.1 Data Encoding/Decoding
The USB employs NRZI data encoding when transmitting packets. In NRZI
encoding, a 1 is represented by no change in level and a 0 is represented by a
change in level. Figure 10-16 shows a data stream and the NRZI equivalent and
Figure 10-17 is a flow diagram for NRZI. The high level represents the J state on
the data lines in this and subsequent figures showing NRZI encoding. A string of
zeros causes the NRZI data to toggle each bit time. A string of ones causes long
periods with no transitions in the data.
10.4.4.2 Bit Stuffing
In order to ensure adequate signal transitions, bit stuffing is employed by the
transmitting device when sending a packet on the USB (see Figure 10-18 and
Figure 10-19). A 0 is inserted after every six consecutive 1’s in the data stream
before the data is NRZI encoded to force a transition in the NRZI data stream.
This gives the receiver logic a data transition at least once every seven bit times to
guarantee the data and clock lock. The receiver must decode the NRZI data,
recognize the stuffed bits, and discard them. Bit stuffing is enabled beginning with
the Sync Pattern and throughout the entire transmission. The data “one” that ends
the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always
enforced, without exception. If required by the bit stuffing rules, a zero bit will be
inserted even if it is the last bit before the end-of-packet (EOP) signal.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-15
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
0
DATA
IDLE
NRZI
IDLE
1
1
August 28, 1998
0
1
0
1
0
0
0
1
0
0
1
1
0
Figure 10-16. NRZI Data Encoding
POWER UP
Freescale Semiconductor, Inc...
NO PACKET
TRANSMISSION
IDLE
BEGIN PACKET
TRANSMISSION
FETCH THE
DATA BIT
NO
IS DATA
BIT = 0?
NO DATA
TRANSITION
NO
YES
TRANSITION
DATA
IS PACKAGE
TRANSFER
DONE?
YES
Figure 10-17. Flow Diagram for NRZI
RAW
DATA
SYNC PATTERN
PACKET DATA
STUFFED BIT
BIT
STUFFED
DATA
NRZI
ENCODED
DATA
PACKET DATA
SYNC PATTERN
SIX ONES
IDLE
SYNC PATTERN
PACKET DATA
Figure 10-18. Bit Stuffing
MOTOROLA
10-16
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
POWER UP
NO PACKET
TRANSMISSION
IDLE
BEGIN PACKET
TRANSMISSION
RESET BIT
COUNTER TO 0
Freescale Semiconductor, Inc...
GET NEXT
BIT
=0
BIT VALUE?
=1
INCREMENT
THE COUNTER
NO
COUNTER = 6?
YES
INSERT A
ZERO BIT
RESET THE BIT
COUNTER TO 0
NO
IS PACKAGE
TRANSFER
DONE?
YES
Figure 10-19. Flow Diagram for Bit Stuffing
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-17
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.5
August 28, 1998
I/O REGISTER DESCRIPTION
The USB Endpoint registers are comprised of a set of control/status registers and
twenty-four data registers that provide storage for the buffering of data between
the USB and the CPU. These registers are shown in Table 10-2.
Table 10-2. Register Summary
Register Name
Bit 7
Freescale Semiconductor, Inc...
USB Control Register 2
(UCR2)
6
5
4
0
TX1ST
0
UADD4
UADD3
UADD2
SUSPND
TXD0IE
RXD0IE
TXD1IE
EOPIE
TX1STR
USB Address Register
USBEN
(UADDR)
UADD6
UADD5
USB Interrupt Register 0
(UIR0)
TXD0F
RXD0F
RSTF
USB Interrupt Register 1
(UIR1)
TXD1F
EOPF
RESUMF
RESUMFR
USB Control Register 0
T0SEQ
(UCR0)
STALL0
TX0E
USB Control Register 1
T1SEQ
(UCR1)
ENDADD
TX1E
SETUP
0
USB Status Register
(USR)
0
RSEQ
RX0E
3
2
1
ENABLE2 ENABLE1 STALL2
UADD1
0
Bit 0
STALL1 $0037
UADD0 $0038
0
TXD0FR RXD0FR
0
Addr
0
TXD1FR EOPFR
$0039
$003A
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C
0
USB Endpoint 0 Data UE0RD7 UE0RD6 UE0RD5 UE0RD4
Register 0 (UE0D0) UE0TD7 UE0TD6 UE0TD5 UE0TD4
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD3 UE0TD2 UE0TD1 UE0TD0
↓
$003D
$0020
↓
USB Endpoint 0 Data UE0RD7 UE0RD6 UE0RD5 UE0RD4
Register 7 (UE0D7) UE0TD7 UE0TD6 UE0TD5 UE0TD4
USB Endpoint 1/2 Data
Register 0 (UE1D0) UE1TD7 UE1TD6 UE1TD5
UE1TD4
UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE1TD3 UE1TD2 UE1TD1 UE1TD0
↓
$0027
$0028
↓
USB Endpoint 1/2 Data
Register 7 (UE1D7) UE1TD7 UE1TD6 UE1TD5
UE1TD4
UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002F
= Unimplemented
MOTOROLA
10-18
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
10.5.1 USB Address Register (UADDR)
UADDR
R
$0038
W
reset ⇒
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
Figure 10-20. USB Address Register (UADDR)
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB pins.
When USBEN is clear, the USB module will not respond to any tokens. Reset
clears this bit.
1 = USB function enabled
0 = USB function disabled
UADD6-UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
UIR0
R
$0039
W
reset ⇒
Bit 7
Bit 6
Bit 5
TXD0F
RXD0F
RSTF
0
0
0
Bit 4
Bit 3
Bit 2
SUSPND
TXD0IE
RXD0IE
0
0
0
Bit 1
Bit 0
0
0
TXD0FR
RXD0FR
0
0
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received. Once the
next set of data is ready in the transmit buffers, software must clear this flag by
writing a logic 1 to the TXD0FR bit. To enable the next data packet
transmission, TX0E must also be set. If TXD0F bit is not cleared, a NAK
handshake will be returned in the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 = Transmit on Endpoint 0 has occurred
0 = Transmit on Endpoint 0 has not occurred
RXD0F — Endpoint 0 Data Receive Flag
This read only bit is set after the USB module has received a data packet and
responded with an ACK handshake packet. Software must clear this flag by
writing a logic 1 to the RXD0FR bit after all of the received data has been read.
Software must also set RX0E bit to one to enable the next data packet
reception. If RXD0F bit is not cleared, a NAK handshake will be returned in the
next OUT transaction.
Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-19
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
1 = Receive on Endpoint 0 has occurred
0 = Receive on Endpoint 0 has not occurred
Freescale Semiconductor, Inc...
RSTF — USB Reset Flag
This read only bit is set when a valid reset signal state is detected on the D+
and D- lines. This reset detection will also generate an internal reset signal to
reset the CPU and other peripherals including the USB module. This bit is
cleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit is
cleared by a POR reset.
SUSPND — USB Suspend Flag
To save power, this read/write bit should be set by the software if a 3ms
constant idle state is detected on USB bus. Setting this bit stops the clock to
the USB and causes the USB module to enter Suspend mode. Unnecessary
analog circuitry will be powered down. Software must clear this bit after the
Resume flag (RESUMF) is set while this Resume interrupt flag is serviced.
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the TXD0F bit becomes set.
1 = USB interrupts enabled for Transmit Endpoint 0
0 = USB interrupts disabled for Transmit Endpoint 0
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the RXD0F bit becomes set.
1 = USB interrupts enabled for Receive Endpoint 0
0 = USB interrupts disabled for Receive Endpoint 0
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a
logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a
logic 0 to RXD0FR has no effect. Reset clears this bit.
10.5.3 USB Interrupt Register 1 (UIR1)
UIR1
R
$003A
W
reset ⇒
Bit 7
Bit 6
Bit 5
Bit 4
TXD1F
EOPF
RESUMF
0
0
0
0
RESUMFR
0
Bit 3
Bit 2
TXD1IE
EOPIE
0
0
Bit 1
Bit 0
0
0
TXD1FR
EOPFR
0
0
= Unimplemented
Figure 10-22. USB Interrupt Register 1(UIR1)
MOTOROLA
10-20
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Freescale Semiconductor, Inc...
TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag
This read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the data
stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and
an ACK handshake packet from the host is received. Once the next set of data
is ready in the transmit buffers, software must clear this flag by writing a logic 1
to the TXD1FR bit. To enable the next data packet transmission, TX1E must
also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in
the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD1F has no effect.
1 = Transmit on Endpoint 1 or Endpoint 2 has occurred
0 = Transmit on Endpoint 1 or Endpoint 2 has not occurred
EOPF — End of Packet Detect Flag
This read only bit is set when a valid End-of-Packet sequence is detected on
the D+ and D- lines. Software must clear this flag by writing a logic 1 to the
EOPFR bit.
Reset clears this bit. Writing a logic 0 to EOPF has no effect.
1 = End-of-Packet sequence has been detected
0 = End-of-Packet sequence has not been detected
RESUMF — Resume Flag
This read only bit is set when USB bus activity is detected while the SUSPND
bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit.
Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
1 = USB bus activity has been detected
0 = No USB bus activity has been detected
RESUMFR — Resume Flag Reset
Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set.
Writing a logic 0 to RESUMFR has no effect. Reset clears this bit.
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the shared
Transmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Reset
clears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2
0 = USB interrupts disabled for Transmit Endpoints 1 and 2
EOPIE — End of Packet Detect Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the EOPF bit
becomes set. Reset clears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2
0 = USB interrupts disabled for Transmit Endpoint 1 and 2
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a
logic 0 to TXD1FR has no effect. Reset clears this bit.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-21
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
EOPFR — End of Packet Flag Reset
Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a
logic 0 to the EOPFR has no effect. Reset clears this bit.
10.5.4 USB Control Register 0 (UCR0)
UCR0
R
$003B
W
reset ⇒
Bit 7
Bit 6
Bit 5
Bit 4
T0SEQ
STALL0
TX0E
RX0E
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
0
0
0
0
Freescale Semiconductor, Inc...
Figure 10-23. USB Control Register 0 (UCR0)
T0SEQ — Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction. Toggling of this bit must be controlled by
software. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 0 transmit
0 = DATA0 Token active for next Endpoint 0 transmit
STALL0 — Endpoint 0 Force Stall Bit
This read/write bit causes Endpoint 0 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. The USB
hardware clears this bit when a SETUP token is received. Reset clears this bit.
1 = Send STALL handshake
0 = Default
TX0E — Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 0. Software should set this bit when data is
ready to be transmitted. It must be cleared by software when no more Endpoint
0 data needs to be transmitted.
If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
RX0E — Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB Host controller
sends an OUT token to Endpoint 0. Software should set this bit when data is
ready to be received. It must be cleared by software when data cannot be
received.
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 OUT tokens. Reset clears this bit.
1 = Data is ready to be received.
0 = Not ready for data. Respond with NAK.
MOTOROLA
10-22
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 0. These bits are cleared by reset.
10.5.5 USB Control Register 1 (UCR1)
Bit 7
UCR1
R
$003C
W
reset ⇒
Bit 6
T1SEQ ENDADD
0
0
Bit 5
TX1E
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
0
0
0
0
0
Freescale Semiconductor, Inc...
Figure 10-24. USB Control Register 1 (UCR1)
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit
0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit
ENDADD — Endpoint Address Select
This read/write bit specifies whether the data inside the registers UE1D0UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are satisfied
(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit
is configured for Endpoint 1, the USB responds with a NAK handshake packet.
1 = The data buffers are used for Endpoint 2
0 = The data buffers are used for Endpoint 1
TX1E — Endpoint 1/Endpoint 2 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.
Software should set the TX1E bit when data is ready to be transmitted. It must
be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake
to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
FRESUM — Force Resume
This read/write bit forces a resume state (“K” or non-idle state) onto the USB
data lines to initiate a remote wake-up. Software should control the timing of the
forced resume to be between 10ms and 15 ms. Setting this bit will not cause
the RESUMF bit to set.
1 = Force data lines to “K” state
0 = Default
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-23
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
10.5.6 USB Control Register 2 (UCR2)
Bit 7
Bit 6
Bit 5
Bit 4
TX1ST
0
0
-
UCR2
R
0
$0037
W
TX1STR
reset ⇒
-
-
Bit 3
Bit 2
ENABLE2 ENABLE1
0
Bit 1
Bit 0
STALL2
STALL1
0
0
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 10-25. USB Control Register 2 (UCR2)
TX1STR — Clear Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a
logic 0 to the TX1STR has no effect. Reset clears this bit.
TX1ST — Transmit First Flag
This read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is set
when the USB control logic is setting the Endpoint 0 Data Receive Flag
(RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at
the end of an Endpoint 0 reception. This bit lets the firmware know that the
Endpoint 0 transmission happened before the Endpoint 0 reception. Reset
clears this bit.
1 = IN transaction occurred before SETUP/OUT.
0 = IN transaction occurred after SETUP/OUT.
ENABLE2 — Endpoint 2 Enable
This read/write bit enables Endpoint 2 and allows the USB to respond to IN
packets addressed to Endpoint 2. Reset clears this bit.
1 = Endpoint 2 is enabled and can respond to an IN token.
0 = Endpoint 2 is disabled
ENABLE1 — Endpoint 1 Enable
This read/write bit enables Endpoint 1 and allows the USB to respond to IN
packets addressed to Endpoint 1. Reset clears this bit.
1 = Endpoint 1 is enabled and can respond to an IN token.
0 = Endpoint 1 is disabled
STALL2 — Endpoint 2 Force Stall Bit
This read/write bit causes Endpoint 2 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
1 = Send STALL handshake.
0 = Default
MOTOROLA
10-24
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
STALL1 — Endpoint 1 Force Stall Bit
This read/write bit causes Endpoint 1 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
1 = Send STALL handshake
0 = Default
Freescale Semiconductor, Inc...
10.5.7 USB Status Register (USR)
USR
R
$003D
W
reset ⇒
Bit 7
Bit 6
Bit 5
Bit 4
RSEQ
SETUP
0
0
U
U
U
U
Bit 3
Bit 2
Bit 1
Bit 0
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
U
U
U
U
= Unimplemented
Figure 10-26. USB Status Register (USR)
RSEQ — Endpoint 0 Receive Sequence Bit
This read only bit indicates the type of data packet last received for Endpoint 0
(DATA0 or DATA1).
1 = DATA1 Token received in last Endpoint 0 receive
0 = DATA0 Token received in last Endpoint 0 receive
SETUP — SETUP Token Detect Bit
This read only bit indicates that a valid SETUP token has been received.
1 = Last token received for Endpoint 0 was a SETUP token
0 = Last token received for Endpoint 0 was not a SETUP token
RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet Size
These read only bits store the number of data bytes received for the last OUT
or SETUP transaction for Endpoint 0. These bits are not affected by reset.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-25
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UE0D0
R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0020
W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
to
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
UE0D7
R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0027
W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
reset ⇒
X
X
X
X
X
X
X
X
Freescale Semiconductor, Inc...
Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7)
UE0RD7 - UE0RD0 — Endpoint 0 Receive Data Buffer
These read only bits are serially loaded with OUT token or SETUP token data
received over the USB’s D+ and D- pins.
UE0TD7 - UE0TD0 — Endpoint 0 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 0.
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UE1D0
R
$0028
W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
to
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
UE1D7
R
$002F
W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
reset ⇒
X
X
X
X
X
X
X
X
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These
buffers are shared by Endpoints 1 and 2 and depend on proper configuration of
the ENDADD bit.
MOTOROLA
10-26
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
10.6
GENERAL RELEASE SPECIFICATION
USB INTERRUPTS
Freescale Semiconductor, Inc...
The USB module is capable of generating interrupts and causing the CPU to
execute the USB interrupt service routine. There are three types of USB
interrupts:
•
End of Transaction interrupts signify a completed transaction (receive or
transmit)
•
Resume interrupts signify that the USB bus is reactivated after having
been suspended
•
End of Packet interrupts signify that a low speed end of packet signal
was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for
determining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,
Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of
transaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module will
generate an interrupt by setting the RXD0F flag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the flowchart of
Figure 10-29.
SETUP transactions cannot be stalled by the USB function. A SETUP received by
a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
a SETUP interrupt are shown in Figure 10-30.
10.6.1.2 Transmit Control Endpoint 0
For a Control IN transaction directed at Endpoint 0, the USB module will generate
an interrupt by setting the TXD0F flag in the UIR0 register. The conditions
necessary for the interrupt to occur are shown in the flowchart of Figure 10-31.
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit Endpoints 1 & 2 share their interrupt flag. For an IN transaction directed
at Endpoint 1 or 2, the USB module will generate an interrupt by setting the
TXD1F flag in the UIR1 register. The conditions necessary for the interrupt to
occur are shown in the flowchart of Figure 10-32.
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-27
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
10.6.2 Resume Interrupt
The USB module will generate a USB interrupt if low speed bus activity is
detected after entering the suspend state. A transition of the USB data lines to the
non-idle state (“K” state) while in the suspend mode will set the RESUMF flag in
the UIR1 register. There is no interrupt enable bit for this interrupt source and an
interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can
only occur while the MC68HC705JB2 is in the suspend mode.
Freescale Semiconductor, Inc...
10.6.3 End of Packet Interrupt
The USB module can generate a USB interrupt upon detection of an end of
packet signal (a single ended 0) for low speed devices. Upon detection of an SE0
sequence, the USB module sets the EOPF bit and will generate an interrupt if the
EOPIE bit in the UIR1 register is set.
MOTOROLA
10-28
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Valid OUT token
received for Endpoint 0
Y
Valid DATA token
received for Endpoint 0?
Time-out
No Response
from USB function
N
Y
N
Endpoint 0 Receive Enabled?
(USBEN = 1)
No Response
from USB function
Freescale Semiconductor, Inc...
Y
N
Endpoint 0 Receive Not Stalled?
(STALL0 = 0)
Send STALL
Handshake
Y
N
Endpoint 0 Receive Ready to Receive?
(RX0E = 1) && (RXD0F = 0)
Send NAK
Handshake
Y
Accept Data
Set/clear RSEQ bit
N
Ignore transaction
No response from
USB function
Error free DATA packet?
Y
Set RXD0F to 1
Receive Control Endpoint
Interrupt Enabled?
(RXD0IE = 1)
N
Y
Valid transaction
Interrupt generated
No Interrupt
Figure 10-29. OUT Token Data Flow for Receive Endpoint 0
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-29
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Valid SETUP token
received for Endpoint 0
Y
N
Endpoint 0 Receive Enabled?
(USBEN = 1)
No Response
from USB function
Y
N
Freescale Semiconductor, Inc...
Endpoint 0 Receive Ready to Receive?
(RX0E = 1) && (RXD0F = 0)
No Response
from USB function
Y
N
STALL0 = 0?
Clear STALL0 bit
Accept Data
set/clear RSEQ bit
Set SETUP to 1
Y
Ignore transaction
No response from
USB function
N
Error free DATA packet?
Y
Set RXD0F to 1
Y
Receive Control Endpoint
Interrupt Enabled?
(RXD0IE = 1)
N
Y
No Interrupt
Valid transaction
Interrupt generated
Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0
MOTOROLA
10-30
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Valid IN token
received for Endpoint 0
Y
N
Transmit Endpoint Enabled?
(USBEN = 1)
No Response
from USB function
Y
Freescale Semiconductor, Inc...
Transmit Endpoint not Stalled by firmware?
(STALL0 = 0)
N
Send STALL
Handshake
Y
N
Transmit Endpoint ready to Transfer?
(TX0E = 1) && (TXD0F = 0)
Send NAK
Handshake
Y
Send DATA
Data PID set by T0SEQ
N
ACK received and no
Time-out condition occur?
No Response
from USB function
Y
Set TXD0F to 1
Transmit Endpoint
Interrupt Enabled?
(TXD0IE = 1)
N
No Interrupt
Valid transaction
Interrupt generated
Figure 10-31. IN Token Data Flow for Transmit Endpoint 0
MC68HC705JB2
REV 1.1
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10-31
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
Valid IN token
received for Endpoints 1 or 2
Transmit Endpoint Enabled?
(USBEN = 1)
N
No Response
from USB function
Y
Transmit Endpoint not Stalled by firmware?
(STALL1 & ENDP1) + (STALL2 & ENDP2)
N
Send STALL
Handshake
N
Send NAK
Handshake
Freescale Semiconductor, Inc...
Y
Transmit Endpoint ready to Transfer?
(TX1E = 1) && (TXD1F = 0) &
((ENDP2 & ENDADD) + (ENDP1 & ENDADD))
Y
Send DATA
Data PID set by T1SEQ
ACK received and no
Time-out condition occurs?
N
No Response
from USB function
Y
Set TXD1F to 1
Transmit Endpoint
Interrupt Enabled?
(TXD1IE = 1)
Valid transaction
Interrupt generated
No Interrupt
Note:
ENDP1 is Endpoint 1 directed traffic
ENDP2 is Endpoint 2 directed traffic
Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/ Endpoint 2
MOTOROLA
10-32
UNIVERSAL SERIAL BUS MODULE
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 11
EPROM
Freescale Semiconductor, Inc...
This section describes erasable programmable read-only memory (EPROM)
programming.
11.1
EPROM
The on-chip user EPROM consists of 2048 bytes of EPROM from $1600 to
$1DFF and 16 bytes of user vectors from $1FF0 to $1FFF.
The bootloader ROM and vectors are located from $1E00 to $1FEF.
12 of the user vectors, $1FF4-$1FFF, are dedicated to reset and interrupt vectors.
The four remaining locations, $1FF0-$1FF3, are reserved for test functions. The
Mask Option Register is located at $01FF.
11.2
BOOTLOADER
This program (contained in an on-chip boot ROM) handles copying of user code
from an external EPROM into the on-chip EPROM. The bootloader function does
not have to be done from an EPROM, but can be done from a host.
11.2.1 Bootloader Mode
Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is
at VTST and the PB0 pin is at logic zero. The bootloader performs one
programming pass at 1ms per byte then does a verify pass.
Table 11-1. Operation Mode Condition After Reset
RESET Pin
IRQ/VPP
PB0/TCAP
MODE
VSS to VDD
VSS to VDD
Single-Chip (Normal)
VTST
VSS
Bootloader
VTST = 2 x VDD
The user code must be a one-to-one correspondence with the internal EPROM
addresses.
MC68HC705JB2
REV 1.1
EPROM
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
11-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.3
August 28, 1998
EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control
Register located at address $3E.
Please contact Motorola for programming board availability.
11.3.1 EPROM Program Control Register (PCR)
This register is provided for programming the on-chip EPROM.
Freescale Semiconductor, Inc...
bit-7
PCR
$003E
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
MORON
ELAT
PGM
0
0
0
Read
RESERVED
Write
Reset
0
0
0
0
0
MORON – Mask Option Register ON
0 = Disable programming to Mask Option Register ($01FF)
1 = Enable programming to Mask Option Register ($01FF)
ELAT – EPROM LATch control
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming (writes
to EPROM cause address and data to be latched). EPROM is in
programming mode and cannot be read if ELAT is 1. This bit should
not be set when no programming voltage is applied to the Vpp pin.
PGM – EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT ≠ 1,
then PGM = 0.
11.3.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
MOTOROLA
11-2
EPROM
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure 11-1 shows the flow required to successfully program the EPROM.
Freescale Semiconductor, Inc...
START
ELAT=1
Write EPROM byte
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write
additional
byte?
N
END
Figure 11-1. EPROM Programming Sequence
MC68HC705JB2
REV 1.1
EPROM
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
11-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
11.4
August 28, 1998
MASK OPTION REGISTER (MOR), $01FF
The Mask Option Register (MOR) contains programmable EPROM bits to control
mask options. In order to program this register the MORON bit in PCR need to be
set to “1” before doing the EPROM programming process.
bit-7
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
IRQTRIG
PULLREN
PAINTEN
OSCDLY
LVREN
1
1
1
1
1
Read
MOR
$01FF
Write
Erased
0
0
0
Freescale Semiconductor, Inc...
Reset
Unaffected
IRQTRIG – IRQ, PA0-PA3 Interrupt Options
1 = Edge-trigger only
0 = Edge-and-level-triggered
PULLREN – Port A and B Pullup/Pulldown Options
1 = Connected
0 = Disconnected
PAINTEN – PA0-PA3 External Interrupt Options
1 = Disabled
0 = Enabled
OSCDLY – Oscillator Delay Option
1 = 128 internal clock cycles
0 = 4064 internal clock cycles
LVREN – LVR Option
1 = Enabled
0 = Disabled
MOTOROLA
11-4
EPROM
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 12
INSTRUCTION SET
This section describes the addressing modes and instruction types.
Freescale Semiconductor, Inc...
12.1
ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, No Offset
•
Indexed, 8-Bit Offset
•
Indexed, 16-Bit Offset
•
Relative
12.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
12.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
MC68HC705JB2
REV 1.1
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
12.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
Freescale Semiconductor, Inc...
12.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
12.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
12.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
MOTOROLA
12-2
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
12.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Freescale Semiconductor, Inc...
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
12.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
12.1.9 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
MC68HC705JB2
REV 1.1
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
12.1.10 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Freescale Semiconductor, Inc...
Instruction
MOTOROLA
12-4
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
12.1.11 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
12.1.12 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
MC68HC705JB2
REV 1.1
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
third byte to the program counter if the specified bit tests true. The bit to be tested
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Freescale Semiconductor, Inc...
Instruction
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
Branch Never
BRN
Branch if Bit Set
MOTOROLA
12-6
Mnemonic
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
12.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Freescale Semiconductor, Inc...
Instruction
Clear Bit
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
12.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
MC68HC705JB2
REV 1.1
Mnemonic
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
12.1.15 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
—
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
↕
A ← (A) + (M)
Add without Carry
↕
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
—
— —
0
b7
—
↕
↕
↕
↕
↕
↕
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
— —
↕
↕
↕
↕
b0
C
b7
— —
↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 12-6. Instruction Set Summary
— — — — —
ff
ff
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
MOTOROLA
12-8
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
Address
Mode
Opcode
Operand
Cycles
Table 12-6. Instruction Set Summary (Continued)
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Freescale Semiconductor, Inc...
Source
Form
Operation
Description
Effect on
CCR
H I N Z C
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— —
—
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
REL
21
rr
3
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
Branch Never
MC68HC705JB2
REV 1.1
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? Mn = 1
PC ← (PC) + 2 + rel ? 1 = 0
↕
↕
— — — —
— — — —
— — — — —
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
CLC
Clear Carry Bit
CLI
Clear Interrupt Mask
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
MOTOROLA
12-10
Cycles
BSR rel
Branch to
Subroutine
COM opr
COMA
COMX
COM opr,X
COM ,X
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
C←0
— — — — 0
INH
98
I←0
— 0 — — —
INH
9A
— — 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
—
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
Mn ← 1
Set Bit n
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
10
12
14
16
18
1A
1C
1E
Effect on
CCR
H I N Z C
BSET n opr
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Description
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
— —
— —
— —
— —
— —
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
—
Address
Mode
Operation
Operand
Freescale Semiconductor, Inc...
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
Freescale Semiconductor, Inc...
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
— —
—
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
—
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
— —
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
X ← (M)
C
0
b7
Negate Byte
(Two’s Complement)
NOP
No Operation
MC68HC705JB2
REV 1.1
— —
↕
↕
↕
↕
↕
↕
↕
—
b0
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— —
↕
— — 0
↕
↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— —
↕
↕
↕
— — — — —
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
INH
42
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
5
3
3
6
5
2
MOTOROLA
12-11
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
August 28, 1998
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
—
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
2
INH
80
9
— — — — —
INH
81
6
— —
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
Effect on
CCR
Description
H I N Z C
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
— —
C
— —
b7
↕
↕
↕
↕
b0
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
— —
↕
↕
↕
b0
— — — — —
↕
↕
↕
↕
↕
ff
ff
Cycles
Opcode
Freescale Semiconductor, Inc...
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— —
—
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
MOTOROLA
12-12
Store Index
Register In Memory
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
↕
↕
↕
↕
↕
↕
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
—
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
2
3
4
5
4
3
Subtract Memory
Byte from
Accumulator
Software Interrupt
TAX
Transfer
Accumulator to
Index Register
A ← (A) – (M)
INH
83
10
— — — — —
INH
97
2
— —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock
and Enable
Interrupts
↕
↕
↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
X ← (A)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
(M) – $00
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
MC68HC705JB2
REV 1.1
— —
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕
↕
—
dd
ff
Cycles
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
Freescale Semiconductor, Inc...
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-13
MSB
LSB
0
Table 12-7. Opcode Map
INH
INH
IMM
DIR
Control
IX
2
2
2
MOTOROLA
12-14
2
2
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
2
2
IMM 2
LDA
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
6
2
IMM 2
ADD
BSR
INSTRUCTION SET
0
3
IX2
IX1
IX
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
EXT
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
IX1 1
5
IX1 1
4
IX1 1
4
AND
BIT
LDA
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
JSR
LDX
STX
DIR Number of Bytes/Addressing Mode
4
F
IX2 2
5
IX2 2
5
IX2 2
6
IX2 2
5
IX2 2
7
IX2 2
5
IX2 2
6
IX2 2
SUB
E
5
D
STX
LDX
JSR
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
BIT
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
IX2 2
5
SUB
C
SUB
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
4
Register/Memory
DIR 3
3
DIR 3
3
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
EXT 3
STX
5 Number of Cycles
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
BIT
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
DIR 3
3
SUB
IX1
2
INH
Read-Modify-Write
INH
6
RTS
INH
10
INH
SWI
INH
2
CLC
INH 2
2
INH 2
2
SEC
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
REL 2
2
3
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
MSB
0
LSB
2
INH 2
2
INH
TXA
SUB
INH
2
DIR
1
9
REL
5
IX 1
5
IX
5
IX
5
RTI
DIR
5
DIR
Bit Manipulation Branch
COM
LSR
ROR
ASR
IX 1
B
IX1 1
6
6
IX1 1
IX1 1
6
COM
LSR
ROR
NEG
A
6
9
3
3
NEG
8
3
7
RORX
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
6
3
11
COMA
INH
3
MUL
INH 1
NEGA
5
5
1
DIR 1
NEG
5
INH 1
3
INH 1
LSRA
3
IX1 1
6
ASR
IX
5
IX
5
1
1
1
1
2
1
STOP
IX
5
1
INH 1
WAIT
INH
2
IX
5
IX
4
IX
5
IX 1
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
ASL/LSL
IX1 1
6
IX1 1
6
ROL
IX1 1
6
IX1 1
5
6
IX1 1
DEC
INC
TST
IX1 1
6
IX1 1
CLR
2
4
3
2
3
BRA
COM
DIR 1
5
DIR 1
LSR
RORA
INH 2
3
ASRX
INH 2
3
INH 2
3
ROLX
INH 2
3
3
INH 2
DECX
INCX
INH 2
3
TSTX
INH 2
3
INH 2
CLRX
TAX
2
5
REL 2
3
BRN
REL
3
BHI
REL
3
BLS
REL 2
3
BCC
5
INH 1
3
ASRA
INH 1
3
INH 1
3
ROLA
INH 1
3
3
INH 1
DECA
INCA
INH 1
3
TSTA
INH 1
3
INH 1
CLRA
1
1
BSET0
DIR 2
5
BCLR0
DIR 2
5
BSET1
DIR 2
5
BCLR1
DIR 2
5
BSET2
REL 2
3
ROR
DIR 1
5
ASR
DIR 1
5
5
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET3
DIR 2
5
BCLR3
DIR 2
5
BSET4
DIR 2
5
BCLR4
DIR 2
5
BSET5
DIR 2
5
BCLR5
DIR 2
5
BSET6
DIR 2
5
BCLR6
DIR 2
5
BSET7
DIR 2
5
DIR 2
BCLR7
1
0
5
BRSET0
3
DIR 2
5
BRCLR0
3
DIR 2
5
BRSET1
3
DIR 2
5
BRCLR1
3
DIR 2
5
BRSET2
3
DIR 2
5
BRCLR2
3
DIR 2
5
BRSET3
3
DIR 2
5
BRCLR3
3
DIR 2
5
BRSET4
3
DIR 2
5
BRCLR4
3
DIR 2
5
BRSET5
3
DIR 2
5
BRCLR5
3
DIR 2
5
BRSET6
3
DIR 2
5
BRCLR6
3
DIR 2
5
BRSET7
3
DIR 2
5
DIR 2
BRCLR7
3
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
3
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
2
IX
5
IX
3
IX
4
IX
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
For More Information On This Product,
Go to: www.freescale.com
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 13
ELECTRICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
13.1
MAXIMUM RATINGS
Table 13-1. Maximum Ratings
(Voltages referenced to VSS)
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3 to VDD +0.3
V
EPROM Programming Voltage
VPP
15
V
I
–25
mA
TA
TL to TH
0 to +70
–40 to +85
°C
TSTG
–65 to +150
°C
Current Drain Per Pin Excluding PB1, PB2, VDD and VSS
Operating Temperature Range
(Standard)
(Extended)
Storage Temperature Range
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to
this high-impedance circuit. For proper operation, it is recommended that VIN and
VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of
operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VDD).
13.2
THERMAL CHARACTERISTICS
Table 13-2. Thermal Characteristics
Characteristic
Thermal Resistance
20-Pin PDIP
20-Pin SOIC
MC68HC705JB2
REV 1.1
Symbol
Value
Unit
θ JA
θ JA
68
91
°C/W
°C/W
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
13-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.3
August 28, 1998
DC ELECTRICAL CHARACTERISTICS
Table 13-3. DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
ILoad = 10.0 µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILoad =–0.8 mA) PA0-5, PB0
VOH
VDD –0.8
—
—
V
VOL
—
—
—
—
—
—
0.4
0.4
0.5
Input High Voltage
PA0-7, PB0-2, IRQ, RESET, OSC1
VIH
0.7×VDD
—
VDD
V
Input Low Voltage
PA0-7, PB0-2, IRQ, RESET, OSC1
VIL
VSS
—
0.2×VDD
V
10
2.3
8.8
1.0
12
4.0
10
2.0
mA
mA
mA
mA
200
300
250
400
µA
µA
Output Low Voltage
(ILoad = 1.6 mA) PA0-3, PB0
(ILoad = 8.0 mA) PA4-7
(ILoad = 25.0 mA) PB1, PB2 (note 8)
Supply Current (see Notes)
Run (USB active)
Run (USB suspended)
Wait (USB active)
Wait (USB suspended)
Stop
IDD
—
25°C
0°C to +70°C
V
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-2
(without individual pulldown/up activated)
IZ
—
—
±10
µA
Input Pulldown Current
PA0-7, PB0
(with individual pulldown activated)
IIL
50
100
200
µA
Input Current
RESET, IRQ, OSC1
Iin
—
—
±1
µA
Cout
Cin
—
—
—
—
12
8
pF
pF
ROSC
1.0
2.0
3.0
MΩ
RPULL-UP
25
100
200
KΩ
LVR Inhibit (see note 9)
VLVRI
3.0
3.3
3.6
V
LVR Recover (see note 9)
VLVRR
3.1
3.5
3.7
V
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, OSC2
Crystal/Ceramic Resonator Oscillator Mode
Internal Resistor
OSC1 to OSC2
Pullup Resistor
PB1, PB2
MOTOROLA
13-2
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25 °C only.
3. Wait IDD: Only timer system (MFT) active.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (f OSC = 6.0 MHz), all inputs 0.2 VDC from
rail; no DC loads, less than 50pF on all outputs, C L = 20 pF on OSC2.
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD-0.2 VDC.
6. Stop IDD measured with OSC1 = VSS.
7. Wait IDD is affected linearly by the OSC2 capacitance.
8. TA = 0°C to +40°C.
9. These are preliminary specifications.
Freescale Semiconductor, Inc...
13.4
USB DC ELECTRICAL CHARACTERISTICS
Table 13-4. USB DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic
Symbol
Conditions
Min
Hi-Z State Data LIne Leakage
ILO
0V<Vin<3.3V
–10
Differential Input Sensitivity
VDI
|(D+)–(D–)|,
and Figure 12-1
0.2
Differential Common Mode
Range
VCM
Includes VDI
range
0.8
2.5
V
Single Ended Receiver
Threshold
VSE
0.8
2.0
V
Static Output Low
VOL
RL of 1.5k to
3.6V
0.3
V
Static Output High
VOH
RL of 15k to
GND
2.8
3.6
V
3.3V External Reference Pin
V3.3
IL=200µA
3.0
3.6
V
MC68HC705JB2
REV 1.1
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
Typ
Max
Unit
+10
µA
V
3.3
MOTOROLA
13-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.5
August 28, 1998
USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS
Table 13-5. USB Low Speed Source Electrical Characteristics
Parameter
Symbol
Transition time:
Rise Time
TR
Freescale Semiconductor, Inc...
Fall Time
TF
Rise/Fall Time Matching
TRFM
Output Signal Crossover
Voltage
VCRS
Conditions
(Notes 1,2,3)
Notes 4, 5, 8
CL=50pF
CL=350pF
CL=50pF
CL=350pF
TR/TF
Min
Typ
Max
75
Unit
300
ns
ns
ns
ns
80
120
%
1.3
2.0
V
1.5225
656.8
Mbs
ns
300
75
1.4775
676.8
1.500
666.0
TDRATE
1.5Mbs ±1.5%
Source Differential Driver Jitter
To Next Transition
For Paired Transitions
TUDJ1
TUDJ2
CL=350pF
Notes 6,7 and
Figure 12-2
–25
–10
25
10
ns
ns
Receiver Data Jitter Tolerance
To Next Transition
For Paired Transitions
TDJR1
TDJR2
CL=350pF
Notes 7 and
Figure 12-4
–75
–45
75
45
ns
ns
Low Speed Data Rate
Source EOP Width
TEOPT
Note 7 and
Figure 12-3
1.25
1.50
µs
Differential to EOP Transition
Skew
TDEOP
Note 7 and
Figure 12-3
–40
100
ns
Receiver EOP Width
Must Reject as EOP
Must Accept
TEOPR1
TEOPR2
Note 7 and
Figure 12-3
330
675
ns
ns
NOTES:
1. All voltages measured from local ground, unless otherwise specified.
2. All timings use a capacitive load of 50pF, unless otherwise specified.
3. Low speed timings have a 1.5k pull-up to 2.8V on the D- data line.
4. Measured from 10% to 90% of the data signal.
5. The rising and falling edges should be smooth transitional (monotonic).
6. Timing differences between the differential data signals.
7. Measured at crossover point of differential data signals.
8. Capacitive loading includes 50pF of tester capacitance.
MOTOROLA
13-4
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
13.6
GENERAL RELEASE SPECIFICATION
CONTROL TIMING
Table 13-6. Control Timing
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Units
Frequency of Operation
Crystal Oscillator Option
External Clock Source
fOSC
fOSC
—
DC
6
6
MHz
MHz
Internal Operating Frequency
Crystal Oscillator (fOSC ÷ 2)
External Clock (fOSC ÷ 2)
fOP
fOP
—
DC
3
3
MHz
MHz
Cycle Time (1/fOP)
tCYC
330
—
ns
RESET Pulse Width Low
tRL
1.5
—
tCYC
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
0.5
—
tCYC
IRQ Interrupt Pulse Period
tILIL
note 1
—
tCYC
PA0 to PA3, Interrupt Pulse Width High
(Edge-Triggered)
tIHIL
0.5
—
tCYC
PA0 to PA3, Interrupt Pulse Period
tIHIH
note 1
—
tCYC
tOH, tOL
—
—
ns
tSLOW
—
—
ns
OSC1 Pulse Width
Output High to Low Transition Period on PB1 (note 3)
1. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus
19 tCYC.
2. Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C)
3. tslow is a parameter dependent on fOSC and loading. Typical value of tslow is TENTATIVELY set at 170 ns with minimal value of
130ns and maximal value of 185ns under the SIMULATION conditions that f OSC is 6.0 MHz and slow output transition feature is
enabled. Capacitive loadings of 50pF on PB1-PB2, are assumed. Actual transition time will be specified to replace the TBDs when
enough characterization has been done on various wafers from different lots. The values listed here represent data off simulation
runs under the specified conditions. Under no circumstances should they be treated as the final specification.
13.7
EPROM PROGRAMMING SPECIFICATIONS
Table 13-7. EPROM Programming Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
VPP
10
12
15
V
IPP
—
3
—
mA
tEPGM
1
4
—
ms
Programming Voltage
IRQ/VPP
Programming Current
IRQ/VPP
Programming Time
per byte
MC68HC705JB2
REV 1.1
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
13-5
Freescale Semiconductor, Inc.
August 28, 1998
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
MOTOROLA
13-6
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc.
August 28, 1998
GENERAL RELEASE SPECIFICATION
SECTION 14
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the two available packages
for MC68HC705JB2: the 20-Pin PDIP and 20-Pin SOIC.
Freescale Semiconductor, Inc...
14.1
20-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
0.25 (0.010)
20 PL
0.25 (0.010)
20 PL
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
Figure 14-1. 20-Pin PDIP Mechanical Dimensions
MC68HC705JB2
REV 1.1
MECHANICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
14-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
14.2
August 28, 1998
20-PIN SURFACE-MOUNT SMALL OUTLINE PACKAGE (SOIC)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
Freescale Semiconductor, Inc...
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
Figure 14-2. 20-Pin SOIC Mechanical Dimensions
MOTOROLA
14-2
MECHANICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
MC68HC705JB2
REV 1.1
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-800-441-2447 or 1-303-675-2140
JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 03-5487-8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MfaxTM, Motorola Fax Back System: [email protected]; http://sps.motorola.com/mfax/; TOUCHTONE 1-602-244-6609;
US and Canada ONLY 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1998
For More Information On This Product,
Go to: www.freescale.com