Hot Swap Controller and Digital Power Monitor with Convert Pin ADM1175 FEATURES FUNCTIONAL BLOCK DIAGRAM ADM1175-1 CONV MUX V VCC 0 SDA 12-BIT ADC I I2C 1 A SCL ADR SENSE CURRENT SENSE AMPLIFIER FET DRIVE CONTROLLER ON GATE 1.3V UV COMPARATOR 05647-001 Allows safe board insertion and removal from a live backplane Controls supply voltages from 3.15 V to 16.5 V Precision current sense amplifier Precision voltage input 12-bit ADC for current and voltage readback Charge pumped gate drive for external N-channel FET Adjustable analog current limit with circuit breaker ±3% accurate hot swap current limit level Fast response limits peak fault current Automatic retry or latch-off on current fault Programmable hot swap timing via TIMER pin Active-high and active-low ON/ONB pin options Convert start pin (CONV) I2C® fast mode-compliant interface (400 kHz maximum) 10-lead MSOP TIMER GND Figure 1. APPLICATIONS Power monitoring/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers 3.15V TO 16.5V RSENSE VCC N-CHANNEL FET SENSE CONTROLLER GATE The ADM1175 is an integrated hot swap controller and current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C interface. An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC pin and the SENSE pin. The ADM1175 limits the current through this resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage (and, therefore, the inrush current) is kept below a preset maximum. The ADM1175 protects the external FET by limiting the time that it spends with maximum current running through it. This current limit period is set by the choice of capacitor attached to the TIMER pin. Additionally, the device provides protection from overcurrent events that may occur once the hot swap event is complete. In the case of a short-circuit event, the current in the sense resistor exceeds an overcurrent trip threshold, and the FET is switched off immediately by pulling down the GATE pin. ADM1175-1 SDA SCL ON CONV P = VI SDA SCL CONV TIMER GND ADR 05647-002 GENERAL DESCRIPTION Figure 2. Applications Diagram A 12-bit ADC can measure the current seen in the sense resistor, as well as the supply voltage on the VCC pin. An industry-standard I2C interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by an I2C command or via the convert (CONV) pin. The CONV pin is especially useful for synchronizing reads on multiple ADM1175 devices. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever it is required. Up to four unique I2C addresses can be created, depending on the way the ADR pin is connected. The ADM1175 is packaged in a 10-lead MSOP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADM1175 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Overview of the Hot Swap Function............................................ 13 Undervoltage Lockout ............................................................... 13 ON/ONB Function..................................................................... 13 TIMER Function ........................................................................ 13 GATE and TIMER Functions During a Hot Swap ................ 14 Hot Swap Retry Cycle on the ADM1175-1 and the ADM1175-3 ................................................................................ 15 Voltage and Current Readback ..................................................... 16 Serial Bus Interface..................................................................... 16 Identifying the ADM1175 on the I2C Bus............................... 16 General I2C Timing.................................................................... 16 Write and Read Operations ...................................................... 18 Quick Command........................................................................ 18 Write Command Byte ................................................................ 18 Write Extended Byte .................................................................. 19 Read Voltage and/or Current Data Bytes ................................ 20 Applications Waveforms................................................................ 22 Kelvin Sense Resistor Connection ........................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 Calculating Current Limits and Fault Current Limit Time .. 14 Initial Timing Cycle ................................................................... 14 REVISION HISTORY 9/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADM1175 SPECIFICATIONS VCC = 3.15 V to 16.5 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted. Table 1. Parameter VCC PIN Operating Voltage Range, VVCC Supply Current, ICC Undervoltage Lockout, VUVLO Undervoltage Lockout Hysteresis, VUVLOHYST ON/ONB PIN Input Current, IINON Rising Threshold, VONTH Trip Threshold Hysteresis, VONHYST Glitch Filter Time CONV PIN Input Current, IINCONV Min Typ 3.15 1.7 2.8 80 −100 −2 1.26 35 1.3 50 3 −1 Trip Threshold Low, VCONVL Trip Threshold High, VCONVH SENSE PIN Input Leakage, ISENSE Overcurrent Fault Timing Threshold, VOCTIM Overcurrent Limit Threshold, VLIM Pull-Up Current Pull-Down Current TIMER PIN Pull-Up Current (Power On Reset), ITIMERUPPOR Pull-Up Current (Fault Mode), ITIMERUPFAULT Pull-Down Current (Retry Mode), ITIMERDNRETRY Pull-Down Current, ITIMERDN Trip Threshold High, VTIMERH Trip Threshold Low, VTIMERL ADR PIN Set Address to 00, VADRLOWV Set Address to 01, RADRLOWZ Unit 16.5 2.5 V mA V mV +100 nA +2 1.34 65 μA V mV μs +1 μA 1.2 1.4 −1 92 97 Conditions VCC rising ON/ONB < 1.5 V ON/ONB rising VCONV(MAX) = 3.6 V V V 100 Fast Overcurrent Trip Threshold, VOCFAST GATE PIN Drive Voltage, VGATE Max +1 μA mV 103 mV 115 mV VSENSE = VVCC VOCTRIM = (VVCC − VSENSE), fault timing starts on the TIMER pin VLIM = (VVCC − VSENSE), closed-loop regulation to a current limit VOCFAST = (VVCC − VSENSE), gate pull-down current turned on 3 9 7 8 6 11 10 12.5 1.5 5 7 9 13 13 17 V V V μA mA mA mA VGATE − VVCC, VVCC = 3.15 V VGATE − VVCC, VVCC = 5 V VGATE − VVCC, VVCC = 16.5 V VGATE = 0 V VGATE = 3 V, VVCC = 3.15 V VGATE = 3 V, VVCC = 5 V VGATE = 3 V, VVCC = 16.5 V −3.5 −40 −5 −60 2 −6.5 −80 3 μA μA μA 1.26 0.175 100 1.3 0.2 1.34 0.225 μA V V Initial cycle, VTIMER = 1 V During current fault, VTIMER = 1 V After current fault and during a cool-down period on a retry device, VTIMER = 1 V Normal operation, VTIMER = 1 V TIMER rising TIMER falling 0 135 150 0.8 165 V kΩ +1 μA 5.5 10 V μA μA Set Address to 10, IADRHIGHZ −1 Set Address to 11, VADRHIGHV Input Current for 11 Decode, IADRLOW Input Current for 00 Decode, IADRHIGH 2 −40 3 −22 Rev. 0 | Page 3 of 24 Low state Resistor to ground state, load pin with specified resistance for 01 decode Open state, maximum load allowed on ADR pin for 10 decode High state VADR = 2.0 V to 5.5 V VADR = 0 V to 0.8 V ADM1175 Parameter MONITORING ACCURACY 1 Current Sense Absolute Accuracy Min Max Unit Conditions −1.45 +1.45 % VSENSE = 75 mV 0°C to +70°C −1.8 +1.8 % VSENSE = 50 mV 0°C to +70°C −2.8 +2.8 % VSENSE = 25 mV 0°C to +70°C −5.7 +5.7 % VSENSE = 12.5 mV 0°C to +70°C −1.5 +1.5 % VSENSE = 75 mV 0°C to +85°C −1.8 +1.8 % VSENSE = 50 mV 0°C to +85°C −2.95 +2.95 % VSENSE = 25 mV 0°C to +85°C −6.1 +6.1 % VSENSE = 12.5 mV 0°C to +85°C −1.95 +1.95 % VSENSE = 75 mV −40°C to +85°C −2.45 +2.45 % VSENSE = 50 mV −40°C to +85°C −3.85 +3.85 % VSENSE = 25 mV −40°C to +85°C −6.7 +6.7 % VSENSE = 12.5 mV −40°C to +85°C mV This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see specs for Current Sense Absolute Accuracy) 0°C to +70°C VCC = 3 V minimum (low range) 0°C to +70°C VCC = 6 V minimum (high range) 0°C to +85°C VCC = 3 V minimum (low range) 0°C to +85°C VCC = 6 V minimum (high range) −40°C to +85°C VCC = 3 V minimum (low range) −40°C to +85°C VCC = 6 V minimum (high range) These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see specs for Voltage Accuracy) VSENSE for ADC Full Scale Voltage Accuracy Typ 105.84 −0.85 +0.85 % −0.9 +0.9 % −0.85 +0.85 % −0.9 +0.9 % −0.9 +0.9 % −1.15 +1.15 % VCC for ADC Full Scale, Low Range (VRANGE = 1) 6.65 V VCC for ADC Full Scale, High Range (VRANGE = 0) 26.35 V I2C TIMING Low Level Input Voltage, VIL High Level Input Voltage, VIH Low Level Output Voltage on SDA, VOL Output Fall Time on SDA from VIHMIN to VILMAX Maximum Width of Spikes Suppressed by Input Filtering on SDA and SCL Pins Input Current, II, on SDA/SCL When Not Driving Out a Logic Low Input Capacitance on SDA/SCL SCL Clock Frequency, fSCL Low Period of the SCL Clock High Period of the SCL Clock 0.3 VBUS 20 + 0.1 CB 50 0.4 250 V V V ns 250 ns −10 +10 μA 0.7 VBUS 5 400 600 1300 Rev. 0 | Page 4 of 24 pF kHz ns ns IOL = 3 mA CB = bus capacitance from SDA to GND ADM1175 Parameter Setup Time for a Repeated Start Condition, tSU;STA SDA Output Data Hold Time, tHD;DAT Setup Time for a Stop Condition, tSU;STO Bus Free Time Between a Stop and a Start Condition, tBUF Capacitive Load for Each Bus Line 1 Min 600 100 600 1300 Typ Max Unit ns 900 ns ns ns 400 pF Conditions Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC error, and error in ADC full-scale code conversion factor. Rev. 0 | Page 5 of 24 ADM1175 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC Pin SENSE Pin TIMER Pin ON/ONB Pin CONV Pin GATE Pin SDA Pin, SCL Pin ADR Pin Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Table 3. Thermal Resistance Rating 20 V 20 V −0.3 V to +6 V −0.3 V to +20 V −0.3 V to +6 V 30 V −0.3 V to +7 V −0.3 V to +6 V −65°C to +125°C −40°C to +85°C 300°C 150°C Package Type 10-Lead MSOP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 θJA 137.5 Unit °C/W ADM1175 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 GATE ADM1175 9 CONV ON/ONB 3 TOP VIEW (Not to Scale) 8 ADR 7 SDA 6 SCL GND 4 TIMER 5 05647-003 VCC 1 SENSE 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 SENSE 3 ON/ONB 4 5 GND TIMER 6 7 8 SCL SDA ADR 9 CONV 10 GATE Description Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage lockout (UVLO) circuit resets the ADM1175 when a low supply voltage is detected. Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current limit. The hot swap operation of the ADM1175 controls the external FET gate to maintain the (VVCC − VSENSE) voltage at 100 mV or below. Undervoltage or Overvoltage Input Pin. This pin is active high on the ADM1175-1 and ADM1175-2 and active-low on the ADM1175-3 and ADM1175-4. An internal ON comparator has a trip threshold of 1.3 V, and the output of this comparator is used as an enable for the hot swap operation. For the ON pin variants with an external resistor divider from VCC to GND, this pin can be used to enable the hot swap operation on a specific voltage on VCC, giving an undervoltage function. Similarly, for the ONB pin variants, an external resistor divider can be used to create an overvoltage function, where the divider sets a voltage on VCC at which the hot swap operation is switched off, pulling the GATE to ground. Chip Ground Pin. Timer Pin. An external capacitor, CTIMER, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay. The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection with an external Zener can be used to force this pin high. I2C Clock Pin. Open-drain input requires an external resistive pull-up. I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up. I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four different I2C addresses. Convert Start Pin. A high level on this pin enables an ADC conversion. The state of an internal control register, which is set through the I2C interface, configures the part to convert current only, voltage only, or both channels when the convert pin is asserted. GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by modulating the GATE pin. Rev. 0 | Page 7 of 24 ADM1175 2.0 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 0.8 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 2 4 6 8 10 12 14 16 18 VCC (V) 0 –40 10 10 DRIVE VOLTAGE (V) 40 60 80 8 6 4 5V VCC 8 3.15V VCC 6 4 2 2 4 6 8 10 12 14 16 18 VCC (V) 0 –40 05647-029 0 –2 –2 –4 –4 IGATE (µA) 0 –6 –8 –12 –12 10 12 14 16 VCC (V) 18 –14 –40 05647-027 8 60 80 –8 –10 6 40 –6 –10 4 20 Figure 8. Drive Voltage (VGATE − VCC) vs. Temperature 0 2 0 TEMPERATURE (°C) Figure 5. Drive Voltage (VGATE − VCC) vs. Supply Voltage 0 –20 05647-030 DRIVE VOLTAGE (V) 12 2 IGATE (µA) 20 Figure 7. Supply Current vs. Temperature (Gate On) 12 –14 0 TEMPERATURE (°C) Figure 4. Supply Current vs. Supply Voltage 0 –20 –20 0 20 40 60 TEMPERATURE (°C) Figure 6. Gate Pull-Up Current vs. Supply Voltage Figure 9. Gate Pull-Up Current vs. Temperature Rev. 0 | Page 8 of 24 80 05647-028 0 05647-022 ICC (mA) 2.0 05647-021 ICC (mA) TYPICAL PERFORMANCE CHARACTERISTICS ADM1175 12 2.0 1.8 10 TIMER THRESHOLD (V) 1.6 6 4 1.4 HIGH 1.2 1.0 0.8 0.6 0.4 LOW 0.2 0 2 4 6 8 10 12 14 16 18 VCC (V) 0 05647-031 0 0 6 8 10 12 14 16 18 Figure 13. Timer Threshold vs. Supply Voltage 2.0 2 1.8 TIMER HIGH THRESHOLD (V) 0 –2 –4 IGATE (µA) 4 VCC (V) Figure 10. Gate Pull-Down Current vs. VCC at VGATE = 5 V –6 –8 –10 1.6 HIGH 1.4 1.2 1.0 0.8 0.6 0.4 LOW –12 0.2 0 2 4 6 8 10 12 14 16 VGATE (V) 0 –40 05647-040 –14 2 05647-038 2 –20 0 20 40 60 05647-039 IGATE (mA) 8 80 TEMPERATURE (°C) Figure 14. Timer Threshold vs. Temperature Figure 11. Gate Pull-Up Current vs. Gate Voltage at VCC = 5 V 100 20 90 VCC = 12V GATE ON TIME (ms) 80 10 VCC = 5V 5 60 50 40 30 0 5 05647-050 0 70 20 VCC = 3V 10 10 15 20 VGATE (V) 25 05647-043 IGATE (mA) 15 Figure 12. Gate Pull-Down Current vs. Gate Voltage 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 CTIMER (µF) Figure 15. Current Limit On Time vs. Timer Capacitance Rev. 0 | Page 9 of 24 5.0 0 –1 –1 –2 –2 –3 –4 –4 –5 –5 2 4 6 8 10 12 14 16 18 VCC (V) –6 –40 –10 –20 –20 –30 –30 ITIMER (µA) –10 –40 –50 –60 –60 –70 –70 4 6 8 10 12 14 16 18 VCC (V) –80 –40 2.5 2.5 2.0 2.0 ITIMER (µA) 3.0 1.5 1.0 0.5 0.5 6 8 10 VCC (V) 12 14 16 18 0 –40 05647-036 4 –20 0 20 40 60 80 1.5 1.0 2 80 Figure 20. Timer Pull-Up Current (C. B. Delay) vs. Temperature 3.0 0 60 TEMPERATURE (°C) Figure 17. Timer Pull-Up Current (C. B. Delay) vs. Supply Voltage 0 40 –40 –50 05647-034 ITIMER (µA) 0 2 20 Figure 19. Timer Pull-Up Current (Initial Cycle) vs. Temperature 0 0 0 TEMPERATURE (°C) Figure 16.Timer Pull-Up Current (Initial Cycle) vs. Supply Voltage –80 –20 05647-035 0 Figure 18. Timer Pull-Down Current (Cool-Off Cycle) vs. Supply Voltage –20 0 20 40 TEMPERATURE (°C) 60 80 05647-037 –6 ITIMER (µA) –3 05647-033 ITIMER (µA) 0 05647-032 ITIMER (µA) ADM1175 Figure 21. Timer Pull-Down Current (Cool-Off Cycle) vs. Temperature Rev. 0 | Page 10 of 24 ADM1175 1000 120 900 HITS PER CODE (1000 READS) 115 110 100 95 90 85 4 6 8 10 12 14 16 18 400 300 200 0 2046 2047 2048 2049 2050 CODE Figure 22. Circuit Breaker Limit Voltage vs. Supply Voltage Figure 25. ADC Noise, Current Channel, Midcode Input, 1000 Reads 1000 110 108 900 VOCFAST HITS PER CODE (1000 READS) 106 104 102 VLIM 100 98 VOCTIM 96 94 800 700 600 500 400 300 200 100 92 –20 0 20 40 60 0 05647-042 90 –40 80 TEMPERATURE (°C) 779 11 DECODE 10 DECODE 782 783 Figure 26. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads 01 DECODE 00 DECODE 1000 HITS PER CODE (1000 READS) 900 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 800 700 600 500 400 300 200 100 0 –30 –25 –20 –15 –10 –5 0 5 IADR (µA) 10 05647-026 0 –35 781 CODE Figure 23. VOCTIM, VLIM, VOCFAST vs. Temperature 3.2 3.0 2.8 2.6 780 05647-061 V (mV) 500 05647-060 2 VCC (V) VADR 600 100 05647-041 80 700 Figure 24. Address Pin Voltage vs. Address Pin Current for Four Addressing Options 3078 3079 3080 3081 3082 CODE Figure 27. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads Rev. 0 | Page 11 of 24 05647-062 VLIM (mV) 105 800 4 3 3 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 28. INL for ADC –4 0 500 1000 1500 2000 2500 CODE Figure 29. DNL for ADC Rev. 0 | Page 12 of 24 3000 3500 4000 05647-024 DNL (LSB) 4 05647-023 INL (LSB) ADM1175 ADM1175 OVERVIEW OF THE HOT SWAP FUNCTION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. The ADM1175 is designed to turn a circuit board supply voltage on and off in a controlled manner, allowing the circuit board to be safely inserted into or removed from a live backplane. The ADM1175 can reside either on the backplane or on the circuit board itself. The ADM1175 controls the inrush current to a fixed maximum level by modulating the gate of an external N-channel FET placed between the live supply rail and the load. This hot swap function protects the card connectors and the FET itself from damage and limits any problems that can be caused by high current loads on the live supply rail. The ADM1175 holds the GATE pin down (and, thus, the FET is held off) until a number of conditions are met. An undervoltage lockout circuit ensures that the device is provided with an adequate input supply voltage. Once the input supply voltage has been successfully detected, the device goes through an initial timing cycle to provide a delay before it attempts to hot swap. This delay ensures that the board is fully seated in the backplane before the board is powered up. Once the initial timing cycle is complete, the hot swap function is switched on under control of the ON/ONB pin. When ON/ONB is asserted (high for the ADM1175-1 and ADM1175-2, low for the ADM1175-3 and ADM1175-4), the hot swap operation starts. The ADM1175 charges up the gate of the FET to turn on the load. It continues to charge up the GATE pin until the linear current limit (set to 100 mV/RSENSE) is reached. For some combinations of low load capacitance and high current limit, this limit may not be reached before the load is fully charged up. If current limit is reached, the ADM1175 regulates the GATE pin to keep the current at this limit. For currents above the overcurrent fault timing threshold, nominally 100 mV/RSENSE, the current fault is timed by sourcing a current out to the TIMER pin. If the load becomes fully charged before the fault current limit time is reached (when the TIMER pin reaches 1.3 V), the current drops below the overcurrent fault timing threshold. The ADM1175 then charges the GATE pin higher to fully enhance the FET for lowest RON, and the TIMER pin is pulled down again. If the fault current limit time is reached before the load drops below the current limit, a fault has been detected, and the hot swap operation is aborted by pulling down on the GATE pin to turn off the FET. The ADM1175-2 and ADM1175-4 are latched off. They attempt to hot swap again only when the ON/ONB pin is deasserted and then asserted again. The ADM1175-1 and ADM1175-3 retry the hot swap operation indefinitely, keeping the FET in its safe operating area (SOA) by using the TIMER pin to time a cool-down period in between hot swap attempts. The current and voltage threshold combinations on the TIMER pin set the retry duty cycle to 3.8%. The ADM1175 is designed to operate over a range of supplies from 3.15 V to 16.5 V. UNDERVOLTAGE LOCKOUT An internal undervoltage lockout (UVLO) circuit resets the ADM1175 if the VCC supply is too low for normal operation. The UVLO has a low-to-high threshold of 2.8 V, with 80 mV hysteresis. Above 2.8 V supply voltage, the ADM1175 starts the initial timing cycle. ON/ONB FUNCTION The ADM1175-1 and ADM1175-2 have an active high ON pin. The ON pin is the input to a comparator that has a low-to-high threshold of 1.3 V, a 50 mV hysteresis, and a glitch filter of 3 μs. A low input on the ON pin turns off the hot swap operation by pulling the GATE pin to ground, turning off the external FET. The TIMER pin is also reset by turning on a pull-down current on this pin. A low-to-high transition on the ON pin starts the hot swap operation. A 10 kΩ pull-up resistor connecting the ON pin to the supply is recommended. Alternatively, an external resistor divider at the ON pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit, thereby setting a voltage level at the VCC supply, where the hot swap operation is to start. An RC filter can be added at the ON pin to increase the delay time at card insertion if the initial timing cycle delay is insufficient. The ADM1175-3 and ADM1175-4 have an active low ONB pin. This pin operates exactly as described above for the ON pin, but the polarity is reversed. This allows this pin to function as an overvoltage detector that can use the external FET as a circuit breaker for overvoltage conditions on the monitored supply. TIMER FUNCTION The TIMER pin handles several timing functions with an external capacitor, CTIMER. There are two comparator thresholds: VTIMERH (0.2 V) and VTIMERL (1.3 V). The four timing current sources are a 5 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and a 100 μA pull-down. The 100 μA pull-down is a non-ideal current source, approximating a 7 kΩ resistor below 0.4 V. These current and voltage levels, together with the value of CTIMER chosen by the user, determine the initial timing cycle time, the fault current limit time, and the hot swap retry duty cycle. Rev. 0 | Page 13 of 24 ADM1175 GATE AND TIMER FUNCTIONS DURING A HOT SWAP CALCULATING CURRENT LIMITS AND FAULT CURRENT LIMIT TIME During hot insertion of a board onto a live supply rail at VCC, the abrupt application of supply voltage charges the external FET drain/gate capacitance, which can cause an unwanted gate voltage spike. An internal circuit holds GATE low before the internal circuitry wakes up. This reduces the FET current surges substantially at insertion. The GATE pin is also held low during the initial timing cycle and until the ON pin has been taken high to start the hot swap operation. The nominal linear current limit is determined by a sense resistor connected between the VCC pin and the SENSE pin, as given by Equation 1. During hot swap operation, the GATE pin is first pulled up by a 12 μA current source. If the current through the sense resistor reaches the overcurrent fault timing threshold, VOCTIM, a pull-up current of 60 μA on the TIMER pin, is turned on, and this pin starts charging up. At a slightly higher voltage in the sense resistor, the error amplifier servos the GATE pin to maintain a constant current to the load by controlling the voltage across the sense resistor to the linear current limit, VLIM. The maximum linear fault current is given by Equation 3. A normal hot swap is complete when the board supply capacitors near full charge, and the current through the sense resistor drops to eventually reach the level of the board load current. As soon as the current drops below the overcurrent fault timing threshold, the current into the TIMER pin switches from being a 60 μA pull-up to a 100 μA pull-down. The ADM1175 then drives the GATE voltage as high as it can to fully enhance the FET and reduce RON losses to a minimum. IOCTIM(MIN) = VOCTIM(MIN)/RSENSE(MAX) = 85 mV/RSENSE(MAX) A hot swap fails if the load current does not drop below the overcurrent fault timing threshold, VOCTIM, before the TIMER pin has charged up to 1.3 V. In this case, the GATE pin is then pulled down with a 2 mA current sink. The GATE pull-down stays on until a hot swap retry starts, which can be forced by deasserting and then reasserting the ON/ONB pin. On the ADM1175-1 and ADM1175-3, the device retries automatically after a cool-down period. The ADM1175 also features a method of protection from sudden load current surges, such as a low impedance fault, when the current seen across the sense resistor may go well beyond the linear current limit. If the fast overcurrent trip threshold, VOCFAST, is exceeded, the 2 mA GATE pull-down is turned on immediately. This pulls the GATE voltage down quickly to enable the ADM1175 to limit the length of the current spike that gets through, and also to bring the current through the sense resistor back into linear regulation as quickly as possible. This process protects the backplane supply from sustained overcurrent conditions that can otherwise cause the backplane supply to droop during the overcurrent event. ILIMIT(NOM) = VLIM(NOM)/RSENSE = 100 mV/RSENSE (1) The minimum linear fault current is given by Equation 2. ILIMIT(MIN) = VLIM(MIN)/RSENSE(MAX) = 90 mV/RSENSE(MAX) ILIMIT(MAX) = VLIM(MAX)/RSENSE(MIN) = 110 mV/RSENSE(MIN) (2) (3) The power rating of the sense resistor should be rated at the maximum linear fault current level. The minimum overcurrent fault timing threshold current is given by Equation 4. (4) The maximum fast overcurrent trip threshold current is given by Equation 5. IOCFAST(MAX) = VOCFAST(MAX)/RSENSE(MIN) = 115 mV/RSENSE(MIN) (5) The fault current limit time is the time that a device spends timing an overcurrent fault, and is given by Equation 6. tFAULT ≈ 21.7 × CTIMER ms/μF (6) INITIAL TIMING CYCLE When VCC is first connected to the backplane supply, the internal supply (Time Point (1) in Figure 30) of the ADM1175 must be charged up. A very short time later (significantly less than 1 ms), the internal supply is fully up and, because the undervoltage lockout voltage has been exceeded at VCC, the device comes out of reset. During this first short reset period, the GATE pin is held down with a 25 mA pull-down current, and the TIMER pin is pulled down with a 100 μA current sink. The ADM1175 then goes through an initial timing cycle. At Time Point (2), the TIMER pin is pulled high with 5 μA. At Time Point (3), the TIMER reaches the VTIMERL threshold, and the first portion of the initial cycle ends. The 100 μA current source then pulls down the TIMER pin until it reaches 0.2 V at Time Point (4). The initial cycle delay (Time Point (2) to Time Point (4)) is related to CTIMER by Equation 7. Rev. 0 | Page 14 of 24 tINITIAL ≈ 270 × CTIMER ms/μF (7) ADM1175 (1) When the initial timing cycle terminates, the device is ready to start a hot swap operation (assuming the ON/ONB pin is asserted). In the example shown in Figure 30, the ON pin is asserted at the same time that VCC is applied, so the hot swap operation starts immediately after Time Point (4). At this point, the FET gate is charged up with a 12 μA current source. At Time Point (5), the threshold voltage of the FET is reached, and the load current begins to flow. The FET is controlled to keep the sense voltage at 100 mV (this corresponds to a maximum load current level defined by the value of RSENSE). At Time Point (6), VGATE and VOUT have reached their full potential, and the load current has settled to its nominal level. Figure 31 illustrates the situation where the ON pin is asserted after VCC is applied. (1) (2) (3)(4) (5) (2) (3)(4) (5)(6) (7) VVCC VON VTIMER VGATE VSENSE (6) VOUT INITIAL TIMING CYCLE 05647-005 VVCC Figure 31. Startup (ON Asserts After Power Is Applied) VON HOT SWAP RETRY CYCLE ON THE ADM1175-1 AND THE ADM1175-3 VTIMER With the ADM1175-1 and the ADM1175-3, the device turns off the FET after an overcurrent fault and then uses the TIMER pin to time a delay before automatically retrying to hot swap. VGATE VSENSE INITIAL TIMING CYCLE Figure 30. Startup (ON Asserts as Power Is Applied) 05647-004 VOUT As with all ADM1175 devices, on overcurrent fault is timed by charging the TIMER cap with a 60 μA pull-up current. When the TIMER pin reaches 1.3 V, the fault current limit time has been reached, and the GATE pin is pulled down. On the ADM1175-1 and the ADM1175-3, the TIMER pin is then pulled down with a 2 μA current sink. When the TIMER pin reaches 0.2 V, it automatically restarts the hot swap operation. The cool-down period is related to CTIMER by Equation 8. tCOOL ≈ 550 × CTIMER ms/μF (8) Thus, the retry duty cycle is given by Equation 9. tFAULT/(tCOOL + tFAULT ) × 100% = 3.8% Rev. 0 | Page 15 of 24 (9) ADM1175 VOLTAGE AND CURRENT READBACK In addition to providing hot swap functionality, the ADM1175 also contains the components to allow voltage and current readback over an Inter-IC (I2C) bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command or an assertion on the convert start (CONV) pin. When all conversions are complete, the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (MSB first), plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle, while the selected device waits for data to be read from it or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. SERIAL BUS INTERFACE Control of the ADM1175 is carried out via the I2C bus. This interface is compatible with I2C fast mode (400 kHz maximum). The ADM1175 is connected to this bus as a slave device, under the control of a master device. 2. IDENTIFYING THE ADM1175 ON THE I2C BUS The ADM1175 has a 7-bit serial bus slave address. When the device powers up, it does so with a default serial bus address. The five MSBs of the address are set to 11010; the two LSBs are determined by the state of the ADR pin. There are four different configurations available on the ADR pin that correspond to four different I2C addresses for the two LSBs (see Table 5). This scheme allows four ADM1175 devices to operate on a single I2C bus. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It can be an instruction, such as telling the slave device to expect a block write; or it can be a register address that tells the slave where subsequent data is to be written. Table 5. Setting I2C Addresses via the ADR Pin ADR Configuration Low State Resistor to GND Floating (Unconnected) High State Address 0xD0 0xD2 0xD4 0xD6 Because data can flow in only one direction, as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. GENERAL I2C TIMING Figure 32 and Figure 33 show timing diagrams for general read and write operations using the I2C. The I2C specification defines conditions for different types of read and write operations, which are discussed later. The general I2C protocol operates as follows: 1. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high can be interpreted as a stop signal. 3. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line SCL remains high. This indicates that a data stream follows. Rev. 0 | Page 16 of 24 When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. ADM1175 9 1 9 1 SCL 0 SDA 0 1 1 A1 1 A0 D7 R/W D6 D5 ACKNOWLEDGE BY SLAVE START BY MASTER FRAME 1 SLAVE ADDRESS 1 D4 D2 D3 D0 D1 ACKNOWLEDGE BY SLAVE FRAME 2 COMMAND CODE 1 9 9 SCL (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 ACKNOWLEDGE BY SLAVE FRAME 3 DATA BYTE D3 D2 D1 D0 ACKNOWLEDGE BY STOP BY SLAVE MASTER FRAME N DATA BYTE 05647-006 SDA (CONTINUED) Figure 32. General I2C Write Timing Diagram 9 1 9 1 SCL 0 SDA 0 1 1 A1 1 A0 D7 R/W D6 D5 D4 ACKNOWLEDGE BY SLAVE START BY MASTER FRAME 1 SLAVE ADDRESS 1 D2 D3 D0 D1 ACKNOWLEDGE BY MASTER FRAME 2 DATA BYTE 1 9 9 SCL (CONTINUED) D7 D6 D5 D4 D3 FRAME 3 DATA BYTE D2 D1 D0 D7 D6 D5 ACKNOWLEDGE BY MASTER D4 D3 FRAME N DATA BYTE D2 D1 D0 NO ACKNOWLEDGE STOP BY MASTER Figure 33. General I2C Read Timing Diagram tLOW tR tHD;STA tF SCL tHD;STA tSU;STA tHIGH tHD;DAT tSU;DAT tSU;STO tBUF P S S Figure 34. Serial Bus Timing Diagram Rev. 0 | Page 17 of 24 P 05647-008 SDA 05647-007 SDA (CONTINUED) ADM1175 WRITE COMMAND BYTE WRITE AND READ OPERATIONS The I C specification defines several protocols for different types of read and write operations. The operations used in the ADM1175 are discussed in the sections that follow. Table 6 shows the abbreviations used in the command diagrams. In the write command byte operation the master device sends a command byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. Table 6. I2C Abbreviations 2. The master sends the 7-bit slave address, followed by the write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. 4. The master sends the command byte. The command byte is identified by an MSB = 0. An MSB = 1 indicates an extended register write (see the Write Extended Byte section). QUICK COMMAND 5. The slave asserts an acknowledge on SDA. The quick command operation allows the master to check if the slave is present on the bus, as follows: 6. The master asserts a stop condition on SDA to end the transaction. Abbreviation S P R W A N 2. 3. 1 The master device asserts a start condition on SDA. The addressed slave device asserts an acknowledge on SDA. 1 2 3 SLAVE S ADDRESS W A 2 3 4 5 6 SLAVE COMMAND S ADDRESS W A A P BYTE The master sends the 7-bit slave address, followed by the write bit (low). 05647-009 1. Condition Start Stop Read Write Acknowledge No acknowledge 05647-010 2 Figure 36. Write Command Byte The seven LSBs of the command byte are used to configure and control the ADM1175. Table 7 provides details of the function of each bit. Figure 35. Quick Command Table 7. Command Byte Operations Bit Default Name Function C0 0 V_CONT C1 0 V_ONCE C2 0 I_CONT C3 0 I_ONCE C4 0 VRANGE C5 C6 0 0 N/A STATUS_RD Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1175 asserts an acknowledge and returns all 0s in the returned data. Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC conversion is complete. Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1175 asserts an acknowledge and returns all 0s in the returned data. Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until ADC conversion is complete. Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for an ADC full-scale result is 26.35 V for VRANGE = 0 and 6.65 V for VRANGE = 1. Unused. Status read. When this bit is set, the data byte read back from the ADM1175 is the STATUS byte. It contains the status of the device alerts. See Table 15 for full details of the STATUS byte. Rev. 0 | Page 18 of 24 ADM1175 WRITE EXTENDED BYTE 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address, followed by the write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. 4. The master sends the register address byte. The MSB of this byte is set to 1 to indicate an extended register write. The two LSBs indicate which of the three extended registers are to be written to (see Table 8). All other bits should be set to 0. 5. The slave asserts an acknowledge on SDA. 6. The master sends the command byte. The command byte is identified by an MSB = 0. An MSB = 1 indicates an extended register write. 7. The slave asserts an acknowledge on SDA. 8. The master asserts a stop condition on SDA to end the transaction. 1 2 3 4 5 6 7 8 SLAVE REGISTER REGISTER S ADDRESS W A ADDRESS A A P DATA 05647-011 In the write extended byte operation, the master device writes to one of the three extended registers of the slave device, as follows: Figure 37. Write Extended Byte Table 9, Table 10, and Table 11 give details of each extended register. Table 8. Extended Register Addresses A6 0 0 0 A5 0 0 0 A4 0 0 0 A3 0 0 0 A2 0 0 0 A1 0 1 1 A0 1 0 1 Extended Register ALERT_EN ALERT_TH CONTROL Table 9. ALERT_EN Register Operations Bit 0 Default 0 Name EN_ADC_OC1 1 0 EN_ADC_OC4 2 1 EN_HS_ALERT 3 0 EN_OFF_ALERT 4 0 CLEAR Function Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH register. Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the ALERT_TH register. Enabled if the hot swap has either latched off or entered a cool-down cycle because of an overcurrent event. Enables an alert if the HS operation is turned off by a transition that deasserts the ON/ONB pin or by an operation that writes the SWOFF bit high. Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These can immediately reset if the source of the alert has not been cleared or disabled with the other bits in this register. This bit self-clears to 0 after the STATUS register bits have been cleared. Table 10. ALERT_TH Register Operations Bit 7:0 Default FF Function The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit number corresponds to the top eight bits of the current channel data. Table 11. CONTROL Register Operations Bit 0 Default 0 Name SWOFF Function Forces hot swap off. Equivalent to deasserting the ON/ONB pin. Rev. 0 | Page 19 of 24 ADM1175 READ VOLTAGE AND/OR CURRENT DATA BYTES For cases where the master is reading voltage only or current only, only two data bytes are read. Step 7 and Step 8 are not required. 1 Voltage and Current Readback 2 2 3 6 7 8 9 10 B6 V10 B5 V9 B4 V8 B3 V7 B2 V6 B1 V5 B0 V4 I11 I10 I9 I8 I7 I6 I5 I4 V3 V2 V1 V0 I3 I2 I1 I0 Voltage Readback The ADM1175 digitizes voltage only. Two bytes are read out of the device in the format shown in Table 13. B1 V5 0 B0 V4 0 3 4 5 6 7 8 Figure 39. Two-Byte Read from ADM1175 Converting ADC Codes to Voltage and Current Readings The following equations can be used to convert ADC codes representing voltage and current from the ADM1175 12-bit ADC into actual voltage and current values. Voltage = (VFULLSCALE/4096) × Code Table 13. Voltage Only Readback Format B7 B6 B5 B4 B3 B2 V11 V10 V9 V8 V7 V6 V3 V2 V1 V0 0 0 2 SLAVE REGISTER REGISTER S ADDRESS R A ADDRESS A N P DATA 05647-013 1 B7 V11 Byte Contents 1 Voltage MSBs 2 Voltage LSBs 5 Figure 38. Three-Byte Read from ADM1175 Table 12. Voltage and Current Readback Format Contents Voltage MSBs Current MSBs LSBs 4 SLAVE S ADDRESS R A DATA 1 A DATA 2 A DATA 3 N P The ADM1175 digitizes both voltage and current. Three bytes are read out of the device in the format shown in Table 12. Byte 1 3 05647-012 The ADM1175 can be set up to provide information in three different ways (see the Write Command Byte section). Depending on how the device is configured, the following data can be read out of the device after a conversion (or conversions). where: VFULLSCALE = 6.65 (7:2 range) or 26.35 (14:1 range). Code is the ADC voltage code read from the device (Bit V0 to V11). Current Readback The ADM1175 digitizes current only. Two bytes are read out of the device in the format shown in Table 14. Table 14. Current Only Readback Format Byte Contents 1 Current MSBs 2 Current LSBs B7 I11 I3 B6 I10 I2 B5 B4 B3 B2 I9 I8 I7 I6 I1 I0 0 0 B1 I5 0 B0 I4 0 Current = ((IFULLSCALE/4096) × Code)/Sense Resistor where: IFULLSCALE = 105.84 mV. Code is the ADC current code read from the device (Bit I0 to Bit I11). Read Status Register The following series of events occurs when the master receives three bytes (voltage and current data) from the slave device: A single register of status data can also be read from the ADM1175. 1. The master device asserts a start condition on SDA. 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address, followed by the read bit (high). 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts an acknowledge on SDA. 3. The addressed slave device asserts an acknowledge on SDA. 4. The master receives the first data byte. 4. The master receives the status byte. 5. The master asserts acknowledge on SDA. 5. The master asserts an acknowledge on SDA. 6. The master receives the second data byte. 1 7. The master asserts an acknowledge on SDA. SLAVE S ADDRESS R A DATA 1 A 8. The master receives the third data byte. 9. The master asserts a no acknowledge on SDA. 10. The master asserts a stop condition on SDA, and the transaction ends. 3 4 5 05647-014 2 Figure 40. Status Read from ADM1175 Table 15 shows the ADM1175 status registers in detail. Note that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the ALERT_EN register (CLEAR). Rev. 0 | Page 20 of 24 ADM1175 Table 15. Status Byte Operations Bit 0 1 Name ADC_OC ADC_ALERT 2 HS_OC 3 4 HS_ALERT OFF_STATUS 5 OFF_ALERT Function An ADC-based overcurrent comparison has been detected on the last three conversions An ADC-based overcurrent trip has happened, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN register. The hot swap is off due to an analog overcurrent event. On parts that latch off, this is the same as the HS_ALERT status bit (if EN_HS_ALERT = 1). On the retry parts, this indicates the current state: a 0 can indicate that the data was read during a period when the device was retrying, or that it has successfully hot swapped by retrying after at least one overcurrent timeout. The hot swap has failed since the last time this was reset. Cleared by writing to Bit 4 of the ALERT_EN register. The state of the ON/ONB pin. Set to 1 if the input pin is deasserted. Can also be set to 1 by writing to the SWOFF bit of the CONTROL register. An alert has been caused by either the ON/ONB pin or the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register. Rev. 0 | Page 21 of 24 ADM1175 APPLICATIONS WAVEFORMS 1 1 2 2 3 3 4 CH2 1.00V CH4 10.0V M40.0ms Figure 41. Inrush Current Control into 220 μF Load (CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT) CH1 1.5A CH3 20.0V CH2 1.00V CH4 10.0V M10.0ms 05647-073 CH1 1.5A CH3 20.0V 05647-070 4 Figure 44. Overcurrent Condition During Operation (ADM1175-1 Model) (CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT) 1 1 2 2 3 3 4 CH2 1.00V CH4 10.0V M10.0ms Figure 42. Overcurrent Condition at Startup (ADM1175-1 Model) (CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT) CH1 1.5A CH3 20.0V 2 3 M20.0ms 05647-072 4 CH2 1.00V CH4 10.0V M20.0ms Figure 45. Overcurrent Condition During Operation (ADM1175-2 Model) (CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT) 1 CH1 1.5A CH3 20.0V CH2 1.00V CH4 10.0V 05647-074 CH1 1.5A CH3 20.0V 05647-071 4 Figure 43. Overcurrent Condition at Startup (ADM1175-2 Model) (CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT) Rev. 0 | Page 22 of 24 ADM1175 KELVIN SENSE RESISTOR CONNECTION SENSE RESISTOR CURRENT FLOW FROM SUPPLY CURRENT FLOW TO LOAD KELVIN SENSE TRACES VCC SENSE ADM1175 Figure 46. Kelvin Sense Connections Rev. 0 | Page 23 of 24 05647-015 When using a low value sense resistor for high current measurement, the problem of parasitic series resistance may arise. The lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. This problem can be avoided by using a Kelvin sense connection. This type of connection separates the current path through the resistor and the voltage drop across the resistor. Figure 46 shows the correct way to connect the sense resistor between the VCC pin and the SENSE pin of the ADM1175. ADM1175 OUTLINE DIMENSIONS 3.10 3.00 2.90 6 10 3.10 3.00 2.90 1 5.15 4.90 4.65 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 47. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model ADM1175-1ARMZ-R71 ADM1175-2ARMZ-R71 ADM1175-3ARMZ-R71 ADM1175-4ARMZ-R71 EVAL-ADM1175EBZ1 1 Hot Swap Retry Option Automatic Retry Version Latched Off Version Automatic Retry Version Latched Off Version ON/ONB Pin ON ON ONB ONB Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 Branding M5P M5R M5S M5T Z = Pb-free part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05647-0-9/06(0) Rev. 0 | Page 24 of 24