PERICOM PI74SSTV16857A

PI74SSTV16857
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14-Bit Registered Buffer
Product Features
Product Description
• PI74 SSTV16857 is designed for low-voltage operation,
VDD = VDDQ = 2.3V to 2.7V
• Supports SSTL_2 Class I and II specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Package available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74SSTV16857 series of logic circuits
are produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTV16857 universal bus driver is designed
for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
Logic Block Diagram
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
38
39
RESET
34
D1
48
35
VREF
R
1
CLK
V
CLK
CLK
Q1
Pericom’s PI74SSTV16857 is characterized for operation from
0° to 70°C.
D
Product Pin Configuration
TO 13 OTHER CHANNELS
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
VDD
VDDQ
VREF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Truth Table(1)
Inputs
Outputs
RESET
CLK
CLK
D
Q
L
X
X
X
L
H
↑
↓
H
H
Η
↑
↓
L
L
H
L or H
L or H
X
Q o(2)
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
↑ = Transition LOW-to-HIGH
input conditions were
↓ = Transition HIGH-to-LOW
established.
X = Irrelevant
1
Q1
1
48
D1
Q2
2
47
D2
GND
3
46
GND
VDDQ
Q3
4
45
5
44
VDD
D3
Q4
6
43
D4
Q5
7
42
D5
GND
8
41
D6
VDDQ
Q6
9
48-Pin 40
A, K 39
10
D7
CLK
Q7
11
38
CLK
VDDQ
GND
12
37
13
36
VDD
GND
Q8
14
35
Q9
15
34
VREF
RESET
VDDQ
GND
16
33
D8
17
32
D9
Q10
18
31
D10
Q11
19
30
D11
Q12
20
29
D12
VDDQ
GND
21
28
22
27
VDD
GND
Q13
23
26
D13
Q14
24
25
D14
PS8460C
06/04/01
PI74SSTV16857
14-Bit
Registered
Buffer
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Ite m
Symbol/Conditions
Ratings
Units
Tstg
–65 to 150
°C
Supply voltage
VDD or VDDQ
–0.5 to 3.6
Input voltage(1)
VI
–0.5 to VDD +0.5
VO
–0.5 to VDDQ +0.5
Input clamp current
IIK, VI<0
–50
O utput clamp current
IOK, VO<0
±50
IO, VO = 0 to VDDQ
±50
IDD, IDDQ or IGND
±100
θJA
70
Storage temperature
(1,2)
O utput voltage
Continuous output current
VDD, VDDQ or GND current/pin
Package Thermal Impedance(3)
V
mA
°C/W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level VO > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
Parame te rs
De s cription
M in.
Nom.
M ax.
VDD
Supply Voltage
2.3
2.5
2.7
VDDQ
I/O Supply Voltage
2.3
2.5
2.7
VREF
Reference Voltage VREF = 0.5X VDDQ
1.15
1.25
1.35
VTT
Termination Voltage
VREF –0.04
VREF
VREF +0.04
VIH
DC Input High Voltage
VIL
DC Input Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VIN
Input Voltage Level
VID
Input Differential Voltage
VIX
Cross Point Voltage of Differential Clock Pair
IOH
High- Level Output Current
–20
IOL
Low- Level Output Current
20
TA
Operating Free- Air Temperature
0
Data Inputs
RESET
CLK,CLK
2
VREF +0.15
VDDQ +0.3
–0.3
VREF –0.15
1.7
VDDQ +0.3
–0.3
0.8
Units
V
–0.3
0.36
VDDQ +0.6
(VDDQ/2) –0.2
(VDDQ/2) +0.2
mA
70
ºC
PS8460C
06/04/01
PI74SSTV16857
14-Bit
Registered
Buffer
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DC Electrical Characteristics
(Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ±200mV, VDDQ = 2.5V ±200mV)
Parame te rs
VIK
2.3V
Typ.(4)
M ax.
Units
–1.2
VDD –0.2
IOH = –16mA
2.3V
1.95
IOL = 100µA
2.3V- 2.7V
0.2
IOH =16mA
2.3V
0.35
All Inputs
VI = VDD or GND
2.7V
5
Standby (Static)
RESET = GND
100
Operating (Static)
VI = VIH (AC) or VIL (AC),
RESET = VDD
TBD
mA
Dynamic operating
- clock only
RESET = VDD,
VI = VIH(AC) or VIL(AC),
CK and CK switching
50% duty cycle .
TBD
µA/
clock
MHz
Dynamic Operating
- per each data
input
RESET = VDD,
VI = VIH(AC) or VIL(AC),
CK and CK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle
TBD
µA/
clock
MHz/
data
Data Inputs
VI = VREF ±350mV
CK and CK
VICR =1.25V, VI(PP) = 360mV
IDDD
Ci
II = –18mA
M in.
2.3V- 2.7V
VOL
IDD
VDD
IOH = –100µA
VOH
II
Te s t Conditions
IO = 0
V
2.7V
2.5V
2.0
3.5
2.0
3.5
µA
pF
Notes:
4. Typical values are at VDD = Nominal VDD, TA = +25°C.
3
PS8460C
06/04/01
PI74SSTV16857
14-Bit
Registered
Buffer
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
VDD = 2.5V ±0.2V
M in.
fclock
Clock frequency
tPD
Clock to output time
tRST
Reset to output time
tSL
Output slew rate
tsu
th
Setup time, fast slew rate(5,7)
Setup time, slow slew rate(6,7)
Hold time, fast slew rate(5,7)
Hold time, slow slew rate(6,7)
M ax.
170
TBD
Units
MHz
TBD
ns
5
1
Data before CK↑, CK↓
Data after CK↑, CK↓
4
V/ns
0.75
0.9
ns
0.75
0.9
Notes: 5. For data signal input slew rate ≥1V/ns.
6. For data signal input slew rate ≥0.5V/ns and <1V/ns.
7. CLK, CLK signals input slew rates are ≥1V/ns.
Switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).
Parame te r
From
(Input)
VDD = 2.5V ±0.2V
To
(Output)
M in.
fmax
Typ.
M ax.
170
tpd
CLK , CLK
Q
tphl
RESET
Q
1.1
MHz
2.8
5.0
4
Units
ns
PS8460C
06/04/01
PI74SSTV16857
14-Bit
Registered
Buffer
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Test Circuit and Switching Waveforms
VTT
LVCMOS
RESET
Input
VDD
VDD/2
tinact
IDD(9)
tact
10%
RL = 50Ω
From Output
0V
90% IDDH
IDDL
Input
VREF
Timing
VICR
VICR
VI(PP)
Input
t PLH
VIH
VREF
CL = 30pF(8)
Load Circuit
Voltage and Current Waveforms
Input Active and Inactive Times
tw
TEST POINT
Under Test
Output
t PHL
VTT
VIL
VOL
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Propagation Delay Times
LVCMOS
Timing
VICR
Input
RESET
VI(PP)
Input
tsu
VIH
VDD/2
VIL
th
t PHL
VOH
VIH
Input
VREF
VOH
VTT
Output
VREF
VIL
VTT
VOL
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (VDD = 2.5V ±0.2V)
Notes:
8. CL includes probe and jig capacitance.
9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
10. All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz, ZO = 50Ω. Input slew rate = 1V/ns ±20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. VTT = VREF = VDDQ/2
13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input.
14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input.
15. tPLH and tPHL are the same as tpd.
5
PS8460C
06/04/01
PI74SSTV16857
14-Bit
Registered
Buffer
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48-Pin TSSOP Package (A)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
.0197
BSC
0.50
DENOTES DIMENSIONS
IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
0.17
0.27
.319
BSC
8.1
48-Pin TSSOP Package (K)
48
.169
.177
4.30
4.50
.0035
.008
.031
.041
0.80
1.05
1
.378 9.60
.386 9.80
0.09
0.20
0.45 .018
0.75 .030
.252
BSC
6.4
SEATING
PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
.016
BSC
0.40
.002
.006
0.05
0.15
.0051
.009
0.13
0.23
Max.
.047
1.20
Ordering Information
Orde ring Code
Package Type
PI74SSTV16857A 48- Pin 240- mil TSSO P
PI74SSTV16857K 48- Pin 173- mil TVSO P
Orde ring Range
–40°C to 85°C
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6
PS8460C
06/04/01