LF to 2.5 GHz TruPwr™ Detector AD8361 FEATURES FUNCTIONAL BLOCK DIAGRAMS Calibrated rms response Excellent temperature stability Up to 30 dB input range at 2.5 GHz 700 mV rms, 10 dBm, re 50 Ω maximum input ±0.25 dB linear response up to 2.5 GHz Single-supply operation: 2.7 V to 5.5 V Low power: 3.3 mW at 3 V supply Rapid power-down to less than 1 µA VPOS TRANSCONDUCTANCE CELLS χ2 FLTR AD8361 ERROR AMP i × 7.5 BUFFER ADD OFFSET BAND-GAP REFERENCE PWDN SREF APPLICATIONS COMM Measurement of CDMA, W-CDMA, QAM, other complex modulation waveforms RF transmitter or receiver power measurement IREF Figure 2. 8-Lead MSOP GENERAL DESCRIPTION VPOS RFIN TRANSCONDUCTANCE CELLS χ2 PWDN INTERNAL FILTER i χ2 FLTR AD8361 ERROR AMP i × 7.5 BUFFER VRMS BAND-GAP REFERENCE COMM IREF 3.0 2.8 Figure 3. 6-Lead SOT-23 SUPPLY REFERENCE MODE 2.6 2.4 2.2 The AD8361 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest-factor (high peak-to-rms ratio) signals, such as CDMA and W-CDMA. INTERNAL REFERENCE MODE 2.0 01088-C-003 The AD8361 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains, up to 2.5 GHz. It is very easy to apply. It requires a single supply only between 2.7 V and 5.5 V, a power supply decoupling capacitor, and an input coupling capacitor in most applications. The output is a linear-responding dc voltage with a conversion gain of 7.5 V/V rms. An external filter capacitor can be added to increase the averaging time constant. V rms (Volts) VRMS 01088-C-002 RFIN INTERNAL FILTER i χ2 1.8 1.6 1.4 GROUND REFERENCE MODE 1.2 1.0 The AD8361 has three operating modes to accommodate a variety of analog-to-digital converter requirements: 0.8 0.6 0.2 0.0 0 0.1 0.2 0.3 RFIN (V rms) 0.4 0.5 01088-C-001 0.4 Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz (6-Lead SOT-23 Package Ground Reference Mode Only) 1. Ground reference mode, in which the origin is zero. 2. Internal reference mode, which offsets the output 350 mV above ground. 3. Supply reference mode, which offsets the output to VS/7.5. The AD8361 is specified for operation from −40°C to +85°C and is available in 8-lead MSOP and 6-lead SOT-23 packages. It is fabricated on a proprietary high fT silicon bipolar process. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8361 TABLE OF CONTENTS Specifications..................................................................................... 3 Applications..................................................................................... 12 Absolute Maximum Ratings............................................................ 4 Output Reference Temperature Drift Compensation ........... 16 ESD Caution.................................................................................. 4 Evaluation Board ............................................................................ 21 Pin Configuration and Function Descriptions............................. 5 Characterization Setups............................................................. 23 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 24 Circuit Description......................................................................... 11 Ordering Guide .......................................................................... 24 REVISION HISTORY 8/04—Data Sheet Changed from Rev. B to Rev. C. Changed Trimpots to Trimmable Potentiometers .........Universal Changes to Specifications ................................................................ 3 Changed Using the AD8361 Section Title to Applications ....... 12 Changes to Figure 43...................................................................... 14 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 2/01—Data Sheet Changed from Rev. A to Rev. B. Rev. C | Page 2 of 24 AD8361 SPECIFICATIONS TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted. Table 1. Parameter SIGNAL INPUT INTERFACE Frequency Range1 Linear Response Upper Limit Input Impedance2 RMS CONVERSION Conversion Gain Dynamic Range ±0.25 dB Error4 ±1 dB Error ±2 dB Error Intercept-Induced Dynamic Range Reduction5, 6 Deviation from CW Response OUTPUT INTERCEPT5 Ground Reference Mode (GRM) Internal Reference Mode (IRM) Supply Reference Mode (SRM) POWER-DOWN INTERFACE PWDN HI Threshold PWDN LO Threshold Power-Up Response Time PWDN Bias Current POWER SUPPLIES Operating Range Quiescent Current Power-Down Current Condition (Input RFIN) Min VS = 3 V Equivalent dBm, re 50 Ω VS = 5 V Equivalent dBm, re 50 Ω Typ Max Unit 2.5 GHz mV rms dBm mV rms dBm Ω||pF 390 4.9 660 9.4 225||1 (Input RFIN to Output V rms) 7.5 fRF = 100 MHz, VS = 5 V Error Referred to Best Fit Line3 CW Input, −40°C < TA < +85°C CW Input, −40°C < TA < +85°C CW Input, −40°C < TA < +85°C CW Input, VS = 5 V, −40°C < TA < +85°C Internal Reference Mode Supply Reference Mode, VS = 3.0 V Supply Reference Mode, VS = 5.0 V 5.5 dB Peak-to-Average Ratio (IS95 Reverse Link) 12 dB Peak-to-Average Ratio (W-CDMA 4 Channels) 18 dB Peak-to-Average Ratio (W-CDMA 15 Channels) Inferred from Best Fit Line3 0 V at SREF, VS at IREF fRF = 100 MHz, VS = 5 V 0 V at SREF, IREF Open fRF = 100 MHz, VS = 5 V 3 V at IREF, 3 V at SREF VS at IREF, VS at SREF fRF = 100 MHz, VS = 5 V 6.5 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 2 pF at FLTR Pin, 224 mV rms at RFIN 100 nF at FLTR Pin, 224 mV rms at RFIN VS − 0.5 −40°C < TA < +85°C 0 mV rms at RFIN, PWDN Input LO7 GRM or IRM, 0 mV rms at RFIN, PWDN Input HI SRM, 0 mV rms at RFIN, PWDN Input HI 2.7 1 8.5 14 23 26 30 1 1 1.5 0.2 1.0 1.2 +150 350 300 500 400 VS/7.5 590 750 0.1 5 320 <1 5.5 1.1 <1 10 × VS Operation at arbitrarily low frequencies is possible; see Applications section. Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively. Calculated using linear regression. 4 Compensated for output reference temperature drift; see Applications section. 5 SOT-23-6L operates in ground reference mode only. 6 The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40. 7 Supply current is input level dependant; see Figure 16. 2 3 Rev. C | Page 3 of 24 dB dB dB dB dB dB dB dB dB dB 0 −50 V/V rms V/V rms V mV mV mV mV V mV V V µs µs µA V mA µA µA AD8361 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VS SREF, PWDN IREF RFIN Equivalent Power, re 50 Ω Internal Power Dissipation1 6-Lead SOT-23 8-Lead MSOP Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V 0 V, VS VS − 0.3 V, VS 1 V rms 13 dBm 200 mW 170 mW 200 mW 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Specification is for the device in free air. 6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W. 8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 4 of 24 AD8361 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 3 PWDN 4 AD8361 TOP VIEW (Not to Scale) 8 SREF 7 VRMS 6 FLTR 5 COMM VRMS 1 6 VPOS AD8361 COMM 2 FLTR 3 5 RFIN TOP VIEW (Not to Scale) 4 PWDN Figure 4. 8-Lead MSOP 01088-C-005 IREF 2 01088-C-004 VPOS 1 Figure 5. 6-Lead SOT-23 Table 3. Pin Function Descriptions Pin No. MSOP 1 2 Pin No. SOT-23 6 N/A Mnemonic VPOS IREF 3 5 RFIN 4 4 PWDN 5 6 2 3 COMM FLTR 7 1 VRMS 8 N/A SREF Description Supply Voltage Pin. Operational range 2.7 V to 5.5 V. Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this pin should be tied to VPOS. Do not ground this pin. Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance is 225 Ω. Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than 100 mV). When a logic high (greater than VS − 0.5 V) is applied, the device is turned off and the supply current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference mode VS divided by 100 kΩ). Device Ground Pin. By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals. Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load >10 kΩ to ground. Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS; otherwise, it should be connected to COMM (ground). Rev. C | Page 5 of 24 AD8361 TYPICAL PERFORMANCE CHARACTERISTICS 2.8 3.0 900MHz 2.6 2.5 2.4 2.0 2.2 100MHz 1.5 1900MHz 2.0 1.0 1.6 ERROR (dB) 2.5GHz 1.4 1.2 1.0 0.5 0 –0.5 –1.0 MEAN ±3 SIGMA 0.8 –1.5 0.6 –2.0 0.4 0 0.1 0.2 0.3 INPUT (V rms) 0.4 0.5 –3.0 0.01 Figure 6. Output vs. Input Level, Frequencies 100 MHz, 900 MHz, 1900 MHz, and 2500 MHz, Supply 2.7 V, Ground Reference Mode, MSOP 5.5 0.4 (+5dBm) 3.0 5.5V 2.5 2.0 4.5 5.0V 1.5 4.0 3.0V 1.0 3.5 ERROR (dB) OUTPUT (V) 0.1 (–7dBm) INPUT (V rms) Figure 9. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine Wave, Supply 3.0 V, Frequency 900 MHz 5.0 3.0 2.5 2.0 2.7V 0.5 0 –0.5 –1.0 1.5 MEAN ±3 SIGMA –1.5 –2.0 0.5 –2.5 0 0.1 0.2 0.3 0.4 0.5 INPUT (V rms) 0.6 0.7 0.8 01088-C-007 1.0 0.0 0.02 (–21dBm) 01088-C-009 0.0 01088-C-006 –2.5 0.2 Figure 7. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz 5.0 IS95 REVERSE LINK 4.5 –3.0 0.01 0.02 (–21dBm) 0.6 (+8.6dBm) 0.1 (–7dBm) INPUT (V rms) 01088-C-010 OUTPUT (V) 1.8 Figure 10. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine Wave, Supply 5.0 V, Frequency 900 MHz 3.0 CW 2.5 2.0 4.0 1.5 ERROR (dB) 1.0 3.0 2.5 WCDMA 4- AND 15-CHANNEL 2.0 IS95 REVERSE LINK CW 0.5 0.0 4-CHANNEL –0.5 –1.0 1.5 15-CHANNEL –1.5 1.0 –2.0 0.5 0 0.1 0.2 0.3 0.4 0.5 INPUT (V rms) 0.6 0.7 0.8 Figure 8. Output vs. Input Level with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 5.0 V –2.5 –3.0 0.01 0.02 0.1 INPUT (V rms) 0.2 0.6 1.0 01088-C-011 0.0 01088-C-008 OUTPUT (V) 3.5 Figure 11. Error from CW Linear Reference vs. Input with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 3.0 V, Frequency 900 MHz Rev. C | Page 6 of 24 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 +85°C ERROR (dB) 0.5 0 –0.5 0 –0.5 –1.0 MEAN ±3 SIGMA –1.5 –1.5 –2.0 –2.0 2.5 –2.5 0.02 (–21dBm) 0.1 (–7dBm) INPUT (V rms) 0.4 (+5dBm) –3.0 0.01 01088-C-012 –3.0 0.01 0.02 (–21dBm) 3.0 11 2.5 10 2.0 VS = 5V INPUT OUT OF RANGE 9 SUPPLY CURRENT (mA) 1.5 1.0 0.5 0 –0.5 –1.0 MEAN ±3 SIGMA –1.5 8 6 +85°C 1 0 01088-C-013 +85°C 3 –3.0 0.01 Figure 13. Error from CW Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 5.0 V, Frequency 900 MHz +25°C 4 –2.5 0.6 (+8.6dBm) +25°C 5 2 0.1 (–7dBm) INPUT (V rms) –40°C VS = 3V INPUT OUT OF RANGE 7 –2.0 0.02 (–21dBm) 0.4 (+5dBm) 0.1 (–7dBm) INPUT (V rms) Figure 15. Output Delta from +25°C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 1900 MHz, Temperature −40°C to +85°C Figure 12. Error from CW Linear Reference vs. Input, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 3.0 V, Frequency 900 MHz ERROR (dB) –40°C 01088-C-015 –1.0 0.5 –40°C 0 0.1 0.2 0.3 0.4 0.5 INPUT (V rms) 0.6 0.7 0.8 01088-C-016 ERROR (dB) AD8361 Figure 16. Supply Current vs. Input Level, Supplies 3.0 V, and 5.0 V, Temperatures −40°C, +25°C, and +85°C 3.0 1.8 250 +25°C 2.5 +85°C 1.6 2.0 +85°C 0.5 0 –0.5 –1.0 –40°C –1.5 –40°C 1.4 +85°C 150 1.2 1.0 100 +25°C 0.8 –40°C 50 –2.0 0.6 –3.0 0.01 0.02 (–21dBm) 0.1 (–7dBm) INPUT (V rms) 0.4 (+5dBm) 0 0 500 1000 1500 FREQUENCY (MHz) 2000 0.4 2500 Figure 17. Input Impedance vs. Frequency, Supply 3 V, Temperatures −40°C, +25°C, and +85°C, MSOP (See Applications for SOT-23 Data) Figure 14. Output Delta from +25°C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 900 MHz, Temperature −40°C to +85°C Rev. C | Page 7 of 24 01088-C-017 –2.5 01088-C-014 ERROR (dB) 1.0 SHUNT CAPACITANCE (pF) 1.5 SHUNT RESISTANCE (Ω) 200 AD8361 0.18 0.03 0.16 0.14 0.01 GAIN CHANGE (V/V rms) INTERCEPT CHANGE (V) 0.02 0.00 –0.01 –0.02 MEAN ±3 SIGMA –0.03 0.12 0.10 MEAN ±3 SIGMA 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 –0.06 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 01088-C-021 –0.04 01088-C-018 –0.05 Figure 21. Conversion Gain Change vs. Temperature, Supply 3 V, Ground Reference Mode, Frequency 900 MHz Figure 18. Output Reference Change vs. Temperature, Supply 3 V, Ground Reference Mode 0.02 0.18 0.16 0.14 GAIN CHANGE (V/V rms) INTERCEPT CHANGE (V) 0.01 0.00 –0.01 MEAN ±3 SIGMA –0.02 0.12 0.10 MEAN ±3 SIGMA 0.08 0.06 0.04 0.02 0.00 –0.02 –20 0 20 40 TEMPERATURE (°C) 60 80 100 –0.06 –40 0 20 40 TEMPERATURE (°C) 60 80 100 Figure 19. Output Reference Change vs. Temperature, Supply 3 V, Internal Reference Mode (MSOP Only) Figure 22. Conversion Gain Change vs. Temperature, Supply 3 V, Internal Reference Mode, Frequency 900 MHz (MSOP Only) 0.03 0.18 0.16 0.02 0.14 GAIN CHANGE (V/V rms) 0.01 0.00 –0.01 –0.02 MEAN ±3 SIGMA –0.03 0.12 0.10 MEAN ±3 SIGMA 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 Figure 20. Output Reference Change vs. Temperature, Supply 3 V, Supply Reference Mode (MSOP Only) –0.06 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 Figure 23. Conversion Gain Change vs. Temperature, Supply 3 V, Supply Reference Mode, Frequency 900 MHz (MSOP Only) Rev. C | Page 8 of 24 01088-C-023 –0.04 –0.05 01088-C-020 INTERCEPT CHANGE (V) –20 01088-C-022 –40 01088-C-019 –0.04 –0.03 AD8361 GATE PULSE FOR 900MHz RF TONE PWDN INPUT 500mV PER VERTICAL DIVISION 370mV 270mV 270mV 500mV PER VERTICAL DIVISION RF INPUT RF INPUT 67mV 67mV 25mV 01088-C-024 25mV 5µs PER HORIZONTAL DIVISION 01088-C-027 370mV 2µs PER HORIZONTAL DIVISION Figure 24. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor Figure 27. Output Response Using Power-Down Mode for Various RF Input Levels, Supply 3 V, Frequency 900 MHz, No Filter Capacitor GATE PULSE FOR 900MHz RF TONE PWDN INPUT 370mV 500mV PER VERTICAL DIVISION 270mV 270mV 500mV PER VERTICAL DIVISION RF INPUT RF INPUT 67mV 01088-C-025 67mV 25mV 50µs PER HORIZONTAL DIVISION 01088-C-028 370mV 25mV 20µs PER HORIZONTAL DIVISION Figure 25. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor Figure 28. Output Response Using Power-Down Mode for Various RF Input Levels, Supply 3 V, Frequency 900 MHz, 0.01 µF Filter Capacitor HPE3631A POWER SUPPLY HPE3631A POWER SUPPLY 2 VPOS IREF SREF 8 C3 3 RFIN FLTR 6 0.1µF 4 PWDN C2 100pF TEK P6204 FET PROBE VRMS 7 C1 R1 75Ω C4 0.01µF AD8361 1 AD8361 1 VPOS SREF 8 2 IREF VRMS 7 C1 C5 100pF R1 75Ω COMM 5 HP8648B SIGNAL GENERATOR TEK TDS784C SCOPE HP8648B SIGNAL GENERATOR TEK P6204 FET PROBE C3 3 RFIN 4 PWDN FLTR 6 0.1µF C5 100pF COMM 5 HP8110A SIGNAL GENERATOR Figure 29. Hardware Configuration for Output Response Using Power-Down Mode Figure 26. Hardware Configuration for Output Response to Modulated Pulse Input Rev. C | Page 9 of 24 01088-C-029 C2 100pF 01088-C-026 C4 0.01µF TEK TDS784C SCOPE AD8361 7.8 16 7.6 14 VS = 3V 7.2 12 7.0 10 PERCENT CONVERSION GAIN (V/V rms) 7.4 6.8 6.6 8 6.4 6 6.2 4 6.0 2 0 6.9 RF INPUT 370mV 7.8 Figure 33. Conversion Gain Distribution Frequency 100 MHz, Supply 5 V, Sample Size 3000 Figure 30. Conversion Gain Change vs. Frequency, Supply 3 V, Ground Reference Mode, Frequency 100 MHz to 2500 MHz, Representative Device SUPPLY 7.4 7.2 7.6 CONVERSION GAIN (V/V rms) 7.0 01088-C-033 1000 CARRIER FREQUENCY (MHz) 12 500mV PER VERTICAL DIVISION 10 PERCENT 270mV 67mV 8 6 01088-C-031 4 25mV 20µs PER HORIZONTAL DIVISION 2 0 0.32 Figure 31. Output Response to Gating on Power Supply, for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor 0.34 0.38 0.36 0.40 IREF MODE INTERCEPT (V) 0.42 0.44 01088-C-034 5.6 100 01088-C-030 5.8 Figure 34. Output Reference, Internal Reference Mode, Supply 5 V, Sample Size 3000 (MSOP Only) HP8110A PULSE GENERATOR AD811 50Ω 12 10 TEK TDS784C SCOPE AD8361 1 VPOS SREF 8 2 IREF VRMS 7 3 RFIN FLTR 6 4 PWDN C1 R1 75Ω HP8648B SIGNAL GENERATOR 8 C3 0.1µF TEK P6204 FET PROBE 6 4 C5 100pF 2 COMM 5 Figure 32. Hardware Configuration for Output Response to Power Supply Gating Measurements Rev. C | Page 10 of 24 0 0.64 0.66 0.70 0.68 0.72 SREF MODE INTERCEPT (V) 0.74 0.76 01088-C-035 C2 100pF 01088-C-032 C4 0.01µF PERCENT 732Ω Figure 35. Output Reference, Supply Reference Mode, Supply 5 V, Sample Size 3000 (MSOP Only) AD8361 CIRCUIT DESCRIPTION The AD8361 is an rms-responding (mean power) detector that provides an approach to the exact measurement of RF power that is basically independent of waveform. It achieves this function through the use of a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high-gain error amplifier. The signal to be measured is applied to the input of the first squaring cell, which presents a nominal (LF) resistance of 225 Ω between the RFIN and COMM pins (connected to the ground plane). Because the input pin is at a bias voltage of about 0.8 V above ground, a coupling capacitor is required. By making this an external component, the measurement range may be extended to arbitrarily low frequencies. The AD8361 responds to the voltage, VIN, at its input by squaring this voltage to generate a current proportional to VIN squared. This is applied to an internal load resistor, across which a capacitor is connected. These form a low-pass filter, which extracts the mean of VIN squared. Although essentially voltageresponding, the associated input impedance calibrates this port in terms of equivalent power. Therefore, 1 mW corresponds to a voltage input of 447 mV rms. The Applications section shows how to match this input to 50 Ω. The voltage across the low-pass filter, whose frequency may be arbitrarily low, is applied to one input of an error-sensing amplifier. A second identical voltage-squaring cell is used to close a negative feedback loop around this error amplifier. This second cell is driven by a fraction of the quasi-dc output voltage of the AD8361. When the voltage at the input of the second squaring cell is equal to the rms value of VIN, the loop is in a stable state, and the output then represents the rms value of the input. The feedback ratio is nominally 0.133, making the rms-dc conversion gain ×7.5, that is VOUT = 7.5 × VIN rms By completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several benefits arise. First, scaling effects in these cells cancel; thus, the overall calibration may be accurate, even though the open-loop response of the squaring cells taken separately need not be. Note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scaling. Second, the tracking in the responses of the dual cells remains very close over temperature, leading to excellent stability of calibration. The squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. However, the dynamic range of such a system is fairly small, due in part to the much larger dynamic range at the output of the squaring cells. There are practical limitations to the accuracy of sensing very small error signals at the bottom end of the dynamic range, arising from small random offsets that limit the attainable accuracy at small inputs. On the other hand, the squaring cells in the AD8361 have a Class-AB aspect; the peak input is not limited by their quiescent bias condition but is determined mainly by the eventual loss of square-law conformance. Consequently, the top end of their response range occurs at a fairly large input level (approximately 700 mV rms) while preserving a reasonably accurate square-law response. The maximum usable range is, in practice, limited by the output swing. The rail-to-rail output stage can swing from a few millivolts above ground to less than 100 mV below the supply. An example of the output induced limit: given a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V supply, the maximum input is (2.9 V rms)/7.5 or 390 mV rms. Filtering An important aspect of rms-dc conversion is the need for averaging (the function is root-MEAN-square). For complex RF waveforms, such as those that occur in CDMA, the filtering provided by the on-chip, low-pass filter, although satisfactory for CW signals above 100 MHz, is inadequate when the signal has modulation components that extend down into the kilohertz region. For this reason, the FLTR pin is provided: a capacitor attached between this pin and VPOS can extend the averaging time to very low frequencies. Offset An offset voltage can be added to the output (when using the MSOP version) to allow the use of ADCs whose range does not extend down to ground. However, accuracy at the low end degrades because of the inherent error in this added voltage. This requires that the IREF (internal reference) pin be tied to VPOS and SREF (supply reference) to ground. In the IREF mode, the intercept is generated by an internal reference cell and is a fixed 350 mV, independent of the supply voltage. To enable this intercept, IREF should be open-circuited, and SREF should be grounded. In the SREF mode, the voltage is provided by the supply. To implement this mode, tie IREF to VPOS and SREF to VPOS. The offset is then proportional to the supply voltage and is 400 mV for a 3 V supply and 667 mV for a 5 V supply. Rev. C | Page 11 of 24 AD8361 APPLICATIONS Basic Connections +VS 2.7V – 5.5V Figure 36 through Figure 38 show the basic connections for the AD8361’s MSOP version in its three operating modes. In all modes, the device is powered by a single supply of between 2.7 V and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01 µF capacitors. The quiescent current of 1.1 mA in operating mode can be reduced to 1 µA by pulling the PWDN pin up to VPOS. The input coupling capacitor combines with the internal input resistance (Figure 37) to provide a high-pass corner frequency given by the equation f 3 dB = 1 2 π × CC × RIN With the 100 pF capacitor shown in Figure 36 through Figure 38, the high-pass corner frequency is about 8 MHz. +VS 2.7V – 5.5V AD8361 RFIN R1 75Ω VPOS SREF 8 2 IREF VRMS 7 3 RFIN FLTR 6 4 PWDN V rms 01088-C-036 CC 100pF 1 CC 100pF RFIN R1 75Ω 1 VPOS SREF 8 2 IREF VRMS 7 3 RFIN FLTR 6 4 PWDN V rms CFLTR COMM 5 Figure 38. Basic Connections for Supply Referenced Mode The output voltage is nominally 7.5 times the input rms voltage (a conversion gain of 7.5 V/V rms). Three modes of operation are set by the SREF and IREF pins. In addition to the ground reference mode shown in Figure 36, where the output voltage swings from around near ground to 4.9 V on a 5.0 V supply, two additional modes allow an offset voltage to be added to the output. In the internal reference mode (Figure 37), the output voltage swing is shifted upward by an internal reference voltage of 350 mV. In supply referenced mode (Figure 38), an offset voltage of VS/7.5 is added to the output voltage. Table 4 summarizes the connections, output transfer function, and minimum output voltage (i.e., zero signal) for each mode. Output Swing 100pF 0.01µF AD8361 0.01µF 01088-C-038 A 75 Ω external shunt resistance combines with the ac-coupled input to give an overall broadband input impedance near 50 Ω. Note that the coupling capacitor must be placed between the input and the shunt impedance. Input impedance and input coupling are discussed in more detail below. 100pF CFLTR COMM 5 Figure 36. Basic Connections for Ground Reference Mode Figure 39 shows the output swing of the AD8361 for a 5 V supply voltage for each of the three modes. It is clear from Figure 39 that operating the device in either internal reference mode or supply referenced mode reduces the effective dynamic range as the output headroom decreases. The response for lower supply voltages is similar (in the supply referenced mode, the offset is smaller), but the dynamic range reduces further as headroom decreases. Figure 40 shows the response of the AD8361 to a CW input for various supply voltages. 5.0 SUPPLY REF 4.5 +VS 2.7V – 5.5V 4.0 100pF R1 75Ω VPOS SREF 8 2 IREF VRMS 7 3 RFIN FLTR 6 V rms PWDN COMM 5 2.5 2.0 1.5 CFLTR 4 GROUND REF 3.0 1.0 0.5 Figure 37. Basic Connections for Internal Reference Mode 0.0 0 0.1 0.2 0.3 0.4 0.5 INPUT (V rms) 0.6 0.7 Figure 39. Output Swing for Ground, Internal, and Supply Referenced Mode, VPOS = 5 V (MSOP Only) Rev. C | Page 12 of 24 0.8 01088-C-039 RFIN 1 01088-C-037 CC 100pF OUTPUT (V) AD8361 0.01µF INTERNAL REF 3.5 AD8361 5.5 should however be noted that offsets at the low end can be either positive or negative, so this plot could also trend upwards at the low end. Figure 9, Figure 10, Figure 12, and Figure 13 show a ±3 sigma distribution of the device error for a large population of devices. 5.5V 5.0 4.5 5.0V 4.0 3.0V OUTPUT (V) 3.5 3.0 2.0 2.5 1.5 2.0 2.7V 1.0 1.5 2.5GHz 0.0 0 0.1 0.2 0.3 0.4 0.5 INPUT (V rms) 0.6 0.7 0.8 01088-C-040 0.5 ERROR (dB) 1.0 0.5 100MHz 0.0 1.9GHz –0.5 100MHz Figure 40. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V and 5.5 V (MSOP Only) –1.0 Dynamic Range –1.5 Because the AD8361 is a linear-responding device with a nominal transfer function of 7.5 V/V rms, the dynamic range in dB is not clear from plots such as Figure 39. As the input level is increased in constant dB steps, the output step size (per dB) also increases. Figure 41 shows the relationship between the output step size (i.e., mV/dB) and input voltage for a nominal transfer function of 7.5 V/V rms. –2.0 0.01 Table 4. Connections and Nominal Transfer Function for Ground, Internal, and Supply Reference Modes Reference Mode Ground Internal Supply IREF VPOS OPEN VPOS SREF COMM COMM VPOS Output Intercept (No Signal) Zero 0.350 V VS/7.5 Output 7.5 VIN 7.5 VIN + 0.350 V 7.5 VIN + VS/7.5 700 600 mV/dB 500 400 300 200 0 0 100 200 300 400 500 INPUT (mV) 600 700 800 01088-C-041 100 Figure 41. Idealized Output Step Size as a Function of Input Voltage Plots of output voltage versus input voltage result in a straight line. It may sometimes be more useful to plot the error on a logarithmic scale, as shown in Figure 42. The deviation of the plot for the ideal straight line characteristic is caused by output clipping at the high end and by signal offsets at the low end. It 0.02 (–21dBm) 0.1 (–7dBm) INPUT (V rms) 0.4 (+5dBm) 1.0 01088-C-042 900MHz Figure 42. Representative Unit, Error in dB vs. Input Level, VS = 2.7 V It is also apparent in Figure 42 that the error plot tends to shift to the right with increasing frequency. Because the input impedance decreases with frequency, the voltage actually applied to the input also tends to decrease (assuming a constant source impedance over frequency). The dynamic range is almost constant over frequency, but with a small decrease in conversion gain at high frequency. Input Coupling and Matching The input impedance of the AD8361 decreases with increasing frequency in both its resistive and capacitive components (Figure 17). The resistive component varies from 225 Ω at 100 MHz down to about 95 Ω at 2.5 GHz. A number of options exist for input matching. For operation at multiple frequencies, a 75 Ω shunt to ground, as shown in Figure 43, provides the best overall match. For use at a single frequency, a resistive or a reactive match can be used. By plotting the input impedance on a Smith Chart, the best value for a resistive match can be calculated. The VSWR can be held below 1.5 at frequencies up to 1 GHz, even as the input impedance varies from part to part. (Both input impedance and input capacitance can vary by up to ±20% around their nominal values.) At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt resistor is not sufficient to reduce the VSWR below 1.5. Where VSWR is critical, remove the shunt component and insert an inductor in series with the coupling capacitor as shown in Figure 44. Table 5 gives recommended shunt resistor values for various frequencies and series inductor values for high frequencies. The coupling capacitor, CC, essentially acts as an ac-short and plays no intentional part in the matching. Rev. C | Page 13 of 24 AD8361 Table 6. Recommended Values for a Reactive Input Matching (Figure 45) AD8361 Figure 43. Input Coupling/Matching Options, Broadband Resistor Match RFIN AD8361 01088-C-044 CC LM RFIN CC RFIN LM AD8361 01088-C-045 CM Figure 45. Input Coupling/Matching Options, Narrowband Reactive Match RSERIES CC RFIN AD8361 Table 5. Recommended Component Values for Resistive or Inductive Input Matching (Figure 43 and Figure 44) Matching Component 63.4 Ω Shunt 75 Ω Shunt 75 Ω Shunt 150 Ω Shunt or 4.7 nH Series 150 Ω Shunt or 4.7 nH Series 150 Ω Shunt or 2.7 nH Series RESISTANCE (Ω) Figure 46. Input Coupling/Matching Options, Attenuating the Input Signal Frequency 100 MHz 800 MHz 900 MHz 1800 MHz 1900 MHz 2500 MHz LM (nH) 180 15 12 4.7 4.7 3.3 Figure 46 shows a technique for coupling the input signal into the AD8361 that may be applicable where the input signal is much larger than the input range of the AD8361. A series resistor combines with the input impedance of the AD8361 to attenuate the input signal. Because this series resistor forms a divider with the frequency dependent input impedance, the apparent gain changes greatly with frequency. However, this method has the advantage of very little power being tapped off in RF power transmission applications. If the resistor is large compared to the transmission line’s impedance, then the VSWR of the system is relatively unaffected. 01088-C-046 RFIN CM (pF) 16 2 2 1.5 1.5 1.5 Input Coupling Using a Series Resistor Figure 44. Input Coupling/Matching Options, Series Inductor Match RFIN Frequency (MHz) 100 800 900 1800 1900 2500 250 1.7 200 1.4 150 1.1 100 0.8 50 0.5 0 Alternatively, a reactive match can be implemented using a shunt inductor to ground and a series capacitor, as shown in Figure 45. A method for hand calculating the appropriate matching components is shown on page 12 of the AD8306 data sheet. Matching in this manner results in very small values for CM, especially at high frequencies. As a result, a stray capacitance as small as 1 pF can significantly degrade the quality of the match. The main advantage of a reactive match is the increase in sensitivity that results from the input voltage being gained up (by the square root of the impedance ratio) by the matching network. Table 6 shows the recommended values for reactive matching. 0 500 1000 1500 2000 2500 FREQUENCY (MHz) 3000 0.2 3500 CAPACITANCE (pF) RSH 01088-C-047 RFIN RFIN 01088-C-043 CC Figure 47. Input Impedance vs. Frequency, Supply 3 V, SOT-23 Selecting the Filter Capacitor The AD8361’s internal 27 pF filter capacitor is connected in parallel with an internal resistance that varies with signal level from 2 kΩ for small signals to 500 Ω for large signals. The resulting low-pass corner frequency between 3 MHz and 12 MHz provides adequate filtering for all frequencies above 240 MHz (i.e., 10 times the frequency at the output of the squarer, which is twice the input frequency). However, signals with high peak-to-average ratios, such as CDMA or W-CDMA signals, and low frequency components require additional filtering. TDMA signals, such as GSM, PDC, or PHS, have a peak-to average ratio that is close to that of a sinusoid, and the internal filter is adequate. Rev. C | Page 14 of 24 AD8361 Table 7. Effect of Waveform and CFILT on Residual AC Waveform IS95 Reverse Link CFILT Open 0.01 µF 0.1 µF IS95 8-Channel Forward Link 0.01 µF 0.1 µF W-CDMA 15 Channel 0.01 µF 0.1 µF Output V dc 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 Residual AC mV p-p mV rms 550 100 1000 180 2000 360 40 6 160 20 430 60 20 3 40 6 110 18 290 40 975 150 2600 430 50 7 190 30 670 95 225 35 940 135 2500 390 45 6 165 25 550 80 current consumption, disabling the device reduces the leakage current to less than 1 µA. Figure 27 and Figure 28 show the response of the output of the AD8361 to a pulse on the PWDN pin, with no capacitance and with a filter capacitance of 0.01 µF, respectively; the turn-on time is a function of the filter capacitor. Figure 31 shows a plot of the output response to the supply being turned on (i.e., PWDN is grounded and VPOS is pulsed) with a filter capacitor of 0.01 µF. Again, the turn-on time is strongly influenced by the size of the filter capacitor. If the input of the AD8361 is driven while the device is disabled (PWDN = VPOS), the leakage current of less than 1 µA increases as a function of input level. When the device is disabled, the output impedance increases to approximately 16 kΩ. Volts to dBm Conversion In many of the plots, the horizontal axis is scaled in both rms volts and dBm. In all cases, dBm are calculated relative to an impedance of 50 Ω. To convert between dBm and volts in a 50 Ω system, the following equations can be used. Figure 48 shows this conversion in graphical form. ⎡ (V rms )2 ⎤ ⎢ ⎥ 50 Ω ⎥ Power (dBm ) = 10log ⎢ = 10log 20 (V rms )2 ⎢ 0.001 W ⎥ ⎢ ⎥ ⎢⎣ ⎥⎦ ( ⎛ dBm ⎞ V rms = 0.001 W × 50 Ω × log −1 ⎜ ⎟= ⎝ 10 ⎠ V rms Operation at Low Frequencies Although the AD8361 is specified for operation up to 2.5 GHz, there is no lower limit on the operating frequency. It is only necessary to increase the input coupling capacitor to reduce the corner frequency of the input high-pass filter (use an input resistance of 225 Ω for frequencies below 100 MHz). It is also necessary to increase the filter capacitor so that the signal at the output of the squaring circuit is free of ripple. The corner frequency is set by the combination of the internal resistance of 2 kΩ and the external filter capacitance. 1 dBm +20 +10 0 0.1 –10 –20 0.01 –30 –40 0.001 Figure 48. Conversion from dBm to rms Volts Power Consumption, Enable and Power-On The quiescent current consumption of the AD8361 varies with the size of the input signal from about 1 mA for no signal up to 7 mA at an input level of 0.66 V rms (9.4 dBm, re 50 Ω). If the input is driven beyond this point, the supply current increases steeply (see Figure 16). There is little variation in quiescent current with power supply voltage. The AD8361 can be disabled either by pulling the PWDN (Pin 4) to VPOS or by simply turning off the power to the device. While turning off the device obviously eliminates the Rev. C | Page 15 of 24 ) log −1 (dBm/10 ) 20 01088-C-048 The filter capacitance of the AD8361 can be augmented by connecting a capacitor between Pin 6 (FLTR) and VPOS. Table 7 shows the effect of several capacitor values for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. Note that large filter capacitors increase the enable and pulse response times, as discussed below. AD8361 Output Drive Capability and Buffering The AD8361 is capable of sourcing an output current of approximately 3 mA. If additional current is required, a simple buffering circuit can be used as shown in Figure 51. Similar circuits can be used to increase or decrease the nominal conversion gain of 7.5 V/V rms (Figure 49 and Figure 50). In Figure 50, the AD8031 buffers a resistive divider to give a slope of 3.75 V/V rms. In Figure 49, the op amp’s gain of two increases the slope to 15 V/V rms. Using other resistor values, the slope can be changed to an arbitrary value. The AD8031 rail-to-rail op amp, used in these example, can swing from 50 mV to 4.95 V on a single 5 V supply and operate at supply voltages down to 2.7 V. If high output current is required (>10 mA), the AD8051, which also has rail-to- rail capability, can be used down to a supply voltage of 3 V. It can deliver up to 45 mA of output current. 5V 100pF 0.01µF 0.01µF VPOS VOUT AD8031 AD8361 15V/V rms OUTPUT REFERENCE TEMPERATURE DRIFT COMPENSATION The error due to low temperature drift of the AD8361 can be reduced if the temperature is known. Many systems incorporate a temperature sensor; the output of the sensor is typically digitized, facilitating a software correction. Using this information, only a two-point calibration at ambient is required. The output voltage of the AD8361 at ambient (25°C) can be expressed by the equation VOUT = (GAIN × VIN ) + ς ΟΣ where GAIN is the conversion gain in V/V rms and VOS is the extrapolated output voltage for an input level of 0 V. GAIN and VOS (also referred to as intercept and output reference) can be calculated at ambient using a simple two-point calibration by measuring the output voltages for two specific input levels. Calibration at roughly 35 mV rms (−16 dBm) and 250 mV rms (+1 dBm) is recommended for maximum linear dynamic range. However, alternative levels and ranges can be chosen to suit the application. GAIN and VOS are then calculated using the equations COMM PWDN GAIN = 01088-C-049 5kΩ 5kΩ 5V 100pF 10kΩ VPOS VOUT 0.01µF 5kΩ AD8361 AD8031 3.75V/V rms 01088-C-050 5kΩ COMM PWDN Both GAIN and VOS drift over temperature. However, the drift of VOS has a bigger influence on the error relative to the output. This can be seen by inserting data from Figure 18 and Figure 21 (intercept drift and conversion gain) into the equation for VOUT. These plots are consistent with Figure 14 and Figure 15, which show that the error due to temperature drift decreases with increasing input level. This results from the offset error having a diminishing influence with increasing level on the overall measurement error. From Figure 18, the average intercept drift is 0.43 mV/°C from −40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a less rigorous compensation scheme, the average drift over the complete temperature range can be calculated as Figure 50. Output Buffering Options, Slope of 3.75 V/V rms 5V 0.01µF 100pF ⎛ 0.010 V − (− 0.028 V ) ⎞ ⎟⎟ = 0.000304 V/°C DRIFTVOS (V/°C ) = ⎜⎜ ⎝ + 85°C − (− 40°C ) ⎠ 0.01µF VPOS VOUT AD8361 AD8031 VIN2 − VIN1 VOS = VOUT1 − (GAIN × VIN1 ) Figure 49. Output Buffering Options, Slope of 15 V/V rms 0.01µF (VOUT2 − VOUT1 ) 7.5V/V rms COMM PWDN 01088-C-051 With the drift of VOS included, the equation for VOUT becomes VOUT = (GAIN × VIN) + VOS + DRIFTVOS × (TEMP − 25°C) Figure 51. Output Buffering Options, Slope of 7.5 V/V rms Rev. C | Page 16 of 24 AD8361 Extended Frequency Characterization The equation can be rewritten to yield a temperature compensated value for VIN: VIN = (VOUT − VOS − DRIFTVOS × (TEMP − 25°C )) GAIN Figure 52 shows the output voltage and error (in dB) as a function of input level for a typical device (note that output voltage is plotted on a logarithmic scale). Figure 53 shows the error in the calculated input level after the temperature compensation algorithm has been applied. For a supply voltage of 5 V, the part exhibits a worst-case linearity error over temperature of approximately ±0.3 dB over a dynamic range of 35 dB. 10 2.5 2.0 1.5 +85°C 1.0 0 VOUT (V) +25°C 0.5 –0.5 –40°C –1.0 –1.5 –2.5 –25 –20 –15 –10 –5 PIN (dBm) 0.1 10 5 0 01088-C-052 –2.0 In order to characterize the AD8361 at frequencies greater than 2.5 GHz, a small collection of devices were tested. Dynamic range, conversion gain, and output intercept were measured at several frequencies over a temperature range of −30°C to +80°C. Both CW and 64 QAM modulated input wave forms were used in the characterization process in order to access varying peakto-average waveform performance. The dynamic range of the device is calculated as the input power range over which the device remains within a permissible error margin to the ideal transfer function. Devices were tested over frequency and temperature. After identifying an acceptable error margin for a given application, the usable dynamic measurement range can be identified using the plots in Figure 54 through Figure 57. For instance, for a 1 dB error margin and a modulated carrier at 3 GHz, the usable dynamic range can be found by inspecting the 3 GHz plot of Figure 57. Note that the −30°C curve crosses the −1 dB error limit at −17 dBm. For a 5 V supply, the maximum input power should not exceed 6 dBm in order to avoid compression. The resultant usable dynamic range is therefore 6 dBm − (−17 dBm) Figure 52. Typical Output Voltage and Error vs. Input Level, 800 MHz, VPOS = 5 V or 23 dBm over a temperature range of −30°C to +80°C. 2.0 10 2.5 1.5 2.0 +80°C 1.0 +25°C 1.5 +85°C 0.5 1.0 0 0.5 +25°C –40°C –1.0 0 –0.5 –1.5 –1.0 –2.0 –1.5 –2.5 –2.0 –3.0 –30 –25 –20 –15 –10 –5 PIN (dBm) 0 5 10 1 –2.5 –25 0.1 –20 –15 –10 –5 0 5 10 PIN (dBm) Figure 53. Error after Temperature Compensation of Output Reference,800 MHz, VPOS = 5 V Figure 54. Transfer Function and Error Plots Measured at 1.5 GHz for a 64 QAM Modulated Signal Rev. C | Page 17 of 24 VOUT (V) –0.5 01088-0-054 ERROR (dB) –30°C 01088-C-053 ERROR (dB) ERROR (dB) 1.0 Although the AD8361 was originally intended as a power measurement and control device for cellular wireless applications, the AD8361 has useful performance at higher frequencies. Typical applications may include MMDS, LMDS, WLAN, and other noncellular activities. AD8361 10 2.5 2.5 2.0 10 2.0 +80°C 1.5 1.5 +25°C 1.0 1.0 CW 1 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 1 VOUT (V) 0 ERROR (dB) 0.5 VOUT (V) 64 QAM 01088-C-055 –2.0 –2.5 –25 0.1 –20 –15 –10 –5 PIN (dBm) 0 5 10 Figure 55. Transfer Function and Error Plots Measured at 2.5 GHz for a 64 QAM Modulated Signal 01088-C-058 ERROR (dB) –30°C 0.1 –2.5 –25 –20 –15 –10 –5 PIN (dBm) 0 5 10 Figure 58. Error from CW Linear Reference vs. Input Drive Level for CW and 64 QAM Modulated Signals at 3.0 GHz 10 2.5 8.0 2.0 +80°C 7.5 CONVERSION GAIN (V/V rms) 1.5 +25°C 1.0 0 VOUT (V) ERROR (dB) –30°C 0.5 1 –0.5 –1.0 –1.5 7.0 6.5 6.0 5.5 0.1 –20 –15 –10 –5 PIN (dBm) 0 5 10 5.0 Figure 56. Transfer Function and Error Plots Measured at 2.7 GHz for a 64 QAM Modulated Signal +80°C +25°C 1.0 1 –0.5 VOUT (V) 0.5 800 1200 1600 2200 2500 2700 3000 FREQUENCY (MHz) –1.0 –1.5 –2.0 –2.5 –25 0.1 –20 –15 –10 –5 PIN (dBm) 0 5 10 Figure 57. Transfer Function and Error Plots Measured at 3.0 GHz for a 64 QAM Modulated Signal 01088-C-057 ERROR (dB) –30°C 0 400 The transfer functions and error for a CW input and a 64 QAM input waveform is shown in Figure 58. The error curve is generated from a linear reference based on the CW data. The increased crest factor of the 64 QAM modulation results in a decrease in output from the AD8361. This decrease in output is a result of the limited bandwidth and compression of the internal gain stages. This inaccuracy should be accounted for in systems where varying crest factor signals need to be measured. 2.0 1.5 200 Figure 59. Conversion Gain vs. Frequency for a Typical Device, Supply 3 V, Ground Reference Mode 10 2.5 100 01088-C-059 –2.5 –25 01088-C-056 –2.0 The conversion gain is defined as the slope of the output voltage versus the input rms voltage. An ideal best fit curve can be found for the measured transfer function at a given supply voltage and temperature. The slope of the ideal curve is identified as the conversion gain for a particular device. The conversion gain relates the measurement sensitivity of the AD8361 to the rms input voltage of the RF waveform. The conversion gain was measured for a number of devices over a temperature range of −30°C to +80°C. The conversion gain for a typical device is shown in Figure 59. Although the conversion gain tends to decrease with increasing frequency, the AD8361 provides measurement capability at frequencies greater than Rev. C | Page 18 of 24 AD8361 One of the AD8361s (U2) has a net gain of about 14 dB preceding it and therefore operates most accurately at low input signal levels. This is referred to as the weak signal path. U4, on the other hand, does not have the added gain and provides accurate response at high levels. The output of U2 is attenuated by R1 in order to cancel the effect of U2’s preceding gain so that the slope of the transfer function (as seen at the slider of R1) is the same as that of U4 by itself. 2.5 GHz. However, it is necessary to calibrate for a given application to accommodate for the change in conversion gain at higher frequencies. Dynamic Range Extension for the AD8361 The accurate measurement range of the AD8361 is limited by internal dc offsets for small input signals and by square law conformance errors for large signals. The measurement range may be extended by using two devices operating at different signal levels and then choosing only the output of the device that provides accurate results at the prevailing input level. The circuit comprising U3, U5, and U6 is a crossfader, in which the relative gains of the two inputs are determined by the output currents of a fuzzy comparator made from Q1 and Q2. Assuming that the slider of R2 is at 2.5 V dc, the fuzzy comparator commands full weighting of the weak signal path when the output of U2 is below about 2.0 V dc, and full weighting of the strong signal path when the output of U3 exceeds about 3.0 V dc. U3 and U5 are OTAs (operational transconductance amplifiers). Figure 60 depicts an implementation of this idea. In this circuit, the selection of the output is made gradually over an input level range of about 3 dB in order to minimize the impact of imperfect matching of the transfer functions of the two AD8361s. Such a mismatch typically arises because of the variation of the gain of the RF preamplifier U1 and both the gain and slope variations of the AD8361s with temperature. 5V 0.01µF RFC 6dB PAD 1 8 2 7 +12V 16kΩ 100pF U1 U2 ERA-3 20dB AD8361 68Ω 5 4 2 R1 5kΩ 5V 6 3 0.1µF 3 U3 6 CA3080 5 12V 8.2nF –5V 5V 20kΩ 1kΩ 5V RF INPUT 6dB SPLITTER Q2 2N3906 R2 10kΩ 100Ω 2 7 U6 1kΩ 3 20kΩ Q1 2N3906 AD820 6 VOUT 4 5V 0.01µF U4 +12V 8 1 100pF 68Ω 20kΩ 2 AD8361 2 7 3 6 4 5 5V 3 12kΩ 0.1µF U5 CA3080 5 6 1MΩ –5V +5V –5V R3 10kΩ Figure 60. Range Extender Application Rev. C | Page 19 of 24 01088-C-060 270Ω 12V AD8361 1. The mismatch in input levels to the crossfader is never large enough to evoke very much distortion because the AD8361s are reasonably well-behaved. 2. The effect of the distortion in this case is merely to distort the otherwise nearly linear slope of the transition between the crossfader’s two inputs. VOUT m1 ≠ m2 DIFFERING SLOPES INDICATE MALADJUSTMENT OF R1 m2 VOUT MISALIGNMENT INDICATES MALADJUSTMENT OF R3 TRANSITION REGION 01088-C-062 U6 provides feedback to linearize the inherent tanh transfer function of the OTAs. When one OTA or the other is fully selected, the feedback is very effective. The active OTA has zero differential input; the inactive one has a potentially large differential input, but this does not matter because the inactive OTA is not contributing to the output. However, when both OTAs are active to some extent, and the two signal inputs to the crossfader are different, it is impossible to have zero differential inputs on the OTAs. In this event, the crossfader admittedly generates distortion because of the nonlinear transfer function of the OTAs. Fortunately, in this application, the distortion is not very objectionable for two reasons: RF INPUT LEVEL – V rms Figure 62. Intercept Adjustment In principle, this method could be extended to three or more AD8361s in pursuit of even more measurement range. However, it is very important to pay close attention to the matter of not excessively overdriving the AD8361s in the weaker signal paths under strong signal conditions. Figure 63 shows the extended range transfer function at multiple temperatures. The discontinuity at approximately 0.2 V rms arises as a result of component temperature dependencies. Figure 64 shows the error in dB of the range extender circuit at ambient temperature. For a 1 dB error margin, the range extender circuit offers 38 dB of measurement range. 3.0 REF LINE m1 2.0 VOUT (V) Figure 61. Slope Adjustment This circuit has three trimmable potentiometers. The suggested setup procedure is as follows: Set R2 so that its slider’s voltage is at the middle of the desired transition zone (about 2.5 V dc is recommended). Set R1 so that the transfer function’s slopes are equal on both sides of the transition zone. This is perhaps best accomplished by making a plot of the overall transfer function (using linear voltage scales for both axes) to assess the match in slope between one side of the transition region and the other (see Figure 61). Note: it may be helpful to adjust R3 to remove any large misalignment in the transfer function in order to correctly perceive slope differences. Finally (re)adjust R3 as required to remove any remaining misalignment in the transfer function (see Figure 62). 0 0 0.2 0.4 0.6 DRIVE LEVEL (V rms) 0.8 01088-C-063 2. 1.0 Figure 63. Output vs. Drive Level over Temperature for a 1 GHz 64 QAM Modulated Signal 5 4 3 2 ERROR (dB) Preset R3 at midrange. 4. 1.0 0.5 1. 3. –30°C 1.5 1 0 –1 –2 –3 –4 –5 –32 –27 –22 –17 –12 –7 –2 DRIVE LEVEL (dBm) 3 8 13 Figure 64. Error from Linear Reference at 25°C for a 1 GHz 64 QAM Modulated Signal Rev. C | Page 20 of 24 01088-C-064 RF INPUT LEVEL – V rms +80°C 01088-C-061 TRANSITION REGION 2.5 AD8361 EVALUATION BOARD Figure 65 and Figure 68 show the schematic of the AD8361 evaluation board. Note that uninstalled components are drawn in as dashed. The layout and silkscreen of the component side are shown in Figure 66, Figure 67, Figure 69, and Figure 70. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.01 µF capacitors. Additional decoupling, in the form of a series resistor or inductor in R6, can also be added. Table 8 details the various configuration options of the evaluation board. Table 8. Evaluation Board Configuration Options Component TP1, TP2 SW1 SW2/SW3 C1, R2 C2, C3, R6 C5 C4, R5 Function Ground and Supply Vector Pins. Device Enable. When in Position A, the PWDN pin is connected to +VS and the AD8361 is in powerdown mode. In Position B, the PWDN pin is grounded, putting the device in operating mode. Operating Mode. Selects either ground reference mode, internal reference mode or supply reference mode. See Table 4 for more details. Input Coupling. The 75 Ω resistor in Position R2 combines with the AD8361’s internal input impedance to give a broadband input impedance of around 50 Ω. For more precise matching at a particular frequency, R2 can be replaced by a different value (see Input Coupling and Matching and Figure 43 through Figure 46). Capacitor C1 ac couples the input signal and creates a high-pass input filter whose corner frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower frequencies. If resistive attenuation is desired at the input, series resistor R1, which is nominally 0 Ω, can be replaced by an appropriate value. Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and 100 pF. A series inductor or small resistor can be placed in R6 for additional decoupling. Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a capacitance in C5. Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms. Rev. C | Page 21 of 24 Default Condition Not Applicable SW1 = B SW2 = A, SW3 = B (Ground Reference Mode) R2 = 75 Ω (Size 0402) C1 = 100 pF (Size 0402) C2 = 0.01 µF (Size 0402) C3 = 100 pF (Size 0402) R6 = 0 Ω (Size 0402) C5 = 1 nF (Size 0603) C4 = R5 = Open (Size 0603) AD8361 VPOS C3 100pF C2 0.01µF VS A VS C3 100pF SW3 AD8361 SW2 B C1 100pF RFIN 1 VPOS SREF 8 2 IREF VRMS 7 VPOS FLTR 6 R4 0Ω R5 C4 (OPEN) (OPEN) PWDN (OPEN) (OPEN) 1 VRMS VPOS 6 2 COMM RFIN 5 3 FLTR PWDN 4 TP2 VPOS J1 Vrms C1 100pF R2 75Ω C5 1nF TP1 COMM 5 TP1 A SW1 1 3 SW1 2 J3 R7 50Ω Figure 68. Evaluation Board Schematic, SOT-23 Figure 65. Evaluation Board Schematic, MSOP 01088-C-069 01088-C-066 Figure 69. Layout of the Component Side, SOT-23 Figure 66. Layout of Component Side, MSOP 01088-C-067 B AD8361 R5 1nF 4 R4 0Ω C4 01088-C-065 VPOS RFIN A B C5 3 R2 75Ω J2 01088-C-070 R6 0Ω C2 0.01µF Figure 70. Silkscreen of the Component Side, SOT-23 Figure 67. Silkscreen of Component Side, MSOP Rev. C | Page 22 of 24 01088-C-068 TP2 AD8361 Problems caused by impedance mismatch may arise using the evaluation board to examine the AD8361 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board, can cause these problems. A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original signal incident at the board. The resultant voltage varies with both cable length and frequency dependence on the relative phase of the initial and reflected signals. Placing the 3 dB pad at the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable length and other fixture issues. In an actual application when the distance between AD8361 and source is short and well defined, this 3 dB attenuator is not needed. Analysis The conversion gain and output reference are derived using the coefficients of a linear regression performed on data collected in its central operating range (35 mV rms to 250 mV rms). This range was chosen to avoid areas of operation where offset distorts the linear response. Error is stated in two forms error from linear response to CW waveform and output delta from 2°C performance. The error from linear response to CW waveform is the difference in output from the ideal output defined by the conversion gain and output reference. This is a measure of both the linearity of the device response to both CW and modulated waveforms. The error in dB uses the conversion gain multiplied by the input as its reference. Error from linear response to CW waveform is not a measure of absolute accuracy, since it is calculated using the gain and output reference of each device. However, it does show the linearity and effect of modulation on the device response. Error from 25° C performance uses the performance of a given device and waveform type as the reference; it is predominantly a measure of output variation with temperature. C4 0.1µF CHARACTERIZATION SETUPS C2 100pF Equipment AD8361 VPOS 1 VPOS SREF 8 IREF 2 IREF VRMS 7 SREF VRMS C3 RFIN R1 75Ω C1 0.1µF FLTR 6 3 RFIN 4 PWDN 01088-C-071 The primary characterization setup is shown in Figure 72. The signal source used was a Rohde & Schwarz SMIQ03B, version 3.90HX. The modulated waveforms used for IS95 reverse link, IS95 nine active channels forward (forward link 18 setting), and W-CDMA 4-channel and 15-channel were generated using the default settings coding and filtering. Signal levels were calibrated into a 50 Ω impedance. COMM 5 PWDN Figure 71. Characterization Board AD8361 CHARACTERIZATION BOARD SMIQ038B RF SOURCE DC OUTPUT RF SIGNAL RFIN VRMS 3dB ATTENUATOR PRUP +VS SREF IREF DC SOURCES PC CONTROLLER DC MATRIX / DC SUPPLIES / DMM Figure 72. Characterization Setup Rev. C | Page 23 of 24 01088-C-072 IEEE BUS AD8361 OUTLINE DIMENSIONS 3.00 BSC 8 2.90 BSC 5 6 4.90 BSC 3.00 BSC 5 4 2.80 BSC 1.60 BSC 4 1 2 3 PIN 1 INDICATOR PIN 1 0.95 BSC 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° SEATING PLANE 1.90 BSC 1.30 1.15 0.90 0.80 0.60 0.40 1.45 MAX 0.50 0.30 0.15 MAX COMPLIANT TO JEDEC STANDARDS MO-187AA 0.22 0.08 SEATING PLANE 10° 4° 0° 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AB Figure 73. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Figure 74. 6-Lead Small Outline Transistor Package [SOT-23] (RT-6) Dimensions shown in millimeters ORDERING GUIDE Model AD8361ARM AD8361ARM-REEL AD8361ARM-REEL7 AD8361ARMZ1 AD8361ARMZ-REEL1 AD8361ARMZ-REEL71 AD8361ART-REEL AD8361ART-REEL7 AD8361ARTZ-RL71 AD8361-EVAL AD8361ART-EVAL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead MSOP, Tube 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP, Tube 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 6-Lead SOT-23, 13" Tape and Reel 6-Lead SOT-23, 7" Tape and Reel 6-Lead SOT-23, 7" Tape and Reel Evaluation Board MSOP Evaluation Board SOT-23-6L Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01088–0–8/04(C) Rev. C | Page 24 of 24 Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RT-6 RT-6 RT-6 Branding J3A J3A J3A J3A J3A J3A J3A J3A J3A