FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency range of 1200 MHz to 2500 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.2 dB SSB noise figure of 9.9 dB SSB noise figure with 5 dBm blocker of 21 dB Input IP3 of 31 dBm Input P1dB of 11 dBm Typical LO drive of 0 dBm Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP VPOS MNGM COMM MNON MNOP MNLE VPOS MNLG NC 1200 MHz to 2500 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5356 36 35 34 33 32 31 30 29 28 The ADL5356 uses a highly linear, doubly balanced, passive mixer core along with integrated RF and local oscillator (LO) balancing circuitry to allow single-ended operation. The ADL5356 incorporates the RF baluns, allowing for optimal performance over a 1200 MHz to 2500 MHz RF input frequency range. Performance is optimized for RF frequencies from 1700 MHz to 2500 MHz using a low-side LO and RF frequencies from 1200 MHz to 1700 MHz using a high-side LO. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −35 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.2 dB and can be used with a wide range of output impedances. LOI2 MNCT 2 26 VGS2 COMM 3 25 VGS1 VPOS 4 24 VGS0 COMM 5 23 LOSW VPOS 6 22 PWDN COMM 7 21 VPOS DVCT 8 20 COMM DVIN 9 19 LOI1 16 17 18 07883-001 15 NC 14 DVLG 13 VPOS 12 DVLE 11 DVON 10 DVOP ADL5356 COMM GENERAL DESCRIPTION 27 DVGM Cellular base station receivers Transmit observation receivers Radio link downconverters 1 VPOS APPLICATIONS MNIN Figure 1. The ADL5356 is fabricated using a BiCMOS high performance IC process. The device is available in a 6 mm × 6 mm, 36-lead LFCSP and operates over a −40°C to +85°C temperature range. An evaluation board is also available. Table 1. Passive Mixers RF Frequency (MHz) 500 to 1700 1200 to 2500 Single Mixer ADL5367 ADL5365 Single Mixer and IF Amp ADL5357 ADL5355 Dual Mixer and IF Amp ADL5358 ADL5356 The ADL5356 provides two switched LO paths that can be used in TDD applications where it is desirable to ping-pong between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5356 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<300 μA) the circuit when desired. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADL5356 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description......................................................................... 17 Applications ....................................................................................... 1 RF Subsystem .............................................................................. 17 General Description ......................................................................... 1 LO Subsystem ............................................................................. 18 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 19 Revision History ............................................................................... 2 Basic Connections ...................................................................... 19 Specifications..................................................................................... 3 IF Port .......................................................................................... 19 5 V Performance ........................................................................... 4 Bias Resistor Selection ............................................................... 19 3.3 V Performance ........................................................................ 4 Mixer VGS Control DAC .......................................................... 19 Absolute Maximum Ratings............................................................ 5 Evaluation Board ............................................................................ 21 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 23 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 7 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 15 Spur Tables .................................................................................. 16 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADL5356 SPECIFICATIONS VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. Table 2. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current 1 2 Conditions Min Tunable to >20 dB over a limited bandwidth Typ Unit 2500 dB Ω MHz 450 5.5 Ω||pF MHz V 15 50 1200 Differential impedance, f = 200 MHz Externally generated Max 230||0.75 30 3.3 −6 5.0 0 13 50 1230 +10 2470 1.0 0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled Apply supply voltage from external circuit through choke inductors. PWDN function is intended for use with VS ≤ 3.6 V only. Rev. 0 | Page 3 of 24 160 230 0 70 dBm dB Ω MHz V V V ns ns μA μA ADL5356 5 V PERFORMANCE VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious IF Channel-to-Channel Isolation POWER SUPPLY Positive Supply Voltage Quiescent Current Total Quiescent Current Conditions Min Typ Max Unit Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential 7.5 8.2 14.5 9.9 21 8.5 dB dB dB dB 25 31 dBm 50 dBm 11 −24 −35 −33 −75 −73 50 dBm dBm dBm dBc dBc dBc dB 5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1697 MHz, each RF tone at −10 dBm fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF tone at −10 dBm Unfiltered IF output −10 dBm input power −10 dBm input power 4.75 LO supply IF supply VS = 5 V 5 170 180 350 5.25 V mA mA mA 3.3 V PERFORMANCE VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) POWER INTERFACE Supply Voltage Quiescent Current Total Quiescent Current Conditions Min Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1697 MHz, each RF tone at −10 dBm fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1697 MHz, each RF tone at −10 dBm 3.0 Resistor programmable Device disabled Rev. 0 | Page 4 of 24 Typ Max Unit 8.3 14.6 8.9 21.2 dB dB dB dBm 48 dBm 7 dBm 3.3 200 300 3.6 V mA μA ADL5356 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 5. Parameter Supply Voltage, VS RF Input Level LO Input Level MNOP, MNON, DVOP, DVON Bias VGS2,VGS1,VGS0, LOSW, PWDN Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 2.2 W 22°C/W 150°C −40°C to +85°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 24 ADL5356 36 35 34 33 32 31 30 29 28 VPOS MNGM COMM MNON MNOP MNLE VPOS MNLG NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 ADL5356 TOP VIEW (Not to Scale) 27 26 25 24 23 22 21 LOI2 VGS2 VGS1 VGS0 LOSW PWDN VPOS 20 COMM 19 LOI1 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND. 07883-002 DVGM COMM DVOP DVON DVLE VPOS DVLG NC VPOS 10 11 12 13 14 15 16 17 18 MNIN MNCT COMM VPOS COMM VPOS COMM DVCT DVIN Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3, 5, 7, 12, 20, 34 4, 6, 10, 16, 21, 30, 36 8 9 11 13, 14 Mnemonic MNIN MNCT COMM VPOS Description RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled. Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor. Device Common (DC Ground). Positive Supply Voltage. DVCT DVIN DVGM DVOP, DVON 15 17 18, 28 19 22 DVLE DVLG NC LOI1 PWDN 23 24, 25, 26 27 29 31 32, 33 LOSW VGS0, VGS1, VGS2 LOI2 MNLG MNLE MNOP, MNON 35 Paddle MNGM EPAD Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor. RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled. Diverstiy Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation. Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using external inductors. Diversity Channel IF Return. This pin must be grounded. Diverstiy Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation. No Connect. Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled. Connect to Ground for Normal Operation. Connect pin to 3 V for disable mode when using VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V. Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2. Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level. Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled. Main Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation. Main Channel IF Return. This pin must be grounded. Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using external inductors. Main Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation. Exposed pad must be connected to ground. Rev. 0 | Page 6 of 24 ADL5356 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 61 400 59 TA = –40°C INPUT IP2 (dBm) 360 TA = +25°C 340 TA = +85°C 57 55 TA = –40°C TA = +25°C 53 TA = +85°C 320 51 49 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 07883-003 300 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) RF FREQUENCY (MHz) 07883-006 SUPPLY CURRENT (mA) 380 Figure 6. Input IP2 vs. RF Frequency Figure 3. Supply Current vs. RF Frequency 13.0 11 TA = +25°C 12.5 12.0 TA = –40°C INPUT P1dB (dBm) 9 TA = +25°C 8 7 TA = +85°C 11.5 TA = +85°C 11.0 TA = –40°C 10.5 10.0 6 9.5 RF FREQUENCY (MHz) 9.0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 07883-004 5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) 07883-007 CONVERSION GAIN (dB) 10 Figure 7. Input P1dB vs. RF Frequency Figure 4. Power Conversion Gain vs. RF Frequency 14 45 13 40 12 SSB NOISE FIGURE (dB) 35 TA = +25°C 30 25 TA = +85°C TA = +85°C TA = +25°C 11 10 9 8 TA = –40°C 7 20 15 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) 5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) Figure 8. SSB Noise Figure vs. RF Frequency Figure 5 .Input IP3 vs. RF Frequency Rev. 0 | Page 7 of 24 07883-008 6 07883-005 INPUT IP3 (dBm) TA = –40°C ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 58 400 57 56 VPOS = 5.0V INPUT IP2 (dBm) SUPPLY CURRENT (mA) VPOS = 5.25V VPOS = 5.25V 380 VPOS = 5.00V 360 340 VPOS = 4.75V 55 54 53 VPOS = 4.75V 52 51 320 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 49 –40 –30 –20 –10 07883-009 300 –40 –30 –20 –10 20 30 40 50 60 70 80 70 80 70 80 Figure 12. Input IP2 vs. Temperature 10.0 14 4.75V 5.00V 5.25V 13 VPOS = 5.25V 9.0 INPUT P1dB (dBm) 9.5 8.0 VPOS = 5.0V 12 11 10 VPOS = 4.75V 9 7.5 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 8 –40 –30 –20 –10 07883-010 7.0 –40 –30 –20 –10 0 10 20 30 40 50 60 TEMPERATURE (°C) Figure 10. Power Conversion Gain vs. Temperature 07883-013 CONVERSION GAIN (dB) 10 TEMPERATURE (°C) Figure 9. Supply Current vs. Temperature 9.5 0 07883-012 50 Figure 13. Input P1dB vs. Temperature 40 12.0 11.5 38 11.0 SSB NOISE FIGURE (dB) VPOS = 5.25V 34 32 VPOS = 5.0V 30 VPOS = 4.75V 28 10.5 VPOS = 5.25V 10.0 9.5 9.0 VPOS = 5.0V VPOS = 4.75V 8.5 8.0 26 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 7.0 –40 –30 –20 –10 0 10 20 30 40 50 60 TEMPERATURE (°C) Figure 11. Input IP3 vs. Temperature Figure 14. SSB Noise Figure vs. Temperature Rev. 0 | Page 8 of 24 07883-014 7.5 24 –40 –30 –20 –10 07883-011 INPUT IP3 (dBm) 36 ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 400 70 65 TA = +25°C 340 TA = +85°C 320 80 130 180 230 55 50 280 330 380 430 IF FREQUENCY (MHz) 40 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) Figure 15. Supply Current vs. IF Frequency Figure 18. Input IP2 vs. IF Frequency 10 14 TA = –40°C 9 13 8 TA = +85°C TA = +25°C 7 INPUT P1dB (dBm) CONVERSION GAIN (dB) TA = –40°C TA = +85°C 45 300 30 TA = +25°C 60 07883-018 360 INPUT IP2 (dBm) TA = –40°C 07883-015 SUPPLY CURRENT (mA) 380 TA = +85°C 6 5 4 3 12 11 TA = +25°C TA = –40°C 10 2 9 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) 8 07883-016 0 30 80 180 230 280 330 380 430 380 430 IF FREQUENCY (MHz) Figure 16. Power Conversion Gain vs. IF Frequency Figure 19. Input P1dB vs. IF Frequency 40 14 TA = –40°C TA = +25°C 13 30 12 25 SSB NOISE FIGURE (dB) 35 TA = +85°C 20 15 10 5 11 10 9 8 0 30 80 130 180 230 280 330 IF FREQUENCY (MHz) 380 430 6 30 80 130 180 230 280 330 IF FREQUENCY (MHz) Figure 17. Input IP3 vs. IF Frequency Figure 20. SSB Noise Figure vs. IF Frequency Rev. 0 | Page 9 of 24 07883-020 7 07883-017 INPUT IP3 (dBm) 130 07883-019 1 ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 11 11.8 TA = +85°C 11.6 11.4 TA = –40°C 9 INPUT P1dB (dB) CONVERSION GAIN (dB) 10 8 TA = +25°C 7 TA = +85°C TA = +25°C 11.2 TA = –40°C 11.0 10.8 10.6 10.4 6 –6 –4 –2 0 2 4 6 8 10 LO POWER (dBm) 10.0 –6 07883-021 5 –4 –2 0 2 4 6 8 10 LO POWER (dBm) Figure 21. Power Conversion Gain vs. LO Power 07883-024 10.2 Figure 24. Input P1dB vs. LO Power 40 –55 38 TA = –40°C –60 36 IF/2 SPURIOUS (dBc) INPUT IP3 (dBm) 34 32 30 TA = +25°C 28 TA = +85°C 26 –65 TA = –40°C –70 TA = +25°C –75 TA = +85°C 24 –80 –6 –4 –2 0 2 4 6 8 10 LO POWER (dBm) –85 1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200 07883-022 20 RF FREQUENCY (MHz) Figure 25. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm Figure 22. Input IP3 vs. LO Power 65 –65 63 –66 –67 IF/3 SPURIOUS (dBc) TA = –40°C 59 57 55 TA = +25°C 53 TA = +85°C 51 –68 –69 –70 –71 –72 –73 47 –74 –6 –4 –2 0 2 4 6 LO POWER (dBm) 8 10 07883-023 49 45 TA = +85°C TA = –40°C TA = +25°C –75 1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200 RF FREQUENCY (MHz) Figure 26. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm Figure 23. Input IP2 vs. LO Power Rev. 0 | Page 10 of 24 07883-026 61 INPUT IP2 (dBm) 07883-025 22 ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 100 500 10 400 8 300 6 200 4 100 2 60 40 20 7.8 8.0 8.2 8.4 8.6 8.8 CONVERSION GAIN (dB) 0 0 07883-027 0 7.6 30 80 130 180 230 280 330 380 07883-055 RESISTANCE (Ω) PERCENTAGE (%) 80 CAPACITANCE (pF) MEAN = 8.26 SD = 0.31% 430 IF FREQUENCY (MHz) Figure 30. IF Output Impedance (R Parallel C Equivalent) Figure 27. Conversion Gain Distribution 0 100 MEAN = 31.67 SD = 0.35% 5 RF PORT RETURN LOSS (dB) 60 40 20 10 15 20 25 20 25 30 35 40 45 INPUT IP3 LO (dBm) 30 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 07883-028 0 RF FREQUENCY (MHz) Figure 28. Input IP3 Distribution 07883-031 PERCENTAGE (%) 80 Figure 31. RF Port Return Loss, Fixed IF 100 0 MEAN = 11.37 SD = 0.49% LO RETURN LOSS (dB) 5 60 40 SELECTED 15 UNSELECTED 11 12 INPUT P1dB (dBm) 13 25 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 LO FREQUENCY (GHz) Figure 32. LO Return Loss, Selected and Unselected Figure 29. Input P1dB Distribution Rev. 0 | Page 11 of 24 2.00 07883-032 0 10 10 20 20 07883-029 PERCENTAGE (%) 80 ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. –15 60 TA = +25°C TA = –40°C –20 40 LO-TO-RF LEAKAGE (dBm) TA = +85°C 30 20 10 –25 TA = –40°C –30 –35 TA = +25°C –40 TA = +85°C –45 RF FREQUENCY (MHz) –50 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 07883-033 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 LO FREQUENCY (MHz) Figure 33. LO Switch Isolation vs. RF Frequency 07883-036 LO SWITCH ISOLATION (dB) 50 Figure 36. LO-to-RF Leakage vs. LO Frequency –16 26 –18 TA = +85°C 32 TA = +25°C 34 TA = –40°C 36 –20 –22 –24 –26 –28 38 RF FREQUENCY (MHz) –30 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 LO FREQUENCY (MHz) 07883-034 40 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Figure 34. RF-to-IF Isolation vs. RF Frequency Figure 37. 2XLO Leakage vs. LO Frequency –10 –35 –40 3XLO LEAKAGE (dBm) –15 TA = –40°C –20 –25 TA = +25°C –30 TA = +85°C –45 –50 3XLO-TO-IF –55 –60 3XLO-TO-RF –35 –40 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 LO FREQUENCY (MHz) Figure 35. LO-to-IF Leakage vs. LO Frequency –70 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 LO FREQUENCY (MHz) Figure 38. 3XLO Leakage vs. LO Frequency Rev. 0 | Page 12 of 24 07883-038 –65 07883-035 LO-TO-IF LEAKAGE (dBm) 2XLO-TO-RF 07883-037 30 2XLO-TO-IF 2XLO LEAKAGE (dBm) RF-TO-IF ISOLATION (dB) 28 ADL5356 30 9 16 25 8 14 7 12 6 10 15 10 RF FREQUENCY (MHz) 0 –30 18 30 300 16 28 14 26 12 24 22 SUPPLY CURRENT (mA) 350 INPUT IP3 (dB) INPUT P1dB (dB) 32 VGS = 000 VGS = 011 VGS = 100 VGS = 110 RF FREQUENCY (MHz) 9 20 15 CONVERSION GAIN 8 10 7 5 6 600 700 800 900 0 1000 1100 1200 1300 1400 1500 1600 LO BIAS RESISTOR VALUE (Ω) INPUT IP3 (dBm) 25 CONVERSION GAIN AND SSB NOISE FIGURE (dB) 30 10 5 10 200 150 LO RESISTOR SUPPLY CURRENT 100 700 800 900 1000 1100 1200 1300 1400 1500 1600 Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value 07883-041 CONVERSION GAIN AND SSB NOISE FIGURE (dB) 35 INPUT IP3 NOISE FIGURE 0 BIAS RESISTOR VALUE (Ω) Figure 40. Input IP3 and Input P1dB vs. RF Frequency for Various VGS Settings 11 –5 IF RESISTOR SUPPLY CURRENT 250 0 600 07883-040 18 6 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 12 –10 50 20 13 –15 Figure 42. SSB Noise Figure vs. 10 MHz Offset Blocker Level 20 8 –20 BLOCKER POWER (dBm) Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for Various VGS Settings 10 –25 07883-043 4 6 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 07883-042 5 8 Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias Resistor Value Rev. 0 | Page 13 of 24 35 13 INPUT IP3 30 12 25 11 NOISE FIGURE 20 10 15 9 CONVERSION GAIN 8 10 7 5 6 600 700 800 900 0 1000 1100 1200 1300 1400 1500 1600 IF BIAS RESISTOR VALUE (Ω) Figure 44. Power Conversion Gain, Noise Figure, and Input IP3 vs. IF Bias Resistor Value INPUT IP3 (dBm) VGS = 000 VGS = 011 VGS = 100 VGS = 110 20 07883-044 5 SSB NOISE FIGURE (dB) 18 SSB NOISE FIGURE (dB) 10 07883-039 CONVERSION GAIN (dB) VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. ADL5356 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 53 52 TA = –40°C TA = +85°C 51 50 49 TA = +25°C 48 47 46 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) 07883-051 IF CHANNEL-TO-CHANNEL ISOLATION (dB) 54 Figure 45. IF Channel-to-Channel Isolation vs. RF Frequency Rev. 0 | Page 14 of 24 ADL5356 3.3 V PERFORMANCE VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 70 215 65 60 INPUT IP2 (dBm) SUPPLY CURRENT (mA) 210 TA = –40°C 205 200 TA = +25°C 195 TA = +85°C 55 TA = –40°C TA = +85°C 50 TA = +25°C 45 40 30 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 07883-045 190 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) RF FREQUENCY (MHz) Figure 46. Supply Current vs. RF Frequency at 3.3 V 07883-048 35 Figure 49. Input IP2 vs. RF Frequency at 3.3 V 11 14 10 12 9 8 TA = +25°C 7 TA = +85°C TA = +25°C 8 6 TA = –40°C 6 4 5 2 4 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) TA = +85°C RF FREQUENCY (MHz) Figure 47. Power Conversion Gain vs. RF Frequency at 3.3 V 07883-049 INPUT P1dB (dBm) 10 07883-046 CONVERSION GAIN (dB) TA = –40°C Figure 50. Input P1dB vs. RF Frequency at 3.3 V 30 14 28 SSB NOISE FIGURE (dB) TA = –40°C 22 20 16 TA = +25°C TA = +85°C 14 10 8 TA = +25°C TA = –40°C 6 4 10 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) Figure 48. Input IP3 vs. RF Frequency at 3.3 V 2 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 RF FREQUENCY (MHz) Figure 51. SSB Noise Figure vs. RF Frequency at 3.3 V Rev. 0 | Page 15 of 24 07883-050 12 07883-047 INPUT IP3 (dBm) 24 18 TA = +85°C 12 26 ADL5356 SPUR TABLES All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm. 5 V Performance VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. M 0 0 1 2 3 4 5 6 7 N 8 9 10 11 12 13 14 15 −40.7 −70.5 <−100 1 −21.6 0.00 −91.0 <−100 <−100 2 −20.2 −72.7 −74.4 <−100 <−100 3 −64.4 −45.9 −82.9 −79.3 <−100 <−100 4 −69.6 −86.4 −96.5 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 7 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 13 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 3.3 V Performance VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VG2 = 0 V, and ZO = 50 Ω, unless otherwise noted. 0 0 1 2 3 4 5 6 7 N 8 9 10 11 12 13 14 15 −49.63 −74.64 <−100 <−100 <−100 <−100 1 −9.84 0.00 −56.52 −88.31 <−100 <−100 <−100 <−100 2 −20.31 −47.95 −57.35 −98.10 <−100 <−100 <−100 <−100 <−100 <−100 3 −43.05 −37.36 −64.17 −62.72 <−100 <−100 <−100 <−100 <−100 <−100 <−100 4 −40.75 −53.08 −80.85 <−100 −99.73 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −64.36 −57.08 −91.01 −91.46 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 −74.07 −85.58 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 M 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. 0 | Page 16 of 24 8 9 10 11 12 13 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 ADL5356 CIRCUIT DESCRIPTION The ADL5356 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of integrated, low loss RF baluns, passive MOSFET mixers, sum termination networks, and IF amplifiers. The LO subsystem consists of an SPDT-terminated FET switch and two multistage limiting LO amplifiers. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. VPOS MNGM COMM MNON MNOP MNLE VPOS MNLG NC A block diagram of the device is shown in Figure 52. 36 35 34 33 32 31 30 29 28 1 27 LOI2 MNCT 2 26 VGS2 COMM 3 25 VGS1 VPOS 4 24 VGS0 COMM 5 23 LOSW VPOS 6 22 PWDN COMM 7 21 VPOS DVCT 8 20 COMM DVIN 9 19 LOI1 13 14 15 16 17 18 DVON DVLE VPOS DVLG NC DVGM 12 DVOP 11 COMM 10 VPOS ADL5356 07883-001 MNIN Figure 52. Simplified Schematic RF SUBSYSTEM The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure 41, Figure 43, and Figure 44 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (No performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 1200 MHz to 2500 MHz. Rev. 0 | Page 17 of 24 ADL5356 LO SUBSYSTEM The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1700 MHz. The best operation is achieved with either low-side LO injection for RF signals in the 1700 MHz to 2500 MHz range or high-side injection for RF signals in the 1200 MHz to 1700 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 1200 MHz to 2500 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5356 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from −6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5356 has a power-down mode that permits the dc current to drop to <300 μA. The logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn. Rev. 0 | Page 18 of 24 ADL5356 APPLICATIONS INFORMATION BASIC CONNECTIONS BIAS RESISTOR SELECTION The ADL5356 mixer is designed to downconvert radio frequencies (RF) primarily between 1200 MHz and 2500 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 53 depicts the basic connections of the mixer. It is recommended to ac-couple the RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN matching network consists of a series 1.8 pF capacitor and a shunt 15 nH inductor to provide the optimized RF input return loss for the desired frequency band. The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5) are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure 41, Figure 43, and Figure 44 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and IP3 performance. IF PORT The ADL5356 features three logic control pins, VGS0 (Pin 24), VGS1 (Pin 25), and VGS2 (Pin26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults VGS0, VGS1, and VGS2 to ground. Power conversion gain, NF, IIP3, and input P1dB can be optimized, as shown in Figure 39 and Figure 40. The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately 200 Ω, as seen in Figure 30, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Table 3. When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 53. MIXER VGS CONTROL DAC Rev. 0 | Page 19 of 24 ADL5356 R10 MAIN_OUTP MAIN_OUTN C32 C33 T1 C19 C17 C27 C8 C21 L2 L1 R3 C25 VCC R1 C22 C18 VCC L6 VCC 36 35 34 33 32 31 30 29 R2 28 C9 C16 MAIN_IN Z1 1 27 2 26 LO2 Z2 R12 C3 R16 VCC R7 C2 3 25 C34 R13 R8 R14 4 R17 24 R11 R15 VCC 5 23 6 22 R19 7 C6 21 VCC C26 C7 ADL5356 8 C15 20 C11 9 DIV_IN Z3 LO1 19 C14 Z4 10 11 12 13 14 15 16 17 18 VCC VCC + C10 L3 C23 VCC R4 VCC C24 R5 C13 GND L5 R6 C1 L4 C12 C28 C20 C29 T2 DIV_OUTN C30 R9 C31 Figure 53. Typical Application Circuit Rev. 0 | Page 20 of 24 07883-153 DIV_OUTP ADL5356 EVALUATION BOARD RO3003 material. Table 7 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 55 and Figure 56. An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 54. The evaluation board is fabricated using Rogers® R10 MAIN_OUTP MAIN_OUTN C32 C33 T1 C19 C17 C27 C8 C21 L1 L2 R3 C18 C25 VCC R1 C22 VCC R2 NC MNLG MNLE MNOP MNON COMM MNGM VPOS VPOS L6 VCC C9 C16 LOI2 MNIN MAIN_IN LO2 R12 Z2 VGS2 MNCT C3 VCC R7 C2 COMM VPOS VGS1 R13 VGS0 R8 C34 R14 ADL5356 COMM VCC C6 R16 R17 LOSW TOP VIEW (Not to Scale) R11 VPOS PWDN COMM VPOS DVCT COMM R15 C7 VCC C11 DVIN DIV_IN R19 C15 LO1 C14 NC DVLG VPOS DVLE DVON DVOP COMM DVGM Z4 VPOS Z3 C26 LOI1 VCC + VCC C10 L3 C23 R4 R5 VCC VCC GND C24 L5 R6 C1 C13 L4 C12 C28 C20 C29 T2 DIV_OUTP DIV_OUTN C30 R9 C31 Figure 54. Evaluation Board Schematic Rev. 0 | Page 21 of 24 07883-154 Z1 ADL5356 Table 7. Evaluation Board Configuration T1, T2, C17, C19, C20, C27 - C33, L1, L2, L4, L5, R3, R6, R9, R10 C14, C16, R15, LOSEL R19, PWDN RF Main and Diversity Input Interface. Main and diversity input channels are ac-coupled through C9 and C11. Z1 to Z4 provide additional component placement for external matching/filter networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional supply bypassing. T1 and T2 are 4:1 impedance transformers used to provide a single-ended IF output interface with C27 and C28 providing center-tap bypassing. C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled output interface. Remove R9 and R10 for balanced output operation. LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2 local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled when the LOSEL jumper is removed. Jumper can be removed to allow LOSEL interface to be exercised using external logic generator. PWDN Interface. When the PWDN 2-pin shunt is inserted, the ADL5356 is powered down. When R19 is open, it pulls the PWDN logic low and enables the device. Jumper can be removed to allow PWDN interface to be excercised using an external logic generator. Grounding the PWDN pin is allowed during nominal operation but is not permitted when supply voltages exceed 3.3 V. Bias Control. R16 and R17 form a voltage divider to provide a 3 V for logic control, bypassed to ground through C34. R7, R8, R11, R12, R13, and R14 provide resistor programmability of VGS0, VGS1, and VGS2. Typically, these nodes can be hardwired for nominal operation. Grounding these pins is allowed for nominal operation. R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set the bias point for the internal IF amplifiers. L3 and L6 are external inductors used to improve isolation and common-mode rejection. Default Conditions C10 = 4.7 μF (Size 3216), C1, C8, C12, C21 = 150 pF (Size 0402), C22, C23, C24, C25, C26 = 10 pF (Size 0402), C13, C15, C18 = 0.1 μF (Size 0402) C2, C7 = 10 pF (Size 0402), C3, C6 = 0.01 μF (Size 0402), C9, C11 = 1.8 pF (Size 0402), Z2, Z4 = 15 nH, Z1, Z3 = open (Size 0402) C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402), C27, C28 = 150 pF (Size 0402), T1, T2 = TC4-1T+ (Mini-Circuits), L1, L2, L4, L5 = 330 nH (Size 0805), R3, R6, R9, R10 = 0 Ω (Size 0402) C14, C16 = 10 pF (Size 0402), R15 = 10 kΩ (Size 0402), LOSEL = 2-pin shunt R19 = 10 kΩ (Size 0402), PWDN = 2-pin shunt R1, R4 = 1.3 kΩ (Size 0402), R2, R5 = 1 kΩ (Size 0402), L3, L6 = 0 Ω (Size 0603), R12, R13, R14 = open (Size 0402), R7, R8, R11 = 0 Ω (Size 0402), R16 = 10 kΩ (Size 0402), R17 = 15 kΩ (Size 0402), C34 = 1 nF (Size 0402) 07883-056 R1, R2, R4, R5, L3, L6, R7, R8, R11 to R14, R16, R17, C34 Description Power Supply Decoupling. Nominal supply decoupling consists of a 0.01 μF capacitor to ground in parallel with 10 pF capacitors to ground positioned as close to the device as possible. 07883-057 Components C1, C8, C10, C12, C13, C15, C18, C21, C22, C23, C24, C25, C26 Z1 to Z4, C2, C3, C6, C7, C9, C11 Figure 55. Evaluation Board Top Layer Figure 56. Evaluation Board Bottom Layer Rev. 0 | Page 22 of 24 ADL5356 OUTLINE DIMENSIONS 0.60 MAX 6.00 BSC SQ TOP VIEW 5.75 BSC SQ 0.50 BSC 0.75 0.60 0.50 1.00 0.85 0.80 SEATING PLANE 12° MAX 1 (BOTTOM VIEW) 19 18 10 PIN 1 INDICATOR 3.85 3.70 SQ 3.55 EXPOSED PAD 9 0.20 MIN 4.00 REF 0.80 MAX 0.65 TYP 0.35 0.28 0.23 36 28 27 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 050808-D PIN 1 INDICATOR 0.60 MAX COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1 Figure 57. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6mm × 6 mm Body, Very Thin Quad (CP-36-1) Dimensions shown in millimeters ORDERING GUIDE Model ADL5356ACPZ-R2 1 ADL5356ACPZ-R71 ADL5356-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 Package Description 36-Lead LFCSP_VQ 36-Lead LFCSP_VQ Evaluation Board Package Option CP-36-1 CP-36-1 ADL5356 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07883-0-10/09(0) Rev. 0 | Page 24 of 24