ETC STPCD01

STPC® CLIENT
PC Compatible Embedded Microprocessor
•
POWERFUL X86 PROCESSOR
•
64-BIT 66MHz BUS INTERFACE
•
64-BIT DRAM CONTROLLER
•
SVGA GRAPHICS CONTROLLER
•
UMA ARCHITECTURE
•
VIDEO SCALER
•
VIDEO OUTPUT PORT
•
VIDEO INPUT PORT
•
CRT CONTROLLER
•
135MHz RAMDAC
•
2 OR 3 LINE FLICKER FILTER
•
SCAN CONVERTER
•
PCI MASTER / SLAVE / ARBITER
•
ISA MASTER/SLAVE
•
IDE CONTROLLER
•
DMA CONTROLLER
•
INTERRUPT CONTROLLER
•
TIMER / COUNTERS
•
POWER MANAGEMENT
PBGA388
Figure 1. Logic Diagram
ISA BUS
x86
Core
STPC CLIENT OVERVIEW
The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller, a
graphics subsystem, a video pipeline, and
support logic including PCI, ISA, and IDE
controllers to provide a single Consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video input stream
and mixing of the video stream with non-video
data from the frame buffer. The chip also includes
anti-flicker filters to provide a stable, high-quality
Digital TV output.
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).
October 13, 2000
ISA
IPC
PCI
EID
Host I/F
EIDE
PCI BUS
PCI
CCIR Input
VIP
TV Output
AntiColVid2D
CRT
DRAM
Issue 2.2
Colour
Monitor
HW
SYNC Output
1/61
STPC CLIENT
•
•
•
•
•
•
•
•
•
X86 Processor core
Fully static 32-bit 5-stage pipeline, x86 processor with DOS, Windows and UNIX compatibility.
Can access up to 4GB of external memory.
KBytes unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Clock core speeds up to of 75 MHz.
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 3.3V operation.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DRAM Controller
Integrated system memory and graphic frame
memory.
Supports up to 128 MBytes system memory
in 4 banks and as little as MBytes.
Supports 4MBytes, 8MBites, 16MBites,
32MBites single-sided and double-sided
DRAM SIMMs.
Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.
Four 4-word read buffers for PCI masters.
Supports Fast Page Mode & EDO DRAMs.
Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.
60, 70, 80 & 100ns DRAM speeds.
Memory hole size of 1 MByte to 8 MBytes
supported for PCI/ISA buses.
Hidden refresh.
To check if your memory device is supported by
the STPC, please refer to Table 6-69 in the
Programming Manual.
•
•
•
•
•
•
•
2/61
Graphics Controller
64-bit windows accelerator.
Backward compatibility to SVGA standards.
Hardware acceleration for text, bitblts, transparent blts and fills.
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, and 24-bit pixels.
•
•
•
•
•
•
•
•
•
•
•
•
•
CRT Controller
Integrated 135MHz triple RAMDAC allowing
up to 1024 x 768 x 75Hz display.
8-, 16-, 24-bit per pixels.
Interlaced or non-interlaced output.
Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Colour space conversion (RGB to YUV and
YUV to RGB).
Programmable window size.
Chroma and colour keying allowing video
overlay.
Programmable two tap filter with gamma correction or three tap flicker filter.
Progressive to interlaced scan converter.
Video Input port
Decodes video inputs in ITU-R 601/656 compatible formats.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
Video pass through to the onboard PAL/
NTSC encoder for full screen video images.
HSYNC and B/T generation or lock onto
external video timing source.
PCI Controller
Integrated PCI arbitration interface able to
directly manage up to 3 PCI masters at a
time.
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
PCI.
Support for burst read/write from PCI master.
The PCI clock runs at a third or half CPU
clock speed.
Issue 2.2 - October 13, 2000
STPC CLIENT
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ISA master/slave
The ISA clock generated from either
14.318MHz oscillator clock or PCI clock
Supports programmable extra wait state for
ISA cycles
Supports I/O recovery time for back to back I/
O cycles.
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
Supports flash ROM.
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
IDE Interface
Supports PIO
Supports up to Mode 5 Timings
Supports up to 4 IDE devices
Individual drive timing for all four IDE devices
Concurrent channel operation (PIO modes) 4 x 32-Bit Buffer FIFO per channel
Support for PIO mode 3 & 4
Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
Integrated peripheral controller
2X8237/AT compatible 7-channel DMA controller.
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
Three 8254 compatible Timer/Counters.
Power Management
Four power saving modes: On, Doze, Standby, Suspend.
Programmable system activity detector
Supports SMM.
Supports STOPCLK.
Supports IO trap & restart.
Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.
Supports RTC, interrupts and DMAs wake-up
Issue 2.2 - October 13, 2000
3/61
STPC CLIENT
4/61
Issue 2.2 - October 13, 2000
UPDATE HISTORY FOR OVERVIEW
UPDATE HISTORY FOR OVERVIEW
The following changes have been made to the Board Layout Chapter on 02/02/2000.
Section
Change
Added
Text
To check if your memory device is supported by the STPC, please refer to
Table 6-69 Host Address to MA Bus Mappingin the Programming Manual.
The following changes have been made to the Board Layout Chapter from Revision 1.0 to Release 1.2.
Section
Change
N/A
Replaced
N/A
Replaced
N/A
Removed
N/A
Removed
N/A
Replaced
N/A
Replaced
N/A
Replaced
N/A
Replaced
N/A
Removed
N/A
Replaced
N/A
Replaced
N/A
Replaced
N/A
Removed
N/A
Added
N/A
Replaced
N/A
Removed
Text
“fully PC compatible” With “with DOS, Windows and UNIX compatibility”
“133 MHz” With 75 MHz”
“Drivers for Windows and other operating systems.”
“Requires external frequency synthesizer and reference sources.”
“Chroma and colour keying for integrated video overlay.” With “Chroma and colour
keying allowing video overlay.
“Accepts video inputs in CCIR 601/656 or ITU-R 601/656, and decodes the
stream.” With “Decodes video inputs in ITU-R 601/656 compatible formats.
“Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3 masters can connect directly.
External PAL allows for greater than 3 masters.”
With
“Integrated PCI arbitration interface able to directly manage up to 3 PCI
masters at a time.”
“0.33X and 0.5X CPU clock PCI clock.” With “The PCI clock runs at a third or
half CPU clock speed.”
“Supports flash ROM.”
“Supports ISA hidden refresh.” With “Supports flash ROM.”
“Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI
and Host bus. NSP compliant.” With “Buffered DMA & ISA master cycles to
reduce bandwidth utilization of the PCI and Host bus. “
“ Supports PIO and Bus Master IDE” With “Supports PIO”
“Transfer Rates to 22 MBytes/sec”
“Individual drive timing for all four IDE devices “
“Concurrent channel operation (PIO & DMA modes) - 4 x 32-Bit Buffer FIFO
per channel”
With
“Concurrent channel operation (PIO modes) - 4 x 32-Bit Buffer FIFO per
channel”
“Support for DMA mode 1 & 2.”
“Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.”
“Supports 13.3/16.6 MB/s DMA data transfers”
“Bus Master with scatter/gather capability “
“Multi-word DMA support for fast IDE drives “
“Individual drive timing for all four IDE devices “
“Supports both legacy & native IDE modes”
“Supports hard drives larger than 528MB”
“Support for CD-ROM and tape peripherals”
“Backward compatibility with IDE (ATA-1).”
“Drivers for Windows and other OSes”
Issue 2.2 - October 13, 2000
5/61
UPDATE HISTORY FOR OVERVIEW
Section
Change
N/A
Added
N/A
Removed
N/A
Replaced
N/A
Removed
6/61
Text
“Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.”
“Supports both legacy & native IDE modes”
“Supports hard drives larger than 528MB”
“Support for CD-ROM and tape peripherals”
“Backward compatibility with IDE (ATA-1).”
“Co-processor error support logic.”
“Supports SMM and APM” With “Supports SMM”
“Slow system clock down to 8MHz”
“Slow Host clock down to 8Hz”
“Slow graphic clock down to 8Hz”
Issue 2.2 - October 13, 2000
GENERAL DESCRIPTION
1.GENERAL DESCRIPTION
At the heart of the STPC Client is an advanced
processor block, dubbed the ST X86. The ST X86
includes a powerful x86 processor core along with
a 64-bit DRAM controller, advanced 64bit accelerated graphics and video controller, a high speed
PCI local-bus controller and Industry standard PC
chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus) and EIDE controller.
The STPC Client has in addition to the 5ST86 a
Video subsystem and high quality digital Television output.
The STMicroelectronics x86 processor core is embedded with standard and application specific peripheral modules on the same silicon die. The core
has all the functionality of the ST Microelectronics
standard x86 processor products, including the
low power System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While running in isolated SMM address space, the SMM interrupt routine can execute without interfering with
the operating system or application programs.
Further power management facilities include a
suspend mode that can be initiated from either
hardware or software. Because of the static nature
of the core, no internal data is lost.
The STPC Client makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memory and graphics frame-buffer. This significantly reduces total system memory with system performances equal to that of a comparable solution with
separate frame buffer and system memory. In addition, memory bandwidth is improved by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the
processor bus rather than the traditional PCI bus.
The 64-bit wide memory array provides the system with 320MB/s peak bandwidth, double that of
an equivalent system using 32 bits. This allows for
higher screen resolutions and greater colour
depth. The processor bus runs at the speed of the
processor (DX devices) or half the speed (DX2 devices).
The ‘standard’ PC chipset functions (DMA, interrupt controller, timers, power management logic)
are integrated with the x86 processor core.
The PCI bus is the main data communication link
to the STPC Client chip. The STPC Client trans-
lates appropriate host bus I/O and Memory cycles
onto the PCI bus. It also supports the generation
of Configuration cycles on the PCI bus. The STPC
Client, as a PCI bus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy
porting of PCI aware system BIOS. The device
contains a PCI arbitration function for three external PCI devices.
The STPC Client integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Client chip set through this bus.
An industry standard EIDE (ATA 2) controller is
built into the STPC Client and connected internally
via the PCI bus.
Graphics functions are controlled by the on-chip
SVGA controller and the monitor display is managed by the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations, which include hardware acceleration of text, bitblts, transparent blts
and fills. These operations can operate on offscreen or on-screen areas. The frame buffer size
is up to 4 MBytes anywhere in the physical main
memory.
The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours at 75Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
STPC Client provides several additional functions
to handle MPEG or similar video streams. The
Video Input Port accepts an encoded digital video
stream in one of a number of industry standard
formats, decodes it, optionally decimates it by a
factor of 2:1, and deposits it into an off screen area
of the frame buffer. An interrupt request can be
generated when an entire field or frame has been
captured.
The video output pipeline incorporates a videoscaler and colour space converter function and
provisions in the CRT controller to display a video
window. While repainting the screen the CRT controller fetches both the video as well as the normal
non-video frame buffer in two separate internal
FIFOs (256-Bytes each). The video stream can be
colour-space converted (optionally) and smooth
Issue 2.2 - October 13, 2000
7/61
GENERAL DESCRIPTION
scaled. Smooth interpolative scaling in both horizontal and vertical direction are implemented. Colour and Chroma key functions are also implemented to allow mixing video stream with non-video frame buffer.
by state.
The video output passes directly to the RAMDAC
for monitor output or through another optional colour space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Windows type displays). The flicker filter is optional
and can be software disabled for use with large
screen area’s of video.
- SUSP# modulation to adjust the system performance in various power down states of the system including full power on state.
The Video output pipeline of the STPC Client interfaces directly to the external digital TV encoder
(STV0119). It takes a 24 bit RGB non-interlaced
pixel stream and converts to a multiplexed 4:2:2
YCrCb 8 bit output stream, the logic includes a
progressive to interlaced scan converter and logic
to insert appropriate CCIR656 timing reference
codes into the output stream. It facilitates the high
quality display of VGA or full screen video streams
received via the Video input port to standard
NTSC or PAL televisions.
The STPC Client core is compliant with the Advanced Power Management (APM) specification
to provide a standard method by which the BIOS
can control the power used by personal computers. The Power Management Unit module (PMU)
controls the power consumption by providing a
comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency's
Energy Star Computer Program. The PMU provides following hardware structures to assist the
software in managing the power consumption by
the system.
- System Activity Detection.
- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- Power control outputs to disable power from different planes of the board.
Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put
the system in decreasing states of power consumption. Alternatively, system activity in a power
down state can generate SMI interrupt to allow the
software to bring the system back up to full power
on state. The chip-set supports up to three power
down states: Doze state, Stand-by state and Suspend mode. These correspond to decreasing levels of power savings.
Power down puts the STPC Client into suspend
mode. The processor completes execution of the
current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped.
A reference design for the STPC Client is available including the schematics and layout files, the
design is a PC ATX motherboard design. The design is available as a demonstration board for application and system development.
The STPC Client is supported by several BIOS
vendors, including the super I/O device used in
the reference design. Drivers for 2D accelerator,
video features and EIDE are available on various
operating systems.
The STPC Client has been designed using modern reusable modular design techniques, it is possible to add to or remove the standard features of
the STPC Client or other variants of the 5ST86
family. Contact your local STMicroelectonics sales
office for further information.
- House-keeping activity detection.
- House-keeping timer to cope with short bursts
of house-keeping activity while dozing or in stand-
8/61
Issue 2.2 - October 13, 2000
GENERAL DESCRIPTION
Figure 1-1. Functional description.
x86
Core
ISA BUS
Host I/F
ISA
IPC
PCI m/s
EIDE
EIDE
PCI BUS
PCI m/s
CCIR Input
VIP
TV Output
Anti-Flicker
Video
pipeline
2D
SVGA
CRTC
Colour
Key
Colour Space
Monitor
Chroma
HW Cursor
SYNC Output
DRAM
Issue 2.2 - October 13, 2000
9/61
GENERAL DESCRIPTION
Figure 1-2. Pictorial Block Diagram Typical Application
Super I/O
RTC
Keyboard / Mouse
Serial Ports
Parallel Port
Floppy
Flash
2x EIDE
ISA
DMUX
MUX
Monitor
IRQ
SVGA
MUX
DMA.REQ
TV
S-VHS
STPC Client
RGB
PAL
DMA.ACK
STV0119
DMUX
NTSC
Video
CCIR601
CCIR656
PCI
4x 16-bit EDO DRAMs
10/61
Issue 2.2 - October 13, 2000
PIN DESCRIPTION
2.PIN DESCRIPTION
2.1. INTRODUCTION
Table 2-1. Signal Description
Group name
Basic Clocks reset & Xtal (SYS)
Memory Interface (DRAM)
PCI interface (excluding VDD5)
ISA / IDE / IPC combined interface
Video Input (VIP)
TV Output (TV)
VGA Monitor interface (VGA)
Grounds
VDD
Analog specific VCC/VDD
Reserved/Test/ Misc./ Speaker
Total Pin Count
The STPC Client integrates most of the functionalities of the PC architecture. As a result, many of
the traditional interconnections between the host
PC microprocessor and the peripheral devices are
totally assimilated to the STPC Client. This offers
improved performance due to the tight coupling of
the processor core and its peripherals. As a result
many of the external pin connections are made directly to the on-chip peripheral functions.
Figure 2-1 shows the STPC Client’s external interfaces. It defines the main busses and their function. Table 2-1 describes the physical implementation listing signals type and their functionality. Table 2-2 provides a full pin listing and description of
the pins. Table 2-3 provides a full listing of pin locations of the STPC Client package by physical
connection. Please refer to the pin allocation
drawing for reference.
Qty
14
89
54
83
9
10
10
69
26
14
10
388
Note: Several interface pins are multiplexed with
other functions, refer to the Pin Description section for further details
Figure 2-1. STPC Client External Interfaces
STPC CLIENT
X86
NORTH
PCI
DRAM
VGA
VIP
TV
89
10
9
10
54
Issue 2.2 - October 13, 2000
SOUTH
SYS
ISA/IDE
IPC
14
73
10
11/61
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
Signal Name
Dir
BASIC CLOCKS RESETS & XTAL
SYSRSTI#
I
SYSRSTO#*
O
XTALI
I
XTALO
I/O
PCI_CLKI
I
PCI_CLKO
O
ISA_CLK
O
ISA_CLK2X
O
OSC14M*
O
HCLK*
O
DEV_CLK
O
GCLK2X*
I/O
DCLK*
I/O
DCLK _DIR*
I
VDD_xxx_PLL
Description
System Reset / Power good
Reset Output to System
14.3MHz External Oscillator Input
14.3MHz External Oscillator Input
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x 2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Host Clock (Test)
24MHz Peripheral Clock (floppy drive)
80MHz Graphics Clock
135MHz Dot Clock
Dot Clock Direction
Power Supply for PLL Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MEMORY INTERFACE
MA[11:0]
RAS#[3:0]
CAS#[7:0]
MWE#
MD[63:0]*
O
O
O
O
I/O
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
12
4
8
1
64
PCI INTERFACE
AD[31:0]*
CBE[3:0]*
FRAME#*
TRDY#*
IRDY#*
STOP#*
DEVSEL#*
PAR*
SERR#*
LOCK#
PCI_REQ#[2:0]*
PCI_GNT#[2:0]*
PCI_INT[3:0]*
VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
I
I
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Target Ready
Initiator Ready
Stop Transaction
Device Select
Parity Signal Transactions
System Error
PCI Lock
PCI Request
PCI Grant
PCI Interrupt Request
5V Power Supply for PCI ESD protection
32
4
1
1
1
1
1
1
1
1
3
3
4
4
ISA AND IDE COMBINED ADDRESS/DATA
LA[23:22]*/ SCS3#,SCS1#
I/O
Unlatched Address (ISA) / Secondary Chip Select (IDE)
LA[21:20]*/ PCS3#,PCS1#
I/O
Unlatched Address (ISA) / Primary Chip Select (IDE)
LA[19:17]*/ DA[2:0]
O
Unlatched Address (ISA) / Address (IDE)
RMRTCCS#* / DD[15]
I/O
ROM/RTC Chip Select / Data Bus bit 15 (IDE)
KBCS#* / DD[14]
I/O
Keyboard Chip Select / Data Bus bit 14 (IDE)
Note; * denotes theat the pin is V5T (see Section 4. )
12/61
Issue 2.2 - October 13, 2000
Qty
2
2
3
1
1
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
Signal Name
RTCRW#* / DD[13]
RTCDS#* / DD[12]
SA[19:8]* / DD[11:0]
SA[7:0]
SD[15:0]*
Dir
I/O
I/O
I/O
I/O
I/O
ISA/IDE COMBINED CONTROL
IOCHRDY* / DIORDY
I/O
ISA CONTROL
ALE*
O
BHE#*
I/O
MEMR#*, MEMW#*
I/O
SMEMR#*, SMEMW#*
O
IOR#*, IOW#*
I/O
MASTER#*
I
MCS16#*, IOCS16#*
I
REF#*
O
AEN*
O
IOCHCK#*
I
ISAOE#*
O
GPIOCS#*
I/O
IDE CONTROL
PIRQ*
SIRQ*
PDRQ*
SDRQ*
PDACK#*
SDACK#*
PIOR#*
PIOW#*
SIOR#*
SIOW#*
IPC
IRQ_MUX[3:0]*
DREQ_MUX[1:0]*
DACK_ENC[2:0]*
TC*
MONITOR INTERFACE
RED, GREEN, BLUE
VSYNC*
HSYNC*
VREF_DAC
RSET
COMP
SCL / DDC[1]*
Description
RTC Read/Write / Data Bus bit 13 (IDE)
RTC Data Strobe / Data Bus bit 12 (IDE)
Latched Address (ISA) / Data Bus (IDE)
Latched Address (IDE)
Data Bus (ISA)
Qty
1
1
16
4
16
I/O Channel Ready (ISA) - Busy/Ready (IDE)
1
Address Latch Enable
System Bus High Enable
Memory Read and Memory Write
System Memory Read and Memory Write
I/O Read and Write
Add On Card Owns Bus
Memory/IO Chip Select16
Refresh Cycle.
Address Enable
I/O Channel Check.
Bidirectional OE Control
General Purpose Chip Select
1
1
2
2
2
1
2
1
1
1
1
1
I
I
I
I
O
O
I/O
O
I/O
O
Primary Interrupt Request
Secondary Interrupt Request
Primary DMA Request
Secondary DMA Request
Primary DMA Acknowledge
Secondary DMA Acknowledge
Primary I/O Read
Primary I/O Write
Secondary I/O Read
Secondary I/O Write
1
1
1
1
1
1
1
1
1
1
I
I
O
O
Multiplexed Interrupt Request
Multiplexed DMA Request
DMA Acknowledge
ISA Terminal Count
4
2
3
1
O
O
O
I
I
I
I/O
Red, Green, Blue
Vertical Synchronization
Horizontal Synchronization
DAC Voltage reference
Resistor Set
Compensation
I²C Interface - Clock / Can be used for VGA DDC[1] signal
3
1
1
1
1
1
1
Note; * denotes theat the pin is V5T (see Section 4. )
Issue 2.2 - October 13, 2000
13/61
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
Signal Name
SDA / DDC[0]*
Dir
I/O
Description
I²C Interface - Data / Can be used for VGA DDC[0] signal
Qty
1
VIDEO INPUT
VCLK*
VIN[7:0]*
I
I
Pixel Clock
YUV Video Data Input CCIR 601 or 656
1
8
DIGITAL TV OUTPUT
TV_YUV[7:0]*
ODD_EVEN*
VCS*
O
O
O
Digital Video Outputs
Frame Synchronisation
Horizontal Line Synchronisation
8
1
1
MISCELLANEOUS
ST[6:0]
CLKDEL[2:0]*
I/O
I/O
Test/Misc. pins
Reserved (Test/Misc pins)
7
3
Note; * denotes theat the pin is V5T (see Section 4. )
14/61
Issue 2.2 - October 13, 2000
PIN DESCRIPTION
2.2.SIGNAL DESCRIPTIONS
2.2.1.
BASIC CLOCKS RESETS & XTAL
PWGD System Reset/Power good. This input is
low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
XTALI 14.3MHz Pull Down (10 kΩ)
XTALO 14.3MHz External Oscillator Input These
pins are the 14.318 MHz external oscillator input;
This clock is used as the reference clock for the internal frequency synthesizer to generate the
HCLK, CLK24M, GCLK2X and DCLK clocks.
Note: These pins are NOT 5V tolerant
(see Table 4-2)
HCLK Host Clock. This is the host 1X clock. Its
frequency can vary from 25 to 75 MHz. All host
transactions and PCI transactions are synchronized to this clock. This clock drives the DRAM
controller to execute the host transactions. In normal mode, this output clock is generated by the internal PLL.
GCLK2X 80MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics engine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal frequency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can replace the internal frequency synthesizer.
DCLK 135MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can go from 8MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.
DCLK_DIR Dot Clock Direction. Specifies if DCLK
is an input (0) or an output (1).
DEV_CLK 24MHz Peripheral Clock Output. This
24MHZ signal is provided as a convenience for
the system integration of a floppy disk driver function in an external chip.
2.2.2.
MEMORY INTERFACE
MA[11:0] Memory Address Output. These 12 multiplexed memory address pins support external
DRAM with up to 4K refresh. These include all
16M x N and some 4M x N DRAM modules. The
address signals must be externally buffered to
support more than 16 DRAM chips. The timing of
these signals can be adjusted by software to
match the timings of most DRAM modules.
MD[63:0] Memory Data I/O. This is the 64-bit
memory data bus. If only half of a bank is populated, MD63-32 is pulled high, data is on MD31-0.
MD[40-0] are read by the device strap option registers during rising edge of PWGD.
RAS#[3:0] Row Address Strobe Output. There
are 4 active low row address strobe outputs, one
for each bank of the memory. Each bank contains
4 or 8-Bytes of data. The memory controller allows
half of a bank (4 Bytes) to be populated to enable
memory upgrade at finer granularity.
The RAS# signals drive the SIMMs directly without any external buffering. These pins are always
outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the
value of the RAS# signals at the pins.
CAS#[7:0] Column Address Strobe Output. There
are 8 active low column address strobe outputs,
one for each Byte of the memory.
The CAS# signals drive the SIMMs either directly
or through external buffers.
These pins are always outputs, but they can also
simultaneously be inputs, to allow the memory
controller to monitor the value of the CAS# signals
at the pins.
MWE# Write Enable Output. Write enable specifies whether the memory access is a read (MWE#
= H) or a write (MWE# = L). This single write enable controls all DRAMs. It can be externally buffered to boost the maximum number of loads
(DRAM chips) supported.
The MWE# signals drive the SIMMs directly without any external buffering.
2.2.3.
VIDEO INPUT
VCLK Pixel Clock Input.
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus interfaces with an MPEG video decoder output port
and typically carries a stream of Cb, Y, Cr, Y digital video at VCLK frequency, clocked on the rising
edge (by default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr, Y input multiplex is supported for double
encoding applications (rising and falling edge of
CKREF are operating).
Issue 2.2 - October 13, 2000
15/61
PIN DESCRIPTION
2.2.4.
TV OUTPUT
DEVSEL# I/O Device Select. This signal is used
as an input when the STPC Client initiates a bus
cycle on the PCI bus to determine if a PCI slave
device has decoded itself to be the target of the
current transaction. It is asserted as an output either when the STPC Client is the target of the current PCI transaction or when no other device asserts DEVSEL# prior to the subtractive decode
phase of the current PCI transaction.
TV_YUV[7:0] Digital video outputs.
ODD_EVEN Frame Synchronization .
VCS Horizontal Line Synchronization.
2.2.5.
PCI INTERFACE
PCI_CLKI 33MHz PCI Input Clock This signal is
the PCI bus clock input and should be driven from
the PCI_CLKO pin.
PCI_CLKO 33MHz PCI Output Clock. This is the
master PCI bus clock output.
AD[31:0] PCI Address/Data. This is the 32-bit PCI
multiplexed address and data bus. This bus is
driven by the master during the address phase
and data phase of write transactions. It is driven
by the target during data phase of read transactions. Signals AD[12:11] for internal use only. Not
to be used for External PCI devices.
CBE#[3:0] Bus Commands/Byte Enables. These
are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Client owns the bus and outputs
when the STPC Client owns the bus.
FRAME# Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Client owns
the PCI bus.
TRDY# Target Ready. This is the target ready signal of the PCI bus. It is driven as an output when
the STPC Client is the target of the current bus
transaction. It is used as an input when STPC Client initiates a cycle on the PCI bus.
IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Client initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to the STPC Client to determine when the
current PCI master is ready to complete the current transaction.
STOP# Stop Transaction. Stop is used to implement the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cycles initiated by the STPC Client and is used as an
output when a PCI master cycle is targeted to the
STPC Client.
16/61
PAR Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master during the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock
cycle)
SERR# System Error. This is the system error signal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if the target aborts an
STPC Client initiated PCI transaction. Its assertion
by either the STPC Client or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.
LOCK# PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
PCI_REQ#[2:0] PCI Request. These pins are the
three external PCI master request pins. They indicate to the PCI arbiter that the external agents require use of the bus.
PCI_GNT#[2:0] PCI Grant. These pins indicate
that the PCI bus has been granted master, requesting it on its PCI_REQ#.
2.2.6.
ISA/IDE COMBINED ADDRESS/DATA
LA[23]/SCS3# Unlatched Address (ISA) / Secondary Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active
or the IDE bus is active.
When the ISA bus is active, this pins is ISA Bus
unlatched address bit 23 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pins is in input
mode.
When the IDE bus is active, this signals is used as
the active high secondary slave IDE chip select
signal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.
Issue 2.2 - October 13, 2000
PIN DESCRIPTION
LA[22]/SCS1# Unlatched Address (ISA) / Secondary Chip Select (IDE) This pin has two functions, depending on whether the ISA bus is active
or the IDE bus is active.
When the ISA bus is active, this pin is ISA bus unlatched address bit 22 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pin is in input mode.
When the IDE bus is active, this signal is used as
the active high secondary slave IDE chip select
signal. This signal is to be externally ANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.
LA[21]/PCS3# Unlatched Address (ISA) / Primary
Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active or the
IDE bus is active.
When the ISA bus is active, this pin is ISA Bus unlatched address bit 21 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pin is in input mode.
When the IDE bus is active, this signas is used as
the active high primary slave IDE chip select signal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.
LA[20]/PCS1# Unlatched Address (ISA) / Primary
Chip Select (IDE). This pin has two functions, depending on whether the ISA bus is active or the
IDE bus is active.
When the ISA bus is active, this pin is ISA Bus unlatched address bit 20 for 16-bit devices. When
the ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pin is in input mode.
When the IDE bus is active, this signals is used as
the active high primary slave IDE chip select signal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.
LA[19:17]/DA[2:0] Unlatched Address (ISA) / Address (IDE). These pins are multi-function pins.
They are used as the ISA bus unlatched address
bits [19:17] for ISA bus or the three address bits
for the IDE bus devices.
When used by the ISA bus, these pins are ISA bus
unlatched address bits 19-17 on 16-bit devices.
When the ISA bus is accessed by any cycle initiated from the PCI bus, these pins are in output
mode. When an ISA bus master owns the bus,
these pins are tristated.
For IDE devices, these signals are used as the
DA[2:0] and are connected directly or through a
buffer to DA[2:0] of the IDE devices. If the toggling
of signals are to be masked during ISA bus cycles,
they can be externally ORed before being connected to the IDE devices.
SA[19:8]/DD[11:0] Unlatched Address (ISA) /
Data Bus (IDE). These are multifunction pins.
When the ISA bus is active, they are used as the
ISA bus system address bits 19-8. When the IDE
bus is active, they serve as IDE signals DD[11:0].
These pins are used as an input when an ISA bus
master owns the bus and are outputs at all other
times.
IDE devices are connected to SA[19:8] directly
and the ISA bus is connected to these pins
through two LS245 transceivers. The transceiver
OEs are connected to ISAOE# and the DIR is connected to MASTER#. The transceiver bus signals
are connected to the CPC and IDE DD busses
and B bus signals are connected to ISA SA bus.
DD[15:12] Databus (IDE). The high 4 bits of the
IDE databus are combined with several of the Xbus lines. Refer to the following section for X-bus
pins for further information.
SA[7:0] ISA Bus address bits [7:0]. These are the
8 low bits of the system address bus of ISA on 8bit slot. These pins are used as an input when an
ISA bus master owns the bus and are outputs at
all other times.
SD[15:0] I/O Data Bus (ISA). These pins are the
external databus to the ISA bus.
2.2.7.
ISA/IDE COMBINED CONTROL
IOCHRDY/DIORDY Channel Ready (ISA) / Busy /
Ready (IDE). This is a multi-function pin. When
the ISA bus is active, this pin is IOCHRDY. When
the IDE bus is active, this serves as IDE signal DIORDY.
IOCHRDY is the I/O channel ready signal of the
ISA bus and is driven as an output in response to
an ISA master cycle targeted to the host bus or an
internal register of the STPC Client. The STPC
Client monitors this signal as an input when performing an ISA cycle on behalf of the host CPU,
DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Client since
the access to the system memory can be considerably delayed due to CRT refresh or a write back
cycle.
Issue 2.2 - October 13, 2000
17/61
PIN DESCRIPTION
2.2.8.
ISA CONTROL
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host Bus) in the system.
The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is
an externally buffered version of this output.
ISA_CLK ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of either the PCICLK or
OSC14M.
ISA_CLKX2 ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal at
twice the frequency of the Clock signal for the ISA
bus. It is also used with ISA_CLK as the multiplexor control lines for the Interrupt Controller Interrupt
input lines.
OSC14M ISA Bus Synchronization Clock Output.
This is the buffered 14.318 Mhz clock to the ISA
bus.
ALE Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Client to indicate that LA23-17,
SA19-0, AEN and SBHE# signals are valid. The
ALE is driven high during refresh, DMA master or
ISA master cycles by the STPC Client.
ALE is driven low after reset.
BHE# System Bus High Enable. This signal, when
asserted, indicates that a data Byte is being transferred on SD15-8 lines. It is used as an input when
an ISA master owns the bus and is an output at all
other times.
MEMR# Memory Read. This is the memory read
command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW# Memory Write. This is the memory write
command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an
output at all other times.
SMEMR# System Memory Read. The STPC Client generates SMEMR# signal of the ISA bus only
when the address is below 1MByte or the cycle is
a refresh cycle.
18/61
SMEMW# System Memory Write. The STPC Client generates SMEMW# signal of the ISA bus
only when the address is below 1MByte.
IOR# I/O Read. This is the I/O read command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other
times.
IOW# I/O Write. This is the I/O write command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other
times.
MASTER# Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
MCS16# Memory Chip Select 16. This is the decode of LA23-17 address pins of the ISA address
bus without any qualification of the command signal lines. MCS16# is always an input. The STPC
Client ignores this signal during I/O and refresh
cycles.
IOCS16# I/O Chip Select 16. This signal is the decode of SA15-0 address pins of the ISA address
bus without any qualification of the command signals. The STPC Client does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Client is executed as an extended 8-bit I/O cycle.
REF# Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Client performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a refresh cycle.
The STPC Client performs a pseudo hidden refresh. It requests the host bus for two host clocks
to drive the refresh address and capture it in external buffers. The host bus is then relinquished
while the refresh cycle continues on the ISA bus.
AEN Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling
of the signal indicates to I/O devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK# I/O Channel Check. I/O Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
Issue 2.2 - October 13, 2000
PIN DESCRIPTION
ISAOE# Bidirectional OE Control. This signal controls the OE signal of the external transceiver that
connects the IDE DD bus and ISA SA bus.
GPIOCS# I/O General Purpose Chip Select 1.
This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be used by the PMU unit to control the
external peripheral devices to power down or any
other desired function.
This pin is also serves as a strap input during reset.
2.2.9.
IDE CONTROL
PIRQ Primary Interrupt Request. Interrupt request
from primary IDE channel.
SIRQ Secondary Interrupt Request. Interrupt request from secondary IDE channel.
PDRQ Primary DMA Request. DMA request from
primary IDE channel.
SDRQ Secondary DMA Request. DMA request
from secondary IDE channel.
PDACK# Primary DMA Acknowledge. DMA acknowledge to primary IDE channel.
SDACK# Secondary DMA Acknowledge. DMA
acknowledge to secondary IDE channel.
PIOR# Primary I/O Read. Primary channel read.
Active low output.
PIOW# Primary I/O Write. Primary channel write.
Active low output.
SIOR# Secondary I/O Read . Secondary channel
read. Active low output.
SIOW# Secondary I/O Write. Secondary channel
write. Active low output.
IDE DD[15] signal.
This signal must be ORed externally with ISAOE#
and is then connected to ROM and RTC. An
LS244 or equivalent function can be used if OE# is
connected to ISAOE# and the output is provided
with a weak pull-up resistor.
KBCS# / DD[14] Keyboard Chip Select. This pin
is a multi-function pin. When ISAOE# is active,
this signal is used as KBCS#. This signal is asserted if a keyboard access is decoded during a I/O
cycle.
When ISAOE# is inactive, this signal is used as
IDE DD[14] signal.
This signal must be ORed externally with ISAOE#
and is then connected to the keyboard. An LS244
or equivalent function can be used if OE# is connected to ISAOE# and the output is provided with
a weak pull-up resistor.
RTCRW# / DD[13] Real Time Clock RW. This pin
is a multi-function pin. When ISAOE# is active,
this signal is used as RTCRW#. This signal is asserted for any I/O write to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[13] signal.
This signal must be ORed externally with ISAOE#
and then connected to the RTC. An LS244 or
equivalent function can be used if OE# is connected to ISAOE# and the output is provided with a
weak pull-up resistor.
RTCDS# / DD[12] Real Time Clock DS. This pin is
a multi-function pin. When ISAOE# is active, this
signal is used as RTCDS. This signal is asserted
for any I/O read to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[12] signal.
This signal must be ORed externally with ISAOE#
and is then connected to RTC. An LS244 or equivalent function can be used if OE# is connected to
ISAOE# and the output is provided with a weak
pull-up resistor.
2.2.11. IPC
2.2.10. X-BUS INTERFACE PINS / IDE DATA
RMRTCCS# / DD[15] ROM/Real Time Clock Chip
Select. This pin is a multi-function pin. When
ISAOE# is active, this signal is used as RMRTCCS#. This signal is asserted if a ROM access
is decoded during a memory cycle. It should be
combined with MEMR# or MEMW# signals to
properly access the ROM. During an I/O cycle,
this signal is asserted if access to the Real Time
Clock (RTC) is decoded. It should be combined
with IOR#+ or IOW# signals to properly access the
real time clock.
When ISAOE# is inactive, this signal is used as
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC Client using ISACLK and ISACLKX2 as the input selection strobes.
Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the
interrupt controller, so that it may be connected directly to the IRQ pin of the RTC.
PCI_INT[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals. They are to be encoded before connection to the STPC Client using
Issue 2.2 - October 13, 2000
19/61
PIN DESCRIPTION
ISACLK and ISACLKX2 as the input selection
strobes.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to
the STPC Client using ISACLK and ISACLKX2 as
the input selection strobes.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Client before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
RSET Resistor Current Set. This reference current input to the RAMDAC is used to set the fullscale output of the RAMDAC.
COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDD to damp oscillations.
DDC[1:0] Direct Data Channel Serial Link. These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I2C electrical specifications, they have opencollector output drivers which are internally connected to VDD through pull-up resistors.
They can instead be used for accessing I²C devices on board. DDC1 and DDC0 correspond to SCL
and SDA respectively.
2.2.12. MONITOR INTERFACE
2.2.13. MISCELLANEOUS
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog color outputs from the RAMDACs. These signals are sensitive to interference,
therefore they need to be properly shielded.
ST[6], Reserved.
ST[5] This is used for speaker output.
ST[4] Reserved.
VSYNC Vertical Synchronization Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronization Pulse. This is
the horizontal synchronization signal from the
VGA controller.
ST[3:0] The pins are for testing the STPC. The
default settings on these pins should be 1111 for
the STPC to function correctly. By setting the
ST[3:0] to 0111, the STPC is tristated.
CLKDEL[2:0] Reserved. The pins are reserved
for Test and Miscellaneous functions)
VREF_DAC DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
20/61
Issue 2.2 - October 13, 2000
PIN DESCRIPTION
Table 2-3. Pinout.
Pin #
AF3
AF15
AE16
G23
F25
AC5
AD5
AF5
AD15
AF16
AC15
AE17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AF19
AD18
AE20
AC19
AF20
AE21
AC20
AF21
AD20
AE22
AF22
AD21
AE23
AC22
AF23
AE24
AF24
AD25
AC25
AC26
AB24
AA25
AA24
Y25
Y24
V23
W24
V26
V24
Pin name
PWGD
XTALI
XTALO
HCLK
DEV_CLK
GCLK2X
DCLK
DCLK_DIR
MA[0]
MA[1]
MA[2]
MA[3]
MA[4]
MA[5]
MA[6]
MA[7]
MA[8]
MA[9]
MA[10]
MA[11]
RAS#[0]
RAS#[1]
RAS#[2]
RAS#[3]
CAS#[0]
CAS#[1]
CAS#[2]
CAS#[3]
CAS#[4]
CAS#[5]
CAS#[6]
CAS#[7]
MWE#
MD[0]
MD[1]
MD[2]
MD[3]
MD[4]
MD[5]
MD[6]
MD[7]
MD[8]
MD[9]
MD[10]
MD[11]
MD[12]
MD[13]
MD[14]
Pin #
U23
U24
R26
P25
P26
N25
N26
M25
M26
M24
M23
L24
J25
J26
H26
G25
G26
AD22
AD23
AE26
AD26
AC24
AB25
AB26
Y23
AA26
Y26
W25
W26
V25
U25
U26
T25
R25
T24
R23
R24
N23
P24
N24
L25
L26
K25
K26
K24
H25
J24
H23
H24
Pin name
MD[15]
MD[16]
MD[17]
MD[18]
MD[19]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
MD[28]
MD[29]
MD[30]
MD[31]
MD[32]
MD[33]
MD[34]
MD[35]
MD[36]
MD[37]
MD[38]
MD[39]
MD[40]
MD[41]
MD[42]
MD[43]
MD[44]
MD[45]
MD[46]
MD[47]
MD[48]
MD[49]
MD[50]
MD[51]
MD[52]
MD[53]
MD[54]
MD[55]
MD[56]
MD[57]
MD[58]
MD[59]
MD[60]
MD[61]
MD[62]
MD[63]
Issue 2.2 - October 13, 2000
Pin #
F24
D25
A20
C20
B19
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
B15
A15
C16
D15
A14
C15
B13
D13
A13
C14
C13
A12
B11
C12
A11
D12
B10
C11
A10
D10
C10
A9
B8
A8
B7
D8
A7
C8
B6
D7
A6
C21
A21
B20
Pin name
PCI_CLKI
PCI_CLKO
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
CBE[0]
CBE[1]
CBE[2]
CBE[3]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
SERR#
LOCK#
PCI_REQ#[0]
PCI_REQ#[1]
PCI_REQ#[2]
21/61
PIN DESCRIPTION
Pin #
C22
B21
D20
D24
C26
A25
B24
Pin name
PCI_GNT#[0]
PCI_GNT#[1]
PCI_GNT#[2]
PCI_INT[0]
PCI_INT[1]
PCI_INT[2]
PCI_INT[3]
F2
G4
F3
F1
G2
G3
H2
J4
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
L1
M2
M1
L3
N2
M4
N1
M3
P4
P3
R2
N3
P1
R1
T2
R3
T1
R4
U2
T3
U1
U4
V2
LA[17]/DA[0]
LA[18]/DA[1]
LA[19]/DA[2]
LA[20]/PCS1#
LA[21]/PCS3#
LA[22]/SCS1#
LA[23]/SCS3#
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]/DD[0]
SA[9]/DD[1]
SA[10]/DD[2]
SA[11]/DD[3]
SA[12] / DD[4]
SA[13] / DD[5]
SA[14] / DD[6]
SA[15] / DD[7]
SA[16] / DD[8]
SA[17] / DD[9]
SA[18] / DD[10]
SA[19] / DD[11]
RTCDS / DD[12]
RTCRW# / DD[13]
KBCS# / DD[14]
RMRTCCS# / DD[15]
SD[0]
SD[1]
SD[2]
SD[3]
SD[4]
SD[5]
SD[6]
SD[7]
SD[8]
SD[9]
22/61
Pin #
U3
V1
W2
W1
V3
Y2
AE4
AD4
AE5
C6
W3
AA2
Y4
AA1
Y3
AB2
AA3
AC2
AB4
AC1
AB3
AD2
AC3
AD1
AF2
AE3
Y1
Pin name
SD[10]
SD[11]
SD[12]
SD[13]
SD[14]
SD[15]
SYSRSTO#
ISA_CLK
ISA_CLK2X
OSC14M
ALE
BHE#
MEMR#
MEMW#
SMEMR#
SMEMW#
IOR#
IOW#
MASTER#
MCS16#
IOCS16#
REF#
AEN
IOCHCK#
ISAOE#
GPIOCS#
IOCHRDY
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
PIRQ
SIRQ
PDRQ
SDRQ
PDACK#
SDACK#
PIOR#
PIOW#
SIOR#
SIOW#
E23
D26
E24
C25
A24
B23
C23
A23
B22
D22
IRQ_MUX[0]
IRQ_MUX[1]
IRQ_MUX[2]
IRQ_MUX[3]
DREQ_MUX[0]
DREQ_MUX[1]
DACK_ENC[0]
DACK_ENC[1]
DACK_ENC[2]
TC
Issue 2.2 - October 13, 2000
Pin #
AE6
AD6
AF6
AE9
AF9
AD7
AE8
AC9
AF8
AD8
Pin name
RED
GREEN
BLUE
VSYNC
HSYNC
VREF_DAC
RSET
COMP
DDC[1] / SCL
DDC[0] / SDA
AD14
AE13
AC12
AD12
AE14
AC14
AF14
AD13
AE15
VCLK
VIN[0]
VIN[1]
VIN[2]
VIN[3]
VIN[4]
VIN[5]
VIN[6]
VIN[7]
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE10
AD9
VTV_YUV[0]
VTV_YUV[1]
VTV_YUV[2]
VTV_YUV[3]
VTV_YUV[4]
VTV_YUV[5]
VTV_YUV[6]
VTV_YUV[7]
VCS
ODD_EVEN
B4
D5
A4
C5
B3
C4
A3
C7
B5
A5
ST[0]
ST[1]
ST[2]
ST[3]
ST[4]
ST[5]
ST[6]
CLKDEL[0]
CLKDEL[1]
CLKDEL[2]
AC7
AF4
W4
AB1
F26
G24
VDD_DAC1
VDD_DAC2
VDD_GCLK_PLL
VDD_DCLK_PLL
VDD_HCLK_PLL
VDD_DEVCLK_PLL
PIN DESCRIPTION
Pin #
A16
B12
B9
D18
A22
B14
C9
D6
D11
D16
D21
F4
F23
G1
K23
L4
L23
P2
T4
T23
T26
AA4
AA23
AB23
AC6
AC11
AC16
AC21
AD19
AF13
VDD5
VDD5
VDD5
VDD5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pin name
AE7
AF7
E25
E26
A1:2
A26
B2
B25:26
C3
C24
D4
D9
D14
D19
D23
H4
J23
L11:16
VSS_DAC1
VSS_DAC2
VSS_DLL
VSS_DLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin #
M11:16
N4
N11:16
P11:16
P23
R11:16
T11:16
V4
W23
AC4
AC8
AC13
AC18
AC23
AD3
AD24
AE1:2
AE25
AF1
AF25
AF26
Pin name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Issue 2.2 - October 13, 2000
23/61
PIN DESCRIPTION
24/61
Issue 2.2 - October 13, 2000
UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
2.3 UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
The following changes have been made to the Pin Description Chapter on 11/02/2000
Section
2.2.5.
Change
Added
Text
“Signals AD[12:11] for internal use only. Not to be used for External PCI devic-
es.”
The following changes have been made to the Pin Description Chapter on 08/02/2000
Section
2.2.3.
Change
Replaced
Text
Signals VIDEO_D[7:0] with VIN, VTV_BT# with ODD_EVEN, VTV_SYNCH with VCS.
The following changes have been made to the Pin Description Chapter on 13/01/2000
Section
2.2.
Change
Added
Text
“to a minimum of 8MHz”
DCLK Dot Clock / Pixel clock. This clock supplies the display controller, the video pipeline, the ramdac,
and the TV output logic. Its value is dependent on the selected display mode.
Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of
8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register
bit.
The following changes have been made to the Pin Description Chapter on 28/09/99
Section
Change
Table 2-1. Changed
Figure 2-1. Changed
Table 2-2. Replaced
2.2.1.
2.2.1.
2.2.3.
Moved
Moved
Replaced
Text
Updated signal pin counts and added abbreviations to table.
Updated External interface pin count
“PWGD” with “SYSRSTI#”
PCI_CLKI and PCI_CLKO moved from 2.2.1. to 2.2.5.
ISA_CLK and ISA_CLKX2 moved from 2.2.1. to 2.2.8.
“Video Interface” with “Video Input”
The following changes have been made to the Pin Description Chapter on 23/09/99
The following changes have been made to the Pin Description Chapter on 11/08/99
Issue 2.2 - October 13, 2000
25/61
UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
Section
Change
2.2.13.
Added
Text
“Note;
By setting signals ST[3:0] to the following value allows the STPC to be put
Tristate. This means the STPC is switched off and no signals are being driven.“
Removed statement; “The direction can be controlled by a strap option or an internal register bit.”
The following changes have been made to the Pin Description Chapter from Revision 1.0 to Release 1.2.
Section
Change
2.1.
Replaced
2.2.1.
Replaced
2.2.1.
Replaced
2.2.6.
Replaced
2.2.6.
Replaced
26/61
Text
“internal” With “assimilated “
“The DRAM controller to execute the host transactions is also driven by this
clock”
With
“This clock drives the DRAM controller to execute the host transactions”
“AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data
bus of the PCI. This bus is driven by the master during the address phase and
data phase of write transactions. It is driven by the target during data phase of
read transactions.”
With
“AD[31:0] PCI Address/Data. This is the 32-bit PCI multiplexed address and
data bus. This bus is driven by the master during the address phase and data
phase of write transactions. It is driven by the target during data phase of read
transactions.”
“IDE devices are connected to SA[19:8] directly and ISA bus is connected to
these pins through two LS245 transceivers. The OE of the transceivers are
connected to ISAOE# and the DIR is connected to MASTER #. The A bus signals of the transceivers are connected to CPC and IDE DD bus and the B bus
signals are connected to ISA SA bus.”
With
“IDE devices are connected to SA[19:8] directly and the ISA bus is connected
to these pins through two LS245 transceivers. The transceiver OEs are connected to ISAOE# and the DIR is connected to MASTER#. The transceiver bus
signals are connected to the CPC and IDE DD busses and B bus signals are
connected to ISA SA bus.”
“For IDE devices, these signals are used as the DA[2:0] and are connected to
DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals is to
be masked during ISA bus cycles, they can be externally ORed before being
connected to the IDE devices.”
With
“For IDE devices, these signals are used as the DA[2:0] and are connected directly or through a buffer to DA[2:0] of the IDE devices. If the toggling of signals
are to be masked during ISA bus cycles, they can be externally ORed before
being connected to the IDE devices.”
Issue 2.2 - October 13, 2000
UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
Section
Change
2.2.8.
Replaced
2.2.12.
Added
2.2.12.
Replaced
Text
“IOCS16# IO Chip Select16. This signal is the decode of the ISA bus SA15-0
address pins of without any qualification of the command signals. The STPC
Client does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal register of the STPC Client is executed as an extended 8-bit
IO cycle.”
With
“IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins
of the ISA address bus without any qualification of the command signals. The
STPC Client does not drive IOCS16# (similar to PC-AT design). An ISA master
access to an internal register of the STPC Client is executed as an extended 8bit IO cycle.”
“They can instead be used for accessing I²C devices on board. DDC1 and
DDC0 correspond to SCL and SDA respectively.”
Updated table 3
Issue 2.2 - October 13, 2000
27/61
UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
28/61
Issue 2.2 - October 13, 2000
STRAP OPTION
3. STRAP OPTION
This chapter defines the STPC Client Strap Options and their location
Memory
Data
Refer to
Lines
MD0
MD1
MD2
DRAM Bank 1
MD3
MD4
MD5
DRAM Bank 0
MD6
MD7
MD8
MD9
MD10
DRAM Bank 3
MD11
MD12
MD13
DRAM Bank 2
MD14
MD15
MD16
MD17
PCI Clock
MD18
MD19
MD20
MD21
MD22
MD23
MD24
HCLK
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
-
Designation
Location
Reserved
Reserved
Speed
Speed
Type
Speed
Speed
Type
Reserved
Reserved
Speed
Speed
Type
Speed
Speed
Type
Reserved
PCI_CLKO Divisor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HCLK PLL Speed
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Index 4A, bit 2
Index 4A, bit 3
Index 4A, bit 4
Index 4A, bit 5
Index 4A, bit 6
Index 4A, bit 7
Index 4B, bit 1
Index 4B, bit 2
Index 4B, bit 3
Index 4B, bit 4
Index 4B, bit 5
Index 4B, bit 6
Index 4B, bit 7
Index 4C, bit 0
Index 4C, bit 1
Index 4C, bit 3
Index 4C, bit 4
Index 5F, bit 0
Index 5F, bit 1
Index 5F, bit 2
Index 5F, bit 3
Index 5F, bit 4
Index 5F, bit 5
-
Issue 2.2 - October 13, 2000
Actual
Settings
User defined
Pull up
User defined
User defined
Pull up
User defined
User defined
Pull up
User defined
User defined
Pull up
User defined
Pull up
User defined
Pull up
Pull up
Pull up
Pull up
Pull up
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
Pull up
Pull up
Pull up
Pull up
Pull down
Note 2
Pull up
Pull down
Note 2
-
Set to ’0’
Set to ’1’
70 ns
EDO
70 ns
60 ns
FPM
60 ns
EDO
70 ns
EDO
70 ns
FPM
60 ns
FPM
60 ns
EDO
HCLK /2
000
001
010
011
100
101
110
111
-
FPM
HCLK /3
Reserved
Reserved
Reserved
25 MHz
50 MHz
60 MHz
66 MHz
75 MHz
-
29/61
STRAP OPTION
Memory
Data
Refer to
Lines
MD38
MD39
MD40
MD41
MD42
MD43
-
Designation
Actual
Settings
Location
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note 1; Setting of Strap Options MD [15:2] have
no effect on the DRAM Controller but are purely
meant for software issues. i.e. Readable in a register.
Note 2; The settings for these Straps is show in
the table below:
Devices Settings
MDBT*710Axx
MDBT*70xxxx1
(Old)
(New)
MD [32]
Pull Up (1)
Pull Down (0)
MD[35]
Pull Up (1)
Pull Down (0)
Note 1; All devices with the exception of the technical
codes; MDBT*S710A
Strap Option
The Devices are identified using the techical code
which is the first line laser marked under the ST logo.
For further details refer to Application Note 1297
3.1 Power on strap registers description
3.1.1 Strap register 0 Index 4Ah (Strap0)
-
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Bit 1
Bit 0
Set to ’1’
-
-
Description
SIMM 0 DRAM type
SIMM 0 speed
SIMM 1 DRAM type:
SIMM 1 speed
Reserved
Reserved
Note that the SIMM speed and type information
read here is meant only for the software and is not
used by the hardware. The software must program the Host and graphics dram controller configuration registers appropriately based on these
bits.
This register defaults to the values sampled on
MD[7:0] pins after reset.
3.1.2 Strap register 1 Index 4Bh (Strap1)
Bits 7-0; This register reflect the status of pins
MD[15:8] respectively. They are expected to be
connected on the system board to the SIMM configuration pins as follows:
Bits 7-0; This register reflect the status of pins
MD[7:0] respectively. They are expected to be
connected on the system board to the SIMM configuration pins as follows:
30/61
Set to ’0’
Issue 2.2 - October 13, 2000
STRAP OPTION
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Bit 1
Bit 0
Description
SIMM 2 DRAM type
SIMM 2 speed
SIMM 3 dram type
SIMM 3 speed
Reserved
Reserved
Note that the SIMM speed and type information
read here is meant only for the software and is not
used by the hardware. The software must program the Host and graphics dram controller configuration registers appropriately based on these
bits.
This register defaults to the values sampled on
MD[15:8] pins after reset.
3.1.3 Strap register 2 Index 4Ch (Strap2)
Bits 4-0; This register reflect the status of pins
MD[20:16] respectively.They are use by the chip
as follows:
Bit 4-2; Reserved.
Bit 1; This bit reflects the value sampled on
MD[17] pin and controls the PCI clock output as
follows:
0: PCI clock output = HCLK / 2
1: PCI clock output = HCLK / 3.
Bit 0; Reserved.
This register defaults to the values sampled on
MD[20:16] pins after reset.
3.1.4 HCLK PLL Strap register Index 5Fh
(HCLK_Strap)
Bits 5-0 of this register reflect the status of the
MD[26:21] & are used as follows:
Bit 5-3 These pins reflect the value sampled on
MD[26:24] pins respectively and control the Host
clock frequency synthesizer
Bit 2- 0 Reserved
This register defaults to the values sampled on
above pins after reset.
These pin must not be pulled low for normal system operation.
Issue 2.2 - October 13, 2000
31/61
ELECTRICAL SPECIFICATIONS
4. ELECTRICAL SPECIFICATIONS
4.1 INTRODUCTION
20 kΩ (±10%) pull-up resistor to prevent spurious
operation.
The electrical specifications in this chapter are valid for the STPC Client.
4.2.3 RESERVED DESIGNATED PINS
4.2 ELECTRICAL CONNECTIONS
Pins designated reserved should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could
cause unexpected results and possible circuit
malfunctions.
4.2.1 POWER/GROUND CONNECTIONS/
DECOUPLING
Due to the high frequency of operation of the
STPC Client, it is necessary to install and test this
device using standard high frequency techniques.
The high clock frequencies used in the STPC Client and its output buffer circuits can cause transient power surges when several output buffers
switch output levels simultaneously. These effects
can be minimized by filtering the DC power leads
with low-inductance decoupling capacitors, using
low impedance wiring, and by utilizing all of the
VSS and VDD pins.
4.2.2 UNUSED INPUT PINS
All inputs not used by the designer and not listed
in the table of pin connections in Chapter 3 should
be connected either to VDD or to VSS. Connect
active-high inputs to VDD through a 20 kΩ (±10%)
pull-down resistor and active-low inputs to VSS
and connect active-low inputs to VCC through a
4.3 ABSOLUTE MAXIMUM RATINGS
The following table lists the absolute maximum
ratings for the STPC Client device. Stresses beyond those listed under Table 4-1 limits may
cause permanent damage to the device. These
are stress ratings only and do not imply that operation under any conditions other than those specified in section "Operating Conditions".
Exposure to conditions beyond Table 4-1 may (1)
reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings
(Table 4-1) may also result in reduced useful life
and reliability.
Table 4-1. Absolute Maximum Ratings
Symbol
VDDx
VI, VO
V5T
VESD
TCASE
PTOT
Parameter
DC Supply Voltage
Digital Input and Output Voltage
5Volt Tolerance
ESD Capacity (Human body mode)
Operating Case Temperature (Note 1)
Total Power Dissipation
Minimum
-0.3
-0.3
2.5
1500
-40
-
Note 1 : -40°C limit of TCASE (extended temperature
range) is given a s a preliminary specification and so as
all the -40°C related data.
32/61
Issue 2.2 - October 13, 2000
Maximum
4.0
VDD + 0.3
5.5
V
+115
4.8
Units
V
V
V
°C
W
ELECTRICAL SPECIFICATIONS
4.4 DC CHARACTERISTICS
Table 4-2. DC Characteristics
Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C (Commercial Range) or -40 to
100°C (Industrial Range) unless otherwise specified
Symbol
VDD
VDD5
PDD
HCLK
VDAC
VOL
VOH
VIL
VIH
ILK
CIN
COUT
CCLK
Parameter
Operating Voltage
5V operating voltage
Supply Power (Note 3)
Internal Clock
DAC Voltage Reference
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Output Capacitance
Clock Capacitance
Test conditions
Note 3
VDD = 3.3V, HCLK = 66Mhz
(Note 1)
ILoad =1.5 to 8mA depending of the pin
ILoad =-0.5 to -8mA depending of the pin
Except XTALI
XTALI
Except XTALI
XTALI
Input, I/O
(Note 2)
(Note 2)
(Note 2)
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not 100% tested.
3. For detailed power consumption figures see Application Note 1297.
4.5 AC CHARACTERISTICS
Table 4-4 through Table 4-8 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float
Min
3.0
4.5
Typ
3.3
5
3.5
1.215
1.235
2.4
-0.3
-0.3
2.1
2.35
-5
Max
3.6
5.5
Unit
V
V
W
75
MHz
1.255
V
0.5
V
V
0.8
V
0.9
V
VDD+0.3
V
VDD+0.3
V
5
µA
pF
pF
pF
delays. These measurements are based on the
measurement points identified in Figure 4-1 and
Figure 4-2. The rising clock edge reference level
VREF , and other reference levels are shown in
Table 4-3 below for the STPC Client. Input or output signals must cross these levels during testing.
Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a
synchronous input signal must be stable for correct operation.
Table 4-3. Drive Level and Measurement Points for Switching Characteristics
Symbol
VREF
VIHD
VILD
Value
1.5
3.0
0.0
Units
V
V
V
Note: Refer to Figure 4-1.
Issue 2.2 - October 13, 2000
33/61
ELECTRICAL SPECIFICATIONS
Figure 4-1 Drive Level and Measurement Points for Switching Characteristics
Tx
VIHD
VRef
CLK:
VILD
A
B
MAX
MIN
Valid
Output n
OUTPUTS:
Valid
Output n+1
VRef
C
D
VIHD
Valid
Input
INPUTS:
VRef
VILD
LEGEND:
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
Figure 4-2 CLK Timing Measurement Points
T1
T2
VIH (MIN)
VRef
CLK
VIL (MAX)
T5
T3
T4
T1 - One Clock Cycle
T2 - Minimum Time at VIH
T3 - Minimum Time at VIL
T4 - Clock Fall Time
T5 - Clock Rise Time
NOTE; All sIgnals are sampled on the rising edge of the CLK.
LEGEND:
Note; The above timings are generic timings and are not specific to the interfaces defined below
34/61
Issue 2.2 - October 13, 2000
ELECTRICAL SPECIFICATIONS
4.5.4 POWER ON SEQUENCE
3 .3 V S u p p ly
1 4M H z
> 1 0 us
S Y S R S T I#
1 .6 V
S tra p O p tio ns
V A L ID C O N F IG U R A T IO N
HCLK
P C I_ C L K
2 .3 m s
SYSRSTO#
FRAM E#
SYSRSTI# has no constraint on its rising time but
needs to be set to high at least 10µs after power
supply is stable.
Strap Options are continuously sampled during
SYSRSTI# low and should be stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# is high.
Issue 2.2 - October 13, 2000
35/61
ELECTRICAL SPECIFICATIONS
4.5.5 PCI AC TIMING CHARACTERISTICS
Table 4-4. PCI Bus AC Timing
Name
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Parameter
PCI_CLKI to AD[31:0] valid
PCI_CLKI to FRAME# valid
PCI_CLKI to CBE#[3:0] valid
PCI_CLKI to PAR valid
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
PCI_CLKI to PCI_GNT# valid
AD[31:0] bus setup to PCI_CLKI
AD[31:0] bus hold from PCI_CLKI
PCI_REQ#[2:0] setup to PCI_CLKI
PCI_REQ#[2:0] hold from PCI_CLKI
CBE#[3:0] setup to PCI_CLKI
CBE#[3:0] hold to PCI_CLKI
IRDY# setup to PCI_CLKI
IRDY# hold to PCI_CLKI
FRAME# setup to PCI_CLKI
FRAME# hold from PCI_CLKI
Min
2
2
2
2
2
2
2
2
2
7
3
10
1
7
5
7
4
7
3
Max
13
11
12
12
13
11
14
11
14
4.5.6 DRAM CONTROLLER AC TIMING CHARCTERISTICS
Figure 4-3 Read Mode (ref table Table 4-5)
tCRAS
tCMA
tCCAS
CLK
tRAD
tRC
tCHR
tRAS
tRCD
tRAH
tCRD
tRP
tCRP
tRAL
RAS#
tCPN
tCOH
tCAH
tRCS
tRCH
CAS#
MA
ROW
Column
MWE#
MD
36/61
Issue 2.2 - October 13, 2000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELECTRICAL SPECIFICATIONS
Figure 4-4 Memory Early Write Mode (ref table Table 4-5)
tCRAS
tCMA
tCCAS
CLK
tRC
tDHR
tWCR
tCHR
tRAS
tRCD
tRAH
tRAL
tRWL
tCRP
tRAD
tCRW
tRP
RAS#
tCPN
tCWL
tRCS
tWCS
tWRH
tCHR
tDS
tWCH
tCPN
tCAH
tRCH
CAS#
MA
ROW
Column
MWE#
MD
Data Valid
Figure 4-5 EDO Read Mode (ref table Table 4-5)
tCCAS
tCMWE
tCMD
tCRAS
tCMA
CLK
tRC
tRAH
tCHR
tRAS
tAR
tCSR
tRCD
tRP
tCRP
tRAD
tRAL
tRCH
RAS#
tCPN
tCOH
tCAH
tRCS
tCPN
CAS#
MA
Row
Column
Row
MWE#
MD
OPEN
Valid data
Issue 2.2 - October 13, 2000
OPEN
37/61
ELECTRICAL SPECIFICATIONS
Figure 4-6 EDO Write Mode (ref table Table 4-5)
tCCAS
tCMWE
tCMD
tCRAS
tCMA
CLK
tRC
tRAH
tCHR
tRAS
tAR
tCSR
tRCD
tRP
tCRP
tRAD
tRAL
tRCH
RAS#
tCPN
tCOH
tCAH
tRCS
tCPN
CAS#
MA
Row
Column
Row
MWE#
OPEN
MD
Valid data
Figure 4-7 Fast Page Mode Read (ref table Table 4-5)
tCRAS
tCMA
tCCAS
tCMD
tCCAS
tCMA
tCCAS
tCMA
tCRAS
tCMD
tCMD
CLK
tCRP
tRAH
tRAD
tAR
tCSH
tRCD
tRAL
tCRP
tRP
RAS#
tCPN
tCPN
tCAH
tCOH
tCPN
tCOH
tCAH
tCOH
tCAH
Column 2
Column N
CAS#
MA
ROW
Column 1
MWE#
MD
38/61
Dout 1
Dout 2
Issue 2.2 - October 13, 2000
Dout N
OPEN
ELECTRICAL SPECIFICATIONS
Figure 4-8 Fast Page Mode Write (ref table Table 4-5)
tCRAS
tCMD
tCCAS
tCMA
CLK
tRAH
tRAD
tWCR
tRAS
tAR
tCRP
tRWL
tDHR
tCSH
tRAL
tRCD
tCRW
tCRP
tRP
RAS#
tWCS
tDS
tCPN
tRC
tCPN
tCAH
tCWL
tCPN
tDS
tCAH
tRAL
tCAH
tDS
tRCH
CAS#
MA
ROW
Column 1
Column 2
Column N
Dout 1
Dout 2
Dout N
MWE#
OE
MD
Figure 4-9 Refresh Cycle (ref table Table 4-5)
tCCAS
tCRAS
CLK
MA[11:0]
tRP
tCSR
tRPC tCRS
tRAS
tCHR
tRP
tRPC tCSR
RAS#[3:0]
tCPN
tCPN
CAS#[7:0]
Issue 2.2 - October 13, 2000
39/61
ELECTRICAL SPECIFICATIONS
Table 4-5. AC Memory Timing Characteristics
Parameter
tCRAS
HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3)
tCCAS
HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3)
tCMA
HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3)
tCMWE
HCLK (or GCLK2X) to MWE# valid (see Note 3)
tCMD
HCLK to MD[63:0] bus valid (see Note 3)
tGCMD
GCLK2X to MD[63:0] bus valid (see Note 3)
tMDG
MD[63:0] Generic hold
tCAH4
Column Address Hold Time
tCHR4
CAS Hold Time
4
tCOH
Data Hold TIme from CAS Low
tCPN4
CAS Precharge Time
tCRP4
CAS to RAS Precharge Time
tCRW4
CAS Low to RAS HIGH (Write only)
tCSR4
CAS Setup Time
tDS4
Data In Setup Time
tRAH4
Row Address Hold Time
4
tRAS
RAS Pulse Width
tRC4
Random Read or Write Time Cycle
tRCD4
RAS to CAS Delay Time
tRCH4
Read Command Hold Time
tRCS4
Read Command Setup Time
tRP4
RAS Precharge Time
tWCH4
Write Command Hold Time
tWCS4
WE Command Setup Time
4
tWRH
WE Hold Time
tWRP4
WE Setup Time
tAR4
Column Address Hold Time from RAS
tRAD4
RAS to valid Column Address Delay
tRAL4
Column Address to RAS Setup Time
tWCR4
Write Command Hold Reference to RAS
tRWL4
Write Command to RAS Setup Time (Note 2)
tCWL4
Write Command to CAS Setup Time (Note 2)
tDHR4
Data Hold Reference to RAS
4
tRPC
RAS High to CAS Low Precharge
tCRS4
CAS Before RAS Setup Time
tCHR4
CAS Before RAS Hold Time
tCSH4
CAS Hold Time after RAS
Note 1; TCycle x nCAS + (tData off - tCAS out)
Min
Max
17
17
17
17
25
23
0
≥1TCycles
≥1TCycles
Note 1
1TCycles
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
≤1TCycles
≥1TCycles
≥1TCycles
≥1TCycles
≥1TCycles
≥3TCycles
≥6TCycles
≥1TCycles
≥1TCycles
≥1TCycles
≥2TCycles
≥1TCycles
≥1TCycles
Note 2
≥1TCycles
≥1TCycles
≥1TCycles
≥2TCycles
≥1TCycles
≥1TCycles
≥1TCycles
≥3TCycles
≥1TCycles
≥1TCycles
≥1TCycles
≥1TCycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Where T Cycle is the the number of clock cycles.
nCAS is the number of CAS Cycles (see section 6.7. )
TDataoff is the Generic Datahold
tCAS Out the CLK (either HCLK or GCLK2X) to CAS Low.
TDataoff and tCAS Out are used to refine the timing programming.
Note 2; Value to be derived from CAS pulse width which is programmable (see section 6.7. ).
Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X
Note 4; These timings are extracted from simulations and are not garanteed by testing
40/61
Issue 2.2 - October 13, 2000
ELECTRICAL SPECIFICATIONS
Table 4-6. Video Input/TV Output AC Timing
Name
t34
t35
t36
t37
t38
t39
t40
t41
t42
Parameter
DCLK to TV_YUV[7:0] bus valid
VIN[7:0] setup to VCLK
VIN[7:0] hold from VCLK
VCLK to ODD_EVEN valid
VCLK to VCS valid
ODD_EVEN setup to VCLK
ODD_EVEN hold from VCLK
VCS setup to VCLK
VCS hold from VCLK
Min
Max
18
21
21
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
45
45
Unit
ns
ns
5
3
10
5
10
5
Table 4-7. Graphics Adapter (VGA) AC Timing
Name
t43
t44
Parameter
DCLK to VSYNC valid
DCLK to HSYNC valid
Min
Issue 2.2 - October 13, 2000
41/61
ELECTRICAL SPECIFICATIONS
4.5.7 ISA INTERFACE AC TIMING CHARCTERISTICS
Figure 4-10 ISA Cycle (ref table Table 4-8)
2
15
38
37
14
13
12
25
9
56
18
29
ALE
22
AEN
Valid AENx
34
33
LA [23:17]
3
Valid Address
42
11
24
41
57
10
27
SA [19:0]
Valid Address, SBHE*
26
23
55
58
59
48
47
28
61
64
CONTROL (Note 1)
IOCS16#
MCS16#
54
IOCHRDY
READ DATA
V.Dat
WRITE DATA
VALID DATA
Note 1; Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
Note; The clock has not been represented as it cannot be accuratly represented depending on the ISA Slave mode.
Table 4-8. ISA Bus AC Timing
Name
24
34
Parameter
Min
LA[23:17] valid before ALE# negated
5T
LA[23:17] valid before MEMR#, MEMW# asserted
3a4 Memory access to 16 bit ISA Slave
5T
4
3b Memory access to 8 bit ISA Slave
5T
94
SA[19:0] & SBHE valid before ALE# negated
1T
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
104
10a4 Memory access to 16 bit ISA Slave
2T
10b4 Memory access to 8 bit ISA Slave
2T
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
104
10c4 Memory access to 16 bit ISA Slave
2T
4
10d Memory access to 8 bit ISA Slave
2T
Note; The signal numbering refers to Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
42/61
Issue 2.2 - October 13, 2000
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycle
Cycle
ELECTRICAL SPECIFICATIONS
Table 4-8. ISA Bus AC Timing
Name
10e4
114
Parameter
Min
SA[19:0] & SBHE valid before IOR#, IOW# asserted
2T
XTALO to IOW# valid
11a4 Memory access to 16 bit ISA Slave - 2BCLK
2T
11b4 Memory access to 16 bit ISA Slave - Standard 3BCLK
2T
11c4 Memory access to 16 bit ISA Slave - 4BCLK
2T
11d4 Memory access to 8 bit ISA Slave - 2BCLK
2T
4
11e
Memory access to 8 bit ISA Slave - Standard 3BCLK
2T
124
ALE# asserted before ALE# negated
1T
ALE# asserted before MEMR#, MEMW# asserted
134
13a4 Memory Access to 16 bit ISA Slave
2T
13b4 Memory Access to 8 bit ISA Slave
2T
ALE# asserted before SMEMR#, SMEMW# asserted
134
13c4 Memory Access to 16 bit ISA Slave
2T
13d4 Memory Access to 8 bit ISA Slave
2T
13e4
ALE# asserted before IOR#, IOW# asserted
2T
4
ALE# asserted before AL[23:17]
14
15T
14a4 Non compressed
14b4 Compressed
15T
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
154
15a4 Memory Access to 16 bit ISA Slave- 4 BCLK
11T
15e4 Memory Access to 8 bit ISA Slave- Standard Cycle
11T
18a4
ALE# negated before LA[23:17] invalid (non compressed)
14T
4
18a
ALE# negated before LA[23:17] invalid (compressed)
14T
MEMR#, MEMW# asserted before LA[23:17]
224
22a4 Memory access to 16 bit ISA Slave.
13T
22b4 Memory access to 8 bit ISA Slave.
13T
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
234
23b4 Memory access to 16 bit ISA Slave Standard cycle
9T
23e4 Memory access to 8 bit ISA Slave Standard cycle
9T
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
234
23h4 Memory access to 16 bit ISA Slave Standard cycle
9T
23l4 Memory access to 16 bit ISA Slave Standard cycle
9T
IOR#, IOW# asserted before IOR#, IOW# negated
234
23o4 Memory access to 16 bit ISA Slave Standard cycle
9T
23r4 Memory access to 8 bit ISA Slave Standard cycle
9T
MEMR#, MEMW# asserted before SA[19:0]
244
24b4 Memory access to 16 bit ISA Slave Standard cycle
10T
24d4 Memory access to 8 bit ISA Slave - 3BLCK
10T
24e4 Memory access to 8 bit ISA Slave Standard cycle
10T
4
24f Memory access to 8 bit ISA Slave - 7BCLK
10T
244
SMEMR#, SMEMW# asserted before SA[19:0]
24h Memory access to 16 bit ISA Slave Standard cycle
10T
24i4 Memory access to 16 bit ISA Slave - 4BCLK
10T
24k4 Memory access to 8 bit ISA Slave - 3BCLK
10T
24l4 Memory access to 8 bit ISA Slave Standard cycle
10T
Note; The signal numbering refers to Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
Issue 2.2 - October 13, 2000
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
43/61
ELECTRICAL SPECIFICATIONS
Table 4-8. ISA Bus AC Timing
Name
244
Parameter
Min
IOR#, IOW# asserted before SA[19:0]
24o4 I/O access to 16 bit ISA Slave Standard cycle
19T
24r4 I/O access to 16 bit ISA Slave Standard cycle
19T
MEMR#, MEMW# asserted before next ALE# asserted
254
10T
25b4 Memory access to 16 bit ISA Slave Standard cycle
25d4 Memory access to 8 bit ISA Slave Standard cycle
10T
SMEMR#, SMEMW# asserted before next ALE# aserted
254
25e4 Memory access to 16 bit ISA Slave - 2BCLK
10T
25f4
Memory access to 16 bit ISA Slave Standard cycle
10T
25h4 Memory access to 8 bit ISA Slave Standard cycle
10T
IOR#, IOW# asserted before next ALE# asserted
254
25i4
I/O access to 16 bit ISA Slave Standard cycle
10T
25k4 I/O access to 16 bit ISA Slave Standard cycle
10T
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
264
26b4 Memory access to 16 bit ISA Slave Standard cycle
12T
4
26d
Memory access to 8 bit ISA Slave Standard cycle
12T
264
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f4
Memory access to 16 bit ISA Slave Standard cycle
12T
26h4 Memory access to 8 bit ISA Slave Standard cycle
12T
IOR#, IOW# asserted before next IOR#, IOW# asserted
264
26i4
I/O access to 16 bit ISA Slave Standard cycle
12T
26k4 I/O access to 8 bit ISA Slave Standard cycle
12T
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
284
28a4 Memory access to 16 bit ISA Slave
3T
28b4 Memory access to 8 bit ISA Slave
3T
Any command negated to IOR#, IOW# asserted
284
28c4 I/O access to ISA Slave
3T
4
29a
MEMR#, MEMW# negated before next ALE# asserted
1T
29b4
SMEMR#, SMEMW# negated before next ALE# asserted
1T
29c4
IOR#, IOW# negated before next ALE# asserted
1T
LA[23:17] valid to IOCHRDY negated
334
33a4 Memory access to 16 bit ISA Slave - 4 BCLK
8T
33b4 Memory access to 8 bit ISA Slave - 7 BCLK
14T
LA[23:17] valid to read data valid
344
34b4 Memory access to 16 bit ISA Slave Standard cycle
8T
34e4 Memory access to 8 bit ISA Slave Standard cycle
14T
ALE# asserted to IOCHRDY# negated
374
37a4 Memory access to 16 bit ISA Slave - 4 BCLK
6T
37b4 Memory access to 8 bit ISA Slave - 7 BCLK
12T
37c4 I/O access to 16 bit ISA Slave - 4 BCLK
6T
37d4 I/O access to 8 bit ISA Slave - 7 BCLK
12T
ALE# asserted to read data valid
384
38b4 Memory access to 16 bit ISA Slave Standard Cycle
4T
38e4 Memory access to 8 bit ISA Slave Standard Cycle
10T
38h4 I/O access to 16 bit ISA Slave Standard Cycle
4T
Note; The signal numbering refers to Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
44/61
Issue 2.2 - October 13, 2000
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ELECTRICAL SPECIFICATIONS
Table 4-8. ISA Bus AC Timing
Name
Parameter
Min
Max
38l4
I/O access to 8 bit ISA Slave Standard Cycle
10T
SA[19:0] SBHE valid to IOCHRDY negated
414
41a4 Memory access to 16 bit ISA Slave
6T
41b4 Memory access to 8 bit ISA Slave
12T
41c4 I/O access to 16 bit ISA Slave
6T
41d4 I/O access to 8 bit ISA Slave
12T
SA[19:0] SBHE valid to read data valid
424
42b4 Memory access to 16 bit ISA Slave Standard cycle
4T
42e4 Memory access to 8 bit ISA Slave Standard cycle
10T
42h4 I/O access to 16 bit ISA Slave Standard cycle
4T
42l4
I/O access to 8 bit ISA Slave Standard cycle
10T
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated
474
47a4 Memory access to 16 bit ISA Slave
2T
47b4 Memory access to 8 bit ISA Slave
5T
47c4 I/O access to 16 bit ISA Slave
2T
4
47d
I/O access to 8 bit ISA Slave
5T
484
MEMR#, SMEMR#, IOR# asserted to read data valid
48b4 Memory access to 16 bit ISA Slave Standard Cycle
2T
48e4 Memory access to 8 bit ISA Slave Standard Cycle
5T
48h4 I/O access to 16 bit ISA Slave Standard Cycle
2T
48l4
I/O access to 8 bit ISA Slave Standard Cycle
5T
IOCHRDY asserted to read data valid
544
54a4 Memory access to 16 bit ISA Slave
1T(R)/2T(W)
54b4 Memory access to 8 bit ISA Slave
1T(R)/2T(W)
54c4 I/O access to 16 bit ISA Slave
1T(R)/2T(W)
54d4 I/O access to 8 bit ISA Slave
1T(R)/2T(W)
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,
4
1T
55a
SMEMW#, IOR#, IOW# negated
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
1T
55b4
564
IOCHRDY asserted to next ALE# asserted
2T
574
IOCHRDY asserted to SA[19:0], SBHE invalid
2T
584
MEMR#, IOR#, SMEMR# negated to read data invalid
0T
594
MEMR#, IOR#, SMEMR# negated to daabus float
0T
Write data before MEMW# asserted
614
61a4 Memory access to 16 bit ISA Slave
2T
Memory access to 8 bit ISA Slave (Byte copy at end of
4
2T
61b
start)
4
Write data before SMEMW# asserted
61
61c4 Memory access to 16 bit ISA Slave
2T
61d4 Memory access to 8 bit ISA Slave
2T
Write Data valid before IOW# asserted
614
61e4 I/O access to 16 bit ISA Slave
2T
61f4
I/O access to 8 bit ISA Slave
2T
64a4
MEMW# negated to write data invalid - 16 bit
1T
64b4
MEMW# negated to write data invalid - 8 bit
1T
Note; The signal numbering refers to Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
Issue 2.2 - October 13, 2000
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
45/61
ELECTRICAL SPECIFICATIONS
Table 4-8. ISA Bus AC Timing
Name
64c4
64d4
64e4
Parameter
Min
SMEMW# negated to write data invalid - 16 bit
1T
SMEMW# negated to write data invalid - 8 bit
1T
IOW# negated to write data invalid
1T
MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte
1T
64f4
by ISA Master
IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by
1T
64g4
ISA Master
Note; The signal numbering refers to Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
46/61
Issue 2.2 - October 13, 2000
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
MECHANICAL DATA
5. MECHANICAL DATA
5.1 388-Pin Package Dimension
Dimensions are shown in Figure 5-2, Table 5-1
and Figure 5-3, Table 5-2.
The pin numbering for the STPC 388-pin Plastic
BGA package is shown in Figure 5-1.
Figure 5-1. 388-Pin PBGA Package - Top View
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
26
A
A
B
C
B
C
D
E
D
E
F
G
H
J
F
G
H
J
K
L
M
N
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
Issue 2.2 - October 13, 2000
21
20
23
22
25
24
26
47/61
MECHANICAL DATA
Figure 5-2. 388-pin PBGA Package - PCB Dimensions
A1 Ball Pad Corner
A
B
A
D
E
F
Detail
C G
Table 5-1. 388-pin PBGA Package - PCB Dimensions
Symbols
A
B
C
D
E
F
G
48/61
Min
34.95
1.22
0.58
1.57
0.15
0.05
0.75
mm
Typ
35.00
1.27
0.63
1.62
0.20
0.10
0.80
Max
35.05
1.32
0.68
1.67
0.25
0.15
0.85
Min
1.375
0.048
0.023
0.062
0.006
0.002
0.030
Issue 2.2 - October 13, 2000
inches
Typ
1.378
0.050
0.025
0.064
0.008
0.004
0.032
Max
1.380
0.052
0.027
0.066
0.001
0.006
0.034
MECHANICAL DATA
Figure 5-3. 388-pin PBGA Package - Dimensions
C
F
D
E
Solderball
Solderball after collapse
B
G
A
Table 5-2. 388-pin PBGA Package - Dimensions
Symbols
A
B
C
D
E
F
G
Min
0.50
1.12
0.60
0.52
0.63
0.60
mm
Typ
0.56
1.17
0.76
0.53
0.78
0.63
30.0
Max
0.62
1.22
0.92
0.54
0.93
0.66
Min
0.020
0.044
0.024
0.020
0.025
0.024
Issue 2.2 - October 13, 2000
inches
Typ
0.022
0.046
0.030
0.021
0.031
0.025
11.8
Max
0.024
0.048
0.036
0.022
0.037
0.026
49/61
MECHANICAL DATA
5.2 388-Pin Package thermal data
Structure in shown in Figure 5-4.
388-pin PBGA package has a Power Dissipation
Capability of 4.5W which increases to 6W when
used with a Heatsink.
Thermal dissipation options are illustrated in Figure 5-5 and Figure 5-6.
Figure 5-4. 388-Pin PBGA structure
Signal layers
Power & Ground layers
Thermal balls
Figure 5-5. Thermal dissipation without heatsink
Board
Ambient
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Junction
Rca
Case
6
Rjc
Junction
6
Board
Case
8.5
125
Rjb
Board
Rba
Ambient
Ambient
Rja = 13 °C/W
50/61
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Airflow = 0
Board temperature taken at the center balls
Issue 2.2 - October 13, 2000
MECHANICAL DATA
Figure 5-6. Thermal dissipation with heatsink
Board
Ambient
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Junction
Rca
Case
3
Rjc
Junction
6
Board
Case
8.5
50
Rjb
Board
Rba
Ambient
Ambient
Rja = 9.5 °C/W
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Airflow = 0
Board temperature taken at the center balls
Heat sink is 11.1°C/W
Issue 2.2 - October 13, 2000
51/61
MECHANICAL DATA
52/61
Issue 2.2 - October 13, 2000
BOARD LAYOUT
6. BOARD LAYOUT
6.1 THERMAL DISSIPATION
Thermal dissipation of the STPC depends mainly
on supply voltage. As a result, when the system
does not need to work at 3.3V, it may be to reduce
the voltage to 3.15V for example. This may save
few 100’s of mW.
The second area that can be concidered is unused interfaces and functions. Depending on the
application, some input signals can be grounded,
and some blocks not powered or shutdown. Clock
speed dynamic adjustment is also a solution that
can be used along with the integrated power management unit.
The standard way to route thermal balls to internal
ground layer implements only one via pad for each
ball pad, connected using a 8-mil wire.
With such configuration the Plastic BGA 388 package dissipates 90% of the heat through the ground
balls, and especially the central thermal balls
which are directly connected to the die, the remaining 10% is dissipated through the case. Adding a heat sink reduces this value to 85%.
As a result, some basic rules have to be applied
when routing the STPC in order to avoid thermal
problems.
First of all, the whole ground layer acts as a heat
sink and ground balls must be directly connected
to it as illustrated in Figure 6-1.
If one ground layer is not enough, a second
ground plane may be added on the solder side.
Figure 6-1. Ground routing
Pad for ground ball
Thru hole to ground layer
To
pL
aye
r:
Sig
na
Gr
ls
oun
d la
yer
Po
we
r la
yer
Bo
tto
m
La
yer
: si
gn
als
+ lo
cal
gro
un
d la
yer
(if n
ee
de
d)
Note: For better visibility, ground balls are not all routed.
Issue 2.2 - October 13, 2000
53/61
BOARD LAYOUT
When considering thermal dissipation, the most
important - and not the more obvious - part of the
layout is the connection between the ground balls
and the ground layer.
To avoid solder wicking over to the via pads during
soldering, it is important to have a solder mask of
4 mil around the pad (NSMD pad), this gives a diameter of 33 mil for a 25 mil ground pad.
A 1-wire connection is shown in Figure 6-2. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.
To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no local board distortion is tolerated.
Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily improved by using four 10 mil wires to connect to the
four vias around the ground pad link as in Figure
6-3. This gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.6°C/W.
The use of a ground plane like in Figure 6-4 is
even better.
The thickness of the copper on PCB layers is typically 34 µm for external layers and 17 µm for internal layers. This means thermal dissipation is not
good and temperature of the board is concentrated around the devices and falls quickly with increased distance.
When it is possible to place a metal layer inside
the PCB, this improves dramatically the heat
spreading and hence thermal dissipation of the
board.
Figure 6-2. Recommended 1-wire ground pad layout
Pad for ground ball (diameter = 25 mil)
Solder Mask (4 mil)
Connection Wire (width = 10 mil)
.5
34
Via (diameter = 24 mil)
il
m
Hole to ground layer (diameter = 12 mil)
1 mil = 0.0254 mm
Figure 6-3. Recommended 4-wire ground pad layout
4 via pads for each ground ball
54/61
Issue 2.2 - October 13, 2000
BOARD LAYOUT
Figure 6-4. Optimum layout for central ground ball
Clearance = 6mil
External diameter = 37 mil
Via to Ground layer
hole diameter = 14 mil
Solder mask
diameter = 33 mil
Pad for ground ball
diameter = 25 mil
connections = 10 mil
The PBGA Package also dissipates heat through
peripheral ground balls. When a heat sink is
placed on the device, heat is more uniformely
spread throughout the moulding increasing heat
dissipation through the peripheral ground balls.
The more via pads are connected to each ground
ball, the more heat is dissipated . The only limitation is the risk of lossing routing channels.
Figure 6-5 shows a routing with a good trade off
between thermal dissipation and number of routing channels.
Figure 6-5. Global ground layout for good thermal dissipation
Via to ground layer
Ground pad
Issue 2.2 - October 13, 2000
55/61
BOARD LAYOUT
Figure 6-6. Bottom side layout and decoupling
Ground plane for thermal dissipation
Via to ground layer
A local ground plane on opposite side of the board
as shown in Figure 6-6 improves thermal dissipation. It is used to connect decoupling capacitances
but can also be used for connection to a heat sink
or to the system’s metal box for better dissipation.
This possibility of using the whole system’s box for
thermal dissipation is very usefull in case of high
temperature inside the system and low temperature outside. In that case, both sides of the PBGA
should be thermally connected to the metal chassis in order to propagate the heat through the metal. Figure 6-7 illustrates such an implementation.
Figure 6-7. Use of metal plate for thermal dissipation
Die
Board
Metal planes
56/61
Thermal conductor
Issue 2.2 - October 13, 2000
BOARD LAYOUT
6.2 HIGH SPEED SIGNALS
Some Interfaces of the STPC run at high speed
and have to be carefully routed or even shielded.
Here is the list of these interfaces, in decreasing
speed order:
All the clocks have to be routed first and shielded
for speeds of 27MHz or more. The high speed signals have the same contrainsts as some of the
memory interface control signals.
The next interfaces to be routed are Memory, Video/graphics, and PCI.
- Memory Interface.
All the analog noise sensitive signals have to be
routed in a separate area and hence can be routed indepedently.
- Graphics and video interfaces
- PCI bus
- 14MHz oscillator stage
Figure 6-8. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
shielded signal lines
Issue 2.2 - October 13, 2000
57/61
ORDERING DATA
7. ORDERING DATA
7.1 ORDERING CODES
ST
PC
D01
STMicroelectronics
Prefix
Product Family
PC: PC Compatible
Product ID
D01: Client
Core Speed
66: 66MHz
75: 75MHz
Package
BT: 388 Overmoulded BGA
Temperature Range
C: Commercial
Case Temperature (Tcase) = 0°C to +100°C
I: Industrial
Case Temperature (Tcase) = -40°C to +100°C
A: Auatomotive
Case Temperature (Tcase) = -40°C to +115°C
Operating Voltage
3 : 3.3V ± 0.3V
58/61
Issue 2.2 - October 13, 2000
66
BT
C
3
ORDERING DATA
7.2 AVAILABLE PART NUMBERS
Part Number
STPCD0166BTC3
STPCD0175BTC3
STPCD0166BTI3
STPCD0175BTI3
STPCD0166BTA3
Core Frequency
( MHz )
66
75
66
75
66
CPU Mode
( DX / DX2 )
DX
DX
DX
DX
DX
Tcase Range
( °C )
Operating Voltage
(V)
0°C to +100°C
-40°C to +100°C
3.3V ± 0.3V
-40°C to +115°C
7.3 CUSTOMER SERVICE
More
information
STMicroelectronics
www.ST.com/STPC.
is
available
on
the
internet
site
http://
Any specific questions are to be addressed directly to the local ST Sales Office.
Issue 2.2 - October 13, 2000
59/61
ORDERING DATA
60/61
Issue 2.2 - October 13, 2000
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 2000 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
61
Issue 2.2