a High Definition Audio SoundMAX® Codec AD1884 FEATURES ENHANCED FEATURES FOUR 192 kHz DACs/ADCs Two stereo headphone amplifiers Microsoft Vista premium logo for notebook 90 dB audio outputs, 85 dB audio inputs Internal 32-bit arithmetic for greater accuracy Impedance and presence detection on all jacks Three independent microphone bias pins Digital and analog PCBeep Three general-purpose digital I/O (GPIO) pins 3.3 V analog and digital supply voltages Advanced power management modes 48-lead, Pb-free LFCSP_VQ package Two independent stereo DAC/ADC pairs Simultaneous record of two stereo channels Simultaneous playback of two stereo channels Independent 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit resolution Selectable stereo mixer on outputs S/PDIF OUTPUT Supports 44.1, 48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit data; PCM, and AC3 formats Digital PCM gain control DEDICATED AUXILIARY PINS Stereo CD/auxiliary I/O port w/GND sense Stereo auxiliary/dock I/O port Mono out pin for internal speakers or telephony AD1884 H D A U D I O I N T E R F A C E DAC1 � HP PORT A DAC0 � HP PORT D S/PDIF OUT � MONO OUT � PORT E � PORT F DIGITAL PCBEEP PCBEEP � ADC0 PORT C PORT B ADC1 Figure 1. Functional Block Diagram Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD1884 CONTENTS General Description ................................................. 3 Additional Information ......................................... 3 Jack Configurations .............................................. 3 AD1884 Specifications .............................................. 4 Test Conditions ................................................... 4 Performance ........................................................ 4 General Specifications ............................................ 4 HD–Audio Link Specification .................................. 6 Power Down States ............................................... 7 Absolute Maximum Ratings ....................................... 8 ESD Sensitivity ..................................................... 8 Environmental Conditions ...................................... 8 Pin Configuration and Function Descriptions ................. 9 HD Audio Widgets ................................................ 12 AD1884 HD Audio Parameters ................................. 13 Outline Dimensions ............................................... 15 Ordering Guide ..................................................... 15 REVISION HISTORY 1/07–Rev 0: Initial version Rev. 0 | Page 2 of 16 | January 2007 AD1884 GENERAL DESCRIPTION The AD1884 family of audio codecs and SoundMAX® software provides superior high definition audio quality that exceeds Vista Premium for notebook performance. The AD1884 has four 192 kHz DACs, four 192 kHz ADCs, S/PDIF output, Digi tal Beep and analog PCBeep. These features make the AD1884 the right choice for notebook PCs that meet the Microsoft Vista premium performance specifications as well as desktop PCs that meet the Microsoft Vista Basic performance specifications. The AD1884 is available in a 48-lead, Pb-free frame chip scale package in both reels and trays. See Ordering Guide on Page 15. ADDITIONAL INFORMATION This data sheet provides a general overview of the AD1884 SoundMAX codec’s architecture and functionality. Additional information on the AD1884 is available in the AD1884 Pro grammers Reference Manual. Please contact your local ADI sales representative for more information. For information on SoundMAX codecs and software see Analog Devices website at http://www.analog.com/soundMAX. JACK CONFIGURATIONS The guideline shown in Table 1 should be used when selecting ports for particular functions. The symbols used in this table are defined as: LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier. Table 1. Port Assignments Port Port A Port B Port C Port D Port E Port F MONO_OUT HP x MIC LO x x x x x LI x x x x x x x x Rev. 0 | Page 3 of 16 | January 2007 AD1884 AD1884 SPECIFICATIONS TEST CONDITIONS Parameter Temperature Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate fS Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band DAC ADC Test Condition 25°C 3.3 V 3.3 V 5.0 V 48 kHz 1008 Hz –3.0 dB Full Scale 20 Hz to 20 kHz 10 kΩ Output Load: Line Out Tests 32 Ω Output Load: Headphone Tests 0 dB Gain PERFORMANCE Parameter Line Out Drive (10 kΩ loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Headphone Drive (32 Ω loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Microphone/Line In (Pin to ADC, Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Min Typ Max Unit –84 90 90 dB dB dB –74 90 90 dB dB dB –78 85 85 dB dB dB GENERAL SPECIFICATIONS Parameter DIGITAL DECIMATION AND INTERPOLATION FILTERS1 Pass Band – fS (kHz) = 8 ~ 192 Pass-Band Ripple– fS (kHz) = 8 ~ 192 Stop Band – fS (kHz) = 8 ~ 192 Stop-Band Rejection – fS (kHz) = 8 ~ 192 Group Delay – fS (kHz) = 8 ~ 192 Group Delay Variation Over Pass Band ANALOG TO DIGITAL CONVERTERS Resolution Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line_In to Other Rev. 0 | Page 4 of 16 | Min Typ 0 Max Unit 0.4 fS ±0.005 Hz dB Hz dB 1/fS μs 0.6 fS –100 20 0 24 ±0.2 –85 –100 January 2007 ±10 ±0.5 ±5 Bits % dB mV –80 dB dB AD1884 Parameter DIGITAL TO ANALOG CONVERTERS Resolution Gain Error1 (Full Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) Total Audible Out-of-Band Energy1 (Measured from 0.6 × fS to 20 kHz) DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) DAC VOLUMES Step Size (DAC-0, DAC-1) Output Gain/Attenuation Range Mute Attenuation of 0 dB Fundamental1 ADC VOLUMES Step Size (ADCSEL-0, ADCSEL-1) PGA Gain/Attenuation Range ANALOG MIXER Signal-to-Noise Ratio Input to Output – Ports B, C, or F, to Port D Output Step Size: All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs ANALOG LINE LEVEL OUTPUTS Full-Scale Output Voltage: Line Out Drive Enabled Ports A, D, E, F, and Mono Out Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance ANALOG HP DRIVE OUTPUTS Full-Scale Output Voltage: Line Out Drive Enabled Ports A and D (when HP Drive is Enabled) Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 ANALOG INPUTS Input Voltages—Port B, C, or E Mic Boost = 0 dB Input Voltages—Microphone Boost Amplifier, Ports B, C, or E Mic Boost = +10 dB Mic Boost = +20 dB Mic Boost = +30 dB Input Impedance PCBEEP Ports B, C, E (Mic Boost = 0 dB) Port F Input Capacitance1 Rev. 0 | Page 5 of 16 | January 2007 Min Typ Max 24 ±10 ±0.5 –85 –95 1.5 –58.5 0 –80 1.5 –58.5 Bits % dB dB dB dB dB dB +22.5 dB dB +12.0 dB dB dB 1000 V rms3 V p-p Ω kΩ pF pF 90 –1.5 –34.5 Unit 1.0 2.83 190 10 15 1.0 2.83 0.5 32 15 1000 V rms V p-p Ω Ω pF pF 1 2.83 V rms V p-p 0.316 0.894 0.1 0.283 0.032 0.089 V rms V p-p V rms V p-p V rms V p-p 23 150 45 5 kΩ kΩ kΩ pF 7.5 AD1884 Parameter MICROPHONE BIAS MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = +5 V or +3.3 V MIC_BIAS_IN (Pin 33) = +5 V MIC_BIAS_IN (Pin 33) = +3.3 V MIC_BIAS-E (When enabled as BIAS) Min Typ Max Unit VREF Setting = Hi-Z VREF Setting = 0 V VREF Setting = 50% VREF Setting = 80% VREF Setting = 100% VREF Setting = 80% VREF Setting = 100% Hi-Z 0 1.65 3.7 3.9 2.86 3.0 V dc V dc V dc V dc V dc V dc V dc VREF Setting = Hi-Z VREF Setting = 0 V VREF Setting = 50% VREF Setting = 80% VREF Setting = 100% Hi-Z 0 1.65 2.86 3.0 V dc V dc V dc V dc V dc 1.6 mA Output Drive Current VREF Setting = 50%, 80%, or 100% GPIO 0 Input Signal High (VIH) Input Signal Low (VIL) Output Signal High (VOH) IOUT = –500 μA IOUT = +1500 μA Output Signal Low (VOL) Input Leakage Current (Signal High) (IIH) Input Leakage Current (Signal Low) (IIL) GPIO 1 and 2 Input Signal High (VIH) Input Signal Low (VIL) IOUT = –500 μA Output Signal High (VOH) Output Signal Low (VOL) IOUT = +1500 μA Input Leakage Current (Signal High) (IIH) Input Leakage Current (Signal Low) (IIL) POWER SUPPLY Analog (AVDD) 3.3 V ±5% Power Supply Range Power Dissipation Supply Current Digital (DVDD) 3.3 V ±10% Power Supply Range Power Dissipation Supply Current Digital I/O (DVIO) 3.3 V ±10% Power Supply Range Power Dissipation Supply Current Power Supply Rejection (reference to fS 100 mV p-p Signal @ 1 kHz)1 1 Guaranteed but not tested. Measurements reflect main ADC. 3 RMS values assume sine wave input. 2 HD–AUDIO LINK SPECIFICATION High-definition audio signals comply with the High-definition Audio specification. Please refer to these specifications at: http://www.intel.com/standards/hdaudio/ Rev. 0 | Page 6 of 16 | January 2007 DVIO × 0.60 0 DVIO × 0.72 0 DVIO DVIO × 0.24 DVIO DVIO × 0.10 V V V V nA μA AVDD AVDD × 0.24 AVDD AVDD × 0.10 V V V V nA μA –150 –50 AVDD × 0.60 0 AVDD × 0.72 0 –150 –50 3.13 3.30 99 31 3.46 V mW mA 2.97 3.30 162 58 3.63 V mW mA 2.97 3.30 3.96 1.2 80 3.63 V mW mA dB AD1884 POWER DOWN STATES Parameter Function Node in D0, All Nodes Active Function Node in D31 Codec in RESET Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (And Associated Amps) Saves MIC_BIAS Powered Down Saves2 IDVDD Typ 58 21 3 IAVDD Typ 31 2 3 Unit mA mA mA 6 5 0 0 5 3 2 0.5 mA mA mA mA 1 Function node D3 state powers down all nodes except for the VREF, Mixer and MIC_BIAS nodes which have independent power controls. VREF should be kept active when background functions such as jack presence detection or analog pass-through are required. Mixer should be kept active when analog pass-through is required. MIC_BIAS can be disabled if microphones are not in use in the power-down state. 2 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the Hi-Z state. The 0 Ω and Hi-Z states remain unaffected by the MIC_BIAS power state. Rev. 0 | Page 7 of 16 | January 2007 AD1884 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Supplies Digital (DVDD) Digital I/O (DVIO) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min –0.30 –0.30 –0.30 –0.30 –0.30 0 –65 Max +3.65 +3.65 +3.65 ±10.0 AVDD + 0.3 DVIO + 0.3 +70 +150 Units V V V mA V V °C °C ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be take to avoid performance degradation or loss of functionality. ENVIRONMENTAL CONDITIONS Ambient Temperature Rating TAMB = TCASE – (PD × θCA) TCASE = Case Temperature in °C PD = Power Dissipation in W θCA = Thermal Resistance (Case-to-Ambient) θJA = Thermal Resistance (Junction-to-Ambient) θJC = Thermal Resistance (Junction-to-Case) All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7. Table 2. Thermal Resistance Package LFCSP_VQ θJA 47 θJC 15 θCA 32 Unit °C/W Rev. 0 | Page 8 of 16 | January 2007 AD1884 43 NC NC = NO CONNECT 44 AVDD NC = NO CONNECT 45 PORT-A_L NC = NO CONNECT 46 NC = NO CONNECT NC = NO CONNECT 47 AVSS GPIO_0/EAPD 48 PORT-A_R SPDIF-OUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 42 41 40 39 38 37 DVCORE 1 36 PORT-D_R NC = NO CONNECT 2 35 PORT-D_L DVI/O 3 34 SENSE_B/SRC_A NC = NO CONNECT 4 33 MIC_BIAS_IN SDATA_OUT 5 32 MONO_OUT BIT_CLK 6 31 GPIO_1/MIC_BIAS-E AD1884JCPZ TOP VIEW DVSS 7 (Not To Scale) 30 GPIO_2 29 MIC_BIAS-C 28 MIC_BIAS-B 27 VREF_FLT PCBEEP 12 25 AVDD 15 16 17 18 19 20 21 22 23 24 PORT-C_R 14 PORT-E_R 13 PORT-C_L AVSS PORT-B_R 26 PORT-B_L 11 NC = NO CONNECT RESET CD_GND (PORT F) 10 NC = NO CONNECT SYNC PORT-F_R 9 PORT-F_L DVDD PORT-E_L 8 SENSE_A/SRC_B SDATA_IN Figure 2. AD1884 48-Lead Package and Pinout Rev. 0 | Page 9 of 16 | January 2007 AD1884 Table 3. AD1884 Pin Descriptions Mnemonic DIGITAL INTERFACE SDATA_OUT Pin No. I/O Description 5 I BIT_CLK SDATA_IN SYNC RESET DIGITAL I/O GPIO_2 GPIO_1/MIC_BIAS-E 6 8 10 11 I I/O I I Link Serial Data Output. AD1884 input stream. Clocked on both edges of the BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock . Link Serial Data Input. AD1884 output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. AD1884 master hardware reset. 30 31 I/O I/O 47 I/O S/PDIF_OUT JACK SENSE AND EAPD SENSE_A/SRC_B SENSE_B/SRC_A ANALOG I/O PCBEEP Port E_L Port E_R Port F_L Port F_R CD_GND 48 O General Purpose I/O/Microphone Bias for Port E. Capable of Hi-Z, 1.65 V, and 2.86 V. Pin 31 shares functionality between GPIO_1 and MIC_BIAS_E. These functions are mutually exclusive. EAPD/General Purpose Input/Output pin. Pin 47 shares functionality between GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function takes priority over the GPIO function. By default, the pin is in a Hi-Z state. External resistors should be used to insure the proper circuit state when this pin is in Hi-Z. S/PDIF_OUT – Supports S/PDIF output. 13 34 I/O I/O Jack Sense A-D Input/Sense B drive. Jack Sense E-F Input/Sense A drive. 12 14 15 16 17 19 LI LI, MIC, LO LI, MIC, LO LI, LO LI, LO I Port B_L Port B_R Port C_L Port C_R MONO_OUT Port D_L Port D_R Port A_L Port A_R FILTER/REFERENCE VREF _FILT MIC_BIAS-B MIC_BIAS-C 21 22 23 24 32 35 36 39 41 LI, MIC LI, MIC LI, MIC LI, MIC LO HP, LO HP, LO HP, LO HP, LO Monaural Input from system for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. CD-Audio-Analog-Ground-Reference. Must be connected to AGND via a 0.1 μF capacitor if not in use as CD_GND. MUST always be ac-coupled. Front Panel stereo MIC/Line-In. Front Panel stereo MIC/Line-In. Rear Panel stereo MIC/Line-In. Rear Panel stereo MIC/Line-In. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. 27 28 29 O O O DVCORE 1 O POWER AND GROUND DVIO 3.3V DVSS DVDD 3.3 V 3 7 9 I I I GPIO_0/EAPD Voltage Reference Filter. Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Both MIC bias pins are capable of Hi-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on Pin 33), Hi-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33). CAUTION: DO NOT APPLY 3.3 V TO THIS PIN! Filter connection for internal core voltage regulator. This pin must be connected to filter caps: 10 μf, 1.0 μf, and 0.1 μf connected in parallel between Pin 1 and DVSS (Pin 7). Link Digital I/O Voltage Reference. 3.3 V Digital Supply Return (ground). Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the internal digital core internal to the AD1884. The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier. Rev. 0 | Page 10 of 16 | January 2007 AD1884 Table 3. AD1884 Pin Descriptions (Continued) Mnemonic AVDD 3.3 V Pin No. 25, 38 I/O I Description CAUTION: DO NOT APPLY 5 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY. Note: AVDD supplies should be well regulated and filtered as supply noise degrades audio performance. MIC_BIAS_IN 33 I Source Power for Microphone Bias Boost Circuitry. 5.0 V or 3.3 V Connect this pin to 5.0 V via a low-pass filter. When connected this way the AD1884 is capable of providing +3.9 V as a mic bias to all of the mic bias pins (except on Pin 31). If 5 V is not available, connect this pin to +3.3 V (AVDD) via a low-pass filter. The AD1884 produces a mic bias voltage relative to the AVDD supply (typically 3.0 V @ AVDD = 3.3 V). 26, 42 I Analog Supply Return (Ground). AVSS should be connected to DVSS using a AVSS conductive trace under, or close to, the AD1884. The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier. Rev. 0 | Page 11 of 16 | January 2007 AD1884 HD AUDIO WIDGETS Table 4. HD Audio Widgets Node ID 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Name ROOT FUNCTION S/PDIF DAC DAC_0 DAC_1 VendorD_1 VendorD_2 Port A Mixer ADC_0 ADC_1 Port D Mixer Port F Mixer ADC Selector 0 ADC Selector 1 Mono Out Selector Port F Out Selector Digital Beep Port A (Headphone) Port D (Line Out) Mono Out Port B (Mic In) Port C (Line In) Port F (Aux In/Out) VendorD_3 VendorD_4 Mixer Power Down Analog PCBeep S/PDIF Out Pin Port E (Dock I/O) VREF Power Down Mono Out Mixer Stereo Mix-Down Analog Mixer Mixer Output Atten Port A Out Selector Port E Out Selector Port E Mixer Port E Mic Boost BIAS Power Down Type ID x x 0 0 0 F F 2 1 1 2 2 3 3 3 3 7 4 4 4 4 4 4 F F 5 4 4 4 F 2 2 2 3 3 3 2 3 F Type Root Function Audio Output Audio Output Audio Output Vendor Defined Vendor Defined Audio Mixer Audio Input Audio Input Audio Mixer Audio Mixer Audio Selector Audio Selector Audio Selector Audio Selector Beep Generator Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Vendor Defined Vendor Defined Power Widget Pin Complex Pin Complex Pin Complex Vendor Defined Audio Mixer Audio Mixer Audio Mixer Audio Selector Audio Selector Audio Selector Audio Mixer Audio Selector Vendor Defined Description Device identification Designates this device as an audio codec S/PDIF digital stream output interface Stereo headphone channel digital/audio converters Stereo front channel digital/audio converters Vendor Defined Vendor Defined Mixes the of DAC_(0, 1) and mixer output amps to drive Port A Stereo record Channel 0 audio/digital converters Stereo record Channel 1 audio/digital converters Mixes the DAC_1 and mixer output amps to drive Port D Mixes the DAC_(0, 1) and mixer output amps to drive Port F Selects and amplifies/attenuates the input to ADC_0 Selects and amplifies/attenuates the input to ADC_1 Selects the mono out DAC_(0, 1) Selects the Port F DAC_(0, 1) Internal digital PCBeep signal Headphone jack pins Line out jack pins Monaural output pin (internal speakers or telephony system) Microphone in jack pins Line in jack pins Auxiliary I/O pins Vendor Defined Vendor Defined Powers down the analog mixer and associated amps External analog PCBeep signal input S/PDIF output pin Analog dock I/O pins Powers down the internal and external VREF circuitry Mixes the DAC_(0, 1) and mixer output amps to drive mono out Mixes the stereo L/R channels to drive mono output Mixes individually gainable analog inputs Attenuates the mixer output to drive the port mixers Selects the Port A DAC_(0, 1) Selects the Port E DAC_(0, 1) Mixes the DAC_(0, 1) and mixer output amps to drive Port E 0 dB, 10 dB, 20 dB, or 30 dB gain boost for Port E Powers down the internal MIC_BIAS_FILT and all MIC_BIAS pins Rev. 0 | Page 12 of 16 | January 2007 AD1884 AD1884 HD AUDIO PARAMETERS Table 5. Root and Function Node Parameters Node ID 00 01 Name ROOT FUNCTION Type Root Function Vendor ID 00 11D41884 Sub Node Revision ID Count 02 04 00100100 00010001 00020025 Func. Group Type 05 00000001 Audio F.G. Caps 08 00010C0C GPIO Caps 11 40000003 Table 6. SubSystem ID 1 Node ID 01 1 31:16 SSID BFD4 Name FUNCTION 15:8 SKU 00 7:0 Asm ID 00 The SSID value is set on codec power-up only. SSID is not reset by link or soft reset in order to preserve modifications by BIOS control. Table 7. Widget Parameters Node ID 01 02 03 04 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Widget Capabilities 09 000004C0 00030311 00000405 00000405 00200103 00100501 00100501 00200103 00200103 0030010D 0030010D 00300101 00300101 0070000C 0040018D 0040058D 0040050C 0040008B 0040008B 0040018D 00500500 00400000 0040030D 0040018D 00F00100 00200103 00200100 0020010B 0030010D 00300101 00300101 00200103 0030010D 00F00100 PCM Size, Rate 0A 000E07FF 000E07E0 000E07FF 000E07FF Stream Formats 0B 00000001 00000005 00000001 00000001 000E07FF 000E07FF 00000001 00000001 Pin Capabilities 0C Input Amp Capabilities 0D 80000000 80000000 80000000 80000000 0000001F 0001001F 00010010 00003727 00003727 00000037 00270300 00270300 00000020 00000010 00003737 80000000 80051F17 80000000 Rev. 0 | Page 13 of 16 | January 2007 Con. List Length 0E 00000003 00000000 00000000 00000002 00000001 00000001 00000002 00000002 00000004 00000004 00000002 00000002 00000000 00000001 00000001 00000001 00000000 00000000 00000001 00000002 00000000 00000001 00000001 0000000A 00000002 00000001 00000004 00000001 00000002 00000002 00000002 00000001 00000003 Output Amp Power States Capabilities 0F 12 00000009 00052727 00000009 00000009 00052727 00052727 00000009 00000009 80053627 80053627 00000009 00000009 800B0F0F 80000000 80000000 80051F1F 80000000 00000009 80052727 80000000 80051F1F 00270300 AD1884 Table 8. Connection List Connection Node ID 02 03 04 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 [0–3] 00090801 [4–7] [8–11] 0 1 I NID 01 I NID 08 00002122 0000000C 0000000D 00002104 0000210F 25209614 25209614 00000403 00000403 03 0C 0D 04 0F 1 14 1 14 03 03 00000007 0000000A 0000001F 07 0A 1F 0000000B 00002120 0B 20 00000002 00000024 8F0A1907 0000210E 0000001E 251A9614 00000020 00000403 00000403 00002123 0000001C 001C1514 02 24 07 0E 1E 1 14 20 03 03 23 26 14 96111C1A 0000A61E 2 3 4 5 6 7 8 9 I NID I 09 I NID I NID I NID I NID I NID I NID I NID 20 20 25 25 19 21 0A 1 0F 1A 1C 11 16 1A 25 21 21 21 16 16 04 04 21 1 16 1E 1 26 04 04 21 15 In Table 9, default configuration values are set on codec powerup only. Default configuration values are not reset by link or soft reset to preserve modifications by BIOS control. Table 9. Default Configuration Bytes 31:30 29:28 27:24 23:20 19:16 15:12 8 7:4 3:0 Def. Device HP Out Speaker Speaker Mic In Mic In CD other SPDIF Out Mic In Conn Type 1/8" Jack ATAPI ATAPI 1/8" Jack ATAPI ATAPI ATAPI Optical 1/8" Jack Color Green Unknown Unknown Pink Unknown Unknown Unknown Black Pink JD OR 0 1 1 0 1 1 1 1 0 Def Assn. 1 1 F F 2 2 F F 2 Seq. F 0 0 0 0 1 0 0 E Location ID 11 12 13 14 15 16 1A 1B 1C Name Port A Port D Mono Out Port B Port C Port F Analog PCBeep S/PDIF Out Pin Port E Value 0321401F 90130110 901301F0 03A190F0 96A30120 99330121 90F301F0 014511F0 21A1902E Connectivity Jack Fixed Fixed Jack Fixed Fixed Fixed Jack Jack Chasis External Internal Internal External Internal Internal Internal External Separate Position Left N/A N/A Left Bottom Special 3 N/A Rear Rear Rev. 0 | Page 14 of 16 | January 2007 AD1884 OUTLINE DIMENSIONS Dimensions are shown in millimeters. 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX PIN 1 INDICATOR 48 1 EXPOSED PAD 6.75 BSC SQ 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 3. 48-Lead, Pb-Free, Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) ORDERING GUIDE Model AD1884JCPZ1 AD1884JCPZ-RL1 1 Temperature Range 0°C to 70°C 0°C to 70°C Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ Z = Pb-free part. Rev. 0 | Page 15 of 16 | January 2007 Package Option CP-48-1 CP-48-1 AD1884 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06537-0-1/07(0) Rev. 0 | Page 16 of 16 | January 2007