TI LM49360RLX

LM49360
LM49360
Mono Class D Audio Codec PMU with Ground Referenced Headphone
Amplifiers, Earpiece Driver, Audio DSP, 2 Step-Down DC-DC Converters, and
7 LDO Regulators
Literature Number: SNAS501A
December 1, 2011
Mono Class D Audio Codec PMU with Ground Referenced
Headphone Amplifiers, Earpiece Driver, Audio DSP, 2 StepDown DC-DC Converters, and 7 LDO Regulators
1.0 General Description
4.0 Features
The LM49360 combines a high performance mixed signal audio subsystem and power management unit (PMU) into a tiny
4.169mm x 3.99mm micro SMD package. The LM49360 includes a high quality stereo DAC, a high quality stereo ADC,
a stereo headphone amplifier, which supports True Ground
operation, a low EMI Class D loudspeaker amplifier, an earpiece speaker amplifier, two high efficiency buck converters,
and seven LDO regulators. It combines advanced audio processing, conversion, mixing, amplification, and power management in the smallest possible footprint while extending the
battery life of feature rich portable devices.
The LM49360 features dual bi-directional I2S or PCM audio
interfaces and an I2C compatible interface for control. This
device can be configured as a sub-PMU for camera/multimedia modules or as a AP-PMU that powers the applications
processor.
The LM49360 employs advanced techniques to extend battery life, to reduce controller overhead, to speed development
time, and to eliminate click and pop artifacts. Boomer audio
power amplifiers are designed specifically for mobile devices
and require minimal PCB area and external components.
■ Ultra efficient, spread spectrum Class D loudspeaker
2.0 Applications
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Smart Phones
Mobile Phones and VOIP Phones
Portable GPS Navigator and Portable Gaming Devices
Portable Media Players
Digital Cameras/Camcorders
3.0 Key Specifications
■ PEP at A_VDD = 3.6V, 32Ω, 1% THD
■ PHP at HP_VDD = 2.8V, Stereo 32Ω,
60mW (typ)
70mW/ch (typ)
1% THD
PLS at LS_VDD = 5V, 8Ω, 1% THD
PLS at LS_VDD = 4.2V, 8Ω, 1% THD
PLS at LS_VDD = 3.6V, 8Ω, 1% THD
SNR (Stereo DAC at 48kHz)
PSRR at 217 Hz, A_VDD = 3.6V,
(HP from AUX)
1.3W (typ)
900mW (typ)
595mW (typ)
97dB (typ)
95dB (typ)
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amplifier
Low voltage, true ground headphone amplifier operation
2 high efficiency 700mA step-down DC/DC converters
2 low noise 400mA LDOs and 4 low noise 200mA LDOs
1 low noise 20mA High Input Low Output (HILO) LDO
Programmable PMU startup sequence capability
High performance 103dB SNR stereo DAC
High performance 98dB SNR stereo ADC
Up to 96kHz stereo audio playback
Up to 48kHz stereo recording
Dual bidirectional I2S or PCM compatible audio interfaces
Read/write I2C compatible control interface
Flexible digital mixer with sample rate conversion
Sigma-delta PLL clock network that supports system
clocks up to 50MHz including 13MHz, 19.2MHz, and
26MHz
Stereo 5 band parametric equalizer
Cascadable DSP effects that allow stereo 10 band
parametric equalization
ALC/Limiter/Compressor on both DAC and ADC paths
Dedicated Earpiece Speaker Amplifier
Stereo auxiliary inputs and mono differential input
Differential microphone input with single-ended option
Automatic level control for digital audio inputs, mono
differential input, microphone input, and stereo auxiliary
inputs
Flexible audio routing from input to output
16 Step volume control for microphone with 2dB steps
32 Step volume control for auxiliary inputs in 1.5dB steps
4 Step volume control for class D loudspeaker amplifier
8 Step volume control for headphone amplifier
Micro-power shutdown mode
Available in the 4.169 x 3.99 mm 64 bump micro SMD
package
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2011 Texas Instruments Incorporated
301282
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LM49360 Mono Class D Audio Codec PMU with Ground Referenced Headphone Amplifiers,
Earpiece Driver, Audio DSP, 2 Step-Down DC-DC Converters, and 7 LDO Regulators
LM49360
LM49360
5.0 LM49360 Overview
301282h8
FIGURE 1. LM49360 Block Diagram
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LM49360
6.0 Typical Application
30128211
FIGURE 2. Sub PMU System Diagram
3
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LM49360
30128216
FIGURE 3. AP PMU System Diagram
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4
LM49360
LM49360 Default Voltage Options
Outputs
Max Output
Current (mA)
Buck1
Buck2
CONFIG = VBATT (SUB_PMU Mode)
Default
Voltage (V)
Start-up Sequence
Loads
700
1.0
t4(t0+32μs)
CVDD _CORE
700
1.5
I2C
CAM_CORE
LDO1
400
1.8
t0
VDD_SDRAM
LDO2
200
2.9
t0
VDD_I/O
LDO3
400
3.3
t4(t0+32μs)
VDD_PLL
LDO4
200
1.8
I2C
BT MODULE
LDO5
200
2.6
I2C
MINT
LDO6
200
2.8
I2C
CAM_I/O
LDO7(HILO)
20
1.0
t4(t0+32μs)
PW_CVDD
Outputs
Max Output
Current (mA)
Buck1
700
CONFIG = GND (AP-PMU Mode)
Default
Voltage (V)
Start-up Sequence
Loads
1.2
t0
TCC Core
VT CAM I/O
TCC 1.8 I/O
Buck2
700
1.8
I2C
LDO1
400
1.8
t4 (t0 + 256)
MIC BIAS
LDO2
200
2.6
I2C
LDO3
400
2.8
t4 (t0 + 256)
TCC 2.8 I/O
LDO4
200
3.3
I2C
DC MOTOR
LDO5
200
3.3
t4 (t0 + 256)
USB
LDO6
200
2.8
t4 (t0 + 256)
TFLASH
LDO7(HILO)
20
1.5
t4 (t0 + 256)
AP LDO ON(Memory)
Outputs
Max Output
Current (mA)
Buck1
Buck2
CONFIG = NC (CAM Application Mode)
Default
Voltage (V)
Start-up Sequence
700
1.2
t0
ISP_CORE
700
1.2
t0
SENSOR_CORE
LDO1
400
1.8
t5(t0 + 320)
CAM SQRAM
LDO2
200
2.8
t4 (t0 + 256)
CAM DIGITAL & PLL
LDO3
400
2.8
t3(t0 + 192)
CAM AF (PIEZO)
LDO4
200
1.8
t5(t0 + 320)
CAM DIGITAL
LDO5
200
2.8
t4 (t0 + 256)
CAM ANALOG
LDO6
200
2.8
t4 (t0 + 256)
HOST I/F
LDO7(HILO)
20
1.2
OVR
OTHERS (1.2V)
5
Loads
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LM49360
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Features ........................................................................................................................................ 1
5.0 LM49360 Overview .......................................................................................................................... 2
6.0 Typical Application ........................................................................................................................... 3
7.0 Connection Diagrams ..................................................................................................................... 10
7.1 PIN TYPE DEFINITIONS ........................................................................................................ 13
8.0 State Machine Description .............................................................................................................. 14
8.1 PMU STATE MACHINE DESCRIPTION .................................................................................... 14
8.2 AUDIO PMC STATE MACHINE DESCRIPTION ......................................................................... 16
8.2.1 State_0 (OFF) .............................................................................................................. 16
8.2.2 State_1 (BIAS) ............................................................................................................. 16
8.2.3 State_2 (AMPS ON) ..................................................................................................... 17
8.2.3.1 AMPLIFIER CONTROL FSM ............................................................................... 17
8.2.4 State_3 (UNMUTE) ...................................................................................................... 17
8.2.5 State_4 (ON) ............................................................................................................... 17
8.2.6 State_5 (MUTE) ........................................................................................................... 17
8.2.7 State_6 (AMPS_OFF) ................................................................................................... 17
8.2.8 State_7 (OFF) .............................................................................................................. 17
9.0 Absolute Maximum Ratings ............................................................................................................ 18
10.0 Operating Ratings ........................................................................................................................ 18
11.0 Total Shutdown Current Consumption ............................................................................................ 18
12.0 PMU Current Consumption ........................................................................................................... 18
13.0 Thermal Shutdown ....................................................................................................................... 19
14.0 Under Voltage Lock Out ............................................................................................................... 19
15.0 Logic and Control ........................................................................................................................ 19
16.0 Electrical Characteristics / Buck Converters ..................................................................................... 20
17.0 Electrical Characteristics / General LDOs 1 to 6 ............................................................................... 20
18.0 Electrical Characteristics / High Input Low Output LDO 7 .................................................................. 21
19.0 Electrical Characteristics / Audio CODEC: A_VDD = LS_VDD = 3.6V; HP_VDD = D_VDD = I/O_VDD =
1.8V .............................................................................................................................................. 22
20.0 Timing Characteristics: DVDD = I/OVDD = 1.8V ................................................................................ 27
21.0 Typical Performance Characteristics .............................................................................................. 29
22.0 System Control ............................................................................................................................ 38
22.1 INPUT POWER SEQUENCING .............................................................................................. 38
22.2 I2C SIGNALS ....................................................................................................................... 38
22.3 I2C DATA VALIDITY ............................................................................................................. 38
22.4 I2C START AND STOP CONDITIONS ..................................................................................... 38
22.5 TRANSFERRING DATA ........................................................................................................ 38
22.6 I2C TIMING PARAMETERS .................................................................................................. 40
22.7 POWER ON SEQUENCE ...................................................................................................... 40
23.0 Device Register Map .................................................................................................................... 46
24.0 Sleep Enables ............................................................................................................................ 51
25.0 LDO Flags and Bypass Pulse Control ............................................................................................. 52
26.0 Sequence and Voltage Programming (Banks 0 to 2) ........................................................................ 53
27.0 Basic PMC Setup Register ........................................................................................................... 64
28.0 PMC Clocks Register ................................................................................................................... 65
29.0 PMC Clock Divide Register ........................................................................................................... 65
30.0 LM49360 Clock Network .............................................................................................................. 66
31.0 PLL Setup Registers .................................................................................................................... 68
32.0 Analog Mixer Control Registers ..................................................................................................... 72
33.0 ADC Control Registers ................................................................................................................. 80
34.0 DAC Control Registers ................................................................................................................. 82
35.0 Digital Mixer Control Registers ...................................................................................................... 83
36.0 Audio Port Control Registers ......................................................................................................... 87
37.0 Digital Effects Engine ................................................................................................................... 94
38.0 DAC Effects Registers ................................................................................................................ 110
39.0 GPIO Registers ......................................................................................................................... 125
40.0 Schematic Diagram .................................................................................................................... 127
41.0 Demonstration Board Layout ....................................................................................................... 129
42.0 Revision History ........................................................................................................................ 133
43.0 Physical Dimensions .................................................................................................................. 134
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FIGURE 1. LM49360 Block Diagram ............................................................................................................. 2
FIGURE 2. Sub PMU System Diagram .......................................................................................................... 3
FIGURE 3. AP PMU System Diagram ........................................................................................................... 4
FIGURE 4. PMU State Machine .................................................................................................................. 15
FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing. ............................................................ 16
FIGURE 6. Zero Cross Detect Comparator (ZXD) ............................................................................................ 17
FIGURE 7. I2C Signals: Data Validity ............................................................................................................ 38
FIGURE 8. I2C Start and Stop Conditions ...................................................................................................... 38
FIGURE 9. I2C Chip Address ..................................................................................................................... 38
FIGURE 10. Example I2C Write Cycle .......................................................................................................... 39
FIGURE 11. Example I2C Read Cycle .......................................................................................................... 39
FIGURE 12. I2C Timing Diagram ................................................................................................................ 39
FIGURE 13. Simplified Startup Sequence if CONFIG = H or Z (SUB_PMU) ............................................................. 40
FIGURE 14. Simplified Startup Sequence if CONFIG = L (PMU) .......................................................................... 41
FIGURE 15. LM493060A CONFIG = H Start-up Sequence ................................................................................. 42
FIGURE 16. LM49360A CONFIG = L Start-up Sequence ................................................................................... 43
FIGURE 17. LM49360A CONFIG = Z Start-up Sequence ................................................................................... 44
FIGURE 18. Typical PWM Operation ............................................................................................................ 54
FIGURE 19. Typical ECO Operation ............................................................................................................ 55
FIGURE 20. Internal Clock Network ............................................................................................................. 67
FIGURE 21. PLL Loop ............................................................................................................................ 68
FIGURE 22. Application Circuit for Headphone Detection ................................................................................... 78
FIGURE 23. Digital Mixer .......................................................................................................................... 83
FIGURE 24. I2S Serial Data Format (24 bit example) ........................................................................................ 87
FIGURE 25. Left Justified Data Format (24 bit example) .................................................................................... 87
FIGURE 26. Right Justified Data Format (24 bit example) .................................................................................. 87
FIGURE 27. PCM Serial Data Format (16 bit example) ...................................................................................... 87
FIGURE 28. Timing for I2S Master ............................................................................................................... 88
FIGURE 29. Timing for I2S Slave ................................................................................................................ 88
FIGURE 30. ADC DSP Effects Chain ........................................................................................................... 94
FIGURE 31. DAC DSP Effects Chain ........................................................................................................... 94
FIGURE 32. ALC Example ........................................................................................................................ 96
FIGURE 33. ALC Limiter ........................................................................................................................... 97
FIGURE 34. Audio Compressor Effect ........................................................................................................ 105
FIGURE 35. Soft Knee Example with Compression Ratio Setting of 1:3.4 ............................................................. 106
FIGURE 36. Demo Board Schematic .......................................................................................................... 127
FIGURE 37. Demo Board Schematic .......................................................................................................... 128
FIGURE 38. Top Silkscreen ..................................................................................................................... 129
FIGURE 39. Top Layer ........................................................................................................................... 129
FIGURE 40. Inner Layer 2 ....................................................................................................................... 130
FIGURE 41. Inner Layer 3 ....................................................................................................................... 130
FIGURE 42. Inner Layer 4 ....................................................................................................................... 131
FIGURE 43. Inner Layer 5 ....................................................................................................................... 131
FIGURE 44. Bottom Layer ...................................................................................................................... 132
FIGURE 45. Bottom Silkscreen ................................................................................................................. 132
List of Tables
TABLE 1. PMU Register Map ....................................................................................................................
TABLE 2. Audio Register Map ....................................................................................................................
TABLE 3. Nonzero I2C Default Registers .......................................................................................................
TABLE 4. 0x00h PMU Setup ......................................................................................................................
TABLE 5. NV BANK (0x01h) ......................................................................................................................
TABLE 6. SLEEP 1 (0x02h) .......................................................................................................................
TABLE 7. FLAGS 1 (0x03h) .......................................................................................................................
TABLE 8. FLAGS 2 (0x04h) .......................................................................................................................
TABLE 9. BYPASS (0x05h) .......................................................................................................................
TABLE 10. SWOVR 1 (0x06h) ....................................................................................................................
TABLE 11. SWOVR 2 (0x07h) ....................................................................................................................
TABLE 12. ENB1Bank 0: CONFIG = Z (0x10h) Bank 1: CONFIG = H (0x20h)Bank 2: CONFIG = L (0x30h) ......................
TABLE 13. Buck 1 and Buck 2 Operation ......................................................................................................
TABLE 14. ENB2 Bank 0: CONFIG = Z (0x11h) Bank 1: CONFIG = H (0x21h)Bank 2: CONFIG = L (0x31h) .....................
TABLE 15. BK1VBank 0: CONFIG = Z (0x12h)Bank 1: CONFIG = H (0x22h)Bank 2: CONFIG = L (0x32h) .......................
TABLE 16. BK2V Bank 0: CONFIG = Z (0x13h)Bank 1: CONFIG = H (0x23h)Bank 2: CONFIG = L (0x33h) ......................
TABLE 17. LDO1 — 6 Bank 0: CONFIG = Z (0x14h:LDO1) → (0x19h:LDO6)Bank 1: CONFIG = H (0x24h:LDO1) →
(0x29h:LDO6)Bank 2: CONFIG = L (0x34h:LDO1) → (0x39h:LDO6) ...............................................................
TABLE 18. LDO7 Bank 0: CONFIG = Z (0x1Ah) Bank 1: CONFIG = H (0x2Ah)Bank 2: CONFIG = L (0x3Ah) ....................
7
46
47
50
51
51
51
52
52
52
52
53
53
55
55
56
56
59
60
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LM49360
List of Figures
LM49360
TABLE 19. THRESBank 0: CONFIG = Z (0x1Bh)Bank 1: CONFIG = H (0x2Bh)Bank 2: CONFIG = L (0x3Bh) ................... 61
TABLE 20. PLDWNBank 0: CONFIG = Z (0x1Ch)Bank 1: CONFIG = H (0x2Ch)Bank 2: CONFIG = L (0x3Ch) .................. 61
TABLE 21. OVRBank 0: CONFIG = Z (0x1Dh)Bank 1: CONFIG = H (0x2Dh)Bank 2: CONFIG = L (0x3Dh) ...................... 61
TABLE 22. SUBOVRBank 0: CONFIG = Z (0x1Eh)Bank 1: CONFIG = H (0x2Eh) ..................................................... 62
TABLE 23. I2C1 (0x40h) ........................................................................................................................... 62
TABLE 24. I2C2 (0x41h) ........................................................................................................................... 63
TABLE 25. BK1_FPWM (0x5Ah) ................................................................................................................. 63
TABLE 26. BK2_FPWM (0x5Eh) ................................................................................................................. 64
TABLE 27. PMC_SETUP (0x00h) ............................................................................................................... 64
TABLE 28. PMC_SETUP (0x01h) ............................................................................................................... 65
TABLE 29. PMC_SETUP (0x02h) ............................................................................................................... 65
TABLE 30. DAC Clock Requirements ........................................................................................................... 66
TABLE 31. ADC Clock Requirements ........................................................................................................... 66
TABLE 32. PLL Settings for Common System Clock Frequencies ......................................................................... 69
TABLE 33. PLL_CLOCK_SOURCE (0x03h) ................................................................................................... 70
TABLE 34. PLL_M (0x04h) ........................................................................................................................ 70
TABLE 35. PLL_N (0x05h) ........................................................................................................................ 70
TABLE 36. PLL_N_MOD (0x06h) ................................................................................................................ 71
TABLE 37. PLL_P1 (0x07h) ....................................................................................................................... 71
TABLE 38. PLL_P2 (0x08h) ....................................................................................................................... 71
TABLE 39. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 72
TABLE 40. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 72
TABLE 41. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 73
TABLE 42. AUX_OUTPUT (0x13h) .............................................................................................................. 73
TABLE 43. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 74
TABLE 44. ADC_INPUT (0x15h) ................................................................................................................. 74
TABLE 45. MIC_INPUT (0x16h) ................................................................................................................. 75
TABLE 46. AUX_LEVEL (0x18h) ................................................................................................................. 76
TABLE 47. MONO_LEVEL (0x19h) .............................................................................................................. 77
TABLE 48. HP_SENSE (0x1Bh) ................................................................................................................. 79
TABLE 49. ADC Basic (0x20h) ................................................................................................................... 80
TABLE 50. ADC_CLK_DIV (0x21h) ............................................................................................................. 80
TABLE 51. ADC_MIXER (0x23h) ................................................................................................................ 81
TABLE 52. DAC Basic (0x30h) .................................................................................................................. 82
TABLE 53. DAC_CLK_DIV (0x31h) ............................................................................................................. 82
TABLE 54. Input Levels 1 (0x40h) ............................................................................................................... 84
TABLE 55. Input Levels 2 (0x41h) ............................................................................................................... 84
TABLE 56. Audio Port 1 Input (0x42h) .......................................................................................................... 85
TABLE 57. Audio Port 2 Input (0x43h) .......................................................................................................... 85
TABLE 58. DAC Input Select (0x44h) ........................................................................................................... 86
TABLE 59. Decimator Input Select (0x45h) .................................................................................................... 86
TABLE 60. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 89
TABLE 61. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 89
TABLE 62. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 90
TABLE 63. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 90
TABLE 64. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 91
TABLE 65. RX_MODE (0x55h/x65h) ............................................................................................................ 92
TABLE 66. TX_MODE (0x56h/x66h) ............................................................................................................ 93
TABLE 67. ADC EFFECTS (0x70h) ............................................................................................................. 95
TABLE 68. DAC EFFECTS (0x71h) ............................................................................................................. 95
TABLE 69. HPF MODE (0x80h) .................................................................................................................. 95
TABLE 70. ADC_ALC_1 (0x81h) ................................................................................................................. 98
TABLE 71. ADC_ALC_2 (0x82h) ................................................................................................................. 98
TABLE 72. ADC_ALC_3 (0x83h) ................................................................................................................. 99
TABLE 73. ADC_ALC_4 (0x84h) ............................................................................................................... 100
TABLE 74. ADC_ALC_5 (0x85h) ............................................................................................................... 101
TABLE 75. ADC_ALC_6 (0x86h) .............................................................................................................. 102
TABLE 76. ADC_ALC_7 (0x87h) .............................................................................................................. 102
TABLE 77. ADC_ALC_8 (0x88h) ............................................................................................................... 102
TABLE 78. ADC_L_LEVEL (0x89h) .......................................................................................................... 103
TABLE 79. ADC_R_LEVEL (0x8Ah) ........................................................................................................... 104
TABLE 80. SOFTCLIP1 (0x90h) ............................................................................................................... 107
TABLE 81. SOFTCLIP2 (0x91h) ............................................................................................................... 108
TABLE 82. SOFTCLIP3 (0x92h) ............................................................................................................... 109
TABLE 83. DAC_ALC_1 (0xA0h) .............................................................................................................. 109
TABLE 84. DAC_ALC_2 (0xA1h) .............................................................................................................. 110
TABLE 85. DAC_ALC_3 (0xA2h) .............................................................................................................. 111
TABLE 86. DAC_ALC_4 (0xA3h) ............................................................................................................. 112
TABLE 87. DAC_ALC_5 (0xA4h) ............................................................................................................. 113
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8
9
114
114
114
115
116
117
118
119
120
121
122
123
124
125
126
126
126
126
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LM49360
TABLE 88. DAC_ALC_6 (0xA5h) .............................................................................................................
TABLE 89. DAC_ALC_7 (0xA6h) .............................................................................................................
TABLE 90. DAC_ALC_8 (0xA7h) ..............................................................................................................
TABLE 91. DAC_L_LEVEL (0xA8h) ..........................................................................................................
TABLE 92. DAC_R_LEVEL (0xA9h) ..........................................................................................................
TABLE 93. EQ_BAND_1 (0xABh) .............................................................................................................
TABLE 94. EQ_BAND_2 (0xACh) .............................................................................................................
TABLE 95. EQ_BAND_3 (0xADh) .............................................................................................................
TABLE 96. EQ_BAND_4 (0xAEh) .............................................................................................................
TABLE 97. EQ_BAND_5 (0xAFh) ..............................................................................................................
TABLE 98. SOFTCLIP1 (0xB0h) ...............................................................................................................
TABLE 99. SOFTCLIP2 (0xB1h) ...............................................................................................................
TABLE 100. SOFTCLIP3 (0xB2h) .............................................................................................................
TABLE 101. GPIO1 (0xE0h) ....................................................................................................................
TABLE 102. GPIO2 (0xE1h) ....................................................................................................................
TABLE 103. RESET (0xF0h) ....................................................................................................................
TABLE 104. Spread Spectrum (0xF1h) .......................................................................................................
TABLE 105. FORCE (0xFE) ....................................................................................................................
LM49360
7.0 Connection Diagrams
64 Bump micro SMD
64 Bump micro SMD Marking
Order Number LM49360RL
See NS Package Number RLA64JBA
Top View
XY — Date Code
TT — Die Traceability
G — Boomer
N6 — LM49360RL
301282q7
30128250
LM49360RL Pinout Diagram
30128251
Top View (Bump Side Down)
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10
Order Number
Package
Package DWG #
Transport Media
MSL Level
Green Status
LM49360RL
64 Bump micro
SMDxt
RLA64JBA
250 units on tape and reel
1
RoHS and
no Sb/Br
LM49360RLX
64 Bump micro
SMDxt
RLA64JBA
1000 units on tape and reel
1
RoHS and
no Sb/Br
11
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LM49360
Ordering Information
LM49360
Pin Descriptions
Pin
Pin Name
Type
Direction
A1
VINL1
Supply
Input
A2
LDO3
Supply
Output
A3
Description
Input for LDO1 and LDO2
LDO3 Output
OVR allows hardware override of the enabling of LDO1 thru LDO7, Buck 1 and Buck
2. The OVR control is enabled in the OVR and ENB2 registers. When bits in these
registers are set, a high on OVR enables the corresponding voltage source. If
CONFIG pin is high, the Bank 1 OVR register has LDO4_OVR bit set, via the
EEPROM after power-up, allowing OVR enabling of LDO4. The functionality of OVR
override is available in all modes (ie CONFIG pin L, H or Z). The OVR pin has an
internal 500KΩ pull-down resistor.
OVR
Digital
Input
A4
LDO5
Supply
Output
A5
VINL3
Supply
Input
Inputs for LDO5, LDO6, LDO7(HILO)
A6
PGND
Supply
Input
PMU and LDO ground
A7 PS_HOLD/SUBOVR Digital
Input
LDO5 Output
CONFIG = Low: In AP_PMU mode, PS_HOLD is a power control input from an
external processor. CONFIG = High or High Z: In sub-PMU mode, setting the
SUBOVR/(BUCK2_EN) pin high enables BUCK2 and any combination of LDO1, 4,
5, 7 or Buck 1 that has its SUBOVR I2C register bit set to 1. In this configuration the
SUBOVR(BUCK2_EN) pin has an internal 500kΩ pull-down resistor.
A8
μPWR
Supply
Input
Filter point for internal μPWR LDO
B1
LDO1
Supply
Output
LDO1 Output
B2
LDO2
Supply
Output
LDO2 Output
B3
VINL2
Supply
Input
B4
LDO4
Supply
Output
LDO4 Output
B5
LDO6
Supply
Output
LDO6 Output
B6
LDO7
Supply
Output
LDO7 low current output used primarily for powering an external module's standby
power input.
Input for LDO3 and LDO4
B7
PWR_ON / EN
Supply
Input
CONFIG = Low: In AP-PMU mode, PWR_ON = low enables standby mode and
PWR_ON = high turns on the BUCK and LDO outputs. The PWR_ON pin expects
to be driven by Vbatt via an external switch. CONFIG = High or High Z: In sub-PMU
mode EN = low enables standby mode and EN = high turns on the BUCK and LDO
outputs. The EN pin expects to be driven by an external processor. PWR_ON/EN
has an internal 500kΩ pull-down resistor.
B8
RESET_N / GPO
Digital
Output
RESET_N is an open drain output that indicates that the BUCK and LDO supplies
are stable. This pin can also be programmed as a general purpose output, GPO, in
sub-PMU mode when CONFIG = High or High Z.
C1
HPR
Analog
Output
Headphone right output
C2
A_VDD
Supply
Input
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and
class D), and Earpiece amplifier power supply input
C3
AGND
Supply
Input
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and
class D), and Earpiece amplifier ground
C4
DAC REF
Analog Input/Output Filter point for the DAC reference
C5
ADC REF
Analog
C6
SDA
Digital
C7
CONFIG
Supply
C8
DGND
D1
HPL
D2
AUX_R/AUX+
Analog
Input
Right analog input or positive differential auxiliary input
D3
AUX_L/AUX-
Analog
Input
Left analog input or negative differential auxiliary input
D4
PORT2_SYNC
Digital
D5
PORT2_SDI
Digital
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Input
Filter point for the ADC reference. Connect this pin to A_VDD.
Input/Output I2C interface data line
Input
Hardwire to DGND for Bank 2 AP-PMU operation. Hardwire to Vbatt for Bank 1 subPMU operation. Leave floating for Bank 0 sub-PMU operation.
Supply
Input
Reserved pin, connect to DGND
Analog
Output
Headphone left output
Input/Output Audio Port 2 sync signal (can be master or slave)
Input
Audio Port 2 serial data input
12
Pin Name
Type
Direction
Description
D6
SCL
Digital
Input
I2C
D7
PVDD
Supply
Input
PMU power supply input
Reserved pin, connect to DGND
D8
DGND
Supply
Input
E1
HP_VSS
Analog
Output
E2
HP_VDD
Supply
Input
E3
EP-/AUXOUT-
Analog
Output
LM49360
Pin
interface clock line
Negative power supply pin for the headphone amplifier
Headphone amplifier power supply pin
Earpiece negative output or Auxiliary negative output
E4 PORT2_SDO / GPIO Digital Input / Output Audio port 2 serial data output or General Purpose Input Output
E5
PORT2_CLK
Digital
Input/Output Audio port 2 clock signal (can be master or slave)
E6
MCLK
Digital
Input
E7
FB2
Supply
Output
E8
VINB2
Supply
Input
Input clock from 0.5MHz to 50 MHz
Buck2 feedback. Active pull-down when Buck2 is off.
Input for Buck2
F1
CP-
Analog Input/Output Fly capacitor negative input
F2
CP+
Analog Input/Output Fly capacitor positive input
F3
EP+/AUXOUT+
Analog
F4
PORT1_SYNC
Digital
F5
PORT1_SDO
Digital
Output
F6
DGND
Supply
Input
Digital ground
F7
B2_GND
Supply
Input
Buck2 ground
Output
Earpiece positive output or Auxiliary positive output
Input/Output Audio Port 1 sync signal (can be master or slave)
Audio Port 1 serial data output
F8
SW2
Supply
Output
Buck2 switch output
G1
LSGND
Supply
Input
Loudspeaker ground
G2
LSVDD
Supply
Input
Loudspeaker amplifier supply input
G3
MONO-
Analog
Input
Mono differential negative input
G4
MIC-
Analog
Input
Microphone negative input
G5
PORT1_SDI
Digital
Input
Audio Port 1 serial data input
G6
D_VDD
Supply
Input
DAC (Digital), ADC (Digital), PLL (Digital), digital mixer, DSP core, and I2C register
power supply input
G7
FB1
Supply
Output
G8
VINB1
Supply
Input
H1
LS -
Analog
Output
Loudspeaker negative output
H2
LS +
Analog
Output
Loudspeaker positive output
H3
MONO+
Analog
Input
Mono differential positive input
H4
MIC +
Analog
Input
Microphone positive input
H5
PORT1_CLK
Digital
H6
I/O_VDD
Supply
H7
B1_GND
H8
SW1
Buck1 feedback. Active pull-down when Buck1 is off.
Input for Buck1
Input/Output Audio Port 1 clock signal (can be master or slave)
Input
Digital I/O (MCLK, I2S/PCM, I2C) interface power supply input
Supply
Input
Buck1 ground
Supply
Output
Buck1 switch output
7.1 PIN TYPE DEFINITIONS
Analog Input —
A pin that is used by the analog and
is never driven by the device. Supplies are part of this classification.
Analog Output —
A pin that is driven by the device and
should not be driven by external
sources.
Analog Input/Output — A pin that is typically used for filtering
a DC signal within the device. Pas-
Digital Input —
Digital Output —
Digital Input/Output —
13
sive components can be connected
to these pins.
A pin that is used by the digital but is
never driven by the device.
A pin that is driven by the device and
should not be driven by another device to avoid contention.
A pin that is either open drain (SDA)
or a bidirectional CMOS in/out. In
the latter case the direction is selected by a control register within the
LM49360.
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LM49360
is programmable, 8μs, 64μs, 128μs, and 256μs. The timing
for each output can be set individually and can be different for
each of the 3 modes. The output voltage is also programmable for each power output and can also be different
for each of the 3 modes. In addition, the device supports various override modes if the user wants to optionally control an
output or leave an output on when the rest of the device is
disabled:
8.0 State Machine Description
8.1 PMU STATE MACHINE DESCRIPTION
The device is based around a power sequencer with 8 selectable stages for powering up and down outputs. There are
3 modes of operation that use this sequencer with different
settings, set by the config pin. Outputs are powered down in
the opposite order from power up. The time between stages
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14
LM49360
301282h9
FIGURE 4. PMU State Machine
15
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LM49360
device to reach the ON state. A command to disable the device takes 0.75k clock cycles (2.2ms) to reach the OFF state.
The stated times are based on using the low power internal
oscillator, which is typically 350kHz but can vary by as much
as 30%.
The ENABLE bit drives a sequencer that is responsible for
controlling bias circuits, clocking, click and pop and clean operation of the volume controls without requiring manual I2C
commands, a simplified overview is shown below:
8.2 AUDIO PMC STATE MACHINE DESCRIPTION
The basic premise of the audio section is that it should be
configured in shutdown and enabled via the ENABLE register
in 0x00h bit[0]. Once it has been enabled the CHIP_ACTIVE
bit is set in 0x00h bit[7]. To disable the device the user should
clear the ENABLE bit (0x00h bit[0]) and wait for the CHIP_ACTIVE(0x00h bit [7]) bit to clear before re-enabling the device.
Sufficient time must be given for the state transitions to complete before issuing another command via I2C. A device enable command takes 8.5k clock cycles (typically 25ms) for the
30128259
FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing.
The Finite State Machine (FSM) can be clocked from a divided down MCLK, an I2S PORT or an internal 350kHz oscillator.
The device will automatically control the internal clock gating
of the MCLK and Oscillator clocks. The I2S clock inputs are
not automatically gated to allow to digital bypass modes when
the analog codec circuits are disabled. The FSM can be
clocked faster if required - the maximum clock speed to the
PMC is 14MHz.
The user can use the internal oscillator for the PMC and it will
only enable the oscillator when required (the low power oscillator is reused by many circuits in the device that require
delays, the PMC controls when it should be enabled). If the
PMC is not using the oscillator (i.e. PMC_CLK_SEL is set to
MCLK) it will remain off unless another circuit requires it. The
PMC will also automatically control the MCLK input buffer to
reduce power on chip but the power spent driving the PCB
trace to the MCLK pin makes the oscillator the preferred solution. The only advantage to using an external pin is where
precise timing of the sequencer is needed. When an external
clock is required it should not be removed until the device has
reached the OFF condition. The function and timing of each
stage is detailed below:
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8.2.1 State_0 (OFF)
In this state the internal clocks and oscillators are disabled
(unless an OVR bit in register 0x00 is set). The device is unbiased and only leakage current is drawn from the supplies.
The I2C port is controllable and all control registers are free
to be changed.
When the ENABLE bit is set the device enables either the
MCLK pad or low power oscillator and waits 2 clock cycles
before rechecking the ENABLE bit. If it is still set the device
proceeds to STATE_1, otherwise the device remains in
STATE_0 and the deglitching digital flip-flops are disabled
and reset.
8.2.2 State_1 (BIAS)
In state 1 the device enables its internal references and common mode points. The preamplifiers to analog inputs are
enabled and the PMC starts to inject current into decoupling
caps. The PMC clock is started and the clocking circuits are
readied. The mixer and amplifiers remain muted.
The device waits 8192 clock cycles (typically 23 to 24ms using
the internal oscillator, enough time for the common mode
points to reach vcm and start to settle without any audible click
and pop or coupling back to driving circuits) before moving to
the next stage.
16
8.2.3.1 AMPLIFIER CONTROL FSM
The muting, unmuting and volume control is always handled
by a separate state machine for each amplifier. This sec-
301282i0
FIGURE 6. Zero Cross Detect Comparator (ZXD)
The controller waits 1ms for this comparator to stabilize then
monitors the output of the comparator for a Zero Crossing
Event. At this exact moment the new gain or mute/unmute
condition is applied to the amplifier (in conjunction with any
changes required to the rest of the analog mixer to ensure
click and pop free operation). The comparator is then powered down. If no zero crossing occurs after 11ms (assume
audio content at frequencies above 36Hz) the changes are
applied regardless and the controller returns to a zero power
state.
The PMC leaves STATE_2 after 256 clock cycles (about
1ms).
monitored for a falling edge. Once a deglitched falling edge is
seen the FSM moves to state 5.
8.2.6 State_5 (MUTE)
The output stages are muted first using the amplifier control
FSM for each channel. The digital logic circuits are also muted
and cleared at this stage. Once the amplifiers are muted and
1ms has passed (256 clock cycles) the PMU moves to state
6. CHIP_ACTIVE is cleared at this stage.
8.2.7 State_6 (AMPS_OFF)
With the output stages muted the I/O amplifiers can be disabled, only the ADCs and DACs remain enabled, flushing out
any residual data from their filters. The device waits another
256 clock cycles.
8.2.4 State_3 (UNMUTE)
In state 3 the audio DACs and ADCs have been cleared and
are unmuted then the digital and analog mixers are unmuted.
The PMC leaves STATE_3 after 256 clock cycles (about
1ms).
8.2.8 State_7 (OFF)
The Bias circuits are disabled and the common mode and
reference bypass points are allowed to discharge. The MCLK
and oscillator are disabled and power is leakage only.
8.2.5 State_4 (ON)
The PMC now sets the CHIP_ACTIVE flag (0x00h bit[7]). The
internal timers are all powered down. The ENABLE pin is
17
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LM49360
ondary state machine notes a change in the requested state
for each amplifier and requests a clock and a 10ms countdown from the PMC clock domain so it can proceed to safely
change the gain of the amplifier.
The amp control FSM checks the current gain and signal
routing and if required (if zipper or click and pop is a risk) enables a small differential comparator on the output of the amp.
8.2.3 State_2 (AMPS ON)
Once the common mode points have settled, the amplifiers
power up with their inputs muted. Any calibration takes place
at this stage. Protection circuits enable and the I/O amplifiers
(not the analog mixer yet) are allowed to unmute once vcm
has settled, ensuring better settling of the common mode
throughout the muted mixer.
LM49360
Human Body Model (Note 4)
Machine Model (Note 5)
Charged Device Model
Junction Temperature
Thermal Resistance
θJA – RLA64 (soldered down
to PCB with 2in2 1oz. copper plane)
Soldering Information
See Applications Note AN-1112.
9.0 Absolute Maximum Ratings (Note
1, Note 2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage
(A_VDD and LS_VDD)
Digital Supply Voltage
D_VDD
I/O Supply Voltage
I/O_VDD
Headphone Supply Voltage
HP_VDD
Buck Input Supply Voltage
VINB1, VINB2
LDO Input Supply Voltage
VINL1, VINL2, VINL3
Storage Temperature
Maximum Continuous Power
Dissipation (Note 3)
ESD Ratings
6.0V
2kV
150V
500V
150°C
60°C/W
2.2V
10.0 Operating Ratings
5.5V
Ambient Temperature Range
TA
Supply Voltage
A_VDD, ADCREF
D_VDD
I/O_VDD
HP_VDD
PVDD, LSVDD, VINB1
VINB2,VINL1,VINL2,VINL3
3.0V
6.0V
6.0V
−65°C to +150°C
2.0W
−40°C to +85°C
2.8V to 5.5V
1.6V to 2.0V
1.6V to 4.5V
1.7V to 2.8V
3.0V to 5.5V
11.0 Total Shutdown Current Consumption
Unless otherwise noted, PVDD = VIN1 = VIN2 = VIN3 = VINB1 = VINB2 = 3.6V, CVINB1 = CVINB2 = 4.7µF, CVIN1 = CVIN2 = CVIN3 = 10µF,
A_VDD = LS_VDD = 3.6V, HP_VDD = D_VDD = IO_VDD = 1.8V. Typical values and limits appearing in boldface type apply over the
entire ambient temperature range for operation, TA = –40 to +85°C. (Note 7).
Symbol
Parameter
Total
Total Shutdown Current
IQ (SHUTDOWN)
Condition
Min
Typ
Max
Units
9.1
20
μA
PMU Standby Conditions: All outputs
disabled, (Note 12)
Audio CODEC Conditions:
Shutdown Mode, fMCLK = 13MHz,
PLL Off
12.0 PMU Current Consumption
Unless otherwise noted, PVDD = VIN1 = VIN2 = VIN3 = VINB1 = VINB2 = 3.6V, CVINB1 = CVINB2 = 4.7µF, CVIN1 = CVIN2 = CVIN3 = 10µF.
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the ambient
junction temperature range for operation, TA = –40 to +85°C. (Note 7).
Typ
Max
Units
IQ (STANDBY)
Symbol
Standby Current
All outputs disabled, (Note 12)
4.5
10.2
µA
IQ(SLEEP)
Current in SLEEP Mode
at no load
All outputs enabled
105
150
µA
IQ (IDLE)
Current at no load
All outputs enabled
365
450
µA
IQ (IDLE 1)
Current at no load
Only Buck 1 enabled
145
170
μA
IQ (IDLE 2)
Current at no load
Only Buck 1, LDO1, LDO2, LDO3,
and LDO6 enabled
250
300
μA
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Parameter
Condition
18
Min
The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature damage caused by
excessive power dissipation. There are a total of three thermal monitors on the LM49360, with one monitoring the upper limit audio
section, another acting as an early warning flag for the PMU section, and a third monitoring the upper limit of the PMU section.
(Note 7).
Symbol
Parameter
Condition
Min
Typ
Max
Units
Upper Limit (Automatic)
160
°C
Lower Limit
(Acts as an early warning flag)
120
°C
TSDPMU
PMU Thermal Shutdown
TSDAUDIO
Audio Codec Thermal Shutdown (Automatic)
155
°C
TSDHYST
TSD Hysteresis
20
°C
14.0 Under Voltage Lock Out
This device has Under Voltage Lock Out (UVLO) that checks the PVDD pin voltage before enabling any of the PMU outputs (LDO’s
1 thru 7, Buck 1 and Buck 2), this occurs during the PMU state machine DELAY (state 6). If the PVDD is below the UVLO threshold
the PMU state machine returns to the STANDBY (state 3) and the PMU outputs remain disabled. If PVDD is greater than the UVLO
threshold than the selected PMU outputs are enabled. Upon enabling the PMU outputs the PVDD pin voltage is continuously
monitored to determine if it is above the UVLO threshold. If the PVDD drops below the UVLO threshold an UVLO_EVENT occurs
and the PMU state machine returns to the STANDBY state and the PMU outputs are disabled.
Symbol
Parameter
UVLO threshold
Condition
Min
UVLO_VSEL = 1010b
Hysteresis
Typ
Max
Units
2.8
V
80
mV
15.0 Logic and Control
Unless otherwise noted, PVDD = VIN1 = VIN2 = VIN3 = VINB1 = VINB2 = 3.6V, CVINB1 = CVINB2 = 4.7µF, CVIN1 = CVIN2 = CVIN3 = 10µF.
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire
ambient temperature range for operation, TA = –40 to +85°C. (Note 7).
Symbol
Parameter
Condition
Min
Typ
Max
Units
MCLK, PORT1_CLK, PORT1_WS,
PORT1 _SDI, PORT2_CLK,
PORT2_WS, PORT2_SDI,
PORT2_SDO/GPIO
0.3 x I/
O_VDD
V
SCL, SDA CONFIG
0.3 x
VBATT
V
Logic and Control Inputs
VIL
VIH
IIL
Input Low Level
Input High Level
Input Low Level Current
SCL, SDA, MCLK, PORT1_CLK,
PORT1_WS, PORT1 _SDI,
PORT2_CLK, PORT2_WS,
PORT2_SDI, PORT2_SDO/GPIO
0.7x I/
O_VDD
V
CONFIG
0.7 x
VBATT
V
SCL, SDA, PS_HOLD / SUBOVR
(BUCK2_EN), PWR_ON / EN, OVR
(LDO4_EN), CONFIG
0.1
0.5
µA
4.7
6.0
µA
VIL = 0V
IIH
Input High Level Current
PS_HOLD / SUBOVR (BUCK2_EN),
PWR_ON
VIH = VIN1
RPD
Pull Down Resistance
From PWR_ON / EN, PS_HOLD /
SUBOVR (BUCK2_EN), OVR
(LDO4_EN)
800
kΩ
Logic and Control Outputs
19
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LM49360
13.0 Thermal Shutdown
LM49360
Symbol
Parameter
Condition
Min
Typ
SDA, RESET_N, IOUT = 2mA
VOL
Output Low Level
PORT1_SDO, PORT2_SDO/GPIO
Units
0.4
V
0.3 x I/
O_VDD
V
Open
Drain
SDA, RESET_N
VOH
Max
Output High Level
PORT1_SDO, PORT2_SDO/GPIO
0.7 x
I/O_VDD
V
16.0 Electrical Characteristics / Buck Converters
Unless otherwise noted, PVDD= VINB1 = VINB2 = 3.6V, CVINB1 = CVINB2 = 4.7µF. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, TA = –40 to
+85°C. (Note 7, Note 8)
Symbol
Parameter
Condition
Min
Max
Units
-3
3
%
-3.7
3.7
%
PWM Mode, No load
VFB
Feedback Voltage
VOUT = 1.1V to 1.8V
PWM Mode, No load
VOUT = 0.6V to 1.0V
Typ
IQ_ECO
ECO Mode IQ
ECO Mode, FB = VIN,
No Switching
60
229
µA
IQ_PWM
PWM Mode IQ
PWM Mode, FB = VIN,
No Switching
465
630
µA
RDSON(P)
Pin-Pin resistance for NMOS
170
200
mΩ
RDSON(N)
Pin-Pin resistance for NMOS
100
120
mΩ
ILIM
1200
1360
mA
4.2
MHz
VIN = VGS = 3.6V
IOUT = 200mA
VIN = VGS = 3.6V
IOUT = -200mA
Switch Peak Current Limit
Open-loop, programmable
tSTARTUP
Start Up Time
IOUT = 0mA to 100mA
fSW
Switching frequency
PWM Mode
1020
50
3.8
4
µs
17.0 Electrical Characteristics / General LDOs 1 to 6
Unless otherwise noted, PVDD = VIN1 = VIN2 = VIN3 = 3.6V, GND = 0V, CVIN1 = CVIN2 = CVIN3 = 10µF. Typical values and limits
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range
for operation, TA = –40 to +85°C. (Note 7)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Condition
IOUT = 1mA, VOUT = 2.85V
Min
Max
Units
-2
2
%
-3
3
%
VOUT = 0V
ISC
Output Current Limit
LDO1, LDO3
VOUT = 0V
LDO2, LDO4, LDO5, LDO6
VDO
Dropout Voltage
IOUT = IMAX (Note 9)
Typ
780
mA
400
mA
140
250
mV
VOUT + 0.5V ≤ VIN ≤ 4.5V
ΔVOUT
Line Regulation
IOUT = IMAX
(Note 10)
Load Regulation
1mA < IOUT < IMAX
IMAX
Max Output Current
ISLEEP
Max Output Current in sleep Mode
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1.0
mV
4
mV
LDO1, LDO3
400
440
mA
LDO2, LDO4, LDO5, LDO6
200
250
mA
20
mA
20
Parameter
Condition
Min
Typ
Max
Units
10Hz < f < 100kHz
eN
Output Voltage Noise
IOUT = IMAX
13
µVRMS
36
dB
IOUT = IMAX, COUT = 1µF
25
µs
IOUT = IMAX (Note 11)
20
mV
COUT = 1µF
PSRR
Power Supply Rejection Ratio
tSTARTUP
Start-up Time from Shutdown
VTRANSIENT Start-up Transient Overshoot
COUT
External Output Capacitance for
Stability
f = 10KHz, COUT = 1µF
IOUT = 20mA
(Note 11)
0.6
1
20
µF
18.0 Electrical Characteristics / High Input Low Output LDO 7
Unless otherwise noted, PVDD = VIN3 = 3.6V, GND = 0V, CVIN3 = 10µF. Typical values and limits appearing in normal type apply
for TJ = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, TA = –40 to +85°
C. (Note 7)
Symbol
Parameter
Max
Units
IOUT = 1mA, VOUT = 1.2V
Condition
Min
-2
2
%
3
%
VOUT
Output Voltage Accuracy
IOUT = 1mA, VOUT = 1.2V,
over temperature
-3
IOUT
Max Output Current
VOUT + 0.5V < VIN3 < 5.5V
20
ISC
Output Current Limit
VOUT = 0V
VDO
Dropout Voltage
ΔVOUT
IOUT = 20mA
mA
65
mV
VOUT + 0.5V ≤ VIN3 ≤ 5.5V,
IOUT = 20mA (Note 10)
0.5
mV
Load Regulation
1mA < IOUT < 20mA
0.5
mV
53
µVRMS
90
µVRMS
35
dB
35
dB
Output Voltage Noise
IOUT = 20mA; No COUT
10Hz = f = 100kHz
f = 10kHz, COUT = 1µF
Power Supply Rejection Ratio
IOUT = 2mA
f = 10kHz, COUT = 1µF
IOUT = 20mA
tSTARTUP
mA
Line Regulation
IOUT = 20mA; COUT = 10µF
PSRR
40
110
54
(Note 9)
10Hz = f = 100kHz
eN
Typ
Start-up Time from Shutdown
IOUT = 20mA ; COUT = 1µF
60
µs
IOUT = 0mA to 2mA
–55
mV
IOUT = 2mA to 0mA
55
mV
IOUT = 20mA; COUT = 1μF(Note 11)
20
mV
VLOADTRANS
Load Transient Overshoot
VTRANSIENT
Start-up Transient Overshoot
COUT
External Output Capacitance for
(Note 11)
Stability
0.6
21
1
20
µF
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LM49360
Symbol
LM49360
19.0 Electrical Characteristics / Audio CODEC: A_VDD = LS_VDD = 3.6V;
HP_VDD = D_VDD = I/O_VDD = 1.8V (Note 1, Note 2) The following specifications apply for RL(LS) = 8Ω,
RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM49360
Symbol
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD, HP_VDD,
and LS_VDD)
DISD
DIDD
AISD
Digital Shutdown Current
Shutdown Mode,
fMCLK = 13MHz, PLL Off
Digital Active Current (MP3 Mode)
4
10
µA
fMCLK = 11.2896MHz, fS = 44.1kHz,
Stereo DAC On, OSRDAC = 64,
PLL Off, HP On
1.2
1.4
mA (max)
Digital Active Current (FM Mode)
fMCLK = 13MHz
Analog Audio modes
0.2
0.5
mA (max)
Digital Active Current
(FM Record Mode)
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
1.3
1.5
mA (max)
Digital Active Current
(CODEC Mode)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
OSRADC = 128, PLL Off, MIC On
0.7
0.8
mA (max)
Analog Shutdown Current
Shutdown Mode
0.1
9
μA (max)
Analog Supply Current (MP3 Mode)
fMCLK = 11.2896MHz, fS = 44.1kHz, Stereo DAC On,
OSRDAC = 64, PLL Off, Stereo HP On
From A_VDD
4.6
6
mA (max)
From HP_VDD
1.7
2.7
mA (max)
From A_VDD
1.8
2.6
mA (max)
From HP_VDD
1.6
2.7
mA (max)
Analog Supply Current
(FM Record Mode)
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
7.3
9.3
mA (max)
Analog Supply Current
(CODEC Mode)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
OSRADC = 128, PLL Off, MIC On,
EP On
7.0
8.7
mA (max)
Analog Supply Current (FM Mode)
AIDD
fMCLK = 13MHz, PLL Off
Stereo Auxiliary Inputs On,
PLL Off, Stereo HP On
fMCLK = 13MHz, fPLLOUT = 12MHz, PLL On only
PLLIDD
PLL Total Active Current
From A_VDD
1.9
2.7
mA (max)
From D_VDD
1.4
2
mA (max)
HPIDD
Headphone Quiescent Current
Stereo HP On only
1.6
mA
LSIDD
Loudspeaker Quiescent Current
LS On only
2.4
mA
MICIDD
Microphone Quiescent Current
Mono MIC
0.4
mA
From A_VDD
6.5
mA
From D_VDD
1.4
mA
From A_VDD
3.5
mA
From D_VDD
1.0
mA
fs = 48kHz, Stereo
ADCIDD
ADC Total Active Current
fS = 48kHz, Stereo
DACIDD
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DAC Total Active Current
22
Parameter
Conditions
AUXINIDD
Mono/Auxiliary Input Amplifier
Quiescent Current
Mono and AUX Input Amplifiers
enabled
AUXOUTIDD
Auxiliary Output Amplifier Quiescent AUXOUT enabled
Current
Earpiece Mode
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
0.6
mA
0.5
mA
1.2
mA
87
%
0.06
%
LOUDSPEAKER AMPLIFIER
LSEFF
Loudspeaker Efficiency
THD+N
Total Harmonic Distortion + Noise
PO = 940mW, RL = 8Ω,
LS_VDD = 4.2V
PO = 300mW, f = 1kHz,
RL = 8Ω, Mono Input Signal
RL = 8Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
PO
Output Power
LS_VDD = 5V
1.3
LS_VDD = 4.2V
900
LS_VDD = 3.6V
595
Power Supply Rejection Ratio
mW
555
mW (min)
RL = 4Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
LS_VDD = 5V
PSRR
W
2.2
W
LS_VDD = 4.2V
1.6
W
LS_VDD = 3.6V
950
mW
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
Mono Input Terminated
VREF = 1.0μF, Input Referred
LS Gain = 12dB
82
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
80
65
dB (min)
dB
Reference = VOUT (1% THD+N ), Mono gain = 0dB
A-weighted, Mono Input Terminated, LS Gain = 8dB
SNR
Signal-to-Noise Ratio
LS_VDD = 4.2V
92
LS_VDD = 3.6V
91
dB
85
dB (min)
Reference = VOUT (1% THD+N ), DAC Gain = 0dB, A-weighted
fS = 48kHz, OSR = 128 LS Gain = 8dB
LS_VDD = 4.2V
84
dB
LS_VDD = 3.6V
83
dB
µV
eOS
Output Noise
Mono gain = 0dB, A-weighted,
Mono Input Terminated, Input Referred
90
VOS
Offset Voltage
Mono gain = 0dB, from Mono Input
10
50
mV (max)
0.03
0.1
% (max)
18.5
mW (min)
HEADPHONE AMPLIFIERS
PO = 15mW, f = 1kHz,
THD+N
Total Harmonic Distortion + Noise
RL = 32Ω
Stereo Analog Input Signal
RL = 32Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
PO
Headphone Output Power
HP_VDD = 2.8V
70
HP_VDD = 1.8V
23
mW
RL = 16Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
HP_VDD = 2.8V
70
mW
HP_VDD = 1.8V
25
mW
23
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LM49360
LM49360
Symbol
LM49360
LM49360
Symbol
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz, Mono Input Terminated
Mono gain = 0dB VREF = 1.0μF, Mono Differential Input Mode,
PSRR
Power Supply Rejection Ratio
Ripple applied to AVDD only
100
Ripple applied to AVDD and HPVDD
92
dB
Ripple applied to AVDD
HPVDD, and DVDD
90
dB
Reference = VOUT (1% THD+N )
Gain = 0dB, A-weighted
Stereo Inputs Terminated
95
90
dB (min)
Reference = VOUT (1% THD+N),
Gain = 0dB,
A-weighted, I2S Input = Digital Zero
97
92
dB (min)
Gain = 0dB, A-weighted,
Stereo Inputs Terminated
12
µV
Gain = 0dB, A-weighted,
I2S Input = Digital Zero
13
µV
PO = 7.5mW, f = 1kHz, RL = 32Ω
Stereo Analog Input Signal
85
dB
0.03
dB
82
dB (min)
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
SNR
eOS
Signal to Noise Ratio
Output Noise
XTALK
Crosstalk
ΔACH-CH
Channel-to-Channel Gain Matching
VOS
Output Offset Voltage (Note 13)
AUX Gain = 0dB
From mono Input
0.25
1
mV (max)
DAC Gain = 0dB
From DAC Input, fMCLK = 12.288MHz
0.25
1
mV (max)
AUX_LINE_OUT, f = 1kHz
From Mono In
RL = 5kΩ, VOUT = 1VRMS
0.006
%
Earpiece mode, f = 1kHz,
From Mono In
RL = 32Ω BTL, POUT = 20mW
0.03
%
Earpiece mode, f = 1kHz
RL = 32Ω BTL, THD+N = 1%
60
AUXILIARY OUTPUT/EARPIECE AMPLIFIER
THD+N
POUT
Total Harmonic Distortion
Output Power
50
mW (min)
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
AUX_LINE_OUT
PSRR
Power Supply Rejection Ratio
80
dB
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
Earpiece mode,
–6dB cut enabled
100
85
dB
SNR
Signal to Noise Ratio
Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated
101
dB
∈OUT
Output Noise
Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated
11.4
μV
MONO gain = 0dB, From Mono Input
AUX_LINE_OUT
4.2
mV
VOS
TWU
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Output Offset Voltage
Turn-On time
Gain = 0dB, From Mono Input
Earpiece mode
3
PMC Clock = 300kHz
29
24
10
mV (max)
ms
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
STEREO ADC
THD+NADC
ADC Total Harmonic Distortion
+ Noise
PBADC
ADC Passband
RADC
ADC Ripple
Mono Differential Input
VIN = 1VRMS, f = 1kHz
Gain = 0dB, fS = 48kHz
HPF On, fS = 48kHz
Lower -3dB Point
ADCLEVEL
ADC Signal to Noise Ratio
%
220
Hz
0.41*fS
kHz
OSRDAC = 128
0.1
dB
Reference = VOUT (0dBFS )
Gain = 6dB
A-weighted From MIC, fS = 8kHz
96
dB
Reference = VOUT (0dBFS )
Gain = 0dB
A-weighted From Stereo Input,
fS = 48kHz
98
dB
1.65
VRMS
0.015
%
HPF On, Upper -3dB Point
SNRADC
0.008
ADC Full Scale Input Level
STEREO DAC
I2S Input, AUXOUT, OSRDAC = 64
VIN = 500mFFSRMS, f = 1kHz
Gain = 0dB
THD+NDAC
DAC Total Harmonic Distortion
+ Noise
DACLEVEL
DAC Full Scale Output Level
1.1
VRMS
RDAC
DAC Ripple
0.1
dB
PBDAC
DAC Passband
Upper –3dB Point
0.45*fS
kHz
SNRDAC
DAC Signal to Noise Ratio
fS = 48kHz, A-weighted, AUXOUT
96
dB
Minimum Gain
–46.5
dB
Maximum Gain
18
dB
Minimum Gain
–46.5
dB
Maximum Gain
18
dB
Minimum Gain
–76.5
dB
Maximum Gain
18
dB
Minimum Gain
–76.5
dB
Maximum Gain
18
dB
Minimum Gain
6
dB
VOLUME CONTROL
VCRAUX
VCRMONO
Stereo Input Volume Control Range
MONO Input Volume Control Range
VCRDAC
DAC Volume Control Range
VCRADC
ADC Volume Control Range
VCRMIC
MIC Volume Control Range
Maximum Gain
36
dB
VCRLS
Loudspeaker Amplifier Volume
Control Range
Minimum Gain
0
dB
Maximum Gain
12
dB
VCRHP
Headphone Amplifier Volume
Control Range
Minimum Gain
–18
dB
Maximum Gain
0
dB
SSLS
Loudspeaker Amplifier Volume
Control Stepsize
4
dB
SSHP
Headphone Amplifier Volume
Control Stepsize
Refer to
Table 45
dB
SSAUX
AUX Input Volume Control Stepsize
1.5
dB
SSMONO
MONO Input Volume Control
Stepsize
1.5
dB
SSDAC
DAC Volume Control Stepsize
1.5
dB
SSADC
ADC Volume Control Stepsize
1.5
dB
SSMIC
MIC Volume Control Stepsize
2
dB
25
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LM49360
LM49360
Symbol
LM49360
LM49360
Symbol
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
SVAUX
AUX Volume Setting Variation
±1
dB (max)
SVMONO
MONO Volume Setting Variation
±1
dB (min)
SVMIC
MIC Volume Setting Variation
±1
dB (max)
AUX Gain = 18dB
10
kΩ
AUX Gain = 0dB
38
kΩ
AUX Gain = –46.5dB
64
kΩ
MONO Gain = 18dB
10
kΩ
MONO Gain = 0dB
38
kΩ
MONO Gain = –46.5dB
64
kΩ
All MIC gain settings
50
kΩ
ANALOG INPUTS
AUX_RIN
MONO_RIN
MIC_RIN
Auxiliary Input Impedance
Mono Input Impedance
Microphone Input Impedance
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. LSVDD must always
be the highest input power supply, LSVDD ≥ PVDD, AVDD, IOVDD, Vin and must be supplied first during initial power-up.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
Note 8: The parameters in the electrical characteristic table are tested under open loop conditions at VIN = 3.6V unless otherwise specified. For performance
over the input voltage range and closed loop condition, refer to the datasheet curves.
Note 9: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.
Note 10: The minimum input voltage equals Vout (nom) + 0.5V or 3.0V, which ever is greater.
Note 11: This specification is guaranteed by design.
Note 12: If CONFIG = L, the device can be placed in the standby state by de-asserting the PS_HOLD and PWR_ON pins as shown in Figure 14. If CONFIG =
H or Z, the device can be placed in the standby state by de-asserting the EN pin as shown in Figure 13. None of the software Override (SWOVR) bits can be set
or the device will not be in the standby state.
Note 13: VOS is reduced through auto-calibration. The procedure to start auto-calibration is to make sure the audio section is disabled by setting chip enable = 0
in audio register 0x00. Select the audio path. Enable audio with chip enable = 1. Wait 500 microseconds for the calibration to complete.
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26
LM49360
Symbol
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Units
(Limit)
PLL
fIN
PLL Input Frequency Range
Minimum MCLK Frequency
0.5
MHz (min)
Maximum MCLK Frequency
50
MHz (max)
I2S MASTER TIMING
I2S_CLKPER
I2S_CLK Period
I2S Master
81.38
ns
tCLK_L
I2S_CLK Low Time
I2S Master
37
ns
tCLK_H
I2S_CLK High Time
I2S Master
37
ns
tWS_DLY
WS Propagation Delay from I2S_CLK
falling edge
I2S Master
21
ns
tSDO_DLY
SDO Propagation Delay from I2S_CLK
falling edge
I2S Master
21
ns
tDST
SDI Setup Time to I2S_CLK Rising
Edge
I2S Master
20
ns
tDHT
SDI Hold Time to I2S_CLK Rising
Edge
I2S Master
20
ns
I2S SLAVE TIMING
I2S_CLKPER
I2S_CLK Period
I2S Slave
tCLK_L
I2S_CLK Low Time
I2S
tCLK_H
I2S_CLK High Time
tSDO_DLY
SDO Propagation Delay from I2S_CLK
falling edge
I2S Slave
tDST
SDI Setup Time to I2S_CLK Rising
Edge
I2S Slave
20
ns (min)
tDHT
SDI Hold Time to I2S_CLK Rising
Edge
I2S Slave
20
ns (min)
tWS_ST
WS Setup Time to I2S_CLK Rising
Edge
I2S Slave
20
ns (min)
tWS_HT
WS Hold Time to I2S_CLK Rising
Edge
I2S Slave
20
ns (min)
SCL Frequency
400
kHz (max)
1
Hold Time (repeated START
Condition)
0.6
μs (min)
2
Clock Low Time
1.3
μs (min)
3
Clock High Time
600
ns (min)
4
Setup Time for a Repeated START
Condition
600
ns (min)
Output
(LM49360 generated)
50
ns (min)
Input
(Master generated)
50
ns (min)
81.38
ns (min)
Slave
37
ns (min)
I2S Slave
37
ns (min)
21
ns
CONTROL INTERFACE TIMING
5
Data Hold Time
6
Data Setup Time
100
ns (min)
7
Rise Time of SDA and SCL
300
ns (max)
8
Fall Time SDA and SCL
300
ns (max)
9
Setup Time for STOP Condition
600
ns (min)
27
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LM49360
20.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Note 1, Note 2) The following specifications
apply for RL(SP) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM49360
LM49360
Parameter
10
Bus Free Time Between a STOP and
START Condition
1.3
μs (min)
CB
Bus Capacitance
200
pF (max)
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Conditions
Units
(Limit)
Symbol
28
Typical
(Note 6)
Limit
(Note 7)
LM49360
21.0 Typical Performance Characteristics
Class D Loudspeaker Amplifier Efficiency
vs Output Power
THD+N < 10%, RL = 8Ω
Green >> LSVDD = 3.6V
Gray >> LSVDD = 4.2V
Blue >> LSVDD = 5V
DAC Frequency Response
fS = 48kHz
Blue >> OSR = 64
Light Blue >> OSR = 128
100
90
EFFICIENCY (%)
80
70
60
50
40
30
20
10
0
301282b3
0
400
800
1200
1600
2000
OUTPUT POWER (mW)
301282b2
DAC THD+N vs Frequency
fS = 48kHz, OSR = 128
I2S Input = 500mFFS
DAC Frequency Response
fS = 8kHz
Blue >> OSR = 64
Light Blue >> OSR = 128
30128277
301282b4
29
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LM49360
DAC THD+N vs Frequency
fS = 48kHz, OSR = 64
I2S Input = 500mFFS
DAC THD+N vs Input Level
fS = 48kHz, OSR = 64
I2S Input = 1kHz
30128285
301282b8
Stereo Audio ADC Frequency Response
fS = 48kHz, OSR = 64
From MIC, MIC Gain = 6dB, CIN = 1µF
Stereo Audio ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
301282b9
301282c0
Mono Voice ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Mono Voice ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
301282a0
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30128222
30
LM49360
Stereo Audio HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MONO/AUX, MONO>AUX Gain = 0dB, CIN = 1µF
Gray >> No HPF
Green >> HPF Mode = '101'
Light Blue >> HPF Mode = '110'
Blue >> HPF Mode = '111'
Mono Voice HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Yellow >> HPF Mode = '000'
Light Green >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Blue >> HPF Mode = '011'
Blue >> HPF Mode = '100'
301282a4
301282a5
Mono Voice HPF ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Yellow >> HPF Mode = '000'
Light Green >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Blue >> HPF Mode = '011'
Blue >> HPF Mode = '100'
ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 0dB, VIN = 1VRMS
301282c5
301282a6
31
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LM49360
ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, VIN = 500mVRMS
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 0dB, fIN = 1kHz
301282h6
301282a2
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, fIN = 1kHz
Loudspeaker THD+N vs Frequency
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, POUT = 400mW, RL = 8Ω
Blue >> LSVDD = 3.6V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
301282a3
301282h0
Loudspeaker THD+N vs Frequency
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, POUT = 400mW, RL = 4Ω
Blue >> LSVDD = 3.6V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
Loudspeaker THD+N vs Output Power
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 8Ω
Blue >> LSVDD = 3.6V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
301282h1
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301282h2
32
Loudspeaker PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 3.6V, VRIPPLE = 200mVPP, Input Referred
30128274
301282h3
Loudspeaker PSRR vs Frequency
Loudspeaker PSRR vs Frequency
fS = 48kHz, OSR = 128
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 5V, VRIPPLE = 200mVPP, Input Referred
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 4.2V, VRIPPLE = 200mVPP, Input Referred
30128276
30128275
HeadphoneTHD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 3.3V, POUT = 15mW, RL = 32Ω
Stereo In Phase
Headphone PSRR vs Frequency
DAC Input, DAC Gain = 0dB, LS Gain = 12dB
LSVDD = 3.6V, AVDD = 3.6V,
DVDD = 1.8V, VRIPPLE = 200mVPP
Ripple on LSVDD, AVDD, DVDD, Input Referred
30128267
30128261
33
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LM49360
Loudspeaker THD+N vs Output Power
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 4Ω
Blue >> LSVDD = 3.6V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
LM49360
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 32Ω
Stereo In Phase
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, POUT = 15mW, RL = 16Ω
Stereo In Phase
30128262
30128263
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 16Ω
Stereo in Phase
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.6V, VRIPPLE = 200mVPP
Ripple on HPVDD, AVDD
30128268
30128264
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.6V, VRIPPLE = 200mVPP
Ripple on AVDD only
Headphone PSRR vs Frequency
DAC Input, DAC Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.6V,
DVDD = 1.8V, VRIPPLE = 200mVPP
Ripple on HPVDD, AVDD, DVDD
30128269
30128273
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34
Earpiece THD+N vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.6V, POUT = 20mW, RL = 32Ω
Earpiece Mode
301282e4
30128265
Earpiece PSRR vs Frequency
Auxiliary Output THD+N vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = –6dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.6V, VRIPPLE = 200mVPP, Earpiece Mode
AVDD = 3.6V, VOUT = 1VRMS, RL = 5kΩ
AUXOUT Mode
301282e6
301282e7
Auxiliary Output THD+N vs Output Voltage
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.6V, fIN = 1kHz, RL = 5kΩ
AUXOUT Mode
Auxiliary Output PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.6V, VRIPPLE = 200mVPP, AUXOUT Mode
301282e8
30128266
35
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LM49360
Headphone Crosstalk vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.6V, POUT = 15mW, RL = 32Ω
LM49360
Buck Load Transient
VIN = 3.6V, VOUT = 2.0V, 1–400mA Load
LDO Load Transient
VIN = 3.6V, VOUT = 2.0V, 1–400mA Load
COUT = 1μF LDO1, LDO3
301282g0
301282g1
LDO Load Transient
VIN = 3.6V, VOUT = 2.0V, 1–400mA Load
COUT = 10μF LDO1, LDO3
LDO Load Transient
VIN = 3.6V, VOUT = 2.0V, 1–200mA Load
COUT = 1μF LDO2, LDO4, LDO5, LDO6
301282g2
301282g3
LDO Load Transient
VIN = 3.6V, VOUT = 2.0V, 1–200mA Load
COUT = 10μF LDO2, LDO4, LDO5, LDO6
Buck Turn On Time
VIN = 3.6V, Config = VBATT
301282g5
301282g4
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36
LM49360
Reset Timing
VIN = 3.6V
LDO Turn On Time
VIN = 3.6V, Config = VBATT
301282g6
301282g7
LDO Output Ripple
VIN = 3.6V, Buck 1 and 2 On
LDO Output Ripple
VIN = 3.6V, Buck 1 and 2 Off
301282g9
301282g8
37
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LM49360
22.4 I2C START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is
HIGH. STOP condition is defined as the SDA transitioning
from LOW to HIGH while SCL is HIGH. The I2C master always
generates START and STOP bits. The I2C bus is considered
to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
22.0 System Control
22.1 INPUT POWER SEQUENCING
The following input power supplies are normally connected to
the battery voltage VBAT: LS_VDD, P_VDD, VIN_B1,
VIN_B2, VIN_L1, VIN_L2, VIN_L3. The power to these supplies should always be the highest voltage and applied first.
The remaining supplies: A_VDD, HP_VDD, D_VDD, and I/
O_VDD must be powered after the VBAT supplies or excessive current may be consumed.
22.2 I2C SIGNALS
For I2C control the LM49360's SCL pin is used for the I2C
clock and the SDA pin is used for the I2C data signal. Both of
these signals require a pull-up resistor according to the I2C
specification. The LM49360 requires two unique I2C slave
addresses, with one address accessing the PMU related I2C
registers and the other address accessing the audio related
I2C registers. Since the LM49360 has three modes of PMU
operation depending on the status of the CONFIG pin, the
I2C address that accesses the PMU related I2C registers also
depends on the status of the CONFIG pin.
If CONFIG is tied to ground, the LM49360 operates in APPMU mode and the PMU related registers are accessed via
the I2C chip address that is defined by 'PMU_L_I2C_ADDR'
of I2C register 0x41h with a default address of 11111012.
If CONFIG is tied to VBATTERY, the LM49360 operates in subPMU mode and the PMU related registers are accessed via
the I2C address that is defined by 'PMU_H_I2C_ADDR' of
I2C register 0x40h with a default address of 11111112.
If CONFIG is left floating, the LM49360 operates in CAM
mode and the PMU related registers are accessed via the
I2C chip address that is defined by 'PMU_Z_I2C_ADDR' of
I2C register 0x40h with a default address of 11111002.
The audio related I2C registers are accessed via the I2C chip
address that is defined by 'AUD_I2C_ADDR' of I2C register
0x41h with a default address of 00110102, independent of the
status of the CONFIG pin.
All of the LM49360's I2C chip addresses are selectable via
I2C registers 0x40h and 0x41h in the PMU register space.
30128224
FIGURE 8. I2C Start and Stop Conditions
22.5 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line
during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second
byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
22.3 I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
30128225
FIGURE 9. I2C Chip Address
30128223
FIGURE 7. I2C Signals: Data Validity
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38
LM49360
Register changes take effect at the SCL rising edge during the last ACK from slave.
30128226
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
FIGURE 10. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
30128227
FIGURE 11. Example I2C Read Cycle
30128228
FIGURE 12. I2C Timing Diagram
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LM49360
22.6 I2C TIMING PARAMETERS
Symbol
Parameter
Limit
Min
Units
Max
1
Hold Time (repeated) START Condition
0.6
µs
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
5
Data Hold Time (Output direction, delay generated by LM49360)
300
900
ns
5
Data Hold Time (Input direction, delay generated by the Master)
0
900
ns
6
Data Setup Time
7
Rise Time of SDA and SCL
20+0.1CB
300
ns
8
Fall Time of SDA and SCL
15+0.1CB
300
ns
9
Set-up Time for STOP condition
600
10
Bus Free Time between a STOP and a START Condition
1.3
CB
Capacitive Load for Each Bus Line
10
ns
100
ns
ns
µs
200
pF
NOTE: Data guaranteed by design
22.7 POWER ON SEQUENCE
30128206
FIGURE 13. Simplified Startup Sequence if CONFIG = H or Z (SUB_PMU)
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40
LM49360
30128207
FIGURE 14. Simplified Startup Sequence if CONFIG = L (PMU)
•
•
•
Note 1 : See detailed on/off sequence diagrams for the CONFIG options.
Note 2 : To initiate the shutdown sequence PS_HOLD needs to be held low greater than 30ms before RESET_N is asserted
low. The PMU then starts the shutdown sequence in the opposite order of the startup sequence.
Note 3 : If PS_HOLD is not asserted within 1.5 seconds of the assertion of PWR_ON, the PMU will start the shutdown sequence
and assert RESET_N.
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LM49360
30128253
FIGURE 15. LM493060A CONFIG = H Start-up Sequence
•
•
•
•
•
•
•
tON : 256μs – Reference and bias turn ON.
tS : Programmable time steps. (Typically 8μs.) time step accuracy is defined by OSC frequency accuracy.
Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers
are not rewritten via I2C.
Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process
duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically
50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.
Note 3: LDO4, LDO5 and LDO6 are enabled via I2C. These outputs will be disabled at ts = 0, when EN goes from High to Low.
Note 4: Buck 2 is enabled by SUBOVR or I2C. If this input is high when EN goes to high then this output turns on after tS7.
Note 5: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained
until device power is removed. Register values are retained when PMU outputs are disabled via EN going low.
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42
LM49360
30128256
FIGURE 16. LM49360A CONFIG = L Start-up Sequence
•
•
•
•
•
•
tBON : 256μs – Reference and bias turn ON.
tS : Programmable time steps. (Typically 64μs) time step accuracy is defined by OSC frequency accuracy.
Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers
are not rewritten via I2C.
Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process
duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically
50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.
Note 3: Buck 2, LDO2, and LDO4 are enabled via I2C.
Note 4: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained
until device power is removed. Register values are retained when PMU outputs are disabled via PS_HOLD going low.
43
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LM49360
30128255
FIGURE 17. LM49360A CONFIG = Z Start-up Sequence
•
•
•
•
•
tBON : 256μs – Reference and bias turn ON
tS : Programmable time steps. (Typically 64μs.) time step accuracy is defined by OSC frequency accuracy.
Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers
are not rewritten via I2C.
Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process
duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically
50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.
Note 3: LDO7 is enabled via I2C.
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44
Note 4: Buck 2 is enabled by SUBOVR or I2C. If this input is high when EN goes to high then this output turn on after tS = 7.
Note 5: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained
until device power is removed. Register values are retained when PMU outputs are disabled via EN going low.
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LM49360
•
•
LM49360
23.0 Device Register Map
TABLE 1. PMU Register Map
Address Register
Default
Value
7
6
5
4
3
2
1
0
Basic Setup
0x00h
PMU
SETUP
0x01h
NV
BANKS
SWOVR
FORCE_ENABLE
RESERVED
RESERVED
0x02h
SLEEP1
LDO4SLP
LDO3SLP LDO2SLP
LDO1SLP
BK2SLP
BK1SLP
0x03h
FLAGS1
LDO6SLP LDO5SLP
LDO6
LDO5
LDO4
LDO3
LDO2
LDO1
0x04h
FLAGS2
UVLO
_EVENT
UVLO
BK2
WAKE
BK1
WAKE
TSDL
TSDH
0x05h
BYPASS
LDO6_BY
LDO5_BY LDO4_BY
LDO3_BY
LDO2_BY
LDO1_BY
0x06h
SWOVR1
LDO6
SWOVR
LDO5
SWOVR
LDO4
SWOVR
LDO3
SWOVR
LDO2
SWOVR
LDO1
SWOVR
0x07h
SWOVR2
RSVD
RSVD
RSVD
RSVD
BK2
_SWOVR
BK1
_SWOVR
0x10h
ENB1
0xFFh LDO6_EN LDO5_EN
LDO1_EN
BK2_EN
BK1_EN
0x11h
ENB2
0x00h
0x12h
BK1V
0x67h
BK1_VSEL
0x13h
BK2V
0x67h
BK2_VSEL
0x14h
LDO1
0xACh
LDO1_DLY
LDO1_VSEL
0x15h
LDO2
0x99h
LDO2_DLY
LDO2_VSEL
0x16h
LDO3
0x79h
LDO3_DLY
LDO3_VSEL
0x17h
LDO4
0xACh
LDO4_DLY
LDO4_VSEL
0x18h
LDO5
0x99h
LDO5_DLY
LDO5_VSEL
0x19h
LDO6
0x99h
LDO6_DLY
0x1Ah
LDO7
0x07h
LDO7_DLY
BK2_RDY BK1_RDY
UVLO
_MASK
RSVD
SW
LDO7
PSHOLD SWOVR
BANK 0 CONFIG = Z (subPMU)
BK2OVR
LDO4_EN
LDO7_EN
0x1Bh
THRES
0x9Ah LDO7_PD RSVD
0x1Ch
PLDWN
0xFFh LDO6_PD LDO5_PD
LDO3_EN LDO2_EN
BK2_DLY
BK1_DLY
LDO6_VSEL
RSVD
LDO7_VSEL
TIMESTEP
UVLO_VSEL
LDO4_PD
LDO3_PD LDO2_PD
LDO1_PD
LDO6OVR LDO5OVR
LDO4OVR LDO3OVR
LDO2OVR LDO1OVR
LDO5
SubOVR
LDO1
SubOVR
0x1Dh
OVR
0x80h
LDO7OV
R
0x1Eh
SubOVR
0x00h
LDO7
SubOVR
0x20h
ENB1
0x1Dh LDO6_EN LDO5_EN
0x21h
ENB2
0x41h
0x22h
BK1V
0x45h
LDO4
SubOVR
BK1
SubOVR
BK2_PD
BK1_PD
BK1OVR
RESET_MODE
BANK 1 CONFIG = H (subPMU)
BK2OVR
LDO4_EN
LDO7_EN
LDO3_EN LDO2_EN
LDO1_EN
BK2_DLY
BK1_DLY
BK1_VSEL
0x23h
BK2V
0x9Ah
0x24h
LDO1
0x0Ch
LDO1_DLY
LDO1_VSEL
0x25h
LDO2
0x1Bh
LDO2_DLY
LDO2_VSEL
0x26h
LDO3
0x3Fh
LDO3_DLY
LDO3_VSEL
0x27h
LDO4
0x0Ch
LDO4_DLY
LDO4_VSEL
0x28h
LDO5
0x15h
LDO5_DLY
LDO5_VSEL
0x29h
LDO6
0x19h
LDO6_DLY
0x2Ah
LDO7
0x2Bh
LDO7_DLY
0x2Bh
THRES
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BK2_EN
BK2_VSEL
0x8Ah LDO7_PD RSVD
LDO6_VSEL
RSVD
TIMESTEP
46
LDO7_VSEL
UVLO_VSEL
BK1_EN
7
0x2Ch
PLDWN
0x2Dh
OVR
0x00h
0x2Eh
SubOVR
/RESET
0x00h
6
5
0xFFh LDO6_PD LDO5_PD
4
3
2
1
LDO4_PD
LDO3_PD LDO2_PD
LDO1_PD
LDO7
OVR
LDO6OVR LDO5OVR
LDO4OVR LDO3OVR
LDO2OVR LDO1OVR
LDO7
SubOVR
LDO5
SubOVR
LDO1
SubOVR
LDO4
SubOVR
BK1
SubOVR
BK2PD
0
BK1PD
BK1OVR
RESET_MODE
BANK 2 CONFIG = L (PMU Mode)
0x30h
ENB1
0xD5h LDO6_EN LDO5_EN
0x31h
ENB2
0x40h
0x32h
BK1V
0x67h
BK1_VSEL
0x33h
BK2V
0xCDh
BK2_VSEL
0x34h
LDO1
0x8Ch
LDO1_DLY
LDO1_VSEL
0x35h
LDO2
0x15h
LDO2_DLY
LDO2_VSEL
0x36h
LDO3
0x99h
LDO3_DLY
LDO3_VSEL
0x37h
LDO4
0x1Fh
LDO4_DLY
LDO4_VSEL
0x38h
LDO5
0x9Fh
LDO5_DLY
LDO5_VSEL
0x39h
LDO6
0x99h
LDO6_DLY
LDO6_VSEL
0x81h
LDO7_DLY
BK2OVR
0x3Ah
LDO7
0x3Bh
THRES
0x9Ah LDO7_PD RSVD
0x3Ch
PLDWN
0xFFh LDO6_PD LDO5_PD
0x3Dh
OVR
0x00h
LDO7OV
R
LDO4_EN
LDO3_EN LDO2_EN
LDO7_EN
LDO1_EN
BK2_DLY
BK2_EN
BK1_EN
BK1_DLY
RSVD
LDO7_VSEL
TIMESTEP
UVLO_VSEL
LDO4_PD
LDO3_PD LDO2_PD
LDO1_PD
BK2PD
LDO6OVR LDO5OVR
LDO4OVR LDO3OVR
LDO2OVR LDO1OVR
BK1PD
BK1OVR
I2C DEVICE ADDRESSES
0x40h
I2C1
RSVD
RSVD
0x41h
I2C2
RSVD
RSVD
PMU_Z_I2C_ADDR
PMU_H_I2C_ADDR
AUD_I2C_ADDR
PMU_L_I2C_ADDR
BUCK MODE SELECTION
0x5Ah
BK1_
FPWM
FORCE_
PWM
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x5Eh
BK2_
FPWM
FORCE_
PWM
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TABLE 2. Audio Register Map
Address
Register
7
6
5
4
3
2
1
0
OSC
ENB
PLL_P2
ENB
PLL
ENB
CHIP
ENABLE
BASIC SETUP
0x00h
PMC
SETUP
0x01h
PMC
CLOCKS
0x02h
PMC
CLK_DIV
CHIP
ACTIVE
PORT2
CLK OVR
PORT1
CLK OVR
MCLK
OVR
PMC_CLK_SEL
PMC_CLK_DIV(R)
PLL
0x03h
PLL_CLK_SEL
0x04h
PLL M
0x05h
PLL N
0x06h
PLL
N_MOD
0x07h
PLL P
0x08h
PLL P2
PLL M
PLL N
PLL P2[8]
PLL P1[8]
PLL N_MOD
PLL P1 [7:0]
PLL P2[7:0]
ANALOG MIXER
0x10h
CLASSD
AUX_LS
MONO_LS
47
DACL_LS
DACR_LS
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LM49360
Default
Value
Address Register
LM49360
Address
Register
0x11h
7
6
5
4
HEAD
PHONESL
AUX_HPL
MONO
_HPL
0x12h
HEAD
PHONESR
AUX_HPR
MONO
_HPR
0x13h
AUX_OUT
AUX_AUX
MONO
_AUX
MIC_AUX
0x14h
OUTPUT
OPTIONS
AUX_LINE
_OUT
AUX_NEG
_6dB
LR_HP_LEVEL
0x15h
ADC
MONO
_ADCL
AUX
_ADCR
MUTE
SE/DIFF
LS_LEVEL
0x16h
MIC_LVL
0x18h
AUXL_LVL
SE/DIFF
0x19h
MONO_LV
AUXL_MON
SE/DIFF
O_IN
0x1Bh
HP
_SENSE
3
2
1
0
DACL_HPL DACR_HPL
MIC_ADCL MIC_ADCR
DACL
_HPR
DACR
_HPR
DACL_AUX
DACR
_AUX
RSVD
DACL
_ADCL
DACR
_ADCR
MIC_LEVEL
AUX_LEVEL
MONO_LEVEL
HP SENSE HP SENSE
_AUX_D
_AUX
HP
SENSE_D
HP SENSE
ADC_OSR
MONO
ADC
0x20h
ADC BASIC DSPONLY
ADC_CLK_SEL
MUTE_R
MUTE_L
0x21h
ADC
CLOCK
0x23h
ADC
_MIXER
0x30h
DAC
_BASIC
0x31h
DAC
_CLOCK
0x40h
IPLVL1
PORT2_RX_R_LVL
PORT2_RX_L_LVL
PORT1_RX_R_LVL
PORT1_RX_L_LVL
0x41h
IPLVL2
INTERP_L_LVL
INTERP_R_LVL
ADC_R_LVL
ADC_L_LVL
0x42h
OPPORT1
MONO
SWAP
R_SEL
L_SEL
0x43h
OPPORT2
MONO
SWAP
R_SEL
0x44h
OPDAC
ADCR
PORT2R
0x45h
OPDECI
ADC_CLK_DIV (T)
STEREO
_LINK
ADC_MIX_LEVEL_R
ADC_MIX_LEVEL_L
DAC
DSPONLY
DAC_CLK_SEL
MUTE_R
MUTE_L
DAC_OSR
DAC_CLK_DIV (S)
DIGITAL MIXER
SWAP
PORT1R
MXRCLK_SEL
L_SEL
ADCL
R_SEL
PORT2L
PORT1L
L_SEL
AUDIO PORT 1
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
0x50h
BASIC
CLK_PH
SYNC_MS
0x51h
CLK_GEN1
0x52h
CLK_GEN2
0x53h
SYNC
_GEN
0x54h
DATA
_WIDTH
0x55h
RX_MODE
A/ULAW
COMPAND
MSB_POSITION
RX_MODE
0x56h
TX_MODE
A/ULAW
COMPAND
MSB_POSITION
TX_MODE
0x60h
BASIC
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
0x61h
CLK_GEN1
CLK_SEL
CLK_MS
TX_ENB
RX_ENB
STEREO
HALF_CYCLE_DIVIDER
SYNTH
_DENOM
SYNTH_NUM
SYNC_WIDTH(MONO MODE)
SYNC_RATE
TX_WIDTH
RX_WIDTH
TX_EXTRA_BITS
AUDIO PORT 2
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CLK_PH
SYNC_MS
CLK_SEL
CLK_MS
TX_ENB
HALF_CYCLE_DIVDER
48
RX_ENB
STEREO
Register
7
6
0x62h
CLK_GEN2
0x63h
SYNC
_GEN
0x64h
DATA
_WIDTH
0x65h
RX_MODE
A/ULAW
COMPAND
0x66h
TX_MODE
A/ULAW
COMPAND
5
4
3
2
1
SYNTH_
DENOM
SYNTH_NUM
SYNC_WIDTH(MONO MODE)
SYNC_RATE
TX_WIDTH
RX_WIDTH
TX_EXTRA_BITS
0
MSB_POSITION
RX_MODE
MSB_POSITION
TX_MODE
EFFECTS ENGINE
0x70h
ADC FX
ADC
SCLP ENB
RSVD
ADC
PK ENB
ADC
ALC ENB
ADC
HPF_ENB
0x71h
DAC FX
DAC
SCLP ENB
RSVD
DAC
EQ ENB
DAC
PK ENB
DAC
ALC ENB
0x80h
HPF
0x81h
ADC
ALC 1
0x82h
ADC
ALC 2
0x83h
ADC
ALC 3
ALC_TARGET_LEVEL
0x84h
ADC
ALC 4
ATTACK_RATE
0x85h
ADC
ALC 5
0x86h
ADC
ALC 6
0x87h
ADC
ALC 7
MAX_LEVEL
0x88h
ADC
ALC 8
MIN_LEVEL
0x89h
ADC L
LEVEL
0x8Ah
ADC R
LEVEL
0x90h
SOFTCLIP
1
0x91h
SOFTCLIP
2
RATIO
0x92h
SOFTCLIP
3
LEVEL
ADC EFFECTS
HPF MODE
SOURCE
OVR
SOURCE
RSEL
SOURCE
LSEL
STEREO
LINK
LIMITER
ADC_SAMPLE
NG_ENB
NOISE_FLOOR
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
HOLDTIME
STEREO
LINK
ADC_L_LEVEL
ADC_R_LEVEL
SOFT
KNEE
THRESHOLD
ADC EFFECT MONITORS
0x98h
LVLMONL
ADC LEFT LEVEL MONITOR
0x99h
LVLMONR
ADC RIGHT LEVEL MONITOR
0x9Ah
FXCLIP
SCLP_R
CLIP
SCLP_L
CLIP
0x9Bh
ALCMONL
SCLP_R
DISTORT
SCLP_L
DISTORT
ADC LEFT ALC MONITOR
0x9Ch
ALCMONR
SCLP_L
DISTORT
SCLP_R
DISTORT
ADC RIGHT ALC MONITOR
GAIN
_R CLIP
GAIN
_L CLIP
ADC_R
CLIP
ADC_L
CLIP
DAC EFFECTS
49
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LM49360
Address
LM49360
Address
Register
0xA0h
7
6
5
4
3
2
1
DAC
ALC 1
STEREO
LINK
LIMITER
0xA1h
DAC
ALC 2
NG_ENB
0xA2h
DAC
ALC 3
AGC_TARGET_LEVEL
0xA3h
DAC
ALC 4
ATTACK_RATE
0xA4h
DAC
ALC 5
0xA5h
DAC
ALC 6
0xA6h
DAC
ALC 7
MAX_LEVEL
0xA7h
DAC
ALC 8
MIN_LEVEL
0xA8h
DAC L
LEVEL
0xA9h
DAC R
LEVEL
0
DAC_SAMPLE
NOISE_FLOOR
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
HOLDTIME
STEREO
LINK
DAC_L_LEVEL
DAC_R_LEVEL
0xABh
EQ BAND 1
LEVEL
FREQ
0xACh
EQ BAND 2
Q
LEVEL
FREQ
0xADh
EQ BAND 3
Q
LEVEL
FREQ
0xAEh
EQ BAND 4
Q
LEVEL
FREQ
0xAFh
EQ BAND 5
LEVEL
FREQ
0xB0h
SOFTCLIP
1
SOFT
KNEE
0xB1h
SOFTCLIP
2
RATIO
0xB2h
SOFTCLIP
3
LEVEL
0xB8h
LVLMONL
0xB9h
LVLMONR
THRESHOLD
DAC EFFECT MONITORS
DAC LEFT LEVEL MONITOR
DAC RIGHT LEVEL MONITOR
0xBAh
FXCLIP
SCLP_R
CLIP
SCLP_L
CLIP
EQ_R
CLIP
EQ_L
CLIP
0xBBh
ALCMONL
SCLP_R
DISTORT
SCLP_L
DISTORT
DAC LEFT ALC MONITOR
0xBCh
ALCMONR
SCLP_L
DISTORT
SCLP_R
DISTORT
DAC RIGHT ALC MONITOR
0xE0h
GPIO1
GPIO_RX
GPIO_TX
0xE1h
GPIO2
RSVD
GAIN
_R CLIP
GAIN
_L CLIP
TEMP
SHORT
RSVD
RSVD
RSVD
SS
_DISABLE
RSVD
RSVD
DACREF
RSVD
RSVD
GPIO
GPIO_MODE
SPREAD SPECTRUM
0xF0h
RESET
0xF1h
SS
0xFEh
FORCE
SOFT
_RESET
RSVD
CPFORCE
Unless otherwise specified, the default values of the I2C registers is 0x00H.
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RSVD
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LM49360
TABLE 3. Nonzero I2C Default Registers
Address
Register
Default Data Value
0x02h
PMC_CLK_DIV
0x50h
0x30h
DAC_BASIC
0x02h
0x31h
DAC_CLOCK
0x03h
0x84h
ADC_ALC_4
0x0Ah
0x85h
ADC_ALC_5
0x0Ah
0x86h
ADC_ALC_6
0x0Ah
0x87h
ADC_ALC_7
0x1Fh
0x89h
ADC_L_LEVEL
0x33h
0x8Ah
ADC_R_LEVEL
0x33h
0xA3h
DAC_ALC_4
0x0Ah
0xA4h
DAC_ALC_5
0x0Ah
0xA5h
DAC_ALC_6
0x0Ah
0xA6h
DAC_ALC_7
0x33h
0xA8h
DAC_L_LEVEL
0x33h
0xA9h
DAC_R_LEVEL
0x33h
0xF0h
RESET
0x02h
TABLE 4. 0x00h PMU Setup
Bits
Field
4:0
RSVD
6:5
FORCE
_ENABLE
7
Description
Reserved
This determines the startup mode of the LM49360.
FORCE_ENABLE
SWOVR
MODE
00
Selected by the CONFIG pin
01
Force Bank 0 (CAM)
10
Force Bank 1 (SUB_PMU)
11
Force Bank 2 (AP_PMU)
If SWOVR (Software Override) is set, it allows PMU outputs to be enabled under I2C control of the
SWOVR (Software Override) bits in I2C registers SWOVR 1 (0x06h) and SWOVR 2 (0x07h)
TABLE 5. NV BANK (0x01h)
Bits
Field
7:0
RSVD
Description
Reserved
24.0 Sleep Enables
TABLE 6. SLEEP 1 (0x02h)
Bits
Field
0
BK1_SLEEP
If set, Buck 1 is set to sleep state.
BK2_SLEEP
If set, Buck 2 is set to sleep state.
1
Description
2
LDO1_SLEEP If set, LDO 1 is set to sleep state.
3
LDO2_SLEEP If set, LDO 2 is set to sleep state.
4
LDO3_SLEEP If set, LDO 3 is set to sleep state.
5
LDO4_SLEEP If set, LDO 4 is set to sleep state.
6
LDO5_SLEEP If set, LDO 5 is set to sleep state.
7
LDO6_SLEEP If set, LDO 6 is set to sleep state.
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LM49360
25.0 LDO Flags and Bypass Pulse Control
TABLE 7. FLAGS 1 (0x03h)
Bits
Field
0
LDO1_ERROR
If 1 an error is present on this LDO.
Description
1
LDO2_ERROR
If 1 an error is present on this LDO.
2
LDO3_ERROR
If 1 an error is present on this LDO.
3
LDO4_ERROR
If 1 an error is present on this LDO.
4
LDO5_ERROR
If 1 an error is present on this LDO.
5
LDO6_ERROR
If 1 an error is present on this LDO.
TABLE 8. FLAGS 2 (0x04h)
Bits
Field
Description
0
TSDH
Set if TSDH is reported from the analog. >160 degrees
1
TSDL
Set if TSDL is reported from the analog. >120 degrees
2
BK1_WAKEUP
Output from BK1 - should toggle in sleep mode when the BUCK wakes up
momentarily to step back above the threshold.
3
BK2_WAKEUP
Output from BK2 - should toggle in sleep mode when the BUCK wakes up
momentarily to step back above the threshold.
4
RESERVED
5
UVLO_EVENT
Reserved bit
6
BK1_RDY
Reports if BK1 is above 90% of it's programmed output voltage.
7
BK2_RDY
Reports if BK2 is above 90% of it's programmed output voltage.
1 = debounced UVLO event detected, 0 = UVLO not currently triggered.
TABLE 9. BYPASS (0x05h)
Bits
Field
0
LDO1_BY
1
LDO2_BY
2
LDO3_BY
3
LDO4_BY
4
LDO5_BY
5
LDO6_BY
6
RSVD
7
UVLO_MASK
Description
If set, the internal reference filter is bypassed. Set this bit high for 1ms after
changing VSEL if the output voltage needs to be adjusted while the LDO is
enabled. Otherwise the internal filter will slow the transition time to over a second.
This is performed automatically every time the LDO is enabled, only use the filter
bypass when adjusting VSEL when the LDO is enabled."
Reserved
If set, the effects of the UVLO trigger are Ignored by the state machine. This can
be useful if the user wishes to determine the current battery voltage without
powering up an ADC. The UVLO trigger level can be increased until the I2C
reports a UVLO event, the level can then be changed back and the mask cleared
to return to normal operation.
TABLE 10. SWOVR 1 (0x06h)
Bits
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Field
Description
0
LDO1_SWOVR
If set, LDO1 will enable when SWOVR is set and the device is in Standby state or
above.
1
LDO2_SWOVR
If set, LDO2 will enable when SWOVR is set and the device is in Standby state or
above.
2
LDO3_SWOVR
If set, LDO3 will enable when SWOVR is set and the device is in Standby state or
above.
3
LDO4_SWOVR
If set, LDO4 will enable when SWOVR is set and the device is in Standby state or
above.
4
LDO5_SWOVR
If set, LDO5 will enable when SWOVR is set and the device is in Standby state or
above.
52
Field
Description
5
LDO6_SWOVR
If set, LDO6 will enable when SWOVR is set and the device is in Standby state or
above.
6
LDO7_SWOVR
If set, the LDO7 will enable when SWOVR is set and the device is in Standby state
or above.
7
SW_PSHOLD
Can be used in AP_PMU mode as an alternative to raising the PS_HOLD pin.
TABLE 11. SWOVR 2 (0x07h)
Bits
Field
Description
0
BK1_SWOVR
If set, Buck 1 will enable when SWOVR is set and the device is in Standby state
or above.
1
BK2_SWOVR
If set, Buck 2 will enable when SWOVR is set and the device is in Standby state
or above.
5:2
RSVD
Reserved
26.0 Sequence and Voltage Programming (Banks 0 to 2)
TABLE 12. ENB1
Bank 0: CONFIG = Z (0x10h)
Bank 1: CONFIG = H (0x20h)
Bank 2: CONFIG = L (0x30h)
Bits
Field
0
BK1_ENABLE
If set, Buck 1 is enabled at timestep BUCK1_DLY.
Description
1
BK2_ENABLE
If set, Buck 2 is enabled at timestep BUCK2_DLY.
2
LDO1_ENABLE
If set, LDO 1 is enabled at timestep LDO1_DLY.
3
LDO2_ENABLE
If set, LDO 2 is enabled at timestep LDO2_DLY.
4
LDO3_ENABLE
If set, LDO 3 is enabled at timestep LDO3_DLY.
5
LDO4_ENABLE
If set, LDO 4 is enabled at timestep LDO4_DLY.
6
LDO5_ENABLE
If set, LDO 5 is enabled at timestep LDO5_DLY.
7
LDO6_ENABLE
If set, LDO 6 is enabled at timestep LDO6_DLY.
Note: Do not set these registers to 0x00. At least one regulator must remain enabled for proper operation.
BUCK INFORMATION
The LM49360 has two integrated high efficiency step-down DC-DC switching buck converters that deliver a constant voltage from
a single cell battery to portable devices. Using voltage mode architecture with synchronous rectification, the buck has the ability
to deliver up to 800mA depending on the input voltage and output voltage, ambient temperature, and the inductor chosen.
There are two modes of operation depending on the current required - PWM (Pulse Width Modulation), ECO (ECOnomy) mode.
The device operates in PWM mode at load currents of approximately 50mA (typ.) or higher. Lighter output current loads cause the
device to automatically switch into ECO mode for reduced current consumption and a longer battery life. Additional features include
soft-start, under voltage protection, current overload protection, and thermal shutdown protection. Only three external power components are required for implementation.
Buck Circuit Operation
The switching buck converter operates as follows. During the first portion of each switching cycle, the control block in the LM49360
turns on the internal PMOS switch. This allows current to flow from the input through the inductor to the output filter capacitor and
load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second
portion of each cycle, the controller turns the PMOS switch off, blocking current flow from the input, and then turns the NMOS
synchronous rectifier on. The inductor draws current from ground through the NMOS to the output filter capacitor and load, which
ramps the inductor current down with a slope of –VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PMOS switch on time to control the average current sent to the load. The effect
is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to
a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW
pin.
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LM49360
Bits
LM49360
ENABLING AND DISABLING VOUT
Do not power down all voltage outputs via the I2C register ENB1 (LDO1, 2, 3, 4, 5, 6, Buck 1 and Buck 2) and I2C register ENB2
(LDO 7). It is recommended to place the LM49360 in the standby mode to disable all the VOUT outputs. If CONFIG = L the device
can be placed in the standby state by de-asserting the PS_HOLD and PWR_ON pins as shown in Figure 14. If CONFIG = H or Z
the device can be placed in the standby state by de-asserting the EN pin as shown in Figure 13. Each individual VOUT can be
disabled and enabled via the I2C registers ENB1 and ENB2, however one VOUT must remained enabled for the proper device
operation. Prior to change a VOUT voltage selection (ie. VSEL) it is recommended to disable the VOUT voltage prior to the VOUT
voltage selection change, then re-enable after making the VOUT voltage selection.
PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate
this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is
regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the
beginning of each clock cycle the PMOS switch is turned on and the inductor current ramps up until the comparator trips and the
control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PMOS is
exceeded. Then the NMOS switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning
off the NMOS and turning on the PMOS.
30128232
FIGURE 18. Typical PWM Operation
Internal Synchronous Operation
While in PWM mode, the buck uses an internal NMOS as a synchronous rectifier to reduce rectifier forward voltage drop and
associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is
relatively low compared to the voltage drop across an ordinary rectifier diode.
Current Limiting
A current limit feature allows the device to protect itself and external components during overload conditions. PWM mode implements current limit using an internal comparator that trips at 1200mA (typ.). If the output is shorted to ground and output voltage
becomes lower than 0.3V (typ.), the device enters a timed current limit mode where the switching frequency will be one fourth, and
NMOS synchronous rectifier is disabled, thereby preventing excess current and thermal runaway.
ECO Mode Operation
The buck switches from ECO state to PWM state based on output load current. At light loads (less than 50mA), the converter
enters ECO mode. In this mode the part operates with low Iq. During ECO operation, the converter positions the output voltage
slightly higher (+30mV typ.) than the nominal output voltage in PWM operation. Because the reference is set higher, the output
voltage increases to reach the target voltage when the part goes from idle state to switching state. Once this voltage is reached
the converter stops switching, thereby reducing switching losses and improving light load efficiency. The output voltage ripple is
slightly higher in ECO mode (30mV peak–peak ripple typ.).
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LM49360
30128233
FIGURE 19. Typical ECO Operation
Inductor Selection for Buck 1 and Buck 2 Operation
A 1.0μH inductor should be selected. The inductor should be able to handle the maximum current without significant degradation
on inductance and it’s saturation current should not be significantly lower than 1.2A. Additionally the inductors DC Resistance
should not be greater than 100mΩ. The table below shows the possible selection of inductor types and suppliers.
TABLE 13. Buck 1 and Buck 2 Operation
Model
Vendor
Dimensions LxWXH (mm)
MIPSZ2012D1R0
FDK
2.0 x 1.25 x 1
90
CBC2016T1R0M
Taiyo Yuden
2.0 x 1.6 x 1.6
100
EPL2010-102ML
Coilcraft
2.0 x 2.0 x 1.05
99
DCR (mΩ)
Buck Output Voltage Selection
The selection of the bucks’ output voltages can be done by writing a specific code into the control registers (addr. 0x12, 0x22, 0x32
for Buck1… addr. 0x13, 0x23, 0x33 for Buck2). The required voltage can be calculated from the following equation.
VOUT (V) = 0.6V + code(dec) x 0.00588V
TABLE 14. ENB2
Bank 0: CONFIG = Z (0x11h)
Bank 1: CONFIG = H (0x21h)
Bank 2: CONFIG = L (0x31h)
Bits
Field
2:0
BK1_DELAY
Description
This sets the time slot when Buck1 enables and disables.
000
Power up in slot 0, Power down in slot 0
001
Power up in slot 1, Power down in slot 1
010
Power up in slot 2, Power down in slot 2
011
Power up in slot 3, Power down in slot 3
100
Power up in slot 4, Power down in slot 4
101
Power up in slot 5, Power down in slot 5
110
Power up in slot 6, Power down in slot 6
111
Power up in slot 7, Power down in slot 7
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LM49360
Bits
Field
5:3
BK2_DELAY
6
LDO7_ENABLE
7
BK2_OVR
Description
This sets the time slot when Buck2 enables and disables.
000
Power up in slot 0, Power down in slot 0
001
Power up in slot 1, Power down in slot 1
010
Power up in slot 2, Power down in slot 2
011
Power up in slot 3, Power down in slot 3
100
Power up in slot 4, Power down in slot 4
101
Power up in slot 5, Power down in slot 5
110
Power up in slot 6, Power down in slot 6
111
Power up in slot 7, Power down in slot 7
If set, LDO 7 is enabled and disabled at time slot LDO7_DLY.
If set, BUCK2 will enable when the OVR pin is asserted.
TABLE 15. BK1V
Bank 0: CONFIG = Z (0x12h)
Bank 1: CONFIG = H (0x22h)
Bank 2: CONFIG = L (0x32h)
Bits
7:0
Field
BK1_VSEL
Description
Sets the Buck 1 output voltage.
Vout(V) = 0.6 + (BK1_VSEL*0.00588)
TABLE 16. BK2V
Bank 0: CONFIG = Z (0x13h)
Bank 1: CONFIG = H (0x23h)
Bank 2: CONFIG = L (0x33h)
Bits
Field
7:0
BK2_VSEL
Description
Sets the Buck 2 output voltage.
Vout(V) = 0.6 + (BK2_VSEL*0.00588)
LDO INFORMATION
There are 8 LDOs in LM49360 grouped as:
6 General type “PERFECT” LDOs
1 HILO LDO
1 µPWR LDO
All LDOs can be programmed through serial interface for different output voltage values, which are summarized in the LDO output
voltage selection register tables.
For stability all LDOs need to have an external capacitor Cout connected to the output with the recommended value of 1μF. It is
important that the capacitance is within the specified value across voltage and temperature.
PMU Enabled
The PMU allows four major methods of enabling and disabling the PMU outputs.
The first method is to use the I2C registers ENB1 and ENB2. Then set the Timestep and Delay for the required power sequence.
The second method is via the OVR pin and the OVR register bits to enable any of the PMU outputs under hardware control. This
mode is available in AP_PMU, SUB-PMU and CAM modes.
The third method is via the SUBOVR pin and the SUBOVR register bits to enable any of the SUB-PMU outputs Buck 1, LDO1,
LDO4, LDO5 and LDO7 under hardware control. This mode is available in SUB-PMU and CAM modes. A subset of this mode is
that the SUBOVR pin can be used to enable Buck 2 without setting a SUBOVR register bit. This means that Buck 2 will always be
enabled when the SUBOVR pin is high.
The fourth method is software control via I2C access to the ENB2, SWOVR 1 and SWOVR 2 registers. This mode is available in
AP_PMU, SUB-PMU and CAM modes.
The PMU outputs are enabled on an “OR” condition of the 4 methods. If the enable bits in the I2C registers ENB1 and ENB2 are
cleared, one of the other three methods can be used to enable and disable the PMU outputs. If the Timestep and Delays are
programmed but the Enables (ENB1, ENB2) are cleared, then the initial enabling of the PMU output via hardware and software
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56
CONFIG
Pin Sate
PMU
Enabled
OVR
Hardware
Override
SUBOVR
Hardware
Override
L, H, Z
Buck1, Buck2,
LDO1, LDO2,
LDO3, LDO4,
LDO5, LDO6,
LDO7
OVR Pin = H &&
OVR Reg bit = 1b
H, Z
Buck1, LDO1,
LDO4, LDO5,
LDO7
SUBOVR Pin = H
&& SUBOVR Reg
bit = 1b
H, Z
Buck2 Only
SUBOVR Pin = H
L, H, Z
Buck 1, Buck 2,
LDO1, LDO2,
LDO3, LDO4,
LDO5, LDO6,
LDO7
L, H, Z
Buck 1, Buck 2,
LDO1, LDO2,
LDO3, LDO4,
LDO5, LDO6,
LDO7
SWOVR
Software
Override
ENB1 & ENB2
Default
Mode
PMU Setup Reg
SWOVR = 1b &&
{SWOVR 1 Reg bit
= 1b || SWOVR 2
Reg bit = 1b}
ENABLE = 1b,
PMU enabled at
the specified
timestep.
The OVR register bits for Buck 1 and LDO1 thru LDO7 are located in the following I2C OVR registers:
- Bank 0: CONFIG = Z (0x1Dh), bits 0 – 7.
- Bank 1: CONFIG = H (0x2Dh), bits 0 – 7.
- Bank 2: CONFIG = L (0x3Dh), bits 0 – 7.
The OVR register bit for Buck 2 is located in the following ENB2 registers:
- Bank 0: CONFIG = Z (0x11h), bit 7.
- Bank 1: CONFIG = H (0x21h), bit 7.
- Bank 2: CONFIG = L (0x31h), bit 7.
The SUBOVR register bits for Buck 1, LDO1, LDO4, LDO5 and LDO7 are located in the following I2C SUBOVR registers
- Bank 0: CONFIG = Z (0x1Eh), bits 3 – 7.
- Bank 0: CONFIG = Z (0x1Eh), bits 3 – 7.
The SWOVR register bits for LDO1, LDO2, LDO3, LDO4, LDO5 and LDO7 (HILO) are located in the I2C SWOVR 1(0x06h). The
SWOVR register bits for Buck 1 and Buck 2 are located I2C SWOVR 2(0x07h). The SWOVR register bit in the I2C PMU Setup
(0x00h) must be set for the register bits in SWOVR 1 and SWOVR 2 to be enabled.
The I2C SWOVR 1(0x06h) register also supports a software PS_HOLD, bit 7.
The enable register bits for Buck 1, Buck 2, LDO1, LDO2, LDO3, LDO4, LDO5 and LDO6 are located in the following I2C ENB1
registers:
- Bank 0: CONFIG = Z (0x10h), bits 0 – 7.
- Bank 1: CONFIG = H (0x20h), bits 0 – 7.
- Bank 2: CONFIG = L (0x30h), bits 0 – 7.
The enable register bit for LDO7 is located in the following I2C ENB2 registers:
- Bank 0: CONFIG = Z (0x11h), bit 6.
- Bank 1: CONFIG = H (0x21h), bits 6.
- Bank 2: CONFIG = L (0x31h), bits 6.
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LM49360
occurs immediately upon the hardware or software override. Subsequently if the PMU is disabled via PWR_ON and PS_HOLD
the (and the enable condition still exist, hardware or software) the subsequent powering of the PMU output will be based upon the
programmed Timestep and Delays.
LM49360
PMU Sleep
The SLEEP state(s) can be enabled and disabled for each of the voltage outputs independently in the I2C register SLEEP (0x02h).
PMU Under Voltage Lock Out (UVLO)
The PMU registers that support the UVLO are listed in the table below. See individual register descriptions for the details.
I2C Register
Name
I2C Register
Address
Bit #
Bit Name
FLAGS 2
0x04h
5
UVLO_EVENT
0x05h
7
UVLO_MASK
[3:0]
UVLO voltage
selection
[2:0]
RESET_MODE.
Allows UVLO or
UVLO to be output
onto RESET_N
BYPASS
CONFIG = Z
(0x1Bh)
THRES
CONFIG = H
(0x2Bh)
CONFIG = L
(0x3Bh)
SUBOVR
CONFIG = Z
(0x1Eh)
CONFIG = H
(0x2Eh)
PMU Thermal Shutdown (TSD)
The PMU registers that support the TSD are listed in the table below. See individual register descriptions for the details.
I2C Register
Name
I2C Register
Address
FLAGS 2
0x04h
Bit #
Bit Name
0
TSDH
1
TSDL
[2:0]
RESET_MODE.
Allows TSDL,
TSDH, TSDL or
TSDH to be output
onto RESET_N
CONFIG = Z
(0x1Eh)
SUBOVR
CONFIG = H
(0x2Eh)
Power Savings
The PMU registers that support the power savings are listed in the table below. See individual register descriptions for the details.
The power saving features are under software control, the setting and clearing of these bits are not control by hardware.
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I2C Register
Name
I2C Register
Address
Bit #
Bit Name
BK1_FPWM
0x5Ah
7
FORCE_PWM
BK2_FPWM
0x5Eh
7
FORCE_PWM
58
The general “PERFECT” LDOs are optimized for supplying both analog and digital loads having ULTRA LOW NOISE (10µVRMS
for IOUT>5mA) and excellent PSRR (75dB at 10kHz) performance. They can be programmed through the serial interface for different
output voltage values.
For fast discharging of output capacitors in shut down, the LDOs can connect a 300Ω pull-down resistor to the output. This resistor
is only connected when the LDO is disabled. See Table 20 for the register description.
In sleep mode, quiescent current is reduced to 30µA for energy saving. In this mode these LDOs should not be loaded with more
than 3-5mA of output current.
HILO LDO
LDO7 (HILO) has lowered output voltage range from 0.8V to 1.55V (step 50mV) controlled by 4 bit control signal as shown in LDO7
(HILO) output voltage selection table below. Typical output current is 2mA but maximum current can reach 20mA. For proper
operation, an input voltage of more than 2V is necessary. Hence, voltage drop on the pass transistor (dropout voltage) always
exceeds 0.45V and is not dependent on output current (in specified current range).
For fast discharging of output capacitors in shut down, the LDO7 (HILO) can connect a 300Ω pull-down resistor to the output. This
resistor is only connected when the LDO is disabled. See Table 20 for the register description.
Since the LDO7 (HILO) is based on the micro power LDO, no extra output capacitor is needed. However, for better dynamic
performance it is recommended that a capacitor in the 100nF to 1μF range be used.
µPWR LDO
This LDO is primarily used for internal supply purposes and fixed to 1.8V, but may deliver up to 30mA of current also externally.
This LDO is ON even in Standby mode (with total PMU current consumption about 2uA) and the user may use it to supply some
backup/always on system(s).
TABLE 17. LDO1 — 6
Bank 0: CONFIG = Z (0x14h:LDO1) → (0x19h:LDO6)
Bank 1: CONFIG = H (0x24h:LDO1) → (0x29h:LDO6)
Bank 2: CONFIG = L (0x34h:LDO1) → (0x39h:LDO6)
Bits
4:0
Field
LDO(1-6)*_VSEL
Description
This sets the output voltage of the corresponding LDO.
LDO*_VSEL
Vout (V)
LDO*_VSEL
Vout (V)
00000
1.2
10000
2.1
00001
1.25
10001
2.2
00010
1.3
10010
2.3
00011
1.35
10011
2.4
00100
1.4
10100
2.5
00101
1.45
10101
2.6
00110
1.5
10110
2.65
00111
1.55
10111
2.7
01000
1.6
11000
2.75
01001
1.65
11001
2.8
01010
1.7
11010
2.85
01011
1.75
11011
2.9
01100
1.8
11100
2.95
01101
1.85
11101
3
01110
1.9
11110
3.1
01111
2
11111
3.3
59
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LM49360
General Type LDOS
LM49360
Bits
Field
7:5
LDO(1-6)_DLY
Description
This sets the time slot when the LDO enables and disables.
LDO(1–6)_DLY
Power Up/Down Time Slot
000
Power up in slot 0, Power down in slot 0
001
Power up in slot 1, Power down in slot 1
010
Power up in slot 2, Power down in slot 2
011
Power up in slot 3, Power down in slot 3
100
Power up in slot 4, Power down in slot 4
101
Power up in slot 5, Power down in slot 5
110
Power up in slot 6, Power down in slot 6
111
Power up in slot 7, Power down in slot 7
TABLE 18. LDO7
Bank 0: CONFIG = Z (0x1Ah)
Bank 1: CONFIG = H (0x2Ah)
Bank 2: CONFIG = L (0x3Ah)
Bits
Field
3:0
LDO7_VSEL
Description
Selects the output voltage.
LDO*_VSEL
Vout (V)
LDO*_VSEL
Vout (V)
0000
1.55
1000
1.15
0001
1.5
1001
1.1
0010
1.45
1010
1.05
0011
1.4
1011
1
0100
1.35
1100
0.95
0101
1.3
1101
0.9
0110
1.25
1110
0.85
0111
1.2
1111
0.8
4
RESERVED
Reserved bit, this bit must remain cleared.
7:5
LDO7_DLY
Sets the time slot when the LDO enables and disables.
LDO7_DLY
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Power Up/Down Time Slot
000
Power up in slot 0, Power down in slot 0
001
Power up in slot 1, Power down in slot 1
010
Power up in slot 2, Power down in slot 2
011
Power up in slot 3, Power down in slot 3
100
Power up in slot 4, Power down in slot 4
101
Power up in slot 5, Power down in slot 5
110
Power up in slot 6, Power down in slot 6
111
Power up in slot 7, Power down in slot 7
60
LM49360
TABLE 19. THRES
Bank 0: CONFIG = Z (0x1Bh)
Bank 1: CONFIG = H (0x2Bh)
Bank 2: CONFIG = L (0x3Bh)
Bits
Field
3:0
UVLO_VSEL
Description
Input on PVDD.
The PVDD voltage level is monitored and if it falls below this value, the PMU will enter
into the STANDBY state.
5:4
UVLO_VSEL
PVDD (V)
UVLO_VSEL
0000
2.3
1000
PVDD (V)
2.7
0001
2.35
1001
2.75
0010
2.4
1010
2.8
0011
2.45
1011
2.85
0100
2.5
1100
2.9
0101
2.55
1101
2.95
0110
2.6
1110
3
0111
2.65
1111
3.05
TIMESTEP
Time per Step
(microseconds)
TIMESTEP
6
RESERVED
7
LDO7_PD
00
8
01
64
10
128
11
256
Reserved bit, this bit must remain cleared.
If set, the LDO7 output will be pulled down by a 300Ω resistor when the LDO is disabled,
speeding the discharge of attached decoupling capacitors.
TABLE 20. PLDWN
Bank 0: CONFIG = Z (0x1Ch)
Bank 1: CONFIG = H (0x2Ch)
Bank 2: CONFIG = L (0x3Ch)
Bits
Field
0
BK1_PD
If set, the Buck1 output will be pulled down by a 300Ω resistor when disabled.
Description
1
BK2_PD
If set, the Buck2 output will be pulled down by a 300Ω resistor when disabled.
2
LDO1_PD
If set, the LDO1 output will be pulled down by a 300Ω resistor when disabled.
3
LDO2_PD
If set, the LDO2 output will be pulled down by a 300Ω resistor when disabled.
4
LDO3_PD
If set, the LDO3 output will be pulled down by a 300Ω resistor when disabled.
5
LDO4_PD
If set, the LDO4 output will be pulled down by a 300Ω resistor when disabled.
6
LDO5_PD
If set, the LDO5 output will be pulled down by a 300Ω resistor when disabled.
7
LDO6_PD
If set, the LDO6 output will be pulled down by a 300Ω resistor when disabled.
TABLE 21. OVR
Bank 0: CONFIG = Z (0x1Dh)
Bank 1: CONFIG = H (0x2Dh)
Bank 2: CONFIG = L (0x3Dh)
This sets the Function of OVR pin mode. If all are zero only Buck2 is enabled by the pin (this pin always forces Buck2 on). Other
outputs can be set by setting the relevant bit here.
Bits
Field
0
BK1_OVR
If set, the Buck 1 output is enabled when OVR is set.
Description
1
LDO1_OVR
If set, the LDO 1 output is enabled when OVR is set.
2
LDO2_OVR
If set, the LDO 2 output is enabled when OVR is set.
3
LDO3_OVR
If set, the LDO 3 output is enabled when OVR is set.
61
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LM49360
Bits
Field
Description
4
LDO4_OVR
If set, the LDO 4 output is enabled when OVR is set.
5
LDO5_OVR
If set, the LDO 5 output is enabled when OVR is set.
6
LDO6_OVR
If set, the LDO 6 output is enabled when OVR is set.
7
LDO7_OVR
If set, the LDO 7 output is enabled when OVR is set.
TABLE 22. SUBOVR
Bank 0: CONFIG = Z (0x1Eh)
Bank 1: CONFIG = H (0x2Eh)
Bits
2:0
Field
RESERVED
Description
Reserved bits, this bit field must remain at 000b.
RESERVED
Function of RESET_N Pin
000
RESET_N (Default)
001
RESET
010
TSDL or UVLO
011
TSDL or UVLO
100
TSDH or TSDL
101
TSDH or TSDL
110
0
111
1
3
BK1_SUBOVR
If set, the Buck1 output enables when SUBOVR is set
(i.e. PS_HOLD in a subPMU mode).
4
LDO1_SUBOVR
If set, the LDO1 output enables when SUBOVR is set
(i.e. PS_HOLD in a subPMU mode).
5
LDO4_SUBOVR
If set, the LDO4 output enables when SUBOVR is set
(i.e. PS_HOLD in a subPMU mode).
6
LDO5_SUBOVR
If set, the LDO5 output enables when SUBOVR is set
(i.e. PS_HOLD in a subPMU mode).
7
LDO7_SUBOVR
If set, the LDO7 output enables when SUBOVR is set
(i.e. PS_HOLD in a subPMU mode).
TABLE 23. I2C1 (0x40h)
Bits
2:0
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Field
PMU_H_I2C_ADDR
Description
The I2C Address for the Power Management CONFIG “H”
PMU_H_I2C
_ADDR
I2C_ADDR
000
1111111
001
1111110
010
1111101
011
1111100
100
1111011
101
1111010
110
1111001
111
1111000
62
5:3
Field
PMU_Z_I2C_ADDR
LM49360
Bits
Description
The
I2C
Address for the Power Management CONFIG “Z”
PMU_Z_I2C_ADDR
I2C_ADDR
000
1111100
001
1111101
010
1111110
011
1111111
100
1111000
101
1111001
110
1111010
111
1111011
6
RESEREVED
Reserved bit, this bit must remain cleared.
7
RESEREVED
Reserved bit, this bit must remain cleared.
TABLE 24. I2C2 (0x41h)
Bits
2:0
5:3
Field
PMU_L_I2C_ADDR
AUD_I2C_ADDR
Description
The I2C Address for the Power Management CONFIG “L”
The
I2C
PMU_L_I2C
_ADDR
I2C_ADDR
000
1111101
001
1111100
010
1111111
011
1111110
100
1111001
101
1111000
110
1111011
111
1111010
Address for the Audio Subsystem
AUD_I2C_ADDR
I2C_ADDR
000
0011010
001
0011011
010
0011000
011
0011001
100
0011110
101
0011111
110
0011100
111
0011101
6
RESERVED
Reserved bit, this bit must remain cleared.
7
RESERVED
Reserved bit, this bit must remain cleared.
TABLE 25. BK1_FPWM (0x5Ah)
Bits
6:0
7
Field
Description
Reserved
Do not change the value of these bits, read the value of these bits and write back when
updating bit 7, FORCE_PWM.
FORCE_PWM
If set, forces the Buck 1 converter into PWM mode. If cleared, the Buck 1 converter will
switch between ECO and PWM mode depending on the load current.
63
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LM49360
TABLE 26. BK2_FPWM (0x5Eh)
Bits
6:0
7
Field
Description
Reserved
Do not change the value of these bits, read the value of these bits and write back when
updating bit 7, FORCE_PWM.
FORCE_PWM
If set, forces the Buck 2 converter into PWM mode. If cleared, the Buck 2 converter will
switch between ECO and PWM mode depending on the load current.
27.0 Basic PMC Setup Register
The LM49360's Power Management Circuit (PMC) controls the basic power management setup for the audio section of the device.
TABLE 27. PMC_SETUP (0x00h)
Bits
0
Field
Description
CHIP_ENABLE
When this bit is set, the power management will enable the MCLK I/O or internal
oscillator1. It will then use this clock to sequence the enabling of the analog references and
bias points. When this bit is cleared, the PMC will bring the analog down gently and disable
the MCLK or oscillator.
CHIP _ENABLE
Chip Status
0
Turn Chip Off
1
Turn Chip On
This enables the PLL.
1
PLL_ENB
PLL_ENABLE
PLL Status
0
PLL Off
1
PLL On
This enables the P2 output of the PLL.
2
PLL_P2ENB
PLL_P2ENB
PLL P2 Status
0
PLL P2 Off
1
PLL P2 On
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can
be used instead of an external system clock to drive the chip's power management (PMC).
3
4
OSC_ENB
MCLK_OVR
OSC_ENABLE
Oscillator Status
0
Oscillator Off
1
Oscillator On
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the PMC clock source (reg 0x01h) and that there is an active clock signal
driving the MCLK pin. Setting this bit reduces power consumption by allowing audio ports
and digital mixer to operate while the analog sections of the chip are powered down.
MCLK_OVR
Comment
0
I/O control is automatic
1
MCLK input forced on.
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
5
PORT1_CLK_OVR
PORT1_CLK_OVR
Comment
0
I/O control is automatic
1
PORT_CLK input forced on
This forces the clock input of Audio Port 2 input to enable regardless of other port settings.
6
PORT2_CLK_OVR
7
CHIP_ACTIVE
PORT2_CLK_OVR
Comment
0
I/O control is automatic
1
PORT_CLK input forced on
This bit is used to read back the enable status of the chip.
1. If the PMC is set to operate from one of the audio ports, then it will wait for the port to be enabled or the relevant override bit to
be set, forcing the port clock input to enable.
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64
LM49360
28.0 PMC Clocks Register
This register is used to control the LM49360's Basic Power Management Clock.
TABLE 28. PMC_SETUP (0x01h)
Bits
Field
1:0
PMC_CLK_SEL
Description
This selects the source of the PMC input clock.
PMC_CLK_SEL
PMC Input Clock Source
00
MCLK (Default divide is 40.5)
01
Internal 300kHz Oscillator
10
DAC SOURCE CLOCK
11
ADC SOURCE CLOCK
29.0 PMC Clock Divide Register
This register is used to control the LM49360's Power Management Circuit Clock Divider.
TABLE 29. PMC_SETUP (0x02h)
Bits
Field
7:0
PMC_CLK_DIV
Description
This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40.5) to get a ≈300kHz PMC
clock from a 12MHz or 12.288MHz MCLK.
Program this divider with the required division, multiplied by 2, and subtract 1.
PMC_CLK_DIV
Divide by
00000000
1
00000001
1
00000010
1.5
00000011
2
00000100
2.5
00000101
3
—
—
11111101
126
11111110
127.5
11111111
128
65
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LM49360
30.0 LM49360 Clock Network
(Refer to Figure 20)
The audio DAC and ADC operate at a clock frequency of 2*OSR*fS where OSR is the oversampling ratio and fS is the sampling
frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two
different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for
48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.
Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC
clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider
could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,
the PORT1_CLK input, the PORT2_CLK input, or PLL output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come
from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
The LM49360's Power Management Circuit (PMC) requires a clock of ≈300kHz that is independent from the DAC or ADC. The
PMC clock divider is available to generate the correct clock to the PMC block. The PMC clock path can be driven directly by the
MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.
TABLE 30. DAC Clock Requirements
DAC Sample Rate
(kHz)
Clock Required at A
(OSR = 128)
Clock Required at A
(OSR = 125)
Clock Required at A
(OSR = 64)
8
2.048 MHz
2 MHz
1.024 MHz
11.025
2.8224 MHz
2.75625 MHz
1.4112 MHz
12
3.072 MHz
3 MHz
1.536 MHz
16
4.096 MHz
4 MHz
2.048 MHz
22.05
5.6448 MHz
5.5125 MHz
2.8224 MHz
24
6.144 MHz
6 MHz
3.072 MHz
32
8.192 MHz
8 MHz
4.096 MHz
44.1
11.2896 MHz
11.025 MHz
5.6448 MHz
48
12.288 MHz
12 MHz
6.144 MHz
96
24.576 MHz
24 MHz
12.288 MHz
TABLE 31. ADC Clock Requirements
ADC Sample Rate
(kHz)
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Clock Required at B
(OSR = 128)
Clock Required at B
(OSR = 125)
8
2.048 MHz
2 MHz
11.025
2.8224 MHz
2.75625 MHz
12
3.072 MHz
3 MHz
16
4.096 MHz
4 MHz
22.05
5.6448 MHz
5.5125 MHz
24
6.144 MHz
6 MHz
32
8.192 MHz
8 MHz
44.1
11.2896 MHz
11.025 MHz
48
12.288 MHz
12 MHz
66
LM49360
30128213
FIGURE 20. Internal Clock Network
67
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LM49360
31.0 PLL Setup Registers
30128230
FIGURE 21. PLL Loop
The LM49360 contains a PLL for flexible operation of its dual audio ports. The PLL has a P1 and P2 output divider thereby allowing
the PLL to generate two distinct clock outputs. The equations for the PLL's generated output clocks are as follows:
fOUT1 = (fIN . N / M . P1)
fOUT2 = (fIN . N / M . P2)
where:
N = PLL_N + PLL_N_MOD
M = (PLL_M + 1) / 2
P1 = (PLL_P1 + 1) / 2
P2 = (PLL_P2 + 1) / 2
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68
LM49360
TABLE 32. PLL Settings for Common System Clock Frequencies
fIN (MHz)
M
N
N_MOD
P
fOUT (Hz)
Error (Hz)
12
2.5
32
0
12.5
12288000
0
13
15.5
175
26
12
12287970
–30
14.4
12.5
128
0
12
12288000
0
16.2
13.5
128
0
12.5
12288000
0
16.8
3.5
32
0
12.5
12288000
0
19.2
12.5
96
0
12
12288000
0
19.68
20.5
160
0
12.5
12288000
0
19.8
16.5
128
0
12.5
12288000
0
26
32.5
192
0
12.5
12288000
0
27
22.5
128
0
12.5
12288000
0
0
12
12.5
147
0
12.5
11289600
12.288
10
147
0
16
11289600
0
13
9
144
19
18.5
11289603
+3
14.4
12.5
147
0
15
11289600
0
16.2
22.5
196
0
12.5
11289600
0
16.8
12.5
126
0
15
11289600
0
19.2
20
147
0
12.5
11289600
0
19.68
20.5
147
0
12.5
11289600
0
19.8
27.5
196
0
12.5
11289600
0
26
18.5
144
19
18
11289602.1
2.1
27
37.5
196
0
12.5
12289600
0
11.2896
10.5
195
0
17.5
12000000
0
12.288
8
125
0
16
12000000
0
13
6.5
102
0
17
12000000
0
13.5
4.5
68
0
17
12000000
0
14.4
6
85
0
17
12000000
0
16.2
13.5
170
0
17
12000000
0
16.8
7
85
0
17
12000000
0
19.2
8
85
0
17
12000000
0
19.68
20.5
200
0
16
12000000
0
19.8
16.5
170
0
17
12000000
0
26
6.5
36
0
12
12000000
0
11.2896
8
125
0
16
11025000
0
12
10
147
0
16
11025000
0
12.288
8
114
27
16
11025000
0
13
6.5
96
15
17.5
11025000
0
13.5
10
147
0
18
11025000
0
14.4
4
49
0
16
11025000
0
16.2
4
49
0
18
11025000
0
16.8
16
189
0
18
11025000
0
19.2
16
147
0
16
11025000
0
19.68
16
189
0
18
11025000
0
19.8
16
147
0
16.5
11025000
0
26
5
27
18
13
11025000
0
69
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LM49360
TABLE 33. PLL_CLOCK_SOURCE (0x03h)
Bits
Field
1:0
PLL_CLK_SEL
Description
This selects the source of the input clock to the PLL.
PLL_CLK_SEL
PLL Input Clock Source
00
MCLK
01
PORT1_CLK
10
PORT2_CLK
11
RESERVED
TABLE 34. PLL_M (0x04h)
Bits
Field
6:0
PLL_M
Description
This programs the PLL's M divider to divide from 1 to 64.
PLL_M
PLL Input Divider Value
000000
1
000001
1
000010
1.5
000011
2
000100
2.5
000101
3
—
—
1111101
63
1111110
63.5
1111111
64
TABLE 35. PLL_N (0x05h)
Bits
Field
7:0
PLL_N
www.ti.com
Description
This programs the PLL N divider to divide from 1 to 250.
PLL_N
Feedback Divider Value
00000000 to 00001010
10
00001011
11
00001100
12
00001101
13
00001110
14
00001111
15
—
—
11111000
248
11111001
249
11111010 to 11111111
250
70
LM49360
TABLE 36. PLL_N_MOD (0x06h)
Bits
Field
4:0
PLL_N_MOD
Description
This programs the sigma-delta modulator in the PLL.
PLL_N_MOD
Fractional Part of N
00000
0
00001
1/32
00010
2/32
00011
3/32
00100
4/32
00101
5/32
—
—
11101
20/32
11110
30/32
11111
31/32
5
PLL_P1[8]
This sets the MSB of the 1st P Divider on the PLL which is part of a standard half-cycle divider
control.
6
PLL_P2[8]
This sets the MSB of the 2nd P Divider on PLL which is part of a standard half-cycle divider
control.
TABLE 37. PLL_P1 (0x07h)
Bits
Field
Description
7:0
PLL_P1[7:0]
This programs the 8 LSBs of the PLL's P1 Divider. These LSBs combine with PL1_P1[8] which
allows the P1 divider to divide by up to 256.
PLL_P1 [8:0]
P1 Divider Value
000000000
1
000000001
1
000000010
1.5
000000011
2
000000100
2.5
000000101
3
—
—
111111101
255
111111110
255.5
111111111
256
TABLE 38. PLL_P2 (0x08h)
Bits
Field
7:0
PLL_P2[7:0]
Description
This programs 8 LSBs of the PLL's P2 Divider. These LSBs combine with PLL_P2[8] which
allows the P2 divider to divide by up to 256.
PLL_P2 [8:0]
P2 Divider Value
000000000
1
000000001
1
000000010
1.5
000000011
2
000000100
2.5
000000101
3
—
—
111111101
255
111111110
255.5
111111111
256
71
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LM49360
32.0 Analog Mixer Control Registers
This register is used to control the LM49360's Analog Mixer:
TABLE 39. CLASS_D_OUTPUT (0x10h)
Bits
Field
0
DACR_LS
The right DAC output is added to the loudspeaker output.
Description
1
DACL_LS
The left DAC output is added to the loudspeaker output.
2
RSVD
Reserved
3
RSVD
Reserved
4
MONO_LS
5
AUX_LS
The MONO input is added to the loudspeaker output.
The AUX input is added to the loudspeaker output.
Class D Loudspeaker Amplifier
The LM49360 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from VDD to GND.
When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase.
Because the outputs of the LM49360 are differential, the two signals cancel each other. This results in no net voltage across the
speaker, thus there is no load current during an idle state, conserving power.
With an input signal applied, the duty cycle (pulse width) of the LM49360 outputs changes. For increasing output voltages, the duty
cycle of LS+ increases, while the duty cycle of LS- decreases. For decreasing output voltages, the converse occurs, the duty cycle
of LS- increases while the duty cycle of LS+ decreases. The difference between the two pulse widths yields the differential output
voltage.
Spread Spectrum Modulation
The LM49360 features a fitlerless spread spectrum modulation scheme that eliminates the need for output filters, ferrite beads or
chokes. The switching frequency varies by ±30% about a 300kHz center frequency, reducing the wideband spectral content,
improving EMI emissions radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits
large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture of the LM49360 spreads
that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction or
efficiency.
Class D Power Dissipation and Efficiency
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it
with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For audio systems, the energy
delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and supersonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band
power being transduced is dissipated in the LM49360 and in the transducer load. The amount of power dissipation in the LM49360's
class D amplifier is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less
than 0.25Ω. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output
power. The LM49360 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a
heat sink.
TABLE 40. LEFT HEADPHONE_OUTPUT (0x11h)
Bits
Field
0
DACR_HPL
The right DAC output is added to the left headphone output.
1
DACL_HPL
The left DAC output is added to the left headphone output.
2
RSVD
Reserved
3
RSVD
Reserved
4
MONO_HPL
5
AUX_HPL
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Description
The MONO input is added to the left headphone output.
The AUX input is added to the left headphone output.
72
LM49360
TABLE 41. RIGHT HEADPHONE_OUTPUT (0x12h)
Bits
Field
Description
0
DACR_HPR
The right DAC output is added to the right headphone output.
1
DACL_HPR
The left DAC output is added to the right headphone output.
2
RSVD
Reserved
3
RSVD
Reserved
4
MONO_HPR
5
AUX _HPR
The MONO input is added to the right headphone output.
The AUX input is added to the right headphone output.
Headphone Amplifier Function
The LM49360 headphone amplifier features National’s ground referenced architecture that eliminates the large DC-blocking capacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge pump creates a negative supply
(HP_VSS) from the positive supply voltage (LS_VDD). The headphone amplifiers operate from these bipolar supplies, with the
amplifier outputs biased about GND, instead of a nominal DC voltage (typically VDD/2), like traditional amplifiers. Because there is
no DC component to the headphone output signals, the large DC-blocking capacitors (typically 220μF) are not necessary, conserving board space and system cost, while improving frequency response.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
Charge Pump Flying Capacitor (C38)
The flying capacitor (C38) affects the load regulation and output impedance of the charge pump. A C38 value that is too low results
in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C38 improves load regulation and lowers charge
pump output impedance to an extent. Above 2.2μF, the RDS(ON) of the charge pump switches and the ESR of C38 and C61 dominate
the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Please refer
to the demonstration board schematic shown in Figure 36.
Charge Pump Flying Capacitor (C61)
The value and ESR of the hold capacitor (C61) directly affects the ripple on CPVSS. Increasing the value of C61 reduces output
ripple. Decreasing the ESR of C61 reduces both output ripple and charge pump output impedance. A lower value capacitor can
be used in systems with low maximum output power requirements. Please refer to the demonstration board schematic shown in
Figure 36.
TABLE 42. AUX_OUTPUT (0x13h)
Bits
Field
0
DACR_AUX
The right DAC output is added to the AUX output.
Description
1
DACL_AUX
The left DAC output is added to the AUX output.
2
MIC_AUX
3
RSVD
4
MONO_AUX
5
AUX_AUX
The MIC input is added to the AUX output.
Reserved
The MONO input is added to the AUX output.
The AUX input is added to the AUX output.
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LM49360
Auxiliary Output Amplifier
The LM49360’s auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its
outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with respect to
each other. This effectively doubles the maximum possible output swing for a specific supply voltage when compared to singleended output configurations. The differential output configuration also allows the load to be isolated from ground since both the
AUX_OUT+ and AUX_OUT- pins are biased at the same DC potential. This eliminates the need for any large and expensive DC
blocking capacitors at the AUXOUT amplifier outputs. The load can then be directly connected to the positive and negative outputs
of the AUXOUT amplifier which then isolates it from any ground noise, thereby improving signal-to-noise-ratio (SNR) and power
supply rejection ratio (PSRR).
The AUXOUT amplifier has two modes of operation. The primary mode of operation is high current drive mode (Earpiece Mode)
where the AUXOUT amplifier can be used to differentially drive a mono earpiece speaker. The secondary mode of operation is
low current drive mode where the AUXOUT amplifier operates in a power saving mode (AUX_LINE_OUT Mode) to provide a
differential output that is used as a mono differential line level input to a standalone mono differential input class D amplifier
(LM4675) for stereo loudspeaker applications.
TABLE 43. OUTPUT_OPTIONS (0x14h)
Bits
Field
0
RSVD
3:1
LR_HP_LEVEL
Description
Reserved
This sets the gain of the left and right headphone amplifiers. The gain of the left and right headphone
amplifiers are always set to the same level.
LR_HP_LEVEL
4
AUX_NEG_6dB
Gain (dB)
000
0
001
–1.5
010
–3
011
–6
100
–9
101
–12
110
–15
111
–18
This sets the gain of the Auxiliary output amplifier.
AUX_NEG_6dB
5
7:6
AUX_LINE_OUT
LS_LEVEL
Gain (dB)
0
0
1
–6
This sets the Auxiliary output amplifier mode of operation.
AUX_LINE_OUT
Auxiliary Output Mode
0
Earpiece Amplifier
1
AUX_LINE_OUT
This sets the gain of the Class D loudspeaker amplifier.
LS_LEVEL
Gain (dB)
00
0
01
4
10
8
11
12
TABLE 44. ADC_INPUT (0x15h)
Bits
Field
0
DACR_ADCR
The right DAC output is added to the ADC right input.
1
DACL_ADCL
The left DAC output is added to the ADC left input.
2
MIC_ADCR
The MIC input is added to the ADC right input.
3
MIC_ADCL
The MIC input is added to the ADC left input.
4
AUX_ADCR
The AUX input is added to the ADC right input.
5
MONO_ADCL
The MONO input is added to the ADC left input.
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Description
74
LM49360
TABLE 45. MIC_INPUT (0x16h)
Bits
Field
3:0
MIC_LEVEL
4
SE_DIFF
5
MUTE
Description
This sets the gain of the microphone preamp.
MIC_LEVEL
Gain
0000
6dB
0001
8dB
0010
10dB
0011
12dB
0100
14dB
0101
16dB
0110
18dB
0111
20dB
1000
22dB
1001
24dB
1010
26dB
1011
28dB
1100
30dB
1101
32dB
1110
34dB
1111
36dB
If set, the MIC negative input is ignored. In single-ended mode, the MIC negative input pin should
be left floating.
If set, the microphone preamp is muted.
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LM49360
TABLE 46. AUX_LEVEL (0x18h)
Bits
5:0
6
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Field
Description
AUX_LEVEL This programs the AUX input level. All gain changes are performed at zero crossings.
SE/DIFF
AUX_LEVEL
Level
AUX_LEVEL
Level
000000
–46.5dB
100000
1.5dB
000001
–45dB
100001
3dB
000010
–43.5dB
100010
4.5dB
000011
–42dB
100011
6dB
000100
–40.5dB
100100
7.5dB
000101
–39dB
100101
9dB
000110
–37.5dB
100110
10.5dB
000111
–36dB
100111
12dB
001000
–34.5dB
101000
13.5dB
001001
–33dB
101001
15dB
001010
–31.5dB
101010
16.5dB
001011
–30dB
101011
18dB
001100
–28.5dB
001101
–27dB
001110
–25.5dB
001111
–24dB
010000
–22.5dB
010001
–21dB
010010
–19.5dB
010011
–18dB
010100
–16.5dB
010101
–15dB
010110
–13.5dB
010111
–12dB
011000
–10.5dB
011000
–9dB
011001
–7.5dB
011010
–6dB
011100
–4.5dB
011101
–3dB
011110
–1.5dB
011111
0dB
If set, the AUXL input is ignored. In single-ended mode, the AUXL input pin should be left
floating.
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LM49360
TABLE 47. MONO_LEVEL (0x19h)
Bits
5:0
Field
Description
MONO_LEVEL This programs the MONO input level. All gain changes are performed at zero crossings.
6
SE/DIFF
7
AUXL_MONO
MONO_LEVEL
Level
MONO_LEVEL
Level
000000
–46.5dB
100000
1.5dB
000001
–45dB
100001
3dB
000010
–43.5dB
100010
4.5dB
000011
–42dB
100011
6dB
000100
–40.5dB
100100
7.5dB
000101
–39dB
100101
9dB
000110
–37.5dB
100110
10.5dB
000111
–36dB
100111
12dB
001000
–34.5dB
101000
13.5dB
001001
–33dB
101001
15dB
001010
–31.5dB
101010
16.5dB
001011
–30dB
101011
18dB
001100
–28.5dB
001101
–27dB
001110
–25.5dB
001111
–24dB
010000
–22.5dB
010001
–21dB
010010
–19.5dB
010011
–18dB
010100
–16.5dB
010101
–15dB
010110
–13.5dB
010111
–12dB
011000
–10.5dB
011000
–9dB
011001
–7.5dB
011010
–6dB
011100
–4.5dB
011101
–3dB
011110
–1.5dB
011111
0dB
If set, the MONO– input is ignored. In single-ended mode, the MONO- input pin should
be left floating.
If set, AUXL is routed to the MONO Input Amplifier.
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LM49360
Headphone Detection Circuit
The LM49360 features a headphone detection circuit (HDC) that automatically enables the headphone amplifier whenever the
insertion of a headphone plug is detected and disables the headphone amplifier during the removal of a headphone plug. The HDC
optimizes power management by automatically disabling any output amplifier that is not in use. The HDC eliminates the necessity
of polling the I2C bus for status changes. However, since the HDC requires the use of the GPIO pin, the PORT2_SDO functionality
sensing is required.
The HDC requires a headphone jack with a normally closed mechanical switch and a pull-up resistor, RPU, tied between the
mechanical switch and I/O_VDD (refer to Figure 22). Choosing a RPU value of at least 500kΩ ensures minimal current draw through
the pull-up resistor. When the headphone amplifier is disabled, an internal 50kΩ pull-down, RPD, is connected to each headphone
amplifier output. Without the presence of a headphone plug, the headphone jack’s mechanical switch is closed thereby connecting
the right headphone amplifier output to RPU. The GPIO pin detects a logic low level due to the voltage division between RPU and
RPD. When the GPIO pin is set to HPSENSE mode, a logic low voltage reading causes the HDC to disable the headphone amplifier.
When a headphone plug is inserted, the mechanical connection between RPU and RPD is broken, resulting in a logic high level
detected by the GPIO pin. A logic high voltage reading causes the HDC to enable the headphone amplifier.
The HDC has four modes of operation that automatically enable/disable different combinations of the audio output amplifiers
contained within the LM49360. Having the choice of four different HDC settings maximizes power management flexibility to suit a
particular application. Please refer to the HP_SENSE (reg 0x1Bh) register table for a detailed discussion on the different HDC
modes of operation.
30128293
FIGURE 22. Application Circuit for Headphone Detection
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78
LM49360
TABLE 48. HP_SENSE (0x1Bh)
Bits
Field
Description
0
HP SENSE
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on. If a headphone removal is detected, the headphone amplifier will
automatically turn off.
HPSENSE
1
HPSENSE_D
0
Off
1
On
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier will turn off. If a headphone removal is
detected, the headphone amplifier will automatically turn off and the Class D loudspeaker amplifier
will turn on. This bit overrides bit 0 of this register.
HPSENSE_D
2
HPSENSE_AUX
HPSENSE_AUX_D
Headphone Sense Status
0
Off
1
On
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Earpiece / Auxout amplifier will turn off. If a headphone removal is
detected, the headphone amplifier will automatically turn off and the Earpiece / Auxout amplifier will
turn on. This bit overrides bit 0 and bit 1 of this register.
HPSENSE_AUX
3
Headphone Sense Status
Headphone Sense Status
0
Off
1
On
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier along with the Earpiece / Auxout
amplifier will turn off. If a headphone removal is detected, the headphone amplifier will automatically
turn off and the Class D loudspeaker amplifier along with the Earpiece / Auxout amplifier will turn
on. This bit overrides bit 0, bit 1, and bit 2 of this register.
HPSENSE_AUX_D
Headphone Sense Status
0
Off
1
On
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LM49360
33.0 ADC Control Registers
This register is used to control the LM49360's ADC:
TABLE 49. ADC Basic (0x20h)
Bits
Field
0
MONO
Description
This sets mono or stereo operation of the ADC.
MONO
1
OSR
ADC Operation
0
Stereo Audio
1
Mono Voice (Right ADC channel disabled, Left ADC channel active)
This sets the oversampling ratio of the ADC.
OSR
Stereo Audio ADC
Oversampling Ratio
Mono Voice ADC Oversampling Ratio
0
128
125
1
128
128
2
MUTE_L
If set, a digital mute is applied to the Left (or mono) ADC output.
3
MUTE_R
If set, a digital mute is applied to the Right ADC output.
6:4
ADC_CLK_SEL
This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
ADC_CLK_SEL
7
ADC_DSP_ONLY
Source
000
MCLK
001
PORT1_RX_CLK
010
PORT2_RX_CLK
011
PLL_OUTPUT1
100
PLL_OUTPUT2
If set, the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asynchronous re-sampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
TABLE 50. ADC_CLK_DIV (0x21h)
Bits
Field
7:0
ADC_CLK_DIV
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Description
This programs the half cycle divider that precedes the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
ADC_CLK_DIV
Divides by
00000000
1
00000001
1
00000010
1.5
00000011
2
—
—
11111101
127
11111110
127.5
11111111
128
80
LM49360
TABLE 51. ADC_MIXER (0x23h)
Bits
Field
1:0
ADC_MIX_LEVEL_L
Description
This sets the input level to the left ADC channel.
ADC_MIX_LEVEL_L
3.2
ADC_MIX_LEVEL_R
Level
00
0dB
01
1.35dB
10
3.5dB
11
6dB
This sets the input level to the right ADC channel.
ADC_MIX_LEVEL_R
4
STEREO_LINK
Level
00
0dB
01
1.35dB
10
3.5dB
11
6dB
If set, this links ADC_MIX_LEVEL_R with ADC_MIX_LEVEL_L.
STEREO_LINK
Status
0
Off
1
On
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LM49360
34.0 DAC Control Registers
This register is used to control the LM49360's DAC.
TABLE 52. DAC Basic (0x30h)
Bits
Field
1:0
MODE
Description
This programs the over sampling ratio of the stereo DAC.
MODE
DAC Oversampling Ratio
00
125
01
128
10
64 (Default)
11
RSVD
2
MUTE_L
This digitally mutes the Left DAC output.
3
MUTE_R
This digitally mutes the Right DAC output.
6:4
DAC_CLK_SEL
7
DSP_ONLY
This selects the source of the DAC clock domain, DAC_SOURCE_CLK.
DAC_CLK_SEL
Source
000
MCLK
001
PORT1_RX_CLK
010
PORT2_RX_CLK
011
PLL_OUTPUT1
100
PLL_OUTPUT2
If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP
functionality is maintained. This can be used to perform asynchronous re-sampling between audio
rates of a common family.
TABLE 53. DAC_CLK_DIV (0x31h)
Bits
Field
7:0
DAC_CLK_DIV
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Description
This programs the half cycle divider that precedes the DAC. The input of this divider should be
around 12MHz. The default of this divider is 0x03 which gives a division by 2.
Program this divider with the division you want, multiplied by 2, and subtract 1.
DAC_CLK_DIV
Divides by
00000000
1
00000001
1
00000010
1.5
00000011
2 (Default)
—
—
11111101
127
11111110
127.5
11111111
128
82
LM49360
35.0 Digital Mixer Control Registers
Digital Mixer
The LM49360’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer
handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input. The digital mixer also
selects the appropriate digital data path (Port1 RX data, Port2 RX data, ADC output, DAC DSP output, or ADC DSP output) that
is used for data transmission on Audio Port 1 and 2. Audio inputs to the digital mixer can be attenuated down to -18dB to avoid
clipping conditions.
Another key feature of the digital mixer is sample rate conversion (SRC) between audio ports. This allows simultaneous operation
of the dual audio ports even if each port is operating at a different sample rate. The LM49360 can be used as an audio port bridge
with SRC capability. The digital mixer allows either straight pass through between audio ports or, if desired, DSP effects can be
added to the digital audio signal during audio port bridge operation. The digital mixer automatically handles stereo I2S to mono
PCM conversion between audio ports and vice versa.
30128237
FIGURE 23. Digital Mixer
The LM49360 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer
also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can be combined
into the same signal path.
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LM49360
This register is used to control the LM49360's digital mixer.
TABLE 54. Input Levels 1 (0x40h)
Bits
Field
1:0
PORT1_RX_L
_LVL
3:2
5:4
7:6
PORT1_RX_R
_LVL
PORT2_RX_L
_LVL
PORT2_RX_R
_LVL
Description
This programs the input level of the data arriving from the left receive channel of Audio Port 1.
PORT1_RX_L_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
This programs the input level of the data arriving from the right receive channel of Audio Port 1.
PORT1_RX_R_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
This programs the input level of the data arriving from the left receive channel of Audio Port 2.
PORT2_RX_L_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
This programs the input level of the data arriving from the right receive channel of Audio Port 2.
PORT2_RX_R_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
TABLE 55. Input Levels 2 (0x41h)
Bits
Field
1:0
ADC_L_LVL
Description
This programs the input level of the data arriving from the left ADC channel.
ADC_L_LVL
3:2
ADC_R_LVL
0dB
01
–6dB
10
–12dB
11
–18dB
This programs the input level of the data arriving from the right ADC channel.
ADC_R_LVL
5:4
INTERP_L_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
This programs the input level of the data arriving from the left DAC's interpolator output.
INTERP_L_LVL
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Level
00
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
84
Field
7:6
INTERP_R_LVL
LM49360
Bits
Description
This programs the input level of the data arriving from the right DAC's interpolator output.
INTERP_R_LVL
Level
00
0dB
01
–6dB
10
–12dB
11
–18dB
TABLE 56. Audio Port 1 Input (0x42h)
Bits
Field
1:0
L_SEL
Description
This selects which input is fed to the Left TX Channel of Audio Port 1.
L_SEL
3:2
R_SEL
Selected Input
00
None
01
ADC_L
10
PORT2_RX_L
11
DAC_INTERP_L
This selects which input is fed to the Right TX Channel of Audio Port 1.
R_SEL
Selected Input
00
None
01
ADC_R
10
PORT2_RX_R
11
DAC_INTERP_R
4
SWAP
If set, this swaps the Left and Right outputs to Audio Port 1.
5
MONO
If set, the right channel is ignored and the left channel becomes (left+right) / 2.
TABLE 57. Audio Port 2 Input (0x43h)
Bits
Field
1:0
L_SEL
Description
This selects which input is fed to Audio Port 2's Left TX Channel.
L_SEL
3:2
R_SEL
Selected Input
00
None
01
ADC_L
10
PORT1_RX_L
11
DAC_INTERP_L
This selects which input is fed to Audio Port 2's Right TX Channel.
R_SEL
Selected Input
00
None
01
ADC_R
10
PORT1_RX_R
11
DAC_INTERP_R
4
SWAP
If set, this swaps the Left and Right outputs to Audio Port 2.
5
MONO
If set, the right channel is ignored and the left channel becomes (left+right) / 2.
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LM49360
TABLE 58. DAC Input Select (0x44h)
Bits
Field
Description
0
PORT1_L
This adds Audio Port 1's left RX channel to the DAC's left input.
1
PORT2_L
This adds Audio Port 2's left RX channel to the DAC's left input.
2
ADC_L
3
PORT1_R
This adds Audio Port 1's right RX channel to the DAC's right input.
4
PORT2_R
This adds Audio Port 2's right RX channel to the DAC's right input.
5
ADC_R
This adds the ADC's right output to the DAC's right input.
6
SWAP
If set, this swaps the Left and Right inputs to the DAC.
This adds the ADC's left output to the DAC's left input
TABLE 59. Decimator Input Select (0x45h)
Bits
Field
1:0
L_SEL
Description
This selects which input is fed to the left ADC's decimator input.
L_SEL
3:2
R_SEL
Selected Input
00
None
01
PORT1_RX_L
10
PORT2_RX_L
11
DAC_INTERP_L
This selects which input is fed to the right ADC's decimator input.
R_SEL
5:4
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MXR_CLK_SEL
Selected Input
00
None
01
PORT1_RX_R
10
PORT2_RX_R
11
DAC_INTERP_R
This selects the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source
with the highest clock frequency. If the DAC interpolator output (DAC_OSR_L or DAC_OSR_R) is
selected, then MXR_CLK_SEL should be set to '10'.
MXR_CLK_SEL
Selected Input
00
Auto
01
MCLK
10
DAC
11
ADC
86
LM49360
36.0 Audio Port Control Registers
30128271
FIGURE 24. I2S Serial Data Format (24 bit example)
30128272
FIGURE 25. Left Justified Data Format (24 bit example)
30128270
FIGURE 26. Right Justified Data Format (24 bit example)
30128234
FIGURE 27. PCM Serial Data Format (16 bit example)
87
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LM49360
301282i1
FIGURE 28. Timing for I2S Master
301282i2
FIGURE 29. Timing for I2S Slave
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88
TABLE 60. BASIC_SETUP (0x50h/0x60h)
Bits
Field
0
STEREO
1
RX_ENABLE
If set, the input is enabled (enables the SDI port and input shift register and any clock
generation required).
2
TX_ENABLE
If set, the output is enabled (enables the SDO port and output shift register and any clock
generation required).
3
CLOCK_MS
If set, the audio port will transmit the clock when either the RX or TX is enabled.
4
SYNC_MS
5
CLOCK_PHASE
6
7
Description
If set, the audio port will receive and transmit stereo data.
If set, the audio port will transmit the sync signal when either the RX or TX is enabled.
STEREO_SYNC_PHASE
SYNC_INVERT
This sets how data is clocked by the Audio Port.
CLOCK_PHASE
Audio Data Mode
0
I2S (TX on falling edge, RX on rising edge)
1
PCM (TX on rising edge, RX on falling edge)
If set, this reverses the left and right channel data of the Audio Port.
STEREO_SYNC_PHASE
Audio Port Data Orientation
0
Left channel data goes to left channel output.
Right channel data goes to right channel output.
1
Right channel data goes to left channel output.
Left channel data goes to right channel output.
If this bit is set, the SYNC is inverted before the receiver and transmitter.
SYNC_INVERT
SYNC ORIENTATION
0
SYNC Low = Left, SYNC High = Right
1
SYNC Low = Right, SYNC High = Left
TABLE 61. CLK_GEN_1 (0x51h/0x61h)
Bits
5:0
6
Field
Description
HALF_CYCLE_CLK_ This programs the half-cycle divider that generates the master clocks in the audio port. The default
DIV
of this divider is 0x00, i.e. bypassed.
Program this divider with the required division multiplied by 2, and subtract 1.
CLOCK_SEL
HALF_CYCLE_CLK_DIV
Divides By
000000
BYPASS
000001
1
000010
1.5
000011
2
—
—
111101
31
111110
31.5
11111
32
This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
89
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LM49360
The following registers are used to control the LM49360's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is
programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.
LM49360
TABLE 62. CLK_GEN_1 (0x52h/62h)
Bits
Field
2:0
SYNTH_NUM
3
SYNTH_DENOM
Description
Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in
master mode.
SYNTH_NUM
Numerator
000
SYNTH_DENOM (1/1)
001
100/SYNTH_DENOM
010
96/SYNTH_DENOM
011
80/SYNTH_DENOM
100
72/SYNTH_DENOM
101
64/SYNTH_DENOM
110
48/SYNTH_DENOM
111
0/SYNTH_DENOM
Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM
Denominator
0
128
1
125
TABLE 63. CLK_GEN_1 (0x53h/63h)
Bits
Field
Description
2:0
SYNC_RATE
This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port
data is mono or stereo.
In MONO mode:
SYNC_RATE
Number of Clock Cycles
000
8
001
12
010
16
011
18
100
20
101
24
110
25
111
32
In STEREO mode:
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SYNC_RATE
Number of Clock Cycles
000
16
001
24
010
32
011
36
100
40
101
48
110
50
111
64
90
Field
5:3
SYNC_WIDTH
LM49360
Bits
Description
In MONO mode, this programs the width (in number of bits) of the SYNC signal.
SYNC_WIDTH
Width of SYNC (in bits)
000
1
001
2
010
4
011
7
100
8
101
11
110
15
111
16
TABLE 64. DATA_WIDTHS (0x54h/64h)
Bits
Field
2:0
RX_WIDTH
5:3
7:6
TX_WIDTH
TX_EXTRA_BITS
Description
This programs the expected bits per word of the serial data input SDI.
RX_WIDTH
Bits
000
24
001
20
010
18
011
16
100
14
101
13
110
12
111
8
This programs the bits per word of the serial data output SDO.
TX_WIDTH
Description
000
24
001
20
010
18
011
16
100
14
101
13
110
12
111
8
This programs the TX data output padding.
TX_EXTRA_BITS
Description
00
0
01
1
10
High-Z
11
High-Z
91
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LM49360
TABLE 65. RX_MODE (0x55h/x65h)
Bits
Field
0
RX_MODE
5:1
MSB_POSITION
Description
This sets the RX data input justification with respect to the SYNC signal.
RX_MODE
Description
0
MSB Justified
1
LSB Justified
This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION
Description
00000
0(Left Justified/PCM Long)
00001
1(I2S/PCM Short)
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
01011
11
01100
12
01101
13
01110
14
01111
15
10000
16
10001
17
10010
18
10011
19
10100
20
10101
21
10110
22
10111
23
11000
24
11001
25
11010
26
11011
27
11100
28
11101
29
11110
30
11111
31
6
COMPAND
If set, received audio data will be companded.
7
μLaw/A-Law
This sets the audio companding mode.
μLaw/A-Law
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Compand Mode
0
μLaw
1
A-Law
92
LM49360
TABLE 66. TX_MODE (0x56h/x66h)
Bits
Field
0
TX_MODE
5:1
MSB_POSITION
Description
This sets the TX data input justification with respect to the SYNC signal.
TX_MODE
Description
0
MSB Justified
1
LSB Justified
This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION
Description
00000
0(Left Justified/PCM Long)
00001
1(I2S/PCM Short)
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
01011
11
01100
12
01101
13
01110
14
01111
15
10000
16
10001
17
10010
18
10011
19
10100
20
10101
21
10110
22
10111
23
11000
24
11001
25
11010
26
11011
27
11100
28
11101
29
11110
30
11111
31
6
COMPAND
If set, transmitted audio data will be companded.
7
μLaw/A-Law
This sets the audio companding mode.
μLaw/A-Law
Compand Mode
0
μLaw
1
A-Law
93
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LM49360
37.0 Digital Effects Engine
Digital Signal Processor (DSP)
The LM49360 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing
up the workload of any other applications processor contained within the system. The LM49360 features two independent DSPs,
one for the DAC and the other for the ADC. The DAC DSP features digital volume control, automatic level control (ALC), digital
soft clip compression and a 5-band parametric EQ. The ADC DSP features digital volume control, automatic level control (ALC)
and digital soft clip compression. The effects chain of each DSP engine is shown by the diagrams below.
30128257
FIGURE 30. ADC DSP Effects Chain
30128236
FIGURE 31. DAC DSP Effects Chain
The ADC and DAC DSP engines can be cascaded together in any order via the digital mixer to combine different audio effects to
the same signal path. For example, a signal can be processed with high-pass filtering from the ADC effects engine with ALC from
the DAC effects engine.
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94
LM49360
TABLE 67. ADC EFFECTS (0x70h)
Bits
Field
Description
0
ADC_HPF_ENB
This enables the ADC's High Pass Filter.
1
ADC_ALC_ENB
This enables the ADC's Automatic Level Control.
2
ADC_PK_ENB
3
RSVD
4
ADC_SCLP_ENB
This enables the ADC's Peak Detector.
Reserved
This enables the ADC's Soft Clip Feature.
TABLE 68. DAC EFFECTS (0x71h)
Bits
Field
0
DAC_ALC_ENB
1
DAC_PK_ENB
This enables the DAC's Peak Detector.
2
DAC_EQ_ENB
This enables the DAC's 5-band Parametric EQ.
3
RSVD
4
ADC_SCLP_ENB
Description
This enables the DAC's Automatic Level Control.
Reserved
This enables the DAC's Soft Clip Feature.
TABLE 69. HPF MODE (0x80h)
Bits
Field
2:0
HPF_MODE
Description
This configures the ADC's High Pass Filter.
HPF_MODE
FILTER CHARACTERISTICS
000
8kHz Voice
001
12kHz Voice
010
16kHz Voice
011
24kHz Voice
100
32kHz Voice
101
32kHz Audio
110
48kHz Audio
111
96kHz Audio
95
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LM49360
ALC Overview
The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC
feature is especially useful whenever the level of the audio input is unknown, unpredictable, or has a large dynamic range. The
main purpose of the ALC is to optimize the dynamic range of the audio input to audio output path.
There are two separate and independent ALC circuits in the LM49360. One of the ALC circuits is located within the DAC DSP
effects block. The other ALC circuit is integrated into the ADC DSP effects block. The DAC ALC controls the DAC digital gain. The
ADC ALC controls the mono/auxiliary input amplifier gain or microphone preamplifier gain. The dual ALCs can be used to regulate
the level of the analog (AUX, MONO, MIC) and digital (Port1 Data In, Port2 Data In) audio inputs. The ALC regulated output can
be routed to any of the LM49360’s amplifier outputs for playback. The ALC regulated output can also be routed to Audio Port1 or
Audio Port2 for digital data transmission via I2S or PCM.
Only audio inputs that are considered signals (rather than noise) are sent to the ALC’s peak detector block. The peak detector
compares the level of the audio input versus the ALC target level (TARGET_LEVEL). Signals lower than the target level will be
amplified and signals higher than the target level will be attenuated. Any audio input that is lower than the level specified by the
noise floor level (NOISE_FLOOR) will be considered as noise and will be gated from the ALC’s peak detector in order to avoid
noise pumping. So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding audio path.
In some instances (ie. Conference calls), it may be desirable to mute audio input signals that consist solely of background noise
from the audio output. This is accomplished by enabling the ALC’s noise gate (NG_ENB). When the noise gate is enabled, signals
lower than the noise floor level will be muted from the audio output.
If the audio input signal is below the target level, the ALC will increase the gain of the corresponding volume control until the signal
reaches the target level. The rate at which the ALC performs gain increases is known as decay rate (DECAY RATE). But before
each ALC gain increase the ALC must wait a predetermined amount of time (HOLD TIME). If the audio input signal is above the
target level, the ALC will decrease the gain of the corresponding volume control until the signal reaches the target level. The rate
at which the ALC performs attenuation is known as attack rate (ATTACK RATE). The ALC’s peak detector tracks increases in
audio input signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK
DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible
operation of the ALC circuit. The ALC’s timers are based on the sample rate of the DAC or ADC, so the closest corresponding
sample rate must be programmed into the DAC SAMPLE setting (for DAC ALC) or the ADC SAMPLE (for ADC ALC).
30128291
FIGURE 32. ALC Example
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96
The LM49360’s ALC features a limiter function. The purpose of the limiter is to limit the maximum level of the audio signal to the
specified ALC target level. When the limiter is enabled, the ALC will decrease the gain of the volume control whenever the audio
signal is higher than the specified target level. The programmed I2C gain setting when the limiter is first enabled is the maximum
gain setting that the ALC limiter will apply to the audio signal. Gain increases beyond the original I2C gain setting are disabled.
This is in contrast to ALC operation with the limiter disabled, where the ALC may increase gain of audio signals below target level
using gain settings beyond the original I2C gain setting. Therefore, it is important to set the gain of the audio path to the desired
setting before enabling the ALC limiter function.
The limiter’s target level can be set just below the clipping level of the output amplifier or ADC in order to prevent harsh distortions
delivered to the loudspeaker or headphone on the receiving end. This method of ALC limiter operation is also known as “no clip”
mode. Operating the ALC limiter in “no clip” mode maximizes the dynamic range of the audio amplifier or ADC while ensuring that
the audio signal will never clip. Utilizing the ALC limiter in “no clip” mode also protects the loudspeaker from damage due to harmful
overdriven conditions.
The ALC limiter’s target level can also be set for a predetermined maximum output power or voltage level. This method of ALC
limiter operation is known as “power limit” mode. Operating the ALC limiter in “power limit” mode prevents the speaker or headphone
from playing at unsafe hearing levels that can permanently damage the end user’s ears. “Power limit” operation is especially useful
for applications such as listening to music through a set of headphones. Another benefit of using the ALC limit in “power limit” mode
is to extend battery life by reducing power consumption of the output amplifiers during audio playback.
30128292
FIGURE 33. ALC Limiter
97
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LM49360
Limiter
LM49360
TABLE 70. ADC_ALC_1 (0x81h)
Bits
Field
2:0
ADC_SAMPLE
Description
This programs the timers on the ALC with the closest sample rate of the ADC.
ADC_SAMPLE
Expected ADC fS
000
8kHz
001
12kHz
010
16kHz
011
24kHz
100
32kHz
101
48kHz
110
96kHz
111
192kHz
3
LIMITER
If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the
signal as soon as it reaches target and release it at the decay rate, once signal level reduces below
target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC
will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling
the Limiter.
4
STEREO LINK
If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo
output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual
mono.
5
SOURCE_RSEL
If both SOURCE_OVR and this bit is set, the right ADC ALC channel will be active.
6
SOURCE_LSEL
If both SOURCE_OVR and this bit is set, the left ADC ALC channel will be active.
7
SOURCE_OVR
If set, the active channel of the ADC ALC is determined by SOURCE_RSEL and SOURCE_LSEL.
If cleared, the active channel of the ADC ALC is determined by the selected input to the ADC.
MONO enables left ALC, AUX enables right ALC, MIC enables left and / or right ALC depending
on which ADC channel MIC is selected to.
TABLE 71. ADC_ALC_2 (0x82h)
Bits
Field
Description
3:0
NOISE_FLOOR
This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from
the ALC to avoid noise pumping.
4
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NG_ENB
NOISE_FLOOR
Noise Floor (dB)
0000
–39
0001
–42
0010
–45
0011
–48
0100
–51
0101
–54
0110
–57
0111
–60
1000
–63
1001
–66
1010
–69
1011
–72
1100
–75
1101
–78
1110
–81
1111
–84
This enables the Noise Gate.
98
Bits
Field
Description
4:0
TARGET_LEVEL
This sets the desired target output level. Signals lower than this will be amplified and signals larger
than this will be attenuated.
TARGET_LEVEL
Target Level (dB)
00000
–1.5
00001
–3
00010
–4.5
00011
–6
00100
–7.5
00101
–9
00110
–10.5
00111
–12
01000
–13.5
01001
–15
01010
–16.5
01011
–18
01100
–19.5
01101
–21
01110
–22.5
01111
–24
10000
–25.5
10001
–27
10010
–28.5
10011
–30
10100
–31.5
10101
–33
10110
–34.5
10111
–36
11000
–37.5
11001
–39
11010
–40.5
11011
–42
11100
–43.5
11101
–45
11110
–46.5
11111
–48
99
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LM49360
TABLE 72. ADC_ALC_3 (0x83h)
LM49360
TABLE 73. ADC_ALC_4 (0x84h)
Bits
Field
4:0
ATTACK_RATE
www.ti.com
Description
This sets the rate at which the ALC will reduce gain if it detects the input signal is large.
ATTACK_RATE
Time between gain steps (μs)
00000
21
00001
42
00010
83
00011
167
00100
250
00101
333
00110
417
00111
542
01000
729
01001
958
01010
1250 (Default)
01011
1604
01100
1896
01101
2208
01110
2792
01111
3708
10000
4792
10001
5688
10010
6563
10011
8396
10100
11000
10101
14167
10110
17083
10111
20000
11000
25000
11001
32000
11010
45000
11011
60000
11100
75000
11101
87500
11110
100000
11111
114583
100
Bits
Field
4:0
DECAY_RATE
7:5
PK_DECAY_RATE
Description
This sets the rate at which the ALC will increase gain if it detects the input signal is too
small.
DECAY_RATE
Time between gain steps (μs)
00000
104
00001
125
00010
167
00011
250
00100
292
00101
396
00110
500
00111
708
01000
896
01001
1250
01010
1396 (Default)
01011
2000
01100
2708
01101
3500
01110
4750
01111
6250
10000
8000
10001
11000
10010
14000
10011
18500
10100
25000
10101
32000
10110
42000
10111
55000
11000
72500
11001
100000
11010
125000
11011
160000
11100
225000
11101
300000
11110
375000
11111
500000 (0.5s)
PK_DECAY_RATE
Max Time to track decay
000
1.3ms (Default)
001
2.6ms
010
5.3ms
011
10.6ms
100
21.3ms
101
42.6.3ms
110
85.5ms
111
2.73 secs
101
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LM49360
TABLE 74. ADC_ALC_5 (0x85h)
LM49360
TABLE 75. ADC_ALC_6 (0x86h)
Bits
Field
4:0
HOLD_TIME
Description
This sets how long the ALC circuit waits before increasing the gain.
HOLD_TIME
Time (ms)
00000
1
00001
1.25
00010
1.6
00011
2
00100
2.5
00101
3.2
00110
4
00111
5
01000
6.25
01001
8
01010
10 (Default)
01011
12.5
01100
16
01101
20
01110
25
01111
32
10000
40
10001
50
10010
64
10011
80
10100
100
10101
125
10110
160
10111
200
11000
250
11001
320
11010
400
11011
500
11100
640
11101
800
11110
1000
11111
1250
TABLE 76. ADC_ALC_7 (0x87h)
Bits
Field
Description
5:0
MAX_LEVEL
This sets the maximum allowed gain of the volume control to the output amplifier
whenever the ALC is use. If the volume control is less than 6 bits, the relevant LSBs are
used as the limit and the MSBs are ignored.
TABLE 77. ADC_ALC_8 (0x88h)
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Bits
Field
Description
5:0
MIN_LEVEL
This sets the minimum allowed gain of the volume control to the output amplifier whenever
the ALC is use. If the volume control is less than 6 bits, the relevant LSBs are used as
the limit and the MSBs are ignored.
102
LM49360
TABLE 78. ADC_L_LEVEL (0x89h)
Bits
Field
5:0
ADC_L_LEVEL
6
STEREO_LINK
Description
This sets the post ADC digital gain of the left channel.
ADC_L_LEVEL
Level
ADC_L_LEVEL
Level
000000
-76.5dB
100000
-28.5dB
000001
-75dB
100001
-27dB
000010
-73.5dB
100010
-25.5dB
000011
-72dB
100011
-24dB
000100
-70.5dB
100100
-22.5dB
000101
-69dB
100101
-21dB
000110
-67.5dB
100110
-20.5dB
000111
-66dB
100111
-18dB
001000
-64.5dB
101000
-16.5dB
001001
-63dB
101001
-15dB
001010
-61.5dB
101010
-13.5dB
001011
-60dB
101011
-12dB
001100
-58.5dB
101100
-10.5dB
001101
-57dB
101101
-9dB
001110
-55.5dB
101110
-7.5dB
001111
-54dB
101111
-6dB
010000
-52.5dB
110000
-4.5dB
010001
-51dB
110001
-3dB
010010
-49.5dB
110010
-1.5dB
010011
-48dB
110011
0dB
010100
-46.5dB
110100
1.5dB
010101
-45dB
110101
3dB
010110
-43.5dB
110110
4.5dB
010111
-42dB
110111
6dB
011000
-40.5dB
111000
7.5dB
011001
-39dB
111001
9dB
011010
-37.5dB
111010
10.5dB
011011
-36dB
111011
12dB
011100
-34.5dB
111100
13.5dB
011101
-33dB
111101
15dB
011110
-31.5dB
111110
16.5dB
011111
-30dB
111111
18dB
If set, this links the ADC_R_LEVEL with ADC_L_LEVEL.
103
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LM49360
TABLE 79. ADC_R_LEVEL (0x8Ah)
Bits
Field
5:0
ADC_R_LEVEL
www.ti.com
Description
This sets the post ADC digital gain of the right channel.
ADC_R_LEVEL
Level
ADC_R_LEVEL
Level
000000
-76.5dB
100000
-28.5dB
000001
-75dB
100001
-27dB
000010
-73.5dB
100010
-25.5dB
000011
-72dB
100011
-24dB
000100
-70.5dB
100100
-22.5dB
000101
-69dB
100101
-21dB
000110
-67.5dB
100110
-20.5dB
000111
-66dB
100111
-18dB
001000
-64.5dB
101000
-16.5dB
001001
-63dB
101001
-15dB
001010
-61.5dB
101010
-13.5dB
001011
-60dB
101011
-12dB
001100
-58.5dB
101100
-10.5dB
001101
-57dB
101101
-9dB
001110
-55.5dB
101110
-7.5dB
001111
-54dB
101111
-6dB
010000
-52.5dB
110000
-4.5dB
010001
-51dB
110001
-3dB
010010
-49.5dB
110010
-1.5dB
010011
-48dB
110011
0dB
010100
-46.5dB
110100
1.5dB
010101
-45dB
110101
3dB
010110
-43.5dB
110110
4.5dB
010111
-42dB
110111
6dB
011000
-40.5dB
111000
7.5dB
011001
-39dB
111001
9dB
011010
-37.5dB
111010
10.5dB
011011
-36dB
111011
12dB
011100
-34.5dB
111100
13.5dB
011101
-33dB
111101
15dB
011110
-31.5dB
111110
16.5dB
011111
-30dB
111111
18dB
104
The LM49360 features a digital audio compressor on both the DAC and ADC paths. The compressor works by reducing the level
of the audio signal that is higher than the level set by the audio compressor threshold level (THRESHOLD) by a fixed ratio (compressor output / compressor input) that is set by a predetermined audio compression ratio (RATIO). Higher compression ratios
result in more compression as shown in Figure 34. The audio compressor can be used in conjunction with the ALC to limit audio
peaks that the ALC may not be fast enough to react to.
30128289
FIGURE 34. Audio Compressor Effect
105
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LM49360
Digital Audio Compressor
LM49360
Soft Knee Function
The LM49360’s audio compressor also features a soft knee function that smooths the harsh edges found during clipping of an
audio signal. For audio signals higher than the compressor threshold level, the soft knee function gradually increases the compression ratio for increasing levels of audio signal beyond the compressor threshold. To achieve the smoothing effect to prevent
hard clipping, the soft knee function initially compresses the audio signal at the smallest ratio and then incrementally increases the
compression ratio if required. The highest level of compression applied by the soft knee function is set by the compressor ratio.
The effect of the soft knee function is shown in Figure 35.
30128290
FIGURE 35. Soft Knee Example with Compression Ratio Setting of 1:3.4
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106
Bits
Field
Description
3:0
THRESHOLD
This sets the threshold level of the audio compressor. Audio signals
above the threshold will be compressed.
4
SOFT_KNEE
THRESHOLD
Threshold Level (dB)
0000
-36dB
0001
-30dB
0010
-24dB
0011
-20dB
0100
-18dB
0101
-17dB
0110
-16dB
0111
-15dB
1000
-14dB
1001
-12dB
1010
-10dB
1011
-8dB
1100
-6dB
1101
-4dB
1110
-2.5dB
1111
-1dB
If set, the audio compressor will automatically apply higher
compression ratios to audio signals higher than the threshold level.
As the audio signal approaches levels higher than the threshold,
SOFT_KNEE will increase the compression RATIO. The highest
compression that the SOFT_KNEE algorithm will apply is the
compression that is set by RATIO.
107
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LM49360
TABLE 80. SOFTCLIP1 (0x90h)
LM49360
TABLE 81. SOFTCLIP2 (0x91h)
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Bits
Field
Description
4:0
RATIO
This sets the ratio at which the audio is compressed to when it
passes beyond the threshold. In SOFT_KNEE mode this is the final
level of compression.
108
RATIO
Ratio
00000
1:1 (Bypass)
00001
1:1.2
00010
1:1.4
00011
1:1.7
00100
1:2.0
00101
1:2.4
00110
1:2.8
00111
1:3.4
01000
1:4.0
01001
1:4.7
01010
1:5.7
01011
1:6.7
01100
1:8.0
01101
1:9.5
01110
1:11.3
01111
1:13.5
10000
1:16.0
10001
1:19.0
10010
1:22.8
10011
1:27.0
10100
1:32.0
10101
1:37.9
10110
1:45.5
10111
1:53.9
11000
1:64.0
11001
1:75.0
11010
1:91.0
11011
1:108
11100
1:128
11101
1:152
11110
1:182
11111
1:215
LM49360
TABLE 82. SOFTCLIP3 (0x92h)
Bits
Field
3:0
LEVEL
Description
This sets the post compressor gain level.
109
LEVEL
Level (dB)
00000
-22.5dB
00001
-21dB
00010
-19.5dB
00011
-18dB
00100
-16.5dB
00101
-15dB
00110
-13.5dB
00111
-12dB
01000
-10.5dB
01001
-9dB
01010
-7.5dB
01011
-6dB
01100
-4.5dB
01101
-3dB
01110
-1.5dB
01111
0dB
10000
1.5dB
10001
3dB
10010
4.5dB
10011
6dB
10100
7.5dB
10101
9dB
10110
10.5dB
10111
12dB
11000
13.5dB
11001
15dB
11010
16.5dB
11011
18dB
11100
19.5dB
11101
21dB
11110
22.5dB
11111
24dB
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LM49360
38.0 DAC Effects Registers
TABLE 83. DAC_ALC_1 (0xA0h)
Bits
Field
Description
2:0
DAC_SAMPLE
This programs the timers on the ALC with the closest DAC sample
rate.
DAC_SAMPLE
Expected DAC fS
000
8kHz
001
12kHz
010
16kHz
011
24kHz
100
32kHz
101
48kHz
110
96kHz
111
192kHz
3
LIMITER
If set, the circuit will never apply gain to the signal, no matter how
small, but it will attenuate the signal as soon as it reaches target
and release it at the decay rate, once signal level reduces below
target. The I2C gain setting (at the time the LIMITER is enabled) is
the maximum gain that the ALC will apply. Care should be taken
when choosing the optimum I2C gain setting whenever enabling the
Limiter.
4
STEREO LINK
If set, the ALC circuit uses the stereo average of the input signals
to control the gain of the stereo output. This maintains stereo
imaging. If this bit is cleared, then both channels operate as dual
mono.
TABLE 84. DAC_ALC_2 (0xA1h)
Bits
Field
3:0
NOISE_FLOOR
4
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NG_ENB
Description
This sets the anticipated noise floor. Signals lower than the
specified noise floor will be gated from the ALC to avoid noise
pumping.
NOISE_FLOOR
Noise Floor (dB)
0000
-39
0001
-42
0010
-45
0011
-48
0100
-51
0101
-54
0110
-57
0111
-60
1000
-63
1001
-66
1010
-69
1011
-72
1100
-75
1101
-78
1110
-81
1111
-84
This enables the Noise Gate.
110
Bits
Field
4:0
TARGET_LEVEL
Description
This sets the desired output level. Signals lower than this will be
amplified and signals larger than this will be attenuated.
111
TARGET_LEVEL
Target Level (dB)
00000
-1.5
00001
-3
00010
-4.5
00011
-6
00100
-7.5
00101
-9
00110
-10.5
00111
-12
01000
-13.5
01001
-15
01010
-16.5
01011
-18
01100
-19.5
01101
-21
01110
-22.5
01111
-24
10000
-25.5
10001
-27
10010
-28.5
10011
-30
10100
-31.5
10101
-33
10110
-34.5
10111
-36
11000
-37.5
11001
-39
11010
-40.5
11011
-42
11100
-43.5
11101
-45
11110
-46.5
11111
-48
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LM49360
TABLE 85. DAC_ALC_3 (0xA2h)
LM49360
TABLE 86. DAC_ALC_4 (0xA3h)
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Bits
Field
Description
4:0
ATTACK_RATE
This sets the rate at which the ALC will reduce gain if it detects the
input signal is too large.
112
ATTACK_RATE
Time between gain steps(us)
00000
21
00001
42
00010
83
00011
167
00100
250
00101
333
00110
417
00111
542
01000
729
01001
958
01010
1250 (Default)
01011
1604
01100
1896
01101
2208
01110
2792
01111
3708
10000
4792
10001
5688
10010
6563
10011
8396
10100
11000
10101
14167
10110
17083
10111
20000
11000
25000
11001
32000
11010
45000
11011
60000
11100
75000
11101
87500
11110
100000
11111
114583
Bits
Field
Description
4:0
DECAY_RATE
This sets the rate at which the ALC will increase gain if it detects the
input signal is too small.
7:5
PK_DECAY_RATE
DECAY_RATE
Time between gain steps(us)
00000
104
00001
125
00010
167
00011
250
00100
292
00101
396
00110
500
00111
708
01000
896
01001
1250
01010
1396 (Default)
01011
2000
01100
2708
01101
3500
01110
4750
01111
6250
10000
8000
10001
11000
10010
14000
10011
18500
10100
25000
10101
32000
10110
42000
10111
55000
11000
72500
11001
100000
11010
125000
11011
160000
11100
225000
11101
300000
11110
375000
11111
500000 (0.5s)
This sets how precise the ALC will track amplitude reductions of the
audio input. The shorter the length of time for PK_DECAY_RATE, the
more responsive the ALC will be when applying gain increases
whenever the audio falls below target level.
113
PK_DECAY_RATE
Time
000
1.3ms (Default)
001
2.6ms
010
5.3ms
011
10.6ms
100
21.3ms
101
42.6ms
110
85.5ms
111
2.73secs
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LM49360
TABLE 87. DAC_ALC_5 (0xA4h)
LM49360
TABLE 88. DAC_ALC_6 (0xA5h)
Bits
Field
Description
4:0
HOLD_TIME
This sets how long the ALC circuit waits before increasing the gain.
HOLDTIME
Time (ms)
00000
1
00001
1.25
00010
1.6
00011
2
00100
2.5
00101
3.2
00110
4
00111
5
01000
6.25
01001
8
01010
10 (Default)
01011
12.5
01100
16
01101
20
01110
25
01111
32
10000
40
10001
50
10010
64
10011
80
10100
100
10101
125
10110
160
10111
200
11000
250
11001
320
11010
400
11011
500
11100
640
11101
800
11110
1000
11111
1250
TABLE 89. DAC_ALC_7 (0xA6h)
Bits
Field
5:0
MAX_LEVEL
Description
This sets the maximum allowed gain to the digital level control
when the ALC is used.
TABLE 90. DAC_ALC_8 (0xA7h)
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Bits
Field
5:0
MIN_LEVEL
Description
This sets the minimum allowed gain to the digital level control
when the ALC is used.
114
LM49360
TABLE 91. DAC_L_LEVEL (0xA8h)
Bits
Field
5:0
DAC_L_LEVEL
6
STEREO_LINK
Description
This sets the pre DAC digital gain.
DAC_L_LEVEL
Level
DAC_L_LEVEL
Level
000000
-76.5dB
100000
-28.5dB
000001
-75dB
100001
-27dB
000010
-73.5dB
100010
-25.5dB
000011
-72dB
100011
-24dB
000100
-70.5dB
100100
-22.5dB
000101
-69dB
100101
-21dB
000110
-67.5dB
100110
-20.5dB
000111
-66dB
100111
-18dB
001000
-64.5dB
101000
-16.5dB
001001
-63dB
101001
-15dB
001010
-61.5dB
101010
-13.5dB
001011
-60dB
101011
-12dB
001100
-58.5dB
101100
-10.5dB
001101
-57dB
101101
-9dB
001110
-55.5dB
101110
-7.5dB
001111
-54dB
101111
-6dB
010000
-52.5dB
110000
-4.5dB
010001
-51dB
110001
-3dB
010010
-49.5dB
110010
-1.5dB
010011
-48dB
110011
0dB
010100
-46.5dB
110100
1.5dB
010101
-45dB
110101
3dB
010110
-43.5dB
110110
4.5dB
010111
-42dB
110111
6dB
011000
-40.5dB
111000
7.5dB
011001
-39dB
111001
9dB
011010
-37.5dB
111010
10.5dB
011011
-36dB
111011
12dB
011100
-34.5dB
111100
13.5dB
011101
-33dB
111101
15dB
011110
-31.5dB
111110
16.5dB
011111
-30dB
111111
18dB
If set, this links DAC_R_LEVEL with DAC_L_LEVEL.
115
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LM49360
TABLE 92. DAC_R_LEVEL (0xA9h)
Bits
Field
5:0
DAC_R_LEVEL
www.ti.com
Description
This sets the pre DAC digital gain.
DAC_R_LEVEL
Level
DAC_R_LEVEL
Level
000000
-76.5dB
100000
-28.5dB
000001
-75dB
100001
-27dB
000010
-73.5dB
100010
-25.5dB
000011
-72dB
100011
-24dB
000100
-70.5dB
100100
-22.5dB
000101
-69dB
100101
-21dB
000110
-67.5dB
100110
-20.5dB
000111
-66dB
100111
-18dB
001000
-64.5dB
101000
-16.5dB
001001
-63dB
101001
-15dB
001010
-61.5dB
101010
-13.5dB
001011
-60dB
101011
-12dB
001100
-58.5dB
101100
-10.5dB
001101
-57dB
101101
-9dB
001110
-55.5dB
101110
-7.5dB
001111
-54dB
101111
-6dB
010000
-52.5dB
110000
-4.5dB
010001
-51dB
110001
-3dB
010010
-49.5dB
110010
-1.5dB
010011
-48dB
110011
0dB
010100
-46.5dB
110100
1.5dB
010101
-45dB
110101
3dB
010110
-43.5dB
110110
4.5dB
010111
-42dB
110111
6dB
011000
-40.5dB
111000
7.5dB
011001
-39dB
111001
9dB
011010
-37.5dB
111010
10.5dB
011011
-36dB
111011
12dB
011100
-34.5dB
111100
13.5dB
011101
-33dB
111101
15dB
011110
-31.5dB
111110
16.5dB
011111
-30dB
111111
18dB
116
LM49360
TABLE 93. EQ_BAND_1 (0xABh)
Bits
Field
1:0
FREQ
6:2
LEVEL
Description
This sets the Sub-bass shelving filter's cut-off frequency.
FREQ
Frequency (Hz)
00
60
01
80
10
100
11
120
This sets the gain at fC.
117
LEVEL
Effect
00000
Off (0dB)
00001
-15dB
00010
-14dB
00011
-13dB
00100
-12dB
00101
-11dB
00110
-10dB
00111
-9dB
01000
-8dB
01001
-7dB
01010
-6dB
01011
-5dB
01100
-4dB
01101
-3dB
01110
-2dB
01111
-1dB
10000
0dB
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11011
11dB
11100
12dB
11101
13dB
11110
14dB
11111
15dB
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LM49360
TABLE 94. EQ_BAND_2 (0xACh)
Bits
Field
1:0
FREQ
6:2
7
www.ti.com
LEVEL
Q
Description
This sets the Bass peak filter's center frequency.
FREQ
Frequency (Hz)
00
150
01
200
10
250
11
300
This sets the gain at fC.
LEVEL
Effect
00000
Off (0dB)
00001
-15dB
00010
-14dB
00011
-13dB
00100
-12dB
00101
-11dB
00110
-10dB
00111
-9dB
01000
-8dB
01001
-7dB
01010
-6dB
01011
-5dB
01100
-4dB
01101
-3dB
01110
-2dB
01111
-1dB
10000
0dB
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11011
11dB
11100
12dB
11101
13dB
11110
14dB
11111
15dB
This programs the width of the peak filter.
118
Q
Bandwidth
0
2/3 Octave
1
4/3 Octave
LM49360
TABLE 95. EQ_BAND_3 (0xADh)
Bits
Field
1:0
FREQ
6:2
7
LEVEL
Q
Description
This sets the Mid peak filter's center frequency.
FREQ
Frequency (Hz)
00
600
01
800
10
1k
11
1.2k
This sets the gain at fC.
LEVEL
Effect
00000
Off (0dB)
00001
-15dB
00010
-14dB
00011
-13dB
00100
-12dB
00101
-11dB
00110
-10dB
00111
-9dB
01000
-8dB
01001
-7dB
01010
-6dB
01011
-5dB
01100
-4dB
01101
-3dB
01110
-2dB
01111
-1dB
10000
0dB
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11011
11dB
11100
12dB
11101
13dB
11110
14dB
11111
15dB
This programs the width of the peak filter.
119
Q
Bandwidth
0
2/3 Octave
1
4/3 Octave
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LM49360
TABLE 96. EQ_BAND_4 (0xAEh)
Bits
Field
1:0
FREQ
Description
This sets the Treble peak filter's center frequency.
FREQ
6:2
7
www.ti.com
LEVEL
Q
Frequency (Hz)
00
2k
01
2.7k
10
3.4k
11
4.1k
This sets the gain at fC.
LEVEL
Effect
00000
Off (0dB)
00001
-15dB
00010
-14dB
00011
-13dB
00100
-12dB
00101
-11dB
00110
-10dB
00111
-9dB
01000
-8dB
01001
-7dB
01010
-6dB
01011
-5dB
01100
-4dB
01101
-3dB
01110
-2dB
01111
-1dB
10000
0dB
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11011
11dB
11100
12dB
11101
13dB
11110
14dB
11111
15dB
This programs the width of the peak filter.
120
Q
Bandwidth
0
2/3 Octave
1
4/3 Octave
LM49360
TABLE 97. EQ_BAND_5 (0xAFh)
Bits
Field
1:0
FREQ
6:2
LEVEL
Description
This sets the presence shelving filter's cut-off frequency.
FREQ
Frequency (Hz)
00
7k
01
9k
10
11k
11
20k
This sets the gain at fC.
121
LEVEL
Effect
00000
Off (0dB)
00001
-15dB
00010
-14dB
00011
-13dB
00100
-12dB
00101
-11dB
00110
-10dB
00111
-9dB
01000
-8dB
01001
-7dB
01010
-6dB
01011
-5dB
01100
-4dB
01101
-3dB
01110
-2dB
01111
-1dB
10000
0dB
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11011
11dB
11100
12dB
11101
13dB
11110
14dB
11111
15dB
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LM49360
TABLE 98. SOFTCLIP1 (0xB0h)
Bits
Field
Description
3:0
TRESHOLD
This sets the threshold level of the audio compressor. Audio signals
above the threshold will be compressed.
4
www.ti.com
SOFT_KNEE
THRESHOLD
Threshold Level (dB)
0000
-36dB
0001
-30dB
0010
-24dB
0011
-20dB
0100
-18dB
0101
-17dB
0110
-16dB
0111
-15dB
1000
-14dB
1001
-12dB
1010
-10dB
1011
-8dB
1100
-6dB
1101
-4dB
1110
-2.5dB
1111
-1dB
If set, the audio compressor will automatically apply higher
compression ratios to audio signals higher than the threshold level.
As the audio signal approaches levels higher than the threshold,
SOFT_KNEE will increase the compression RATIO. The highest
compression that the SOFT_KNEE algorithm will apply is the
compression that is set by RATIO.
122
LM49360
TABLE 99. SOFTCLIP2 (0xB1h)
Bits
Field
Description
4:0
RATIO
This sets the ratio at which the audio is compressed to when it
passes beyond the threshold. In soft clip mode, this is the final level
of compression.
123
RATIO
Ratio
00000
1:1 (Bypass)
00001
1:1.2
00010
1:1.4
00011
1:1.7
00100
1:2.0
00101
1:2.4
00110
1:2.8
00111
1:3.4
01000
1:4.0
01001
1:4.7
01010
1:5.7
01011
1:6.7
01100
1:8.0
01101
1:9.5
01110
1:11.3
01111
1:13.5
10000
1:16.0
10001
1:19.0
10010
1:22.8
10011
1:27.0
10100
1:32.0
10101
1:37.9
10110
1:45.5
10111
1:53.9
11000
1:64
11001
1:75.9
11010
1:91.0
11011
1:108
11100
1:128
11101
1:152
11110
1:182
11111
1:215
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LM49360
TABLE 100. SOFTCLIP3 (0xB2h)
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Bits
Field
4:0
LEVEL
Description
This sets the post compressor gain level.
124
LEVEL
Level (dB)
00000
-22.5dB
00001
-21dB
00010
-19.5dB
00011
-18dB
00100
-16.5dB
00101
-15dB
00110
-13.5dB
00111
-12dB
01000
-10.5dB
01001
-9dB
01010
-7.5dB
01011
-6dB
01100
-4.5dB
01101
-3dB
01110
-1.5dB
01111
0dB
10000
1.5dB
10001
3dB
10010
4.5dB
10011
6dB
10100
7.5dB
10101
9dB
10110
10.5dB
10111
12dB
11000
13.5dB
11001
15dB
11010
16.5dB
11011
18dB
11100
19.5dB
11101
21dB
11110
22.5dB
11111
24dB
LM49360
39.0 GPIO Registers
TABLE 101. GPIO1 (0xE0h)
Bits
Field
5:0
GPIO_MODE
6
7
Description
This sets the mode of the GPIO pin.
GPIO_MODE
GPIO STATUS
000000
If GPIO Mode is disabled, PORT2_SDO is controlled by
the Port2 serial interface configuration. In all the other
modes, PORT2_SDO is configured as the GPIO pin.
000001
GPIO_RX (in)
000010
CHIP ENABLE (in)
000011
CHIP ENABLE (in)
000100
ADC MUTE (in)
000101
ADC MUTE (in)
000110
HP SENSE (in)
000111
HP SENSE (in)
001000
SPARE (in)
001001
SPARE (in)
001010
GPIO TX (out)
001011
CHIP ACTIVE (out)
001100
CHIP ACTIVE (out)
001101
HP ENABLE (out)
001110
HP ENABLE (out)
001111
LS ENABLE (out)
010000
LS ENABLE (out)
010001
EP ENABLE (out)
010010
EP ENABLE (out)
010011
ADC CLIPPED (out)
010100
ADC CLIPPED (out)
010101
DAC CLIPPED (out)
010110
DAC CLIPPED (out)
010111
SOMETHING CLIPPED (out)
011000
SOMETHING CLIPPED (out)
011001
ADC NG ACTIVE (out)
011010
ADC NG ACTIVE (out)
011011
DAC NG ACTIVE (out)
011100
DAC NG ACTIVE (out)
011101
THERMAL (out)
011110
THERMAL (out)
011111
LS SHORT CCT (out)
100000
LS SHORT CCT (out)
100001
ANALOG ERROR
Thermal or LS CCT condition (out)
100010
ANALOG ERROR (out)
100011
ERROR (out)
Thermal or LS CCT
or Clipping
100100
ERROR (out)
100101 – 111111
RESERVED
GPIO_TX
Whenever GPIO_MODE is set to '001010', the GPIO pin will output a logic level based on
this bit setting. Setting this bit high will result in a logic high GPIO output.
GPIO_RX
This bit reports the logic level is present on the GPIO pin.
125
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LM49360
TABLE 102. GPIO2 (0xE1h)
Bits
Field
Description
0
SHORT
This bit will go high whenever a short circuit condition occurs on the Class
D loudspeaker amplifier outputs. Once triggered by a short circuit event,
an I2C write of 1 to this bit clear this bit.
1
TEMP
This bit will go high whenever the temperature of the LM49360 reaches
a critical temperature. Once triggered by a thermal event, an I2C write of
1 to this bit clear this bit.
TABLE 103. RESET (0xF0h)
Bits
Field
Description
4:0
RSVD
5
SOFT_RESET
Reserved.
Setting this bit resets the digital core of LM49360. SOFT_RESET does
not affect the current I2C register settings.
TABLE 104. Spread Spectrum (0xF1h)
Bits
Field
1:0
RSVD
2
SS_DISABLE
Description
Reserved
If this bit is set, Spread Spectrum mode will be disabled from the Class
D amplifier.
TABLE 105. FORCE (0xFE)
Bits
Field
0
RSVD
1
DACREF
Description
Reserved
This bit determines whether the DAC reference voltage is internally
generated or externally driven.
DACREF
2
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CP_FORCE
STATUS
0
DACREF uses an internal bandgap
reference.
1
DACREF is driven by an external
voltage reference.
If set, a -LS_VDD rail will be generated on HP_VSS, even if the
headphone output stage is not required.
126
FIGURE 36. Demo Board Schematic
30128220
LM49360
40.0 Schematic Diagram
127
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128
FIGURE 37. Demo Board Schematic
30128245
LM49360
LM49360
41.0 Demonstration Board Layout
30128243
FIGURE 38. Top Silkscreen
30128244
FIGURE 39. Top Layer
129
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LM49360
30128238
FIGURE 40. Inner Layer 2
30128239
FIGURE 41. Inner Layer 3
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130
LM49360
30128240
FIGURE 42. Inner Layer 4
30128241
FIGURE 43. Inner Layer 5
131
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LM49360
30128231
FIGURE 44. Bottom Layer
30128242
FIGURE 45. Bottom Silkscreen
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132
LM49360
42.0 Revision History
Rev
Date
1.0
11/14/11
Description
Initial WEB released.
1.01
12/01/11
Changed the Vdo Max limit in the “EC LDOs 1 to 6” table from (200 to 250).
133
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LM49360
43.0 Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD–64 Package
Order Number LM49360RL
NS Package Number RLA64JBA
X1 = 4.169±.03mm, X2 = 3.99±.03mm, X3 = 0.65±.075mm
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134
LM49360
Notes
135
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