áç PRELIMINARY XRT75L03D THREE-CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APRIL 2002 GENERAL DESCRIPTION The XRT75L03D is a Three-Channel fully integrated Line Interface Unit (LIU) and Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates three independent Receivers, Transmitters and Jitter Attenuators in a single 128-Lead QFP package. Each channel of the XRT75L03D can be independently configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) rates. Each transmitter can be turned off and tristated for redundancy support and power conservation. The XRT75L03D’s differential receivers provide high noise interference margin and are able to receive the data over 1000 feet of cable, or with cable attenuation of up to 12 dB. The XRT75L03D incorporates an advanced crystalless jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. Also the jitter attenuator can be used for clock smoothing in SONET STS1 to DS3 de-mapping. The XRT75L03D provides both Serial Microprocessor Interface as well as Hardware mode for programming and control. The XRT75L03D supports local,remote and digital loop-backs. The XRT75L03D also contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error. REV. P1.0.0 • Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications • Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications Transmitter: • Compliant with Bellcore GR-499, GR-253 and ANSI T1.102 Specification for transmit pulse • Tri-state Transmit output capability for redundancy applications • Transmitter can be turned on or off Jitter Attenuator: • On chip advanced crystal-less Jitter Attenuators • Jitter Attenuators can be selected in Receive or Transmit paths • Compliant with jitter transfer template outlined in ITU G.751, G.752, G.755, GR-253 and GR-499CORE,1995 standards • Meets ETSI TBR 24 Jitter Transfer Requirements • 16, 32 or 128 bits selectable FIFO size • De-Synchronizer for SONET STS-1 to DS3 demapping • Meets the Jitter and Wander described in the ANSI T1.105.03b specifications • Jitter Attenuators can be disabled Control and Diagnostics: • 5 wire Serial Microprocessor Interface for control and configuration • Supports optional internal Transmit Driver Monitoring FEATURES Receiver: • PRBS Error Counter Register to accumulate errors • On chip Clock and Data Recovery circuit for high input jitter tolerance • Supports Local, Remote and Digital Loop-backs • Meets E3/DS3/STS-1 Jitter Tolerance Requirements • 5 V Tolerant I/O • Detects and Clears LOS as per G.775 • -40°C to 85°C Industrial Temperature Range • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation APPLICATIONS • Hardware Mode for control and configuration • Single 3.3 V ± 5% power supply • Available in 128 pin TQFP • On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled • E3/DS3 Access Equipment • On-chip Clock Synthesizer generates the appropriate rate clock from a single frequency Crystal • DSLAMs • Provides low jitter clock outputs for either E3, DS3 or STS-1 rates • CSU/DSU Equipment • STS1-SPE to DS3 Mapper • Digital Cross Connect Systems • Routers • Fiber Optic Terminals Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç XRT75L03D THREE-CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER PRELIMINARY REV. P1.0.0 FIGURE 1. BLOCK DIAGRAM OF THE XRT75L03D SD I SD O IN T S C lk CLK_OU T E 3 C L K _n , DS3CLK_n, S T S -1 C L K _ n R L O L _ (n ) RxON R x C lk IN V X R T 75L03D Se rial Processor Interface CS RESET H O S T /H W S T S -1 /D S 3_ (n ) E 3 _ (n) R E Q E N _ (n ) R T IP _ (n ) R R in g _ (n ) Slicer AG C/ Equalizer Clock & Data Recovery Jitter Attenuator LOS Detector S R /D R L L B _(n ) Clock Synthesizer Peak Detector Local Loop Back MUX Invert R x C lk _ (n ) HD B3/ B3ZS Decoder R P O S _ (n ) R N E G _ (n )/ L C V _ (n ) Rem ote LoopBack R L B _ (n) R L O S _(n ) L O S T H R _ (n ) T T IP _(n ) T R ing _ (n) M TIP _ (n ) M R in g_ (n) J A T x /R x Line Driver D evice M onitor Tx Pulse Shaping Jitter Attenuator Tim ing Control MUX T P D a ta _ (n ) HD B3/ B3ZS Encoder T N D a ta _ (n ) T xC lk_ (n ) T A O S _ (n ) Tx Control D M O _ (n ) T xL E V _ (n ) T xO N _ (n ) C h a nn e l 0 C h a nn e l 1 C h an n e l 2 N o tes : 1 . (n ) = 0 , 1 or 2 fo r res p e c tive C h an n els 2 . S eria l P roc e s s o r In te rfac e in p ut p ins a re sh a re d b y th e th re e C h a n n e ls in " H o s t" M o d e a n d re d efin e d in th e " H a rd w a re " M o d e . Transmit Interface Characteristics Receive Interface Characteristics • Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line • Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery • Integrated Pulse Shaping Circuit • Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications • Built-in B3ZS/HDB3 Encoder (which can be disabled) • Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms • Accepts Transmit Clock with duty cycle of 30%-70% • Built-in B3ZS/HDB3 Decoder (which can be disabled) • Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications • Recovered Data can be muted while the LOS Condition is declared • Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102_1993 • Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment • Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253CORE • Transmitter can be turned off in order to support redundancy designs ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT75L03DIV 128 Pin TQFP -40°C to +85°C 2